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Elijah Orr / mbed-renbed

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TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_eth.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 110:165afa46840b

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	101:7cff1c4259d7	1	/**
Kojto	101:7cff1c4259d7	2	******************************************************************************
Kojto	101:7cff1c4259d7	3	* @file stm32f4xx_hal_eth.h
Kojto	101:7cff1c4259d7	4	* @author MCD Application Team
Kojto	110:165afa46840b	5	* @version V1.4.1
Kojto	110:165afa46840b	6	* @date 09-October-2015
Kojto	101:7cff1c4259d7	7	* @brief Header file of ETH HAL module.
Kojto	101:7cff1c4259d7	8	******************************************************************************
Kojto	101:7cff1c4259d7	9	* @attention
Kojto	101:7cff1c4259d7	10	*
Kojto	101:7cff1c4259d7	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	101:7cff1c4259d7	12	*
Kojto	101:7cff1c4259d7	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	101:7cff1c4259d7	14	* are permitted provided that the following conditions are met:
Kojto	101:7cff1c4259d7	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	101:7cff1c4259d7	16	* this list of conditions and the following disclaimer.
Kojto	101:7cff1c4259d7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	101:7cff1c4259d7	18	* this list of conditions and the following disclaimer in the documentation
Kojto	101:7cff1c4259d7	19	* and/or other materials provided with the distribution.
Kojto	101:7cff1c4259d7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	101:7cff1c4259d7	21	* may be used to endorse or promote products derived from this software
Kojto	101:7cff1c4259d7	22	* without specific prior written permission.
Kojto	101:7cff1c4259d7	23	*
Kojto	101:7cff1c4259d7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	101:7cff1c4259d7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	101:7cff1c4259d7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	101:7cff1c4259d7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	101:7cff1c4259d7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	101:7cff1c4259d7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	101:7cff1c4259d7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	101:7cff1c4259d7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	101:7cff1c4259d7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	101:7cff1c4259d7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	101:7cff1c4259d7	34	*
Kojto	101:7cff1c4259d7	35	******************************************************************************
Kojto	101:7cff1c4259d7	36	*/
Kojto	101:7cff1c4259d7	37
Kojto	101:7cff1c4259d7	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	101:7cff1c4259d7	39	#ifndef __STM32F4xx_HAL_ETH_H
Kojto	101:7cff1c4259d7	40	#define __STM32F4xx_HAL_ETH_H
Kojto	101:7cff1c4259d7	41
Kojto	101:7cff1c4259d7	42	#ifdef __cplusplus
Kojto	101:7cff1c4259d7	43	extern "C" {
Kojto	101:7cff1c4259d7	44	#endif
Kojto	101:7cff1c4259d7	45
Kojto	110:165afa46840b	46	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
Kojto	110:165afa46840b	47	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	101:7cff1c4259d7	48	/* Includes ------------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	49	#include "stm32f4xx_hal_def.h"
Kojto	101:7cff1c4259d7	50
Kojto	101:7cff1c4259d7	51	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	101:7cff1c4259d7	52	* @{
Kojto	101:7cff1c4259d7	53	*/
Kojto	101:7cff1c4259d7	54
Kojto	101:7cff1c4259d7	55	/** @addtogroup ETH
Kojto	101:7cff1c4259d7	56	* @{
Kojto	101:7cff1c4259d7	57	*/
Kojto	101:7cff1c4259d7	58
Kojto	101:7cff1c4259d7	59	/** @addtogroup ETH_Private_Macros
Kojto	101:7cff1c4259d7	60	* @{
Kojto	101:7cff1c4259d7	61	*/
Kojto	101:7cff1c4259d7	62	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
Kojto	101:7cff1c4259d7	63	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	64	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
Kojto	101:7cff1c4259d7	65	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
Kojto	101:7cff1c4259d7	66	((SPEED) == ETH_SPEED_100M))
Kojto	101:7cff1c4259d7	67	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
Kojto	101:7cff1c4259d7	68	((MODE) == ETH_MODE_HALFDUPLEX))
Kojto	101:7cff1c4259d7	69	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
Kojto	101:7cff1c4259d7	70	((MODE) == ETH_RXINTERRUPT_MODE))
Kojto	101:7cff1c4259d7	71	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
Kojto	101:7cff1c4259d7	72	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
Kojto	101:7cff1c4259d7	73	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
Kojto	101:7cff1c4259d7	74	((MODE) == ETH_MEDIA_INTERFACE_RMII))
Kojto	101:7cff1c4259d7	75	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	76	((CMD) == ETH_WATCHDOG_DISABLE))
Kojto	101:7cff1c4259d7	77	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	78	((CMD) == ETH_JABBER_DISABLE))
Kojto	101:7cff1c4259d7	79	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
Kojto	101:7cff1c4259d7	80	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
Kojto	101:7cff1c4259d7	81	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
Kojto	101:7cff1c4259d7	82	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
Kojto	101:7cff1c4259d7	83	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
Kojto	101:7cff1c4259d7	84	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
Kojto	101:7cff1c4259d7	85	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
Kojto	101:7cff1c4259d7	86	((GAP) == ETH_INTERFRAMEGAP_40BIT))
Kojto	101:7cff1c4259d7	87	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	88	((CMD) == ETH_CARRIERSENCE_DISABLE))
Kojto	101:7cff1c4259d7	89	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	90	((CMD) == ETH_RECEIVEOWN_DISABLE))
Kojto	101:7cff1c4259d7	91	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	92	((CMD) == ETH_LOOPBACKMODE_DISABLE))
Kojto	101:7cff1c4259d7	93	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	94	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
Kojto	101:7cff1c4259d7	95	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	96	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
Kojto	101:7cff1c4259d7	97	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	98	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
Kojto	101:7cff1c4259d7	99	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
Kojto	101:7cff1c4259d7	100	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
Kojto	101:7cff1c4259d7	101	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
Kojto	101:7cff1c4259d7	102	((LIMIT) == ETH_BACKOFFLIMIT_1))
Kojto	101:7cff1c4259d7	103	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	104	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
Kojto	101:7cff1c4259d7	105	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	106	((CMD) == ETH_RECEIVEAll_DISABLE))
Kojto	101:7cff1c4259d7	107	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	108	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	109	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
Kojto	101:7cff1c4259d7	110	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
Kojto	101:7cff1c4259d7	111	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
Kojto	101:7cff1c4259d7	112	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
Kojto	101:7cff1c4259d7	113	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	114	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
Kojto	101:7cff1c4259d7	115	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
Kojto	101:7cff1c4259d7	116	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
Kojto	101:7cff1c4259d7	117	#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	118	((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
Kojto	101:7cff1c4259d7	119	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
Kojto	101:7cff1c4259d7	120	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
Kojto	101:7cff1c4259d7	121	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
Kojto	101:7cff1c4259d7	122	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
Kojto	101:7cff1c4259d7	123	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
Kojto	101:7cff1c4259d7	124	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
Kojto	101:7cff1c4259d7	125	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
Kojto	101:7cff1c4259d7	126	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
Kojto	101:7cff1c4259d7	127	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	128	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
Kojto	101:7cff1c4259d7	129	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
Kojto	101:7cff1c4259d7	130	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
Kojto	101:7cff1c4259d7	131	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
Kojto	101:7cff1c4259d7	132	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
Kojto	101:7cff1c4259d7	133	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	134	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
Kojto	101:7cff1c4259d7	135	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	136	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
Kojto	101:7cff1c4259d7	137	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	138	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
Kojto	101:7cff1c4259d7	139	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
Kojto	101:7cff1c4259d7	140	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
Kojto	101:7cff1c4259d7	141	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
Kojto	101:7cff1c4259d7	142	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
Kojto	101:7cff1c4259d7	143	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
Kojto	101:7cff1c4259d7	144	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
Kojto	101:7cff1c4259d7	145	((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto	101:7cff1c4259d7	146	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
Kojto	101:7cff1c4259d7	147	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
Kojto	101:7cff1c4259d7	148	((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto	101:7cff1c4259d7	149	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
Kojto	101:7cff1c4259d7	150	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
Kojto	101:7cff1c4259d7	151	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
Kojto	101:7cff1c4259d7	152	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
Kojto	101:7cff1c4259d7	153	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
Kojto	101:7cff1c4259d7	154	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
Kojto	101:7cff1c4259d7	155	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
Kojto	101:7cff1c4259d7	156	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
Kojto	101:7cff1c4259d7	157	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	158	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
Kojto	101:7cff1c4259d7	159	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	160	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
Kojto	101:7cff1c4259d7	161	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	162	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
Kojto	101:7cff1c4259d7	163	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	164	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
Kojto	101:7cff1c4259d7	165	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
Kojto	101:7cff1c4259d7	166	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
Kojto	101:7cff1c4259d7	167	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
Kojto	101:7cff1c4259d7	168	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
Kojto	101:7cff1c4259d7	169	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
Kojto	101:7cff1c4259d7	170	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
Kojto	101:7cff1c4259d7	171	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
Kojto	101:7cff1c4259d7	172	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
Kojto	101:7cff1c4259d7	173	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	174	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
Kojto	101:7cff1c4259d7	175	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	176	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
Kojto	101:7cff1c4259d7	177	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
Kojto	101:7cff1c4259d7	178	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
Kojto	101:7cff1c4259d7	179	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
Kojto	101:7cff1c4259d7	180	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
Kojto	101:7cff1c4259d7	181	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	182	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
Kojto	101:7cff1c4259d7	183	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	184	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
Kojto	101:7cff1c4259d7	185	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	186	((CMD) == ETH_FIXEDBURST_DISABLE))
Kojto	101:7cff1c4259d7	187	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
Kojto	101:7cff1c4259d7	188	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
Kojto	101:7cff1c4259d7	189	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
Kojto	101:7cff1c4259d7	190	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
Kojto	101:7cff1c4259d7	191	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
Kojto	101:7cff1c4259d7	192	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
Kojto	101:7cff1c4259d7	193	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
Kojto	101:7cff1c4259d7	194	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
Kojto	101:7cff1c4259d7	195	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
Kojto	101:7cff1c4259d7	196	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
Kojto	101:7cff1c4259d7	197	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
Kojto	101:7cff1c4259d7	198	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto	101:7cff1c4259d7	199	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
Kojto	101:7cff1c4259d7	200	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
Kojto	101:7cff1c4259d7	201	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
Kojto	101:7cff1c4259d7	202	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
Kojto	101:7cff1c4259d7	203	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
Kojto	101:7cff1c4259d7	204	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
Kojto	101:7cff1c4259d7	205	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
Kojto	101:7cff1c4259d7	206	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
Kojto	101:7cff1c4259d7	207	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
Kojto	101:7cff1c4259d7	208	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
Kojto	101:7cff1c4259d7	209	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
Kojto	101:7cff1c4259d7	210	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto	101:7cff1c4259d7	211	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
Kojto	101:7cff1c4259d7	212	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
Kojto	101:7cff1c4259d7	213	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
Kojto	101:7cff1c4259d7	214	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
Kojto	101:7cff1c4259d7	215	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
Kojto	101:7cff1c4259d7	216	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
Kojto	101:7cff1c4259d7	217	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
Kojto	101:7cff1c4259d7	218	((FLAG) == ETH_DMATXDESC_IC) \|\| \
Kojto	101:7cff1c4259d7	219	((FLAG) == ETH_DMATXDESC_LS) \|\| \
Kojto	101:7cff1c4259d7	220	((FLAG) == ETH_DMATXDESC_FS) \|\| \
Kojto	101:7cff1c4259d7	221	((FLAG) == ETH_DMATXDESC_DC) \|\| \
Kojto	101:7cff1c4259d7	222	((FLAG) == ETH_DMATXDESC_DP) \|\| \
Kojto	101:7cff1c4259d7	223	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
Kojto	101:7cff1c4259d7	224	((FLAG) == ETH_DMATXDESC_TER) \|\| \
Kojto	101:7cff1c4259d7	225	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
Kojto	101:7cff1c4259d7	226	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
Kojto	101:7cff1c4259d7	227	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
Kojto	101:7cff1c4259d7	228	((FLAG) == ETH_DMATXDESC_ES) \|\| \
Kojto	101:7cff1c4259d7	229	((FLAG) == ETH_DMATXDESC_JT) \|\| \
Kojto	101:7cff1c4259d7	230	((FLAG) == ETH_DMATXDESC_FF) \|\| \
Kojto	101:7cff1c4259d7	231	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
Kojto	101:7cff1c4259d7	232	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
Kojto	101:7cff1c4259d7	233	((FLAG) == ETH_DMATXDESC_NC) \|\| \
Kojto	101:7cff1c4259d7	234	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
Kojto	101:7cff1c4259d7	235	((FLAG) == ETH_DMATXDESC_EC) \|\| \
Kojto	101:7cff1c4259d7	236	((FLAG) == ETH_DMATXDESC_VF) \|\| \
Kojto	101:7cff1c4259d7	237	((FLAG) == ETH_DMATXDESC_CC) \|\| \
Kojto	101:7cff1c4259d7	238	((FLAG) == ETH_DMATXDESC_ED) \|\| \
Kojto	101:7cff1c4259d7	239	((FLAG) == ETH_DMATXDESC_UF) \|\| \
Kojto	101:7cff1c4259d7	240	((FLAG) == ETH_DMATXDESC_DB))
Kojto	101:7cff1c4259d7	241	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
Kojto	101:7cff1c4259d7	242	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
Kojto	101:7cff1c4259d7	243	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
Kojto	101:7cff1c4259d7	244	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
Kojto	101:7cff1c4259d7	245	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
Kojto	101:7cff1c4259d7	246	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
Kojto	101:7cff1c4259d7	247	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
Kojto	101:7cff1c4259d7	248	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
Kojto	101:7cff1c4259d7	249	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
Kojto	101:7cff1c4259d7	250	((FLAG) == ETH_DMARXDESC_ES) \|\| \
Kojto	101:7cff1c4259d7	251	((FLAG) == ETH_DMARXDESC_DE) \|\| \
Kojto	101:7cff1c4259d7	252	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
Kojto	101:7cff1c4259d7	253	((FLAG) == ETH_DMARXDESC_LE) \|\| \
Kojto	101:7cff1c4259d7	254	((FLAG) == ETH_DMARXDESC_OE) \|\| \
Kojto	101:7cff1c4259d7	255	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
Kojto	101:7cff1c4259d7	256	((FLAG) == ETH_DMARXDESC_FS) \|\| \
Kojto	101:7cff1c4259d7	257	((FLAG) == ETH_DMARXDESC_LS) \|\| \
Kojto	101:7cff1c4259d7	258	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
Kojto	101:7cff1c4259d7	259	((FLAG) == ETH_DMARXDESC_LC) \|\| \
Kojto	101:7cff1c4259d7	260	((FLAG) == ETH_DMARXDESC_FT) \|\| \
Kojto	101:7cff1c4259d7	261	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
Kojto	101:7cff1c4259d7	262	((FLAG) == ETH_DMARXDESC_RE) \|\| \
Kojto	101:7cff1c4259d7	263	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
Kojto	101:7cff1c4259d7	264	((FLAG) == ETH_DMARXDESC_CE) \|\| \
Kojto	101:7cff1c4259d7	265	((FLAG) == ETH_DMARXDESC_MAMPCE))
Kojto	101:7cff1c4259d7	266	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
Kojto	101:7cff1c4259d7	267	((BUFFER) == ETH_DMARXDESC_BUFFER2))
Kojto	101:7cff1c4259d7	268	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
Kojto	101:7cff1c4259d7	269	((FLAG) == ETH_PMT_FLAG_MPR))
Kojto	101:7cff1c4259d7	270	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
Kojto	101:7cff1c4259d7	271	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
Kojto	101:7cff1c4259d7	272	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
Kojto	101:7cff1c4259d7	273	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
Kojto	101:7cff1c4259d7	274	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
Kojto	101:7cff1c4259d7	275	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
Kojto	101:7cff1c4259d7	276	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
Kojto	101:7cff1c4259d7	277	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
Kojto	101:7cff1c4259d7	278	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
Kojto	101:7cff1c4259d7	279	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
Kojto	101:7cff1c4259d7	280	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
Kojto	101:7cff1c4259d7	281	((FLAG) == ETH_DMA_FLAG_T))
Kojto	101:7cff1c4259d7	282	#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
Kojto	101:7cff1c4259d7	283	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
Kojto	101:7cff1c4259d7	284	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
Kojto	101:7cff1c4259d7	285	((IT) == ETH_MAC_IT_PMT))
Kojto	101:7cff1c4259d7	286	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
Kojto	101:7cff1c4259d7	287	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
Kojto	101:7cff1c4259d7	288	((FLAG) == ETH_MAC_FLAG_PMT))
Kojto	101:7cff1c4259d7	289	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
Kojto	101:7cff1c4259d7	290	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
Kojto	101:7cff1c4259d7	291	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
Kojto	101:7cff1c4259d7	292	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
Kojto	101:7cff1c4259d7	293	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
Kojto	101:7cff1c4259d7	294	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
Kojto	101:7cff1c4259d7	295	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
Kojto	101:7cff1c4259d7	296	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
Kojto	101:7cff1c4259d7	297	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
Kojto	101:7cff1c4259d7	298	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
Kojto	101:7cff1c4259d7	299	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
Kojto	101:7cff1c4259d7	300	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
Kojto	101:7cff1c4259d7	301	#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) \|\| (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
Kojto	101:7cff1c4259d7	302	((IT) != 0x00))
Kojto	101:7cff1c4259d7	303	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
Kojto	101:7cff1c4259d7	304	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
Kojto	101:7cff1c4259d7	305	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
Kojto	101:7cff1c4259d7	306	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	307	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
Kojto	101:7cff1c4259d7	308
Kojto	101:7cff1c4259d7	309
Kojto	101:7cff1c4259d7	310	/**
Kojto	101:7cff1c4259d7	311	* @}
Kojto	101:7cff1c4259d7	312	*/
Kojto	101:7cff1c4259d7	313
Kojto	101:7cff1c4259d7	314	/** @addtogroup ETH_Private_Defines
Kojto	101:7cff1c4259d7	315	* @{
Kojto	101:7cff1c4259d7	316	*/
Kojto	101:7cff1c4259d7	317	/* Delay to wait when writing to some Ethernet registers */
Kojto	101:7cff1c4259d7	318	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	319
Kojto	101:7cff1c4259d7	320	/* ETHERNET Errors */
Kojto	101:7cff1c4259d7	321	#define ETH_SUCCESS ((uint32_t)0)
Kojto	101:7cff1c4259d7	322	#define ETH_ERROR ((uint32_t)1)
Kojto	101:7cff1c4259d7	323
Kojto	101:7cff1c4259d7	324	/* ETHERNET DMA Tx descriptors Collision Count Shift */
Kojto	101:7cff1c4259d7	325	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
Kojto	101:7cff1c4259d7	326
Kojto	101:7cff1c4259d7	327	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
Kojto	101:7cff1c4259d7	328	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto	101:7cff1c4259d7	329
Kojto	101:7cff1c4259d7	330	/* ETHERNET DMA Rx descriptors Frame Length Shift */
Kojto	101:7cff1c4259d7	331	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
Kojto	101:7cff1c4259d7	332
Kojto	101:7cff1c4259d7	333	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
Kojto	101:7cff1c4259d7	334	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto	101:7cff1c4259d7	335
Kojto	101:7cff1c4259d7	336	/* ETHERNET DMA Rx descriptors Frame length Shift */
Kojto	101:7cff1c4259d7	337	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
Kojto	101:7cff1c4259d7	338
Kojto	101:7cff1c4259d7	339	/* ETHERNET MAC address offsets */
Kojto	101:7cff1c4259d7	340	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
Kojto	101:7cff1c4259d7	341	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
Kojto	101:7cff1c4259d7	342
Kojto	101:7cff1c4259d7	343	/* ETHERNET MACMIIAR register Mask */
Kojto	101:7cff1c4259d7	344	#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
Kojto	101:7cff1c4259d7	345
Kojto	101:7cff1c4259d7	346	/* ETHERNET MACCR register Mask */
Kojto	101:7cff1c4259d7	347	#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
Kojto	101:7cff1c4259d7	348
Kojto	101:7cff1c4259d7	349	/* ETHERNET MACFCR register Mask */
Kojto	101:7cff1c4259d7	350	#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
Kojto	101:7cff1c4259d7	351
Kojto	101:7cff1c4259d7	352	/* ETHERNET DMAOMR register Mask */
Kojto	101:7cff1c4259d7	353	#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
Kojto	101:7cff1c4259d7	354
Kojto	101:7cff1c4259d7	355	/* ETHERNET Remote Wake-up frame register length */
Kojto	101:7cff1c4259d7	356	#define ETH_WAKEUP_REGISTER_LENGTH 8
Kojto	101:7cff1c4259d7	357
Kojto	101:7cff1c4259d7	358	/* ETHERNET Missed frames counter Shift */
Kojto	101:7cff1c4259d7	359	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
Kojto	101:7cff1c4259d7	360	/**
Kojto	101:7cff1c4259d7	361	* @}
Kojto	101:7cff1c4259d7	362	*/
Kojto	101:7cff1c4259d7	363
Kojto	101:7cff1c4259d7	364	/* Exported types ------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	365	/** @defgroup ETH_Exported_Types ETH Exported Types
Kojto	101:7cff1c4259d7	366	* @{
Kojto	101:7cff1c4259d7	367	*/
Kojto	101:7cff1c4259d7	368
Kojto	101:7cff1c4259d7	369	/**
Kojto	101:7cff1c4259d7	370	* @brief HAL State structures definition
Kojto	101:7cff1c4259d7	371	*/
Kojto	101:7cff1c4259d7	372	typedef enum
Kojto	101:7cff1c4259d7	373	{
Kojto	101:7cff1c4259d7	374	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
Kojto	101:7cff1c4259d7	375	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
Kojto	101:7cff1c4259d7	376	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
Kojto	101:7cff1c4259d7	377	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
Kojto	101:7cff1c4259d7	378	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
Kojto	101:7cff1c4259d7	379	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
Kojto	101:7cff1c4259d7	380	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
Kojto	101:7cff1c4259d7	381	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
Kojto	101:7cff1c4259d7	382	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
Kojto	101:7cff1c4259d7	383	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
Kojto	101:7cff1c4259d7	384	}HAL_ETH_StateTypeDef;
Kojto	101:7cff1c4259d7	385
Kojto	101:7cff1c4259d7	386	/**
Kojto	101:7cff1c4259d7	387	* @brief ETH Init Structure definition
Kojto	101:7cff1c4259d7	388	*/
Kojto	101:7cff1c4259d7	389
Kojto	101:7cff1c4259d7	390	typedef struct
Kojto	101:7cff1c4259d7	391	{
Kojto	101:7cff1c4259d7	392	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
Kojto	101:7cff1c4259d7	393	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
Kojto	101:7cff1c4259d7	394	and the mode (half/full-duplex).
Kojto	101:7cff1c4259d7	395	This parameter can be a value of @ref ETH_AutoNegotiation */
Kojto	101:7cff1c4259d7	396
Kojto	101:7cff1c4259d7	397	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
Kojto	101:7cff1c4259d7	398	This parameter can be a value of @ref ETH_Speed */
Kojto	101:7cff1c4259d7	399
Kojto	101:7cff1c4259d7	400	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
Kojto	101:7cff1c4259d7	401	This parameter can be a value of @ref ETH_Duplex_Mode */
Kojto	101:7cff1c4259d7	402
Kojto	101:7cff1c4259d7	403	uint16_t PhyAddress; /*!< Ethernet PHY address.
Kojto	101:7cff1c4259d7	404	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto	101:7cff1c4259d7	405
Kojto	101:7cff1c4259d7	406	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
Kojto	101:7cff1c4259d7	407
Kojto	101:7cff1c4259d7	408	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
Kojto	101:7cff1c4259d7	409	This parameter can be a value of @ref ETH_Rx_Mode */
Kojto	101:7cff1c4259d7	410
Kojto	101:7cff1c4259d7	411	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
Kojto	101:7cff1c4259d7	412	This parameter can be a value of @ref ETH_Checksum_Mode */
Kojto	101:7cff1c4259d7	413
Kojto	101:7cff1c4259d7	414	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
Kojto	101:7cff1c4259d7	415	This parameter can be a value of @ref ETH_Media_Interface */
Kojto	101:7cff1c4259d7	416
Kojto	101:7cff1c4259d7	417	} ETH_InitTypeDef;
Kojto	101:7cff1c4259d7	418
Kojto	101:7cff1c4259d7	419
Kojto	101:7cff1c4259d7	420	/**
Kojto	101:7cff1c4259d7	421	* @brief ETH MAC Configuration Structure definition
Kojto	101:7cff1c4259d7	422	*/
Kojto	101:7cff1c4259d7	423
Kojto	101:7cff1c4259d7	424	typedef struct
Kojto	101:7cff1c4259d7	425	{
Kojto	101:7cff1c4259d7	426	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
Kojto	101:7cff1c4259d7	427	When enabled, the MAC allows no more then 2048 bytes to be received.
Kojto	101:7cff1c4259d7	428	When disabled, the MAC can receive up to 16384 bytes.
Kojto	101:7cff1c4259d7	429	This parameter can be a value of @ref ETH_Watchdog */
Kojto	101:7cff1c4259d7	430
Kojto	101:7cff1c4259d7	431	uint32_t Jabber; /*!< Selects or not Jabber timer
Kojto	101:7cff1c4259d7	432	When enabled, the MAC allows no more then 2048 bytes to be sent.
Kojto	101:7cff1c4259d7	433	When disabled, the MAC can send up to 16384 bytes.
Kojto	101:7cff1c4259d7	434	This parameter can be a value of @ref ETH_Jabber */
Kojto	101:7cff1c4259d7	435
Kojto	101:7cff1c4259d7	436	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
Kojto	101:7cff1c4259d7	437	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
Kojto	101:7cff1c4259d7	438
Kojto	101:7cff1c4259d7	439	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
Kojto	101:7cff1c4259d7	440	This parameter can be a value of @ref ETH_Carrier_Sense */
Kojto	101:7cff1c4259d7	441
Kojto	101:7cff1c4259d7	442	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
Kojto	101:7cff1c4259d7	443	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
Kojto	101:7cff1c4259d7	444	in Half-Duplex mode.
Kojto	101:7cff1c4259d7	445	This parameter can be a value of @ref ETH_Receive_Own */
Kojto	101:7cff1c4259d7	446
Kojto	101:7cff1c4259d7	447	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
Kojto	101:7cff1c4259d7	448	This parameter can be a value of @ref ETH_Loop_Back_Mode */
Kojto	101:7cff1c4259d7	449
Kojto	101:7cff1c4259d7	450	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
Kojto	101:7cff1c4259d7	451	This parameter can be a value of @ref ETH_Checksum_Offload */
Kojto	101:7cff1c4259d7	452
Kojto	101:7cff1c4259d7	453	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
Kojto	101:7cff1c4259d7	454	when a collision occurs (Half-Duplex mode).
Kojto	101:7cff1c4259d7	455	This parameter can be a value of @ref ETH_Retry_Transmission */
Kojto	101:7cff1c4259d7	456
Kojto	101:7cff1c4259d7	457	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
Kojto	101:7cff1c4259d7	458	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
Kojto	101:7cff1c4259d7	459
Kojto	101:7cff1c4259d7	460	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
Kojto	101:7cff1c4259d7	461	This parameter can be a value of @ref ETH_Back_Off_Limit */
Kojto	101:7cff1c4259d7	462
Kojto	101:7cff1c4259d7	463	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
Kojto	101:7cff1c4259d7	464	This parameter can be a value of @ref ETH_Deferral_Check */
Kojto	101:7cff1c4259d7	465
Kojto	101:7cff1c4259d7	466	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
Kojto	101:7cff1c4259d7	467	This parameter can be a value of @ref ETH_Receive_All */
Kojto	101:7cff1c4259d7	468
Kojto	101:7cff1c4259d7	469	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
Kojto	101:7cff1c4259d7	470	This parameter can be a value of @ref ETH_Source_Addr_Filter */
Kojto	101:7cff1c4259d7	471
Kojto	101:7cff1c4259d7	472	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
Kojto	101:7cff1c4259d7	473	This parameter can be a value of @ref ETH_Pass_Control_Frames */
Kojto	101:7cff1c4259d7	474
Kojto	101:7cff1c4259d7	475	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
Kojto	101:7cff1c4259d7	476	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
Kojto	101:7cff1c4259d7	477
Kojto	101:7cff1c4259d7	478	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
Kojto	101:7cff1c4259d7	479	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
Kojto	101:7cff1c4259d7	480
Kojto	101:7cff1c4259d7	481	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
Kojto	101:7cff1c4259d7	482	This parameter can be a value of @ref ETH_Promiscuous_Mode */
Kojto	101:7cff1c4259d7	483
Kojto	101:7cff1c4259d7	484	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto	101:7cff1c4259d7	485	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
Kojto	101:7cff1c4259d7	486
Kojto	101:7cff1c4259d7	487	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto	101:7cff1c4259d7	488	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
Kojto	101:7cff1c4259d7	489
Kojto	101:7cff1c4259d7	490	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
Kojto	101:7cff1c4259d7	491	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto	101:7cff1c4259d7	492
Kojto	101:7cff1c4259d7	493	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
Kojto	101:7cff1c4259d7	494	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto	101:7cff1c4259d7	495
Kojto	101:7cff1c4259d7	496	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
Kojto	101:7cff1c4259d7	497	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
Kojto	101:7cff1c4259d7	498
Kojto	101:7cff1c4259d7	499	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
Kojto	101:7cff1c4259d7	500	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
Kojto	101:7cff1c4259d7	501
Kojto	101:7cff1c4259d7	502	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
Kojto	101:7cff1c4259d7	503	automatic retransmission of PAUSE Frame.
Kojto	101:7cff1c4259d7	504	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
Kojto	101:7cff1c4259d7	505
Kojto	101:7cff1c4259d7	506	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
Kojto	101:7cff1c4259d7	507	unicast address and unique multicast address).
Kojto	101:7cff1c4259d7	508	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
Kojto	101:7cff1c4259d7	509
Kojto	101:7cff1c4259d7	510	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
Kojto	101:7cff1c4259d7	511	disable its transmitter for a specified time (Pause Time)
Kojto	101:7cff1c4259d7	512	This parameter can be a value of @ref ETH_Receive_Flow_Control */
Kojto	101:7cff1c4259d7	513
Kojto	101:7cff1c4259d7	514	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
Kojto	101:7cff1c4259d7	515	or the MAC back-pressure operation (Half-Duplex mode)
Kojto	101:7cff1c4259d7	516	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
Kojto	101:7cff1c4259d7	517
Kojto	101:7cff1c4259d7	518	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
Kojto	101:7cff1c4259d7	519	comparison and filtering.
Kojto	101:7cff1c4259d7	520	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
Kojto	101:7cff1c4259d7	521
Kojto	101:7cff1c4259d7	522	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
Kojto	101:7cff1c4259d7	523
Kojto	101:7cff1c4259d7	524	} ETH_MACInitTypeDef;
Kojto	101:7cff1c4259d7	525
Kojto	101:7cff1c4259d7	526
Kojto	101:7cff1c4259d7	527	/**
Kojto	101:7cff1c4259d7	528	* @brief ETH DMA Configuration Structure definition
Kojto	101:7cff1c4259d7	529	*/
Kojto	101:7cff1c4259d7	530
Kojto	101:7cff1c4259d7	531	typedef struct
Kojto	101:7cff1c4259d7	532	{
Kojto	101:7cff1c4259d7	533	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
Kojto	101:7cff1c4259d7	534	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
Kojto	101:7cff1c4259d7	535
Kojto	101:7cff1c4259d7	536	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
Kojto	101:7cff1c4259d7	537	This parameter can be a value of @ref ETH_Receive_Store_Forward */
Kojto	101:7cff1c4259d7	538
Kojto	101:7cff1c4259d7	539	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
Kojto	101:7cff1c4259d7	540	This parameter can be a value of @ref ETH_Flush_Received_Frame */
Kojto	101:7cff1c4259d7	541
Kojto	101:7cff1c4259d7	542	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
Kojto	101:7cff1c4259d7	543	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
Kojto	101:7cff1c4259d7	544
Kojto	101:7cff1c4259d7	545	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
Kojto	101:7cff1c4259d7	546	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
Kojto	101:7cff1c4259d7	547
Kojto	101:7cff1c4259d7	548	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
Kojto	101:7cff1c4259d7	549	This parameter can be a value of @ref ETH_Forward_Error_Frames */
Kojto	101:7cff1c4259d7	550
Kojto	101:7cff1c4259d7	551	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
Kojto	101:7cff1c4259d7	552	and length less than 64 bytes) including pad-bytes and CRC)
Kojto	101:7cff1c4259d7	553	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
Kojto	101:7cff1c4259d7	554
Kojto	101:7cff1c4259d7	555	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
Kojto	101:7cff1c4259d7	556	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
Kojto	101:7cff1c4259d7	557
Kojto	101:7cff1c4259d7	558	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
Kojto	101:7cff1c4259d7	559	frame of Transmit data even before obtaining the status for the first frame.
Kojto	101:7cff1c4259d7	560	This parameter can be a value of @ref ETH_Second_Frame_Operate */
Kojto	101:7cff1c4259d7	561
Kojto	101:7cff1c4259d7	562	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
Kojto	101:7cff1c4259d7	563	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
Kojto	101:7cff1c4259d7	564
Kojto	101:7cff1c4259d7	565	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
Kojto	101:7cff1c4259d7	566	This parameter can be a value of @ref ETH_Fixed_Burst */
Kojto	101:7cff1c4259d7	567
Kojto	101:7cff1c4259d7	568	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
Kojto	101:7cff1c4259d7	569	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
Kojto	101:7cff1c4259d7	570
Kojto	101:7cff1c4259d7	571	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
Kojto	101:7cff1c4259d7	572	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
Kojto	101:7cff1c4259d7	573
Kojto	101:7cff1c4259d7	574	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
Kojto	101:7cff1c4259d7	575	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
Kojto	101:7cff1c4259d7	576
Kojto	101:7cff1c4259d7	577	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
Kojto	101:7cff1c4259d7	578	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto	101:7cff1c4259d7	579
Kojto	101:7cff1c4259d7	580	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
Kojto	101:7cff1c4259d7	581	This parameter can be a value of @ref ETH_DMA_Arbitration */
Kojto	101:7cff1c4259d7	582	} ETH_DMAInitTypeDef;
Kojto	101:7cff1c4259d7	583
Kojto	101:7cff1c4259d7	584
Kojto	101:7cff1c4259d7	585	/**
Kojto	101:7cff1c4259d7	586	* @brief ETH DMA Descriptors data structure definition
Kojto	101:7cff1c4259d7	587	*/
Kojto	101:7cff1c4259d7	588
Kojto	101:7cff1c4259d7	589	typedef struct
Kojto	101:7cff1c4259d7	590	{
Kojto	101:7cff1c4259d7	591	__IO uint32_t Status; /!< Status /
Kojto	101:7cff1c4259d7	592
Kojto	101:7cff1c4259d7	593	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
Kojto	101:7cff1c4259d7	594
Kojto	101:7cff1c4259d7	595	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
Kojto	101:7cff1c4259d7	596
Kojto	101:7cff1c4259d7	597	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
Kojto	101:7cff1c4259d7	598
Kojto	101:7cff1c4259d7	599	/!< Enhanced ETHERNET DMA PTP Descriptors /
Kojto	101:7cff1c4259d7	600	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
Kojto	101:7cff1c4259d7	601
Kojto	101:7cff1c4259d7	602	uint32_t Reserved1; /!< Reserved /
Kojto	101:7cff1c4259d7	603
Kojto	101:7cff1c4259d7	604	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
Kojto	101:7cff1c4259d7	605
Kojto	101:7cff1c4259d7	606	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
Kojto	101:7cff1c4259d7	607
Kojto	101:7cff1c4259d7	608	} ETH_DMADescTypeDef;
Kojto	101:7cff1c4259d7	609
Kojto	101:7cff1c4259d7	610
Kojto	101:7cff1c4259d7	611	/**
Kojto	101:7cff1c4259d7	612	* @brief Received Frame Informations structure definition
Kojto	101:7cff1c4259d7	613	*/
Kojto	101:7cff1c4259d7	614	typedef struct
Kojto	101:7cff1c4259d7	615	{
Kojto	101:7cff1c4259d7	616	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
Kojto	101:7cff1c4259d7	617
Kojto	101:7cff1c4259d7	618	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
Kojto	101:7cff1c4259d7	619
Kojto	101:7cff1c4259d7	620	uint32_t SegCount; /!< Segment count /
Kojto	101:7cff1c4259d7	621
Kojto	101:7cff1c4259d7	622	uint32_t length; /!< Frame length /
Kojto	101:7cff1c4259d7	623
Kojto	101:7cff1c4259d7	624	uint32_t buffer; /!< Frame buffer /
Kojto	101:7cff1c4259d7	625
Kojto	101:7cff1c4259d7	626	} ETH_DMARxFrameInfos;
Kojto	101:7cff1c4259d7	627
Kojto	101:7cff1c4259d7	628
Kojto	101:7cff1c4259d7	629	/**
Kojto	101:7cff1c4259d7	630	* @brief ETH Handle Structure definition
Kojto	101:7cff1c4259d7	631	*/
Kojto	101:7cff1c4259d7	632
Kojto	101:7cff1c4259d7	633	typedef struct
Kojto	101:7cff1c4259d7	634	{
Kojto	101:7cff1c4259d7	635	ETH_TypeDef Instance; /!< Register base address */
Kojto	101:7cff1c4259d7	636
Kojto	101:7cff1c4259d7	637	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
Kojto	101:7cff1c4259d7	638
Kojto	101:7cff1c4259d7	639	uint32_t LinkStatus; /!< Ethernet link status /
Kojto	101:7cff1c4259d7	640
Kojto	101:7cff1c4259d7	641	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
Kojto	101:7cff1c4259d7	642
Kojto	101:7cff1c4259d7	643	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
Kojto	101:7cff1c4259d7	644
Kojto	101:7cff1c4259d7	645	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
Kojto	101:7cff1c4259d7	646
Kojto	101:7cff1c4259d7	647	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
Kojto	101:7cff1c4259d7	648
Kojto	101:7cff1c4259d7	649	HAL_LockTypeDef Lock; /!< ETH Lock /
Kojto	101:7cff1c4259d7	650
Kojto	101:7cff1c4259d7	651	} ETH_HandleTypeDef;
Kojto	101:7cff1c4259d7	652
Kojto	101:7cff1c4259d7	653	/**
Kojto	101:7cff1c4259d7	654	* @}
Kojto	101:7cff1c4259d7	655	*/
Kojto	101:7cff1c4259d7	656
Kojto	101:7cff1c4259d7	657	/* Exported constants --------------------------------------------------------*/
Kojto	101:7cff1c4259d7	658	/** @defgroup ETH_Exported_Constants ETH Exported Constants
Kojto	101:7cff1c4259d7	659	* @{
Kojto	101:7cff1c4259d7	660	*/
Kojto	101:7cff1c4259d7	661
Kojto	101:7cff1c4259d7	662	/** @defgroup ETH_Buffers_setting ETH Buffers setting
Kojto	101:7cff1c4259d7	663	* @{
Kojto	101:7cff1c4259d7	664	*/
Kojto	101:7cff1c4259d7	665	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC /
Kojto	101:7cff1c4259d7	666	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
Kojto	101:7cff1c4259d7	667	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
Kojto	101:7cff1c4259d7	668	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
Kojto	101:7cff1c4259d7	669	#define ETH_VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
Kojto	101:7cff1c4259d7	670	#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
Kojto	101:7cff1c4259d7	671	#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
Kojto	101:7cff1c4259d7	672	#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
Kojto	101:7cff1c4259d7	673
Kojto	101:7cff1c4259d7	674	/* Ethernet driver receive buffers are organized in a chained linked-list, when
Kojto	101:7cff1c4259d7	675	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
Kojto	101:7cff1c4259d7	676	to the driver receive buffers memory.
Kojto	101:7cff1c4259d7	677
Kojto	101:7cff1c4259d7	678	Depending on the size of the received ethernet packet and the size of
Kojto	101:7cff1c4259d7	679	each ethernet driver receive buffer, the received packet can take one or more
Kojto	101:7cff1c4259d7	680	ethernet driver receive buffer.
Kojto	101:7cff1c4259d7	681
Kojto	101:7cff1c4259d7	682	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
Kojto	101:7cff1c4259d7	683	and the total count of the driver receive buffers ETH_RXBUFNB.
Kojto	101:7cff1c4259d7	684
Kojto	101:7cff1c4259d7	685	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
Kojto	101:7cff1c4259d7	686	example, they can be reconfigured in the application layer to fit the application
Kojto	101:7cff1c4259d7	687	needs */
Kojto	101:7cff1c4259d7	688
Kojto	101:7cff1c4259d7	689	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
Kojto	101:7cff1c4259d7	690	packet */
Kojto	101:7cff1c4259d7	691	#ifndef ETH_RX_BUF_SIZE
Kojto	101:7cff1c4259d7	692	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto	101:7cff1c4259d7	693	#endif
Kojto	101:7cff1c4259d7	694
Kojto	101:7cff1c4259d7	695	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
Kojto	101:7cff1c4259d7	696	#ifndef ETH_RXBUFNB
Kojto	101:7cff1c4259d7	697	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
Kojto	101:7cff1c4259d7	698	#endif
Kojto	101:7cff1c4259d7	699
Kojto	101:7cff1c4259d7	700
Kojto	101:7cff1c4259d7	701	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
Kojto	101:7cff1c4259d7	702	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
Kojto	101:7cff1c4259d7	703	driver transmit buffers memory to the TxFIFO.
Kojto	101:7cff1c4259d7	704
Kojto	101:7cff1c4259d7	705	Depending on the size of the Ethernet packet to be transmitted and the size of
Kojto	101:7cff1c4259d7	706	each ethernet driver transmit buffer, the packet to be transmitted can take
Kojto	101:7cff1c4259d7	707	one or more ethernet driver transmit buffer.
Kojto	101:7cff1c4259d7	708
Kojto	101:7cff1c4259d7	709	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
Kojto	101:7cff1c4259d7	710	and the total count of the driver transmit buffers ETH_TXBUFNB.
Kojto	101:7cff1c4259d7	711
Kojto	101:7cff1c4259d7	712	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
Kojto	101:7cff1c4259d7	713	example, they can be reconfigured in the application layer to fit the application
Kojto	101:7cff1c4259d7	714	needs */
Kojto	101:7cff1c4259d7	715
Kojto	101:7cff1c4259d7	716	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
Kojto	101:7cff1c4259d7	717	packet */
Kojto	101:7cff1c4259d7	718	#ifndef ETH_TX_BUF_SIZE
Kojto	101:7cff1c4259d7	719	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto	101:7cff1c4259d7	720	#endif
Kojto	101:7cff1c4259d7	721
Kojto	101:7cff1c4259d7	722	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
Kojto	101:7cff1c4259d7	723	#ifndef ETH_TXBUFNB
Kojto	101:7cff1c4259d7	724	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
Kojto	101:7cff1c4259d7	725	#endif
Kojto	101:7cff1c4259d7	726
Kojto	101:7cff1c4259d7	727	/**
Kojto	101:7cff1c4259d7	728	* @}
Kojto	101:7cff1c4259d7	729	*/
Kojto	101:7cff1c4259d7	730
Kojto	101:7cff1c4259d7	731	/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
Kojto	101:7cff1c4259d7	732	* @{
Kojto	101:7cff1c4259d7	733	*/
Kojto	101:7cff1c4259d7	734
Kojto	101:7cff1c4259d7	735	/*
Kojto	101:7cff1c4259d7	736	DMA Tx Descriptor
Kojto	101:7cff1c4259d7	737	-----------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	738	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
Kojto	101:7cff1c4259d7	739	-----------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	740	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
Kojto	101:7cff1c4259d7	741	-----------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	742	TDES2 \| Buffer1 Address [31:0] \|
Kojto	101:7cff1c4259d7	743	-----------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	744	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
Kojto	101:7cff1c4259d7	745	-----------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	746	*/
Kojto	101:7cff1c4259d7	747
Kojto	101:7cff1c4259d7	748	/**
Kojto	101:7cff1c4259d7	749	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
Kojto	101:7cff1c4259d7	750	*/
Kojto	101:7cff1c4259d7	751	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
Kojto	101:7cff1c4259d7	752	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
Kojto	101:7cff1c4259d7	753	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
Kojto	101:7cff1c4259d7	754	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
Kojto	101:7cff1c4259d7	755	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
Kojto	101:7cff1c4259d7	756	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
Kojto	101:7cff1c4259d7	757	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
Kojto	101:7cff1c4259d7	758	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
Kojto	101:7cff1c4259d7	759	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
Kojto	101:7cff1c4259d7	760	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
Kojto	101:7cff1c4259d7	761	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
Kojto	101:7cff1c4259d7	762	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
Kojto	101:7cff1c4259d7	763	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
Kojto	101:7cff1c4259d7	764	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
Kojto	101:7cff1c4259d7	765	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
Kojto	101:7cff1c4259d7	766	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
Kojto	101:7cff1c4259d7	767	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
Kojto	101:7cff1c4259d7	768	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
Kojto	101:7cff1c4259d7	769	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
Kojto	101:7cff1c4259d7	770	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
Kojto	101:7cff1c4259d7	771	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
Kojto	101:7cff1c4259d7	772	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
Kojto	101:7cff1c4259d7	773	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
Kojto	101:7cff1c4259d7	774	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
Kojto	101:7cff1c4259d7	775	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
Kojto	101:7cff1c4259d7	776	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
Kojto	101:7cff1c4259d7	777	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
Kojto	101:7cff1c4259d7	778	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
Kojto	101:7cff1c4259d7	779	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
Kojto	101:7cff1c4259d7	780
Kojto	101:7cff1c4259d7	781	/**
Kojto	101:7cff1c4259d7	782	* @brief Bit definition of TDES1 register
Kojto	101:7cff1c4259d7	783	*/
Kojto	101:7cff1c4259d7	784	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
Kojto	101:7cff1c4259d7	785	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
Kojto	101:7cff1c4259d7	786
Kojto	101:7cff1c4259d7	787	/**
Kojto	101:7cff1c4259d7	788	* @brief Bit definition of TDES2 register
Kojto	101:7cff1c4259d7	789	*/
Kojto	101:7cff1c4259d7	790	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
Kojto	101:7cff1c4259d7	791
Kojto	101:7cff1c4259d7	792	/**
Kojto	101:7cff1c4259d7	793	* @brief Bit definition of TDES3 register
Kojto	101:7cff1c4259d7	794	*/
Kojto	101:7cff1c4259d7	795	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
Kojto	101:7cff1c4259d7	796
Kojto	101:7cff1c4259d7	797	/*---------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	798	TDES6 \| Transmit Time Stamp Low [31:0] \|
Kojto	101:7cff1c4259d7	799	-----------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	800	TDES7 \| Transmit Time Stamp High [31:0] \|
Kojto	101:7cff1c4259d7	801	----------------------------------------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	802
Kojto	101:7cff1c4259d7	803	/* Bit definition of TDES6 register */
Kojto	101:7cff1c4259d7	804	#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
Kojto	101:7cff1c4259d7	805
Kojto	101:7cff1c4259d7	806	/* Bit definition of TDES7 register */
Kojto	101:7cff1c4259d7	807	#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
Kojto	101:7cff1c4259d7	808
Kojto	101:7cff1c4259d7	809	/**
Kojto	101:7cff1c4259d7	810	* @}
Kojto	101:7cff1c4259d7	811	*/
Kojto	101:7cff1c4259d7	812	/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
Kojto	101:7cff1c4259d7	813	* @{
Kojto	101:7cff1c4259d7	814	*/
Kojto	101:7cff1c4259d7	815
Kojto	101:7cff1c4259d7	816	/*
Kojto	101:7cff1c4259d7	817	DMA Rx Descriptor
Kojto	101:7cff1c4259d7	818	--------------------------------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	819	RDES0 \| OWN(31) \| Status [30:0] \|
Kojto	101:7cff1c4259d7	820	---------------------------------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	821	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
Kojto	101:7cff1c4259d7	822	---------------------------------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	823	RDES2 \| Buffer1 Address [31:0] \|
Kojto	101:7cff1c4259d7	824	---------------------------------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	825	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
Kojto	101:7cff1c4259d7	826	---------------------------------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	827	*/
Kojto	101:7cff1c4259d7	828
Kojto	101:7cff1c4259d7	829	/**
Kojto	101:7cff1c4259d7	830	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
Kojto	101:7cff1c4259d7	831	*/
Kojto	101:7cff1c4259d7	832	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
Kojto	101:7cff1c4259d7	833	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
Kojto	101:7cff1c4259d7	834	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
Kojto	101:7cff1c4259d7	835	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
Kojto	101:7cff1c4259d7	836	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
Kojto	101:7cff1c4259d7	837	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
Kojto	101:7cff1c4259d7	838	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
Kojto	101:7cff1c4259d7	839	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
Kojto	101:7cff1c4259d7	840	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
Kojto	101:7cff1c4259d7	841	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
Kojto	101:7cff1c4259d7	842	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
Kojto	101:7cff1c4259d7	843	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
Kojto	101:7cff1c4259d7	844	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
Kojto	101:7cff1c4259d7	845	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
Kojto	101:7cff1c4259d7	846	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
Kojto	101:7cff1c4259d7	847	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
Kojto	101:7cff1c4259d7	848	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
Kojto	101:7cff1c4259d7	849	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
Kojto	101:7cff1c4259d7	850	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
Kojto	101:7cff1c4259d7	851
Kojto	101:7cff1c4259d7	852	/**
Kojto	101:7cff1c4259d7	853	* @brief Bit definition of RDES1 register
Kojto	101:7cff1c4259d7	854	*/
Kojto	101:7cff1c4259d7	855	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
Kojto	101:7cff1c4259d7	856	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
Kojto	101:7cff1c4259d7	857	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
Kojto	101:7cff1c4259d7	858	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
Kojto	101:7cff1c4259d7	859	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
Kojto	101:7cff1c4259d7	860
Kojto	101:7cff1c4259d7	861	/**
Kojto	101:7cff1c4259d7	862	* @brief Bit definition of RDES2 register
Kojto	101:7cff1c4259d7	863	*/
Kojto	101:7cff1c4259d7	864	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
Kojto	101:7cff1c4259d7	865
Kojto	101:7cff1c4259d7	866	/**
Kojto	101:7cff1c4259d7	867	* @brief Bit definition of RDES3 register
Kojto	101:7cff1c4259d7	868	*/
Kojto	101:7cff1c4259d7	869	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
Kojto	101:7cff1c4259d7	870
Kojto	101:7cff1c4259d7	871	/*---------------------------------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	872	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
Kojto	101:7cff1c4259d7	873	---------------------------------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	874	RDES5 \| Reserved[31:0] \|
Kojto	101:7cff1c4259d7	875	---------------------------------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	876	RDES6 \| Receive Time Stamp Low [31:0] \|
Kojto	101:7cff1c4259d7	877	---------------------------------------------------------------------------------------------------------------------
Kojto	101:7cff1c4259d7	878	RDES7 \| Receive Time Stamp High [31:0] \|
Kojto	101:7cff1c4259d7	879	--------------------------------------------------------------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	880
Kojto	101:7cff1c4259d7	881	/* Bit definition of RDES4 register */
Kojto	101:7cff1c4259d7	882	#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
Kojto	101:7cff1c4259d7	883	#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
Kojto	101:7cff1c4259d7	884	#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
Kojto	101:7cff1c4259d7	885	#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
Kojto	101:7cff1c4259d7	886	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
Kojto	101:7cff1c4259d7	887	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
Kojto	101:7cff1c4259d7	888	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
Kojto	101:7cff1c4259d7	889	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
Kojto	101:7cff1c4259d7	890	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
Kojto	101:7cff1c4259d7	891	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
Kojto	101:7cff1c4259d7	892	#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
Kojto	101:7cff1c4259d7	893	#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
Kojto	101:7cff1c4259d7	894	#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
Kojto	101:7cff1c4259d7	895	#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
Kojto	101:7cff1c4259d7	896	#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
Kojto	101:7cff1c4259d7	897	#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
Kojto	101:7cff1c4259d7	898	#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
Kojto	101:7cff1c4259d7	899	#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
Kojto	101:7cff1c4259d7	900	#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
Kojto	101:7cff1c4259d7	901
Kojto	101:7cff1c4259d7	902	/* Bit definition of RDES6 register */
Kojto	101:7cff1c4259d7	903	#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
Kojto	101:7cff1c4259d7	904
Kojto	101:7cff1c4259d7	905	/* Bit definition of RDES7 register */
Kojto	101:7cff1c4259d7	906	#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
Kojto	101:7cff1c4259d7	907	/**
Kojto	101:7cff1c4259d7	908	* @}
Kojto	101:7cff1c4259d7	909	*/
Kojto	101:7cff1c4259d7	910	/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
Kojto	101:7cff1c4259d7	911	* @{
Kojto	101:7cff1c4259d7	912	*/
Kojto	101:7cff1c4259d7	913	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	914	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	915
Kojto	101:7cff1c4259d7	916	/**
Kojto	101:7cff1c4259d7	917	* @}
Kojto	101:7cff1c4259d7	918	*/
Kojto	101:7cff1c4259d7	919	/** @defgroup ETH_Speed ETH Speed
Kojto	101:7cff1c4259d7	920	* @{
Kojto	101:7cff1c4259d7	921	*/
Kojto	101:7cff1c4259d7	922	#define ETH_SPEED_10M ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	923	#define ETH_SPEED_100M ((uint32_t)0x00004000)
Kojto	101:7cff1c4259d7	924
Kojto	101:7cff1c4259d7	925	/**
Kojto	101:7cff1c4259d7	926	* @}
Kojto	101:7cff1c4259d7	927	*/
Kojto	101:7cff1c4259d7	928	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
Kojto	101:7cff1c4259d7	929	* @{
Kojto	101:7cff1c4259d7	930	*/
Kojto	101:7cff1c4259d7	931	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
Kojto	101:7cff1c4259d7	932	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	933	/**
Kojto	101:7cff1c4259d7	934	* @}
Kojto	101:7cff1c4259d7	935	*/
Kojto	101:7cff1c4259d7	936	/** @defgroup ETH_Rx_Mode ETH Rx Mode
Kojto	101:7cff1c4259d7	937	* @{
Kojto	101:7cff1c4259d7	938	*/
Kojto	101:7cff1c4259d7	939	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	940	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	941	/**
Kojto	101:7cff1c4259d7	942	* @}
Kojto	101:7cff1c4259d7	943	*/
Kojto	101:7cff1c4259d7	944
Kojto	101:7cff1c4259d7	945	/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
Kojto	101:7cff1c4259d7	946	* @{
Kojto	101:7cff1c4259d7	947	*/
Kojto	101:7cff1c4259d7	948	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	949	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	950	/**
Kojto	101:7cff1c4259d7	951	* @}
Kojto	101:7cff1c4259d7	952	*/
Kojto	101:7cff1c4259d7	953
Kojto	101:7cff1c4259d7	954	/** @defgroup ETH_Media_Interface ETH Media Interface
Kojto	101:7cff1c4259d7	955	* @{
Kojto	101:7cff1c4259d7	956	*/
Kojto	101:7cff1c4259d7	957	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	958	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
Kojto	101:7cff1c4259d7	959	/**
Kojto	101:7cff1c4259d7	960	* @}
Kojto	101:7cff1c4259d7	961	*/
Kojto	101:7cff1c4259d7	962
Kojto	101:7cff1c4259d7	963	/** @defgroup ETH_Watchdog ETH Watchdog
Kojto	101:7cff1c4259d7	964	* @{
Kojto	101:7cff1c4259d7	965	*/
Kojto	101:7cff1c4259d7	966	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	967	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
Kojto	101:7cff1c4259d7	968	/**
Kojto	101:7cff1c4259d7	969	* @}
Kojto	101:7cff1c4259d7	970	*/
Kojto	101:7cff1c4259d7	971
Kojto	101:7cff1c4259d7	972	/** @defgroup ETH_Jabber ETH Jabber
Kojto	101:7cff1c4259d7	973	* @{
Kojto	101:7cff1c4259d7	974	*/
Kojto	101:7cff1c4259d7	975	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	976	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
Kojto	101:7cff1c4259d7	977	/**
Kojto	101:7cff1c4259d7	978	* @}
Kojto	101:7cff1c4259d7	979	*/
Kojto	101:7cff1c4259d7	980
Kojto	101:7cff1c4259d7	981	/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
Kojto	101:7cff1c4259d7	982	* @{
Kojto	101:7cff1c4259d7	983	*/
Kojto	101:7cff1c4259d7	984	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
Kojto	101:7cff1c4259d7	985	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
Kojto	101:7cff1c4259d7	986	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
Kojto	101:7cff1c4259d7	987	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
Kojto	101:7cff1c4259d7	988	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
Kojto	101:7cff1c4259d7	989	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
Kojto	101:7cff1c4259d7	990	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
Kojto	101:7cff1c4259d7	991	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
Kojto	101:7cff1c4259d7	992	/**
Kojto	101:7cff1c4259d7	993	* @}
Kojto	101:7cff1c4259d7	994	*/
Kojto	101:7cff1c4259d7	995
Kojto	101:7cff1c4259d7	996	/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
Kojto	101:7cff1c4259d7	997	* @{
Kojto	101:7cff1c4259d7	998	*/
Kojto	101:7cff1c4259d7	999	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1000	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
Kojto	101:7cff1c4259d7	1001	/**
Kojto	101:7cff1c4259d7	1002	* @}
Kojto	101:7cff1c4259d7	1003	*/
Kojto	101:7cff1c4259d7	1004
Kojto	101:7cff1c4259d7	1005	/** @defgroup ETH_Receive_Own ETH Receive Own
Kojto	101:7cff1c4259d7	1006	* @{
Kojto	101:7cff1c4259d7	1007	*/
Kojto	101:7cff1c4259d7	1008	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1009	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
Kojto	101:7cff1c4259d7	1010	/**
Kojto	101:7cff1c4259d7	1011	* @}
Kojto	101:7cff1c4259d7	1012	*/
Kojto	101:7cff1c4259d7	1013
Kojto	101:7cff1c4259d7	1014	/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
Kojto	101:7cff1c4259d7	1015	* @{
Kojto	101:7cff1c4259d7	1016	*/
Kojto	101:7cff1c4259d7	1017	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
Kojto	101:7cff1c4259d7	1018	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1019	/**
Kojto	101:7cff1c4259d7	1020	* @}
Kojto	101:7cff1c4259d7	1021	*/
Kojto	101:7cff1c4259d7	1022
Kojto	101:7cff1c4259d7	1023	/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
Kojto	101:7cff1c4259d7	1024	* @{
Kojto	101:7cff1c4259d7	1025	*/
Kojto	101:7cff1c4259d7	1026	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
Kojto	101:7cff1c4259d7	1027	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1028	/**
Kojto	101:7cff1c4259d7	1029	* @}
Kojto	101:7cff1c4259d7	1030	*/
Kojto	101:7cff1c4259d7	1031
Kojto	101:7cff1c4259d7	1032	/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
Kojto	101:7cff1c4259d7	1033	* @{
Kojto	101:7cff1c4259d7	1034	*/
Kojto	101:7cff1c4259d7	1035	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1036	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
Kojto	101:7cff1c4259d7	1037	/**
Kojto	101:7cff1c4259d7	1038	* @}
Kojto	101:7cff1c4259d7	1039	*/
Kojto	101:7cff1c4259d7	1040
Kojto	101:7cff1c4259d7	1041	/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
Kojto	101:7cff1c4259d7	1042	* @{
Kojto	101:7cff1c4259d7	1043	*/
Kojto	101:7cff1c4259d7	1044	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
Kojto	101:7cff1c4259d7	1045	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1046	/**
Kojto	101:7cff1c4259d7	1047	* @}
Kojto	101:7cff1c4259d7	1048	*/
Kojto	101:7cff1c4259d7	1049
Kojto	101:7cff1c4259d7	1050	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
Kojto	101:7cff1c4259d7	1051	* @{
Kojto	101:7cff1c4259d7	1052	*/
Kojto	101:7cff1c4259d7	1053	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1054	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
Kojto	101:7cff1c4259d7	1055	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
Kojto	101:7cff1c4259d7	1056	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
Kojto	101:7cff1c4259d7	1057	/**
Kojto	101:7cff1c4259d7	1058	* @}
Kojto	101:7cff1c4259d7	1059	*/
Kojto	101:7cff1c4259d7	1060
Kojto	101:7cff1c4259d7	1061	/** @defgroup ETH_Deferral_Check ETH Deferral Check
Kojto	101:7cff1c4259d7	1062	* @{
Kojto	101:7cff1c4259d7	1063	*/
Kojto	101:7cff1c4259d7	1064	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	1065	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1066	/**
Kojto	101:7cff1c4259d7	1067	* @}
Kojto	101:7cff1c4259d7	1068	*/
Kojto	101:7cff1c4259d7	1069
Kojto	101:7cff1c4259d7	1070	/** @defgroup ETH_Receive_All ETH Receive All
Kojto	101:7cff1c4259d7	1071	* @{
Kojto	101:7cff1c4259d7	1072	*/
Kojto	101:7cff1c4259d7	1073	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
Kojto	101:7cff1c4259d7	1074	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1075	/**
Kojto	101:7cff1c4259d7	1076	* @}
Kojto	101:7cff1c4259d7	1077	*/
Kojto	101:7cff1c4259d7	1078
Kojto	101:7cff1c4259d7	1079	/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
Kojto	101:7cff1c4259d7	1080	* @{
Kojto	101:7cff1c4259d7	1081	*/
Kojto	101:7cff1c4259d7	1082	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
Kojto	101:7cff1c4259d7	1083	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
Kojto	101:7cff1c4259d7	1084	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1085	/**
Kojto	101:7cff1c4259d7	1086	* @}
Kojto	101:7cff1c4259d7	1087	*/
Kojto	101:7cff1c4259d7	1088
Kojto	101:7cff1c4259d7	1089	/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
Kojto	101:7cff1c4259d7	1090	* @{
Kojto	101:7cff1c4259d7	1091	*/
Kojto	101:7cff1c4259d7	1092	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
Kojto	101:7cff1c4259d7	1093	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
Kojto	101:7cff1c4259d7	1094	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
Kojto	101:7cff1c4259d7	1095	/**
Kojto	101:7cff1c4259d7	1096	* @}
Kojto	101:7cff1c4259d7	1097	*/
Kojto	101:7cff1c4259d7	1098
Kojto	101:7cff1c4259d7	1099	/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
Kojto	101:7cff1c4259d7	1100	* @{
Kojto	101:7cff1c4259d7	1101	*/
Kojto	101:7cff1c4259d7	1102	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1103	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
Kojto	101:7cff1c4259d7	1104	/**
Kojto	101:7cff1c4259d7	1105	* @}
Kojto	101:7cff1c4259d7	1106	*/
Kojto	101:7cff1c4259d7	1107
Kojto	101:7cff1c4259d7	1108	/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
Kojto	101:7cff1c4259d7	1109	* @{
Kojto	101:7cff1c4259d7	1110	*/
Kojto	101:7cff1c4259d7	1111	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1112	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	1113	/**
Kojto	101:7cff1c4259d7	1114	* @}
Kojto	101:7cff1c4259d7	1115	*/
Kojto	101:7cff1c4259d7	1116
Kojto	101:7cff1c4259d7	1117	/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
Kojto	101:7cff1c4259d7	1118	* @{
Kojto	101:7cff1c4259d7	1119	*/
Kojto	101:7cff1c4259d7	1120	#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
Kojto	101:7cff1c4259d7	1121	#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1122	/**
Kojto	101:7cff1c4259d7	1123	* @}
Kojto	101:7cff1c4259d7	1124	*/
Kojto	101:7cff1c4259d7	1125
Kojto	101:7cff1c4259d7	1126	/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
Kojto	101:7cff1c4259d7	1127	* @{
Kojto	101:7cff1c4259d7	1128	*/
Kojto	101:7cff1c4259d7	1129	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
Kojto	101:7cff1c4259d7	1130	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	1131	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1132	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	1133	/**
Kojto	101:7cff1c4259d7	1134	* @}
Kojto	101:7cff1c4259d7	1135	*/
Kojto	101:7cff1c4259d7	1136
Kojto	101:7cff1c4259d7	1137	/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
Kojto	101:7cff1c4259d7	1138	* @{
Kojto	101:7cff1c4259d7	1139	*/
Kojto	101:7cff1c4259d7	1140	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
Kojto	101:7cff1c4259d7	1141	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	1142	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1143	/**
Kojto	101:7cff1c4259d7	1144	* @}
Kojto	101:7cff1c4259d7	1145	*/
Kojto	101:7cff1c4259d7	1146
Kojto	101:7cff1c4259d7	1147	/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
Kojto	101:7cff1c4259d7	1148	* @{
Kojto	101:7cff1c4259d7	1149	*/
Kojto	101:7cff1c4259d7	1150	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1151	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
Kojto	101:7cff1c4259d7	1152	/**
Kojto	101:7cff1c4259d7	1153	* @}
Kojto	101:7cff1c4259d7	1154	*/
Kojto	101:7cff1c4259d7	1155
Kojto	101:7cff1c4259d7	1156	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
Kojto	101:7cff1c4259d7	1157	* @{
Kojto	101:7cff1c4259d7	1158	*/
Kojto	101:7cff1c4259d7	1159	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
Kojto	101:7cff1c4259d7	1160	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
Kojto	101:7cff1c4259d7	1161	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
Kojto	101:7cff1c4259d7	1162	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
Kojto	101:7cff1c4259d7	1163	/**
Kojto	101:7cff1c4259d7	1164	* @}
Kojto	101:7cff1c4259d7	1165	*/
Kojto	101:7cff1c4259d7	1166
Kojto	101:7cff1c4259d7	1167	/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
Kojto	101:7cff1c4259d7	1168	* @{
Kojto	101:7cff1c4259d7	1169	*/
Kojto	101:7cff1c4259d7	1170	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	1171	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1172	/**
Kojto	101:7cff1c4259d7	1173	* @}
Kojto	101:7cff1c4259d7	1174	*/
Kojto	101:7cff1c4259d7	1175
Kojto	101:7cff1c4259d7	1176	/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
Kojto	101:7cff1c4259d7	1177	* @{
Kojto	101:7cff1c4259d7	1178	*/
Kojto	101:7cff1c4259d7	1179	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	1180	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1181	/**
Kojto	101:7cff1c4259d7	1182	* @}
Kojto	101:7cff1c4259d7	1183	*/
Kojto	101:7cff1c4259d7	1184
Kojto	101:7cff1c4259d7	1185	/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
Kojto	101:7cff1c4259d7	1186	* @{
Kojto	101:7cff1c4259d7	1187	*/
Kojto	101:7cff1c4259d7	1188	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	1189	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1190	/**
Kojto	101:7cff1c4259d7	1191	* @}
Kojto	101:7cff1c4259d7	1192	*/
Kojto	101:7cff1c4259d7	1193
Kojto	101:7cff1c4259d7	1194	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
Kojto	101:7cff1c4259d7	1195	* @{
Kojto	101:7cff1c4259d7	1196	*/
Kojto	101:7cff1c4259d7	1197	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
Kojto	101:7cff1c4259d7	1198	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1199	/**
Kojto	101:7cff1c4259d7	1200	* @}
Kojto	101:7cff1c4259d7	1201	*/
Kojto	101:7cff1c4259d7	1202
Kojto	101:7cff1c4259d7	1203	/** @defgroup ETH_MAC_addresses ETH MAC addresses
Kojto	101:7cff1c4259d7	1204	* @{
Kojto	101:7cff1c4259d7	1205	*/
Kojto	101:7cff1c4259d7	1206	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1207	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	1208	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
Kojto	101:7cff1c4259d7	1209	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
Kojto	101:7cff1c4259d7	1210	/**
Kojto	101:7cff1c4259d7	1211	* @}
Kojto	101:7cff1c4259d7	1212	*/
Kojto	101:7cff1c4259d7	1213
Kojto	101:7cff1c4259d7	1214	/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
Kojto	101:7cff1c4259d7	1215	* @{
Kojto	101:7cff1c4259d7	1216	*/
Kojto	101:7cff1c4259d7	1217	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1218	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
Kojto	101:7cff1c4259d7	1219	/**
Kojto	101:7cff1c4259d7	1220	* @}
Kojto	101:7cff1c4259d7	1221	*/
Kojto	101:7cff1c4259d7	1222
Kojto	101:7cff1c4259d7	1223	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
Kojto	101:7cff1c4259d7	1224	* @{
Kojto	101:7cff1c4259d7	1225	*/
Kojto	101:7cff1c4259d7	1226	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
Kojto	101:7cff1c4259d7	1227	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
Kojto	101:7cff1c4259d7	1228	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
Kojto	101:7cff1c4259d7	1229	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
Kojto	101:7cff1c4259d7	1230	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
Kojto	101:7cff1c4259d7	1231	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
Kojto	101:7cff1c4259d7	1232	/**
Kojto	101:7cff1c4259d7	1233	* @}
Kojto	101:7cff1c4259d7	1234	*/
Kojto	101:7cff1c4259d7	1235
Kojto	101:7cff1c4259d7	1236	/** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
Kojto	101:7cff1c4259d7	1237	* @{
Kojto	101:7cff1c4259d7	1238	*/
Kojto	101:7cff1c4259d7	1239	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
Kojto	101:7cff1c4259d7	1240	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
Kojto	101:7cff1c4259d7	1241	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
Kojto	101:7cff1c4259d7	1242	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
Kojto	101:7cff1c4259d7	1243	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
Kojto	101:7cff1c4259d7	1244	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
Kojto	101:7cff1c4259d7	1245	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
Kojto	101:7cff1c4259d7	1246	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
Kojto	101:7cff1c4259d7	1247	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
Kojto	101:7cff1c4259d7	1248	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
Kojto	101:7cff1c4259d7	1249	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
Kojto	101:7cff1c4259d7	1250	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
Kojto	101:7cff1c4259d7	1251	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
Kojto	101:7cff1c4259d7	1252	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
Kojto	101:7cff1c4259d7	1253	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
Kojto	101:7cff1c4259d7	1254	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
Kojto	101:7cff1c4259d7	1255	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
Kojto	106:ba1f97679dad	1256	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
Kojto	106:ba1f97679dad	1257	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
Kojto	106:ba1f97679dad	1258	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
Kojto	106:ba1f97679dad	1259	#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
Kojto	101:7cff1c4259d7	1260	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
Kojto	101:7cff1c4259d7	1261	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
Kojto	101:7cff1c4259d7	1262	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
Kojto	101:7cff1c4259d7	1263	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
Kojto	101:7cff1c4259d7	1264	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
Kojto	101:7cff1c4259d7	1265	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
Kojto	101:7cff1c4259d7	1266	/**
Kojto	101:7cff1c4259d7	1267	* @}
Kojto	101:7cff1c4259d7	1268	*/
Kojto	101:7cff1c4259d7	1269
Kojto	101:7cff1c4259d7	1270	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
Kojto	101:7cff1c4259d7	1271	* @{
Kojto	101:7cff1c4259d7	1272	*/
Kojto	101:7cff1c4259d7	1273	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1274	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
Kojto	101:7cff1c4259d7	1275	/**
Kojto	101:7cff1c4259d7	1276	* @}
Kojto	101:7cff1c4259d7	1277	*/
Kojto	101:7cff1c4259d7	1278
Kojto	101:7cff1c4259d7	1279	/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
Kojto	101:7cff1c4259d7	1280	* @{
Kojto	101:7cff1c4259d7	1281	*/
Kojto	101:7cff1c4259d7	1282	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
Kojto	101:7cff1c4259d7	1283	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1284	/**
Kojto	101:7cff1c4259d7	1285	* @}
Kojto	101:7cff1c4259d7	1286	*/
Kojto	101:7cff1c4259d7	1287
Kojto	101:7cff1c4259d7	1288	/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
Kojto	101:7cff1c4259d7	1289	* @{
Kojto	101:7cff1c4259d7	1290	*/
Kojto	101:7cff1c4259d7	1291	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1292	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
Kojto	101:7cff1c4259d7	1293	/**
Kojto	101:7cff1c4259d7	1294	* @}
Kojto	101:7cff1c4259d7	1295	*/
Kojto	101:7cff1c4259d7	1296
Kojto	101:7cff1c4259d7	1297	/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
Kojto	101:7cff1c4259d7	1298	* @{
Kojto	101:7cff1c4259d7	1299	*/
Kojto	101:7cff1c4259d7	1300	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
Kojto	101:7cff1c4259d7	1301	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1302	/**
Kojto	101:7cff1c4259d7	1303	* @}
Kojto	101:7cff1c4259d7	1304	*/
Kojto	101:7cff1c4259d7	1305
Kojto	101:7cff1c4259d7	1306	/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
Kojto	101:7cff1c4259d7	1307	* @{
Kojto	101:7cff1c4259d7	1308	*/
Kojto	101:7cff1c4259d7	1309	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
Kojto	101:7cff1c4259d7	1310	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
Kojto	101:7cff1c4259d7	1311	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
Kojto	101:7cff1c4259d7	1312	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
Kojto	101:7cff1c4259d7	1313	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
Kojto	101:7cff1c4259d7	1314	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
Kojto	101:7cff1c4259d7	1315	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
Kojto	101:7cff1c4259d7	1316	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
Kojto	101:7cff1c4259d7	1317	/**
Kojto	101:7cff1c4259d7	1318	* @}
Kojto	101:7cff1c4259d7	1319	*/
Kojto	101:7cff1c4259d7	1320
Kojto	101:7cff1c4259d7	1321	/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
Kojto	101:7cff1c4259d7	1322	* @{
Kojto	101:7cff1c4259d7	1323	*/
Kojto	101:7cff1c4259d7	1324	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
Kojto	101:7cff1c4259d7	1325	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1326	/**
Kojto	101:7cff1c4259d7	1327	* @}
Kojto	101:7cff1c4259d7	1328	*/
Kojto	101:7cff1c4259d7	1329
Kojto	101:7cff1c4259d7	1330	/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
Kojto	101:7cff1c4259d7	1331	* @{
Kojto	101:7cff1c4259d7	1332	*/
Kojto	101:7cff1c4259d7	1333	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
Kojto	101:7cff1c4259d7	1334	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1335	/**
Kojto	101:7cff1c4259d7	1336	* @}
Kojto	101:7cff1c4259d7	1337	*/
Kojto	101:7cff1c4259d7	1338
Kojto	101:7cff1c4259d7	1339	/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
Kojto	101:7cff1c4259d7	1340	* @{
Kojto	101:7cff1c4259d7	1341	*/
Kojto	101:7cff1c4259d7	1342	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
Kojto	101:7cff1c4259d7	1343	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
Kojto	101:7cff1c4259d7	1344	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
Kojto	101:7cff1c4259d7	1345	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
Kojto	101:7cff1c4259d7	1346	/**
Kojto	101:7cff1c4259d7	1347	* @}
Kojto	101:7cff1c4259d7	1348	*/
Kojto	101:7cff1c4259d7	1349
Kojto	101:7cff1c4259d7	1350	/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
Kojto	101:7cff1c4259d7	1351	* @{
Kojto	101:7cff1c4259d7	1352	*/
Kojto	101:7cff1c4259d7	1353	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
Kojto	101:7cff1c4259d7	1354	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1355	/**
Kojto	101:7cff1c4259d7	1356	* @}
Kojto	101:7cff1c4259d7	1357	*/
Kojto	101:7cff1c4259d7	1358
Kojto	101:7cff1c4259d7	1359	/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
Kojto	101:7cff1c4259d7	1360	* @{
Kojto	101:7cff1c4259d7	1361	*/
Kojto	101:7cff1c4259d7	1362	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
Kojto	101:7cff1c4259d7	1363	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1364	/**
Kojto	101:7cff1c4259d7	1365	* @}
Kojto	101:7cff1c4259d7	1366	*/
Kojto	101:7cff1c4259d7	1367
Kojto	101:7cff1c4259d7	1368	/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
Kojto	101:7cff1c4259d7	1369	* @{
Kojto	101:7cff1c4259d7	1370	*/
Kojto	101:7cff1c4259d7	1371	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
Kojto	101:7cff1c4259d7	1372	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1373	/**
Kojto	101:7cff1c4259d7	1374	* @}
Kojto	101:7cff1c4259d7	1375	*/
Kojto	101:7cff1c4259d7	1376
Kojto	101:7cff1c4259d7	1377	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
Kojto	101:7cff1c4259d7	1378	* @{
Kojto	101:7cff1c4259d7	1379	*/
Kojto	101:7cff1c4259d7	1380	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
Kojto	101:7cff1c4259d7	1381	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
Kojto	101:7cff1c4259d7	1382	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
Kojto	101:7cff1c4259d7	1383	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
Kojto	101:7cff1c4259d7	1384	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
Kojto	101:7cff1c4259d7	1385	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
Kojto	101:7cff1c4259d7	1386	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
Kojto	101:7cff1c4259d7	1387	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
Kojto	101:7cff1c4259d7	1388	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
Kojto	101:7cff1c4259d7	1389	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
Kojto	101:7cff1c4259d7	1390	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
Kojto	101:7cff1c4259d7	1391	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
Kojto	101:7cff1c4259d7	1392	/**
Kojto	101:7cff1c4259d7	1393	* @}
Kojto	101:7cff1c4259d7	1394	*/
Kojto	101:7cff1c4259d7	1395
Kojto	101:7cff1c4259d7	1396	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
Kojto	101:7cff1c4259d7	1397	* @{
Kojto	101:7cff1c4259d7	1398	*/
Kojto	101:7cff1c4259d7	1399	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
Kojto	101:7cff1c4259d7	1400	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
Kojto	101:7cff1c4259d7	1401	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
Kojto	101:7cff1c4259d7	1402	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
Kojto	101:7cff1c4259d7	1403	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
Kojto	101:7cff1c4259d7	1404	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
Kojto	101:7cff1c4259d7	1405	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
Kojto	101:7cff1c4259d7	1406	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
Kojto	101:7cff1c4259d7	1407	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
Kojto	101:7cff1c4259d7	1408	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
Kojto	101:7cff1c4259d7	1409	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
Kojto	101:7cff1c4259d7	1410	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
Kojto	101:7cff1c4259d7	1411	/**
Kojto	101:7cff1c4259d7	1412	* @}
Kojto	101:7cff1c4259d7	1413	*/
Kojto	101:7cff1c4259d7	1414
Kojto	101:7cff1c4259d7	1415	/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
Kojto	101:7cff1c4259d7	1416	* @{
Kojto	101:7cff1c4259d7	1417	*/
Kojto	101:7cff1c4259d7	1418	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
Kojto	101:7cff1c4259d7	1419	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1420	/**
Kojto	101:7cff1c4259d7	1421	* @}
Kojto	101:7cff1c4259d7	1422	*/
Kojto	101:7cff1c4259d7	1423
Kojto	101:7cff1c4259d7	1424	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
Kojto	101:7cff1c4259d7	1425	* @{
Kojto	101:7cff1c4259d7	1426	*/
Kojto	101:7cff1c4259d7	1427	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
Kojto	101:7cff1c4259d7	1428	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
Kojto	101:7cff1c4259d7	1429	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
Kojto	101:7cff1c4259d7	1430	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
Kojto	101:7cff1c4259d7	1431	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
Kojto	101:7cff1c4259d7	1432	/**
Kojto	101:7cff1c4259d7	1433	* @}
Kojto	101:7cff1c4259d7	1434	*/
Kojto	101:7cff1c4259d7	1435
Kojto	101:7cff1c4259d7	1436	/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
Kojto	101:7cff1c4259d7	1437	* @{
Kojto	101:7cff1c4259d7	1438	*/
Kojto	101:7cff1c4259d7	1439	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
Kojto	101:7cff1c4259d7	1440	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
Kojto	101:7cff1c4259d7	1441	/**
Kojto	101:7cff1c4259d7	1442	* @}
Kojto	101:7cff1c4259d7	1443	*/
Kojto	101:7cff1c4259d7	1444
Kojto	101:7cff1c4259d7	1445	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
Kojto	101:7cff1c4259d7	1446	* @{
Kojto	101:7cff1c4259d7	1447	*/
Kojto	101:7cff1c4259d7	1448	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
Kojto	101:7cff1c4259d7	1449	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
Kojto	101:7cff1c4259d7	1450	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
Kojto	101:7cff1c4259d7	1451	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
Kojto	101:7cff1c4259d7	1452	/**
Kojto	101:7cff1c4259d7	1453	* @}
Kojto	101:7cff1c4259d7	1454	*/
Kojto	101:7cff1c4259d7	1455
Kojto	101:7cff1c4259d7	1456	/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
Kojto	101:7cff1c4259d7	1457	* @{
Kojto	101:7cff1c4259d7	1458	*/
Kojto	101:7cff1c4259d7	1459	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
Kojto	101:7cff1c4259d7	1460	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
Kojto	101:7cff1c4259d7	1461	/**
Kojto	101:7cff1c4259d7	1462	* @}
Kojto	101:7cff1c4259d7	1463	*/
Kojto	101:7cff1c4259d7	1464
Kojto	101:7cff1c4259d7	1465	/** @defgroup ETH_PMT_Flags ETH PMT Flags
Kojto	101:7cff1c4259d7	1466	* @{
Kojto	101:7cff1c4259d7	1467	*/
Kojto	101:7cff1c4259d7	1468	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
Kojto	101:7cff1c4259d7	1469	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
Kojto	101:7cff1c4259d7	1470	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
Kojto	101:7cff1c4259d7	1471	/**
Kojto	101:7cff1c4259d7	1472	* @}
Kojto	101:7cff1c4259d7	1473	*/
Kojto	101:7cff1c4259d7	1474
Kojto	101:7cff1c4259d7	1475	/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
Kojto	101:7cff1c4259d7	1476	* @{
Kojto	101:7cff1c4259d7	1477	*/
Kojto	101:7cff1c4259d7	1478	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
Kojto	101:7cff1c4259d7	1479	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
Kojto	101:7cff1c4259d7	1480	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
Kojto	101:7cff1c4259d7	1481	/**
Kojto	101:7cff1c4259d7	1482	* @}
Kojto	101:7cff1c4259d7	1483	*/
Kojto	101:7cff1c4259d7	1484
Kojto	101:7cff1c4259d7	1485	/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
Kojto	101:7cff1c4259d7	1486	* @{
Kojto	101:7cff1c4259d7	1487	*/
Kojto	101:7cff1c4259d7	1488	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
Kojto	101:7cff1c4259d7	1489	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
Kojto	101:7cff1c4259d7	1490	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
Kojto	101:7cff1c4259d7	1491	/**
Kojto	101:7cff1c4259d7	1492	* @}
Kojto	101:7cff1c4259d7	1493	*/
Kojto	101:7cff1c4259d7	1494
Kojto	101:7cff1c4259d7	1495	/** @defgroup ETH_MAC_Flags ETH MAC Flags
Kojto	101:7cff1c4259d7	1496	* @{
Kojto	101:7cff1c4259d7	1497	*/
Kojto	101:7cff1c4259d7	1498	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
Kojto	101:7cff1c4259d7	1499	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
Kojto	101:7cff1c4259d7	1500	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
Kojto	101:7cff1c4259d7	1501	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
Kojto	101:7cff1c4259d7	1502	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
Kojto	101:7cff1c4259d7	1503	/**
Kojto	101:7cff1c4259d7	1504	* @}
Kojto	101:7cff1c4259d7	1505	*/
Kojto	101:7cff1c4259d7	1506
Kojto	101:7cff1c4259d7	1507	/** @defgroup ETH_DMA_Flags ETH DMA Flags
Kojto	101:7cff1c4259d7	1508	* @{
Kojto	101:7cff1c4259d7	1509	*/
Kojto	101:7cff1c4259d7	1510	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
Kojto	101:7cff1c4259d7	1511	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
Kojto	101:7cff1c4259d7	1512	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
Kojto	101:7cff1c4259d7	1513	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
Kojto	101:7cff1c4259d7	1514	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write transfer, 1-read transfer /
Kojto	101:7cff1c4259d7	1515	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
Kojto	101:7cff1c4259d7	1516	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
Kojto	101:7cff1c4259d7	1517	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
Kojto	101:7cff1c4259d7	1518	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
Kojto	101:7cff1c4259d7	1519	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
Kojto	101:7cff1c4259d7	1520	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
Kojto	101:7cff1c4259d7	1521	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
Kojto	101:7cff1c4259d7	1522	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
Kojto	101:7cff1c4259d7	1523	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
Kojto	101:7cff1c4259d7	1524	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
Kojto	101:7cff1c4259d7	1525	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
Kojto	101:7cff1c4259d7	1526	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
Kojto	101:7cff1c4259d7	1527	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
Kojto	101:7cff1c4259d7	1528	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
Kojto	101:7cff1c4259d7	1529	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
Kojto	101:7cff1c4259d7	1530	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
Kojto	101:7cff1c4259d7	1531	/**
Kojto	101:7cff1c4259d7	1532	* @}
Kojto	101:7cff1c4259d7	1533	*/
Kojto	101:7cff1c4259d7	1534
Kojto	101:7cff1c4259d7	1535	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
Kojto	101:7cff1c4259d7	1536	* @{
Kojto	101:7cff1c4259d7	1537	*/
Kojto	101:7cff1c4259d7	1538	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
Kojto	101:7cff1c4259d7	1539	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
Kojto	101:7cff1c4259d7	1540	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
Kojto	101:7cff1c4259d7	1541	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
Kojto	101:7cff1c4259d7	1542	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
Kojto	101:7cff1c4259d7	1543	/**
Kojto	101:7cff1c4259d7	1544	* @}
Kojto	101:7cff1c4259d7	1545	*/
Kojto	101:7cff1c4259d7	1546
Kojto	101:7cff1c4259d7	1547	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
Kojto	101:7cff1c4259d7	1548	* @{
Kojto	101:7cff1c4259d7	1549	*/
Kojto	101:7cff1c4259d7	1550	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
Kojto	101:7cff1c4259d7	1551	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
Kojto	101:7cff1c4259d7	1552	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
Kojto	101:7cff1c4259d7	1553	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
Kojto	101:7cff1c4259d7	1554	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
Kojto	101:7cff1c4259d7	1555	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
Kojto	101:7cff1c4259d7	1556	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
Kojto	101:7cff1c4259d7	1557	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
Kojto	101:7cff1c4259d7	1558	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
Kojto	101:7cff1c4259d7	1559	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
Kojto	101:7cff1c4259d7	1560	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
Kojto	101:7cff1c4259d7	1561	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
Kojto	101:7cff1c4259d7	1562	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
Kojto	101:7cff1c4259d7	1563	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
Kojto	101:7cff1c4259d7	1564	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
Kojto	101:7cff1c4259d7	1565	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
Kojto	101:7cff1c4259d7	1566	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
Kojto	101:7cff1c4259d7	1567	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
Kojto	101:7cff1c4259d7	1568	/**
Kojto	101:7cff1c4259d7	1569	* @}
Kojto	101:7cff1c4259d7	1570	*/
Kojto	101:7cff1c4259d7	1571
Kojto	101:7cff1c4259d7	1572	/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
Kojto	101:7cff1c4259d7	1573	* @{
Kojto	101:7cff1c4259d7	1574	*/
Kojto	101:7cff1c4259d7	1575	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
Kojto	101:7cff1c4259d7	1576	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
Kojto	101:7cff1c4259d7	1577	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
Kojto	101:7cff1c4259d7	1578	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
Kojto	101:7cff1c4259d7	1579	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
Kojto	101:7cff1c4259d7	1580	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
Kojto	101:7cff1c4259d7	1581
Kojto	101:7cff1c4259d7	1582	/**
Kojto	101:7cff1c4259d7	1583	* @}
Kojto	101:7cff1c4259d7	1584	*/
Kojto	101:7cff1c4259d7	1585
Kojto	101:7cff1c4259d7	1586
Kojto	101:7cff1c4259d7	1587	/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
Kojto	101:7cff1c4259d7	1588	* @{
Kojto	101:7cff1c4259d7	1589	*/
Kojto	101:7cff1c4259d7	1590	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
Kojto	101:7cff1c4259d7	1591	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
Kojto	101:7cff1c4259d7	1592	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
Kojto	101:7cff1c4259d7	1593	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
Kojto	101:7cff1c4259d7	1594	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
Kojto	101:7cff1c4259d7	1595	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
Kojto	101:7cff1c4259d7	1596
Kojto	101:7cff1c4259d7	1597	/**
Kojto	101:7cff1c4259d7	1598	* @}
Kojto	101:7cff1c4259d7	1599	*/
Kojto	101:7cff1c4259d7	1600
Kojto	101:7cff1c4259d7	1601	/** @defgroup ETH_DMA_overflow ETH DMA overflow
Kojto	101:7cff1c4259d7	1602	* @{
Kojto	101:7cff1c4259d7	1603	*/
Kojto	101:7cff1c4259d7	1604	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
Kojto	101:7cff1c4259d7	1605	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
Kojto	101:7cff1c4259d7	1606	/**
Kojto	101:7cff1c4259d7	1607	* @}
Kojto	101:7cff1c4259d7	1608	*/
Kojto	101:7cff1c4259d7	1609
Kojto	101:7cff1c4259d7	1610	/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
Kojto	101:7cff1c4259d7	1611	* @{
Kojto	101:7cff1c4259d7	1612	*/
Kojto	101:7cff1c4259d7	1613	#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /!< External interrupt line 19 Connected to the ETH EXTI Line /
Kojto	101:7cff1c4259d7	1614
Kojto	101:7cff1c4259d7	1615	/**
Kojto	101:7cff1c4259d7	1616	* @}
Kojto	101:7cff1c4259d7	1617	*/
Kojto	101:7cff1c4259d7	1618
Kojto	101:7cff1c4259d7	1619	/**
Kojto	101:7cff1c4259d7	1620	* @}
Kojto	101:7cff1c4259d7	1621	*/
Kojto	101:7cff1c4259d7	1622
Kojto	101:7cff1c4259d7	1623	/* Exported macro ------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	1624	/** @defgroup ETH_Exported_Macros ETH Exported Macros
Kojto	101:7cff1c4259d7	1625	* @brief macros to handle interrupts and specific clock configurations
Kojto	101:7cff1c4259d7	1626	* @{
Kojto	101:7cff1c4259d7	1627	*/
Kojto	101:7cff1c4259d7	1628
Kojto	101:7cff1c4259d7	1629	/** @brief Reset ETH handle state
Kojto	101:7cff1c4259d7	1630	* @param __HANDLE__: specifies the ETH handle.
Kojto	101:7cff1c4259d7	1631	* @retval None
Kojto	101:7cff1c4259d7	1632	*/
Kojto	101:7cff1c4259d7	1633	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
Kojto	101:7cff1c4259d7	1634
Kojto	101:7cff1c4259d7	1635	/**
Kojto	101:7cff1c4259d7	1636	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
Kojto	101:7cff1c4259d7	1637	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1638	* @param __FLAG__: specifies the flag of TDES0 to check.
Kojto	101:7cff1c4259d7	1639	* @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto	101:7cff1c4259d7	1640	*/
Kojto	101:7cff1c4259d7	1641	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto	101:7cff1c4259d7	1642
Kojto	101:7cff1c4259d7	1643	/**
Kojto	101:7cff1c4259d7	1644	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
Kojto	101:7cff1c4259d7	1645	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1646	* @param __FLAG__: specifies the flag of RDES0 to check.
Kojto	101:7cff1c4259d7	1647	* @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto	101:7cff1c4259d7	1648	*/
Kojto	101:7cff1c4259d7	1649	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto	101:7cff1c4259d7	1650
Kojto	101:7cff1c4259d7	1651	/**
Kojto	101:7cff1c4259d7	1652	* @brief Enables the specified DMA Rx Desc receive interrupt.
Kojto	101:7cff1c4259d7	1653	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1654	* @retval None
Kojto	101:7cff1c4259d7	1655	*/
Kojto	101:7cff1c4259d7	1656	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
Kojto	101:7cff1c4259d7	1657
Kojto	101:7cff1c4259d7	1658	/**
Kojto	101:7cff1c4259d7	1659	* @brief Disables the specified DMA Rx Desc receive interrupt.
Kojto	101:7cff1c4259d7	1660	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1661	* @retval None
Kojto	101:7cff1c4259d7	1662	*/
Kojto	101:7cff1c4259d7	1663	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
Kojto	101:7cff1c4259d7	1664
Kojto	101:7cff1c4259d7	1665	/**
Kojto	101:7cff1c4259d7	1666	* @brief Set the specified DMA Rx Desc Own bit.
Kojto	101:7cff1c4259d7	1667	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1668	* @retval None
Kojto	101:7cff1c4259d7	1669	*/
Kojto	101:7cff1c4259d7	1670	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
Kojto	101:7cff1c4259d7	1671
Kojto	101:7cff1c4259d7	1672	/**
Kojto	101:7cff1c4259d7	1673	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
Kojto	101:7cff1c4259d7	1674	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1675	* @retval The Transmit descriptor collision counter value.
Kojto	101:7cff1c4259d7	1676	*/
Kojto	101:7cff1c4259d7	1677	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
Kojto	101:7cff1c4259d7	1678
Kojto	101:7cff1c4259d7	1679	/**
Kojto	101:7cff1c4259d7	1680	* @brief Set the specified DMA Tx Desc Own bit.
Kojto	101:7cff1c4259d7	1681	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1682	* @retval None
Kojto	101:7cff1c4259d7	1683	*/
Kojto	101:7cff1c4259d7	1684	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
Kojto	101:7cff1c4259d7	1685
Kojto	101:7cff1c4259d7	1686	/**
Kojto	101:7cff1c4259d7	1687	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
Kojto	101:7cff1c4259d7	1688	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1689	* @retval None
Kojto	101:7cff1c4259d7	1690	*/
Kojto	101:7cff1c4259d7	1691	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
Kojto	101:7cff1c4259d7	1692
Kojto	101:7cff1c4259d7	1693	/**
Kojto	101:7cff1c4259d7	1694	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
Kojto	101:7cff1c4259d7	1695	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1696	* @retval None
Kojto	101:7cff1c4259d7	1697	*/
Kojto	101:7cff1c4259d7	1698	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
Kojto	101:7cff1c4259d7	1699
Kojto	101:7cff1c4259d7	1700	/**
Kojto	101:7cff1c4259d7	1701	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
Kojto	101:7cff1c4259d7	1702	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1703	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
Kojto	101:7cff1c4259d7	1704	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	1705	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
Kojto	101:7cff1c4259d7	1706	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
Kojto	101:7cff1c4259d7	1707	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
Kojto	101:7cff1c4259d7	1708	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
Kojto	101:7cff1c4259d7	1709	* @retval None
Kojto	101:7cff1c4259d7	1710	*/
Kojto	101:7cff1c4259d7	1711	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
Kojto	101:7cff1c4259d7	1712
Kojto	101:7cff1c4259d7	1713	/**
Kojto	101:7cff1c4259d7	1714	* @brief Enables the DMA Tx Desc CRC.
Kojto	101:7cff1c4259d7	1715	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1716	* @retval None
Kojto	101:7cff1c4259d7	1717	*/
Kojto	101:7cff1c4259d7	1718	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
Kojto	101:7cff1c4259d7	1719
Kojto	101:7cff1c4259d7	1720	/**
Kojto	101:7cff1c4259d7	1721	* @brief Disables the DMA Tx Desc CRC.
Kojto	101:7cff1c4259d7	1722	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1723	* @retval None
Kojto	101:7cff1c4259d7	1724	*/
Kojto	101:7cff1c4259d7	1725	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
Kojto	101:7cff1c4259d7	1726
Kojto	101:7cff1c4259d7	1727	/**
Kojto	101:7cff1c4259d7	1728	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto	101:7cff1c4259d7	1729	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1730	* @retval None
Kojto	101:7cff1c4259d7	1731	*/
Kojto	101:7cff1c4259d7	1732	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
Kojto	101:7cff1c4259d7	1733
Kojto	101:7cff1c4259d7	1734	/**
Kojto	101:7cff1c4259d7	1735	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto	101:7cff1c4259d7	1736	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1737	* @retval None
Kojto	101:7cff1c4259d7	1738	*/
Kojto	101:7cff1c4259d7	1739	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
Kojto	101:7cff1c4259d7	1740
Kojto	101:7cff1c4259d7	1741	/**
Kojto	101:7cff1c4259d7	1742	* @brief Enables the specified ETHERNET MAC interrupts.
Kojto	101:7cff1c4259d7	1743	* @param __HANDLE__ : ETH Handle
Kojto	101:7cff1c4259d7	1744	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto	101:7cff1c4259d7	1745	* enabled or disabled.
Kojto	101:7cff1c4259d7	1746	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1747	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto	101:7cff1c4259d7	1748	* @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto	101:7cff1c4259d7	1749	* @retval None
Kojto	101:7cff1c4259d7	1750	*/
Kojto	101:7cff1c4259d7	1751	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
Kojto	101:7cff1c4259d7	1752
Kojto	101:7cff1c4259d7	1753	/**
Kojto	101:7cff1c4259d7	1754	* @brief Disables the specified ETHERNET MAC interrupts.
Kojto	101:7cff1c4259d7	1755	* @param __HANDLE__ : ETH Handle
Kojto	101:7cff1c4259d7	1756	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto	101:7cff1c4259d7	1757	* enabled or disabled.
Kojto	101:7cff1c4259d7	1758	* This parameter can be any combination of the following values:
Kojto	101:7cff1c4259d7	1759	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto	101:7cff1c4259d7	1760	* @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto	101:7cff1c4259d7	1761	* @retval None
Kojto	101:7cff1c4259d7	1762	*/
Kojto	101:7cff1c4259d7	1763	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
Kojto	101:7cff1c4259d7	1764
Kojto	101:7cff1c4259d7	1765	/**
Kojto	101:7cff1c4259d7	1766	* @brief Initiate a Pause Control Frame (Full-duplex only).
Kojto	101:7cff1c4259d7	1767	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1768	* @retval None
Kojto	101:7cff1c4259d7	1769	*/
Kojto	101:7cff1c4259d7	1770	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
Kojto	101:7cff1c4259d7	1771
Kojto	101:7cff1c4259d7	1772	/**
Kojto	101:7cff1c4259d7	1773	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
Kojto	101:7cff1c4259d7	1774	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1775	* @retval The new state of flow control busy status bit (SET or RESET).
Kojto	101:7cff1c4259d7	1776	*/
Kojto	101:7cff1c4259d7	1777	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
Kojto	101:7cff1c4259d7	1778
Kojto	101:7cff1c4259d7	1779	/**
Kojto	101:7cff1c4259d7	1780	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
Kojto	101:7cff1c4259d7	1781	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1782	* @retval None
Kojto	101:7cff1c4259d7	1783	*/
Kojto	101:7cff1c4259d7	1784	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
Kojto	101:7cff1c4259d7	1785
Kojto	101:7cff1c4259d7	1786	/**
Kojto	101:7cff1c4259d7	1787	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
Kojto	101:7cff1c4259d7	1788	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1789	* @retval None
Kojto	101:7cff1c4259d7	1790	*/
Kojto	101:7cff1c4259d7	1791	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
Kojto	101:7cff1c4259d7	1792
Kojto	101:7cff1c4259d7	1793	/**
Kojto	101:7cff1c4259d7	1794	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
Kojto	101:7cff1c4259d7	1795	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1796	* @param __FLAG__: specifies the flag to check.
Kojto	101:7cff1c4259d7	1797	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	1798	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
Kojto	101:7cff1c4259d7	1799	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
Kojto	101:7cff1c4259d7	1800	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
Kojto	101:7cff1c4259d7	1801	* @arg ETH_MAC_FLAG_MMC : MMC flag
Kojto	101:7cff1c4259d7	1802	* @arg ETH_MAC_FLAG_PMT : PMT flag
Kojto	101:7cff1c4259d7	1803	* @retval The state of ETHERNET MAC flag.
Kojto	101:7cff1c4259d7	1804	*/
Kojto	101:7cff1c4259d7	1805	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
Kojto	101:7cff1c4259d7	1806
Kojto	101:7cff1c4259d7	1807	/**
Kojto	101:7cff1c4259d7	1808	* @brief Enables the specified ETHERNET DMA interrupts.
Kojto	101:7cff1c4259d7	1809	* @param __HANDLE__ : ETH Handle
Kojto	101:7cff1c4259d7	1810	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto	101:7cff1c4259d7	1811	* enabled @ref ETH_DMA_Interrupts
Kojto	101:7cff1c4259d7	1812	* @retval None
Kojto	101:7cff1c4259d7	1813	*/
Kojto	101:7cff1c4259d7	1814	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
Kojto	101:7cff1c4259d7	1815
Kojto	101:7cff1c4259d7	1816	/**
Kojto	101:7cff1c4259d7	1817	* @brief Disables the specified ETHERNET DMA interrupts.
Kojto	101:7cff1c4259d7	1818	* @param __HANDLE__ : ETH Handle
Kojto	101:7cff1c4259d7	1819	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto	101:7cff1c4259d7	1820	* disabled. @ref ETH_DMA_Interrupts
Kojto	101:7cff1c4259d7	1821	* @retval None
Kojto	101:7cff1c4259d7	1822	*/
Kojto	101:7cff1c4259d7	1823	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
Kojto	101:7cff1c4259d7	1824
Kojto	101:7cff1c4259d7	1825	/**
Kojto	101:7cff1c4259d7	1826	* @brief Clears the ETHERNET DMA IT pending bit.
Kojto	101:7cff1c4259d7	1827	* @param __HANDLE__ : ETH Handle
Kojto	101:7cff1c4259d7	1828	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
Kojto	101:7cff1c4259d7	1829	* @retval None
Kojto	101:7cff1c4259d7	1830	*/
Kojto	101:7cff1c4259d7	1831	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
Kojto	101:7cff1c4259d7	1832
Kojto	101:7cff1c4259d7	1833	/**
Kojto	101:7cff1c4259d7	1834	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto	101:7cff1c4259d7	1835	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1836	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
Kojto	101:7cff1c4259d7	1837	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto	101:7cff1c4259d7	1838	*/
Kojto	101:7cff1c4259d7	1839	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
Kojto	101:7cff1c4259d7	1840
Kojto	101:7cff1c4259d7	1841	/**
Kojto	101:7cff1c4259d7	1842	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto	101:7cff1c4259d7	1843	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1844	* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
Kojto	101:7cff1c4259d7	1845	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto	101:7cff1c4259d7	1846	*/
Kojto	101:7cff1c4259d7	1847	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
Kojto	101:7cff1c4259d7	1848
Kojto	101:7cff1c4259d7	1849	/**
Kojto	101:7cff1c4259d7	1850	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
Kojto	101:7cff1c4259d7	1851	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1852	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
Kojto	101:7cff1c4259d7	1853	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	1854	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
Kojto	101:7cff1c4259d7	1855	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
Kojto	101:7cff1c4259d7	1856	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
Kojto	101:7cff1c4259d7	1857	*/
Kojto	101:7cff1c4259d7	1858	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
Kojto	101:7cff1c4259d7	1859
Kojto	101:7cff1c4259d7	1860	/**
Kojto	101:7cff1c4259d7	1861	* @brief Set the DMA Receive status watchdog timer register value
Kojto	101:7cff1c4259d7	1862	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1863	* @param __VALUE__: DMA Receive status watchdog timer register value
Kojto	101:7cff1c4259d7	1864	* @retval None
Kojto	101:7cff1c4259d7	1865	*/
Kojto	101:7cff1c4259d7	1866	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
Kojto	101:7cff1c4259d7	1867
Kojto	101:7cff1c4259d7	1868	/**
Kojto	101:7cff1c4259d7	1869	* @brief Enables any unicast packet filtered by the MAC address
Kojto	101:7cff1c4259d7	1870	* recognition to be a wake-up frame.
Kojto	101:7cff1c4259d7	1871	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1872	* @retval None
Kojto	101:7cff1c4259d7	1873	*/
Kojto	101:7cff1c4259d7	1874	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
Kojto	101:7cff1c4259d7	1875
Kojto	101:7cff1c4259d7	1876	/**
Kojto	101:7cff1c4259d7	1877	* @brief Disables any unicast packet filtered by the MAC address
Kojto	101:7cff1c4259d7	1878	* recognition to be a wake-up frame.
Kojto	101:7cff1c4259d7	1879	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1880	* @retval None
Kojto	101:7cff1c4259d7	1881	*/
Kojto	101:7cff1c4259d7	1882	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
Kojto	101:7cff1c4259d7	1883
Kojto	101:7cff1c4259d7	1884	/**
Kojto	101:7cff1c4259d7	1885	* @brief Enables the MAC Wake-Up Frame Detection.
Kojto	101:7cff1c4259d7	1886	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1887	* @retval None
Kojto	101:7cff1c4259d7	1888	*/
Kojto	101:7cff1c4259d7	1889	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
Kojto	101:7cff1c4259d7	1890
Kojto	101:7cff1c4259d7	1891	/**
Kojto	101:7cff1c4259d7	1892	* @brief Disables the MAC Wake-Up Frame Detection.
Kojto	101:7cff1c4259d7	1893	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1894	* @retval None
Kojto	101:7cff1c4259d7	1895	*/
Kojto	101:7cff1c4259d7	1896	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto	101:7cff1c4259d7	1897
Kojto	101:7cff1c4259d7	1898	/**
Kojto	101:7cff1c4259d7	1899	* @brief Enables the MAC Magic Packet Detection.
Kojto	101:7cff1c4259d7	1900	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1901	* @retval None
Kojto	101:7cff1c4259d7	1902	*/
Kojto	101:7cff1c4259d7	1903	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
Kojto	101:7cff1c4259d7	1904
Kojto	101:7cff1c4259d7	1905	/**
Kojto	101:7cff1c4259d7	1906	* @brief Disables the MAC Magic Packet Detection.
Kojto	101:7cff1c4259d7	1907	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1908	* @retval None
Kojto	101:7cff1c4259d7	1909	*/
Kojto	101:7cff1c4259d7	1910	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto	101:7cff1c4259d7	1911
Kojto	101:7cff1c4259d7	1912	/**
Kojto	101:7cff1c4259d7	1913	* @brief Enables the MAC Power Down.
Kojto	101:7cff1c4259d7	1914	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1915	* @retval None
Kojto	101:7cff1c4259d7	1916	*/
Kojto	101:7cff1c4259d7	1917	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
Kojto	101:7cff1c4259d7	1918
Kojto	101:7cff1c4259d7	1919	/**
Kojto	101:7cff1c4259d7	1920	* @brief Disables the MAC Power Down.
Kojto	101:7cff1c4259d7	1921	* @param __HANDLE__: ETH Handle
Kojto	101:7cff1c4259d7	1922	* @retval None
Kojto	101:7cff1c4259d7	1923	*/
Kojto	101:7cff1c4259d7	1924	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
Kojto	101:7cff1c4259d7	1925
Kojto	101:7cff1c4259d7	1926	/**
Kojto	101:7cff1c4259d7	1927	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
Kojto	101:7cff1c4259d7	1928	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1929	* @param __FLAG__: specifies the flag to check.
Kojto	101:7cff1c4259d7	1930	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	1931	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
Kojto	101:7cff1c4259d7	1932	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
Kojto	101:7cff1c4259d7	1933	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
Kojto	101:7cff1c4259d7	1934	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
Kojto	101:7cff1c4259d7	1935	*/
Kojto	101:7cff1c4259d7	1936	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
Kojto	101:7cff1c4259d7	1937
Kojto	101:7cff1c4259d7	1938	/**
Kojto	101:7cff1c4259d7	1939	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
Kojto	101:7cff1c4259d7	1940	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1941	* @retval None
Kojto	101:7cff1c4259d7	1942	*/
Kojto	101:7cff1c4259d7	1943	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
Kojto	101:7cff1c4259d7	1944
Kojto	101:7cff1c4259d7	1945	/**
Kojto	101:7cff1c4259d7	1946	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
Kojto	101:7cff1c4259d7	1947	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1948	* @retval None
Kojto	101:7cff1c4259d7	1949	*/
Kojto	101:7cff1c4259d7	1950	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
Kojto	101:7cff1c4259d7	1951	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
Kojto	101:7cff1c4259d7	1952
Kojto	101:7cff1c4259d7	1953	/**
Kojto	101:7cff1c4259d7	1954	* @brief Enables the MMC Counter Freeze.
Kojto	101:7cff1c4259d7	1955	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1956	* @retval None
Kojto	101:7cff1c4259d7	1957	*/
Kojto	101:7cff1c4259d7	1958	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
Kojto	101:7cff1c4259d7	1959
Kojto	101:7cff1c4259d7	1960	/**
Kojto	101:7cff1c4259d7	1961	* @brief Disables the MMC Counter Freeze.
Kojto	101:7cff1c4259d7	1962	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1963	* @retval None
Kojto	101:7cff1c4259d7	1964	*/
Kojto	101:7cff1c4259d7	1965	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
Kojto	101:7cff1c4259d7	1966
Kojto	101:7cff1c4259d7	1967	/**
Kojto	101:7cff1c4259d7	1968	* @brief Enables the MMC Reset On Read.
Kojto	101:7cff1c4259d7	1969	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1970	* @retval None
Kojto	101:7cff1c4259d7	1971	*/
Kojto	101:7cff1c4259d7	1972	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
Kojto	101:7cff1c4259d7	1973
Kojto	101:7cff1c4259d7	1974	/**
Kojto	101:7cff1c4259d7	1975	* @brief Disables the MMC Reset On Read.
Kojto	101:7cff1c4259d7	1976	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1977	* @retval None
Kojto	101:7cff1c4259d7	1978	*/
Kojto	101:7cff1c4259d7	1979	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
Kojto	101:7cff1c4259d7	1980
Kojto	101:7cff1c4259d7	1981	/**
Kojto	101:7cff1c4259d7	1982	* @brief Enables the MMC Counter Stop Rollover.
Kojto	101:7cff1c4259d7	1983	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1984	* @retval None
Kojto	101:7cff1c4259d7	1985	*/
Kojto	101:7cff1c4259d7	1986	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
Kojto	101:7cff1c4259d7	1987
Kojto	101:7cff1c4259d7	1988	/**
Kojto	101:7cff1c4259d7	1989	* @brief Disables the MMC Counter Stop Rollover.
Kojto	101:7cff1c4259d7	1990	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1991	* @retval None
Kojto	101:7cff1c4259d7	1992	*/
Kojto	101:7cff1c4259d7	1993	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
Kojto	101:7cff1c4259d7	1994
Kojto	101:7cff1c4259d7	1995	/**
Kojto	101:7cff1c4259d7	1996	* @brief Resets the MMC Counters.
Kojto	101:7cff1c4259d7	1997	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	1998	* @retval None
Kojto	101:7cff1c4259d7	1999	*/
Kojto	101:7cff1c4259d7	2000	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
Kojto	101:7cff1c4259d7	2001
Kojto	101:7cff1c4259d7	2002	/**
Kojto	101:7cff1c4259d7	2003	* @brief Enables the specified ETHERNET MMC Rx interrupts.
Kojto	101:7cff1c4259d7	2004	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	2005	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	101:7cff1c4259d7	2006	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2007	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2008	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2009	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2010	* @retval None
Kojto	101:7cff1c4259d7	2011	*/
Kojto	101:7cff1c4259d7	2012	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
Kojto	101:7cff1c4259d7	2013	/**
Kojto	101:7cff1c4259d7	2014	* @brief Disables the specified ETHERNET MMC Rx interrupts.
Kojto	101:7cff1c4259d7	2015	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	2016	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	101:7cff1c4259d7	2017	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2018	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2019	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2020	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2021	* @retval None
Kojto	101:7cff1c4259d7	2022	*/
Kojto	101:7cff1c4259d7	2023	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
Kojto	101:7cff1c4259d7	2024	/**
Kojto	101:7cff1c4259d7	2025	* @brief Enables the specified ETHERNET MMC Tx interrupts.
Kojto	101:7cff1c4259d7	2026	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	2027	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	101:7cff1c4259d7	2028	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2029	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2030	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2031	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2032	* @retval None
Kojto	101:7cff1c4259d7	2033	*/
Kojto	101:7cff1c4259d7	2034	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
Kojto	101:7cff1c4259d7	2035
Kojto	101:7cff1c4259d7	2036	/**
Kojto	101:7cff1c4259d7	2037	* @brief Disables the specified ETHERNET MMC Tx interrupts.
Kojto	101:7cff1c4259d7	2038	* @param __HANDLE__: ETH Handle.
Kojto	101:7cff1c4259d7	2039	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	101:7cff1c4259d7	2040	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	2041	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2042	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2043	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto	101:7cff1c4259d7	2044	* @retval None
Kojto	101:7cff1c4259d7	2045	*/
Kojto	101:7cff1c4259d7	2046	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
Kojto	101:7cff1c4259d7	2047
Kojto	101:7cff1c4259d7	2048	/**
Kojto	101:7cff1c4259d7	2049	* @brief Enables the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2050	* @retval None
Kojto	101:7cff1c4259d7	2051	*/
Kojto	101:7cff1c4259d7	2052	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2053
Kojto	101:7cff1c4259d7	2054	/**
Kojto	101:7cff1c4259d7	2055	* @brief Disables the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2056	* @retval None
Kojto	101:7cff1c4259d7	2057	*/
Kojto	101:7cff1c4259d7	2058	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2059
Kojto	101:7cff1c4259d7	2060	/**
Kojto	101:7cff1c4259d7	2061	* @brief Enable event on ETH External event line.
Kojto	101:7cff1c4259d7	2062	* @retval None.
Kojto	101:7cff1c4259d7	2063	*/
Kojto	101:7cff1c4259d7	2064	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2065
Kojto	101:7cff1c4259d7	2066	/**
Kojto	101:7cff1c4259d7	2067	* @brief Disable event on ETH External event line
Kojto	101:7cff1c4259d7	2068	* @retval None.
Kojto	101:7cff1c4259d7	2069	*/
Kojto	101:7cff1c4259d7	2070	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2071
Kojto	101:7cff1c4259d7	2072	/**
Kojto	101:7cff1c4259d7	2073	* @brief Get flag of the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2074	* @retval None
Kojto	101:7cff1c4259d7	2075	*/
Kojto	101:7cff1c4259d7	2076	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2077
Kojto	101:7cff1c4259d7	2078	/**
Kojto	101:7cff1c4259d7	2079	* @brief Clear flag of the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2080	* @retval None
Kojto	101:7cff1c4259d7	2081	*/
Kojto	101:7cff1c4259d7	2082	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2083
Kojto	101:7cff1c4259d7	2084	/**
Kojto	101:7cff1c4259d7	2085	* @brief Enables rising edge trigger to the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2086	* @retval None
Kojto	101:7cff1c4259d7	2087	*/
Kojto	101:7cff1c4259d7	2088	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
Kojto	101:7cff1c4259d7	2089
Kojto	101:7cff1c4259d7	2090	/**
Kojto	101:7cff1c4259d7	2091	* @brief Disables the rising edge trigger to the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2092	* @retval None
Kojto	101:7cff1c4259d7	2093	*/
Kojto	110:165afa46840b	2094	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2095
Kojto	101:7cff1c4259d7	2096	/**
Kojto	101:7cff1c4259d7	2097	* @brief Enables falling edge trigger to the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2098	* @retval None
Kojto	101:7cff1c4259d7	2099	*/
Kojto	101:7cff1c4259d7	2100	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2101
Kojto	101:7cff1c4259d7	2102	/**
Kojto	101:7cff1c4259d7	2103	* @brief Disables falling edge trigger to the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2104	* @retval None
Kojto	101:7cff1c4259d7	2105	*/
Kojto	101:7cff1c4259d7	2106	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2107
Kojto	101:7cff1c4259d7	2108	/**
Kojto	101:7cff1c4259d7	2109	* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2110	* @retval None
Kojto	101:7cff1c4259d7	2111	*/
Kojto	101:7cff1c4259d7	2112	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
Kojto	101:7cff1c4259d7	2113	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP
Kojto	101:7cff1c4259d7	2114
Kojto	101:7cff1c4259d7	2115	/**
Kojto	101:7cff1c4259d7	2116	* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
Kojto	101:7cff1c4259d7	2117	* @retval None
Kojto	101:7cff1c4259d7	2118	*/
Kojto	101:7cff1c4259d7	2119	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto	101:7cff1c4259d7	2120	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	101:7cff1c4259d7	2121
Kojto	101:7cff1c4259d7	2122	/**
Kojto	101:7cff1c4259d7	2123	* @brief Generate a Software interrupt on selected EXTI line.
Kojto	101:7cff1c4259d7	2124	* @retval None.
Kojto	101:7cff1c4259d7	2125	*/
Kojto	101:7cff1c4259d7	2126	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
Kojto	101:7cff1c4259d7	2127
Kojto	101:7cff1c4259d7	2128	/**
Kojto	101:7cff1c4259d7	2129	* @}
Kojto	101:7cff1c4259d7	2130	*/
Kojto	101:7cff1c4259d7	2131	/* Exported functions --------------------------------------------------------*/
Kojto	101:7cff1c4259d7	2132
Kojto	101:7cff1c4259d7	2133	/** @addtogroup ETH_Exported_Functions
Kojto	101:7cff1c4259d7	2134	* @{
Kojto	101:7cff1c4259d7	2135	*/
Kojto	101:7cff1c4259d7	2136
Kojto	101:7cff1c4259d7	2137	/* Initialization and de-initialization functions ****************************/
Kojto	101:7cff1c4259d7	2138
Kojto	101:7cff1c4259d7	2139	/** @addtogroup ETH_Exported_Functions_Group1
Kojto	101:7cff1c4259d7	2140	* @{
Kojto	101:7cff1c4259d7	2141	*/
Kojto	101:7cff1c4259d7	2142	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2143	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2144	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2145	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2146	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
Kojto	101:7cff1c4259d7	2147	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
Kojto	101:7cff1c4259d7	2148
Kojto	101:7cff1c4259d7	2149	/**
Kojto	101:7cff1c4259d7	2150	* @}
Kojto	101:7cff1c4259d7	2151	*/
Kojto	101:7cff1c4259d7	2152	/* IO operation functions ****************************************************/
Kojto	101:7cff1c4259d7	2153
Kojto	101:7cff1c4259d7	2154	/** @addtogroup ETH_Exported_Functions_Group2
Kojto	101:7cff1c4259d7	2155	* @{
Kojto	101:7cff1c4259d7	2156	*/
Kojto	101:7cff1c4259d7	2157	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
Kojto	101:7cff1c4259d7	2158	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2159	/* Communication with PHY functions*/
Kojto	101:7cff1c4259d7	2160	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
Kojto	101:7cff1c4259d7	2161	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
Kojto	101:7cff1c4259d7	2162	/* Non-Blocking mode: Interrupt */
Kojto	101:7cff1c4259d7	2163	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2164	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2165	/* Callback in non blocking modes (Interrupt) */
Kojto	101:7cff1c4259d7	2166	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2167	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2168	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2169	/**
Kojto	101:7cff1c4259d7	2170	* @}
Kojto	101:7cff1c4259d7	2171	*/
Kojto	101:7cff1c4259d7	2172
Kojto	101:7cff1c4259d7	2173	/* Peripheral Control functions **********************************************/
Kojto	101:7cff1c4259d7	2174
Kojto	101:7cff1c4259d7	2175	/** @addtogroup ETH_Exported_Functions_Group3
Kojto	101:7cff1c4259d7	2176	* @{
Kojto	101:7cff1c4259d7	2177	*/
Kojto	101:7cff1c4259d7	2178
Kojto	101:7cff1c4259d7	2179	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2180	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2181	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
Kojto	101:7cff1c4259d7	2182	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
Kojto	101:7cff1c4259d7	2183	/**
Kojto	101:7cff1c4259d7	2184	* @}
Kojto	101:7cff1c4259d7	2185	*/
Kojto	101:7cff1c4259d7	2186
Kojto	101:7cff1c4259d7	2187	/* Peripheral State functions ************************************************/
Kojto	101:7cff1c4259d7	2188
Kojto	101:7cff1c4259d7	2189	/** @addtogroup ETH_Exported_Functions_Group4
Kojto	101:7cff1c4259d7	2190	* @{
Kojto	101:7cff1c4259d7	2191	*/
Kojto	101:7cff1c4259d7	2192	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
Kojto	101:7cff1c4259d7	2193	/**
Kojto	101:7cff1c4259d7	2194	* @}
Kojto	101:7cff1c4259d7	2195	*/
Kojto	101:7cff1c4259d7	2196
Kojto	101:7cff1c4259d7	2197	/**
Kojto	101:7cff1c4259d7	2198	* @}
Kojto	101:7cff1c4259d7	2199	*/
Kojto	101:7cff1c4259d7	2200
Kojto	101:7cff1c4259d7	2201	/**
Kojto	101:7cff1c4259d7	2202	* @}
Kojto	101:7cff1c4259d7	2203	*/
Kojto	101:7cff1c4259d7	2204
Kojto	101:7cff1c4259d7	2205	/**
Kojto	101:7cff1c4259d7	2206	* @}
Kojto	101:7cff1c4259d7	2207	*/
Kojto	101:7cff1c4259d7	2208
Kojto	110:165afa46840b	2209	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\|\
Kojto	110:165afa46840b	2210	STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	101:7cff1c4259d7	2211
Kojto	101:7cff1c4259d7	2212	#ifdef __cplusplus
Kojto	101:7cff1c4259d7	2213	}
Kojto	101:7cff1c4259d7	2214	#endif
Kojto	101:7cff1c4259d7	2215
Kojto	101:7cff1c4259d7	2216	#endif /* __STM32F4xx_HAL_ETH_H */
Kojto	101:7cff1c4259d7	2217
Kojto	101:7cff1c4259d7	2218
Kojto	101:7cff1c4259d7	2219	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_eth.h@121:672067c3ada4, 2016-04-14 (annotated)

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