Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_MAXWSNENV/pwrman_regs.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
99:dbbf35b96557 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /*******************************************************************************
Kojto 99:dbbf35b96557 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Kojto 99:dbbf35b96557 3 *
Kojto 99:dbbf35b96557 4 * Permission is hereby granted, free of charge, to any person obtaining a
Kojto 99:dbbf35b96557 5 * copy of this software and associated documentation files (the "Software"),
Kojto 99:dbbf35b96557 6 * to deal in the Software without restriction, including without limitation
Kojto 99:dbbf35b96557 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Kojto 99:dbbf35b96557 8 * and/or sell copies of the Software, and to permit persons to whom the
Kojto 99:dbbf35b96557 9 * Software is furnished to do so, subject to the following conditions:
Kojto 99:dbbf35b96557 10 *
Kojto 99:dbbf35b96557 11 * The above copyright notice and this permission notice shall be included
Kojto 99:dbbf35b96557 12 * in all copies or substantial portions of the Software.
Kojto 99:dbbf35b96557 13 *
Kojto 99:dbbf35b96557 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Kojto 99:dbbf35b96557 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Kojto 99:dbbf35b96557 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Kojto 99:dbbf35b96557 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Kojto 99:dbbf35b96557 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Kojto 99:dbbf35b96557 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Kojto 99:dbbf35b96557 20 * OTHER DEALINGS IN THE SOFTWARE.
Kojto 99:dbbf35b96557 21 *
Kojto 99:dbbf35b96557 22 * Except as contained in this notice, the name of Maxim Integrated
Kojto 99:dbbf35b96557 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Kojto 99:dbbf35b96557 24 * Products, Inc. Branding Policy.
Kojto 99:dbbf35b96557 25 *
Kojto 99:dbbf35b96557 26 * The mere transfer of this software does not imply any licenses
Kojto 99:dbbf35b96557 27 * of trade secrets, proprietary technology, copyrights, patents,
Kojto 99:dbbf35b96557 28 * trademarks, maskwork rights, or any other form of intellectual
Kojto 99:dbbf35b96557 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Kojto 99:dbbf35b96557 30 * ownership rights.
Kojto 99:dbbf35b96557 31 *******************************************************************************
Kojto 99:dbbf35b96557 32 */
Kojto 99:dbbf35b96557 33
Kojto 99:dbbf35b96557 34 #ifndef _MXC_PWRMAN_REGS_H_
Kojto 99:dbbf35b96557 35 #define _MXC_PWRMAN_REGS_H_
Kojto 99:dbbf35b96557 36
Kojto 99:dbbf35b96557 37 #ifdef __cplusplus
Kojto 99:dbbf35b96557 38 extern "C" {
Kojto 99:dbbf35b96557 39 #endif
Kojto 99:dbbf35b96557 40
Kojto 99:dbbf35b96557 41 #include <stdint.h>
Kojto 99:dbbf35b96557 42
Kojto 99:dbbf35b96557 43 /**
Kojto 99:dbbf35b96557 44 * @file pwrman_regs.h
Kojto 99:dbbf35b96557 45 * @addtogroup pwrman PWRMAN
Kojto 99:dbbf35b96557 46 * @{
Kojto 99:dbbf35b96557 47 */
Kojto 99:dbbf35b96557 48
Kojto 99:dbbf35b96557 49 /**
Kojto 99:dbbf35b96557 50 * @brief Defines PAD Modes for Wake Up Detection.
Kojto 99:dbbf35b96557 51 */
Kojto 99:dbbf35b96557 52 typedef enum {
Kojto 99:dbbf35b96557 53 /** WUD Mode for Selected PAD = Clear/Activate */
Kojto 99:dbbf35b96557 54 MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
Kojto 99:dbbf35b96557 55 /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
Kojto 99:dbbf35b96557 56 MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
Kojto 99:dbbf35b96557 57 /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
Kojto 99:dbbf35b96557 58 MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
Kojto 99:dbbf35b96557 59 /** WUD Mode for Selected PAD = No pad state change */
Kojto 99:dbbf35b96557 60 MXC_E_PWRMAN_PAD_MODE_NONE
Kojto 99:dbbf35b96557 61 } mxc_pwrman_pad_mode_t;
Kojto 99:dbbf35b96557 62
Kojto 99:dbbf35b96557 63 /* Offset Register Description
Kojto 99:dbbf35b96557 64 ====== =========================================== */
Kojto 99:dbbf35b96557 65 typedef struct {
Kojto 99:dbbf35b96557 66 __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
Kojto 99:dbbf35b96557 67 __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
Kojto 99:dbbf35b96557 68 __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
Kojto 99:dbbf35b96557 69 __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
Kojto 99:dbbf35b96557 70 __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
Kojto 99:dbbf35b96557 71 __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
Kojto 99:dbbf35b96557 72 __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
Kojto 99:dbbf35b96557 73 __I uint32_t rsv001C[5]; /* 0x001C */
Kojto 99:dbbf35b96557 74
Kojto 99:dbbf35b96557 75 __IO uint32_t wud_seen0; /* 0x0030 Wake-up Detect Status for P0/P1/P2/P3 */
Kojto 99:dbbf35b96557 76 __IO uint32_t wud_seen1; /* 0x0034 Wake-up Detect Status for P4/P5/P6/P7 */
Kojto 99:dbbf35b96557 77 __IO uint32_t die_type; /* 0x0038 Die ID Register (Device Type) */
Kojto 99:dbbf35b96557 78 __IO uint32_t base_part_num; /* 0x003C Base Part Number */
Kojto 99:dbbf35b96557 79 __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
Kojto 99:dbbf35b96557 80 __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
Kojto 99:dbbf35b96557 81 __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
Kojto 99:dbbf35b96557 82 } mxc_pwrman_regs_t;
Kojto 99:dbbf35b96557 83
Kojto 99:dbbf35b96557 84 /*
Kojto 99:dbbf35b96557 85 Register offsets for module PWRMAN.
Kojto 99:dbbf35b96557 86 */
Kojto 99:dbbf35b96557 87 #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
Kojto 99:dbbf35b96557 88 #define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
Kojto 99:dbbf35b96557 89 #define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
Kojto 99:dbbf35b96557 90 #define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
Kojto 99:dbbf35b96557 91 #define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
Kojto 99:dbbf35b96557 92 #define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
Kojto 99:dbbf35b96557 93 #define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
Kojto 99:dbbf35b96557 94 #define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x00000030UL)
Kojto 99:dbbf35b96557 95 #define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000034UL)
Kojto 99:dbbf35b96557 96 #define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
Kojto 99:dbbf35b96557 97 #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
Kojto 99:dbbf35b96557 98 #define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
Kojto 99:dbbf35b96557 99 #define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
Kojto 99:dbbf35b96557 100 #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
Kojto 99:dbbf35b96557 101
Kojto 99:dbbf35b96557 102 /*
Kojto 99:dbbf35b96557 103 Field positions and masks for module PWRMAN.
Kojto 99:dbbf35b96557 104 */
Kojto 99:dbbf35b96557 105 #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS 0
Kojto 99:dbbf35b96557 106 #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS))
Kojto 99:dbbf35b96557 107 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS 1
Kojto 99:dbbf35b96557 108 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS))
Kojto 99:dbbf35b96557 109 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
Kojto 99:dbbf35b96557 110 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
Kojto 99:dbbf35b96557 111 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
Kojto 99:dbbf35b96557 112 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
Kojto 99:dbbf35b96557 113 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
Kojto 99:dbbf35b96557 114 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
Kojto 99:dbbf35b96557 115 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
Kojto 99:dbbf35b96557 116 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
Kojto 99:dbbf35b96557 117 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
Kojto 99:dbbf35b96557 118 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
Kojto 99:dbbf35b96557 119 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
Kojto 99:dbbf35b96557 120 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
Kojto 99:dbbf35b96557 121 #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS 12
Kojto 99:dbbf35b96557 122 #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS))
Kojto 99:dbbf35b96557 123 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
Kojto 99:dbbf35b96557 124 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
Kojto 99:dbbf35b96557 125 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 17
Kojto 99:dbbf35b96557 126 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
Kojto 99:dbbf35b96557 127 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 18
Kojto 99:dbbf35b96557 128 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
Kojto 99:dbbf35b96557 129 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 19
Kojto 99:dbbf35b96557 130 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
Kojto 99:dbbf35b96557 131 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 20
Kojto 99:dbbf35b96557 132 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
Kojto 99:dbbf35b96557 133 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
Kojto 99:dbbf35b96557 134 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
Kojto 99:dbbf35b96557 135 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
Kojto 99:dbbf35b96557 136 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
Kojto 99:dbbf35b96557 137 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
Kojto 99:dbbf35b96557 138 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
Kojto 99:dbbf35b96557 139
Kojto 99:dbbf35b96557 140 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 0
Kojto 99:dbbf35b96557 141 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
Kojto 99:dbbf35b96557 142 #define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS 1
Kojto 99:dbbf35b96557 143 #define MXC_F_PWRMAN_INTFL_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS))
Kojto 99:dbbf35b96557 144 #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
Kojto 99:dbbf35b96557 145 #define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
Kojto 99:dbbf35b96557 146 #define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS 3
Kojto 99:dbbf35b96557 147 #define MXC_F_PWRMAN_INTFL_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS))
Kojto 99:dbbf35b96557 148 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 4
Kojto 99:dbbf35b96557 149 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
Kojto 99:dbbf35b96557 150
Kojto 99:dbbf35b96557 151 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 0
Kojto 99:dbbf35b96557 152 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
Kojto 99:dbbf35b96557 153 #define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS 1
Kojto 99:dbbf35b96557 154 #define MXC_F_PWRMAN_INTEN_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS))
Kojto 99:dbbf35b96557 155 #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
Kojto 99:dbbf35b96557 156 #define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
Kojto 99:dbbf35b96557 157 #define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS 3
Kojto 99:dbbf35b96557 158 #define MXC_F_PWRMAN_INTEN_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS))
Kojto 99:dbbf35b96557 159 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 4
Kojto 99:dbbf35b96557 160 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
Kojto 99:dbbf35b96557 161
Kojto 99:dbbf35b96557 162 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 0
Kojto 99:dbbf35b96557 163 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
Kojto 99:dbbf35b96557 164 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS 1
Kojto 99:dbbf35b96557 165 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS))
Kojto 99:dbbf35b96557 166 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
Kojto 99:dbbf35b96557 167 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
Kojto 99:dbbf35b96557 168 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS 3
Kojto 99:dbbf35b96557 169 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS))
Kojto 99:dbbf35b96557 170 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 4
Kojto 99:dbbf35b96557 171 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
Kojto 99:dbbf35b96557 172
Kojto 99:dbbf35b96557 173 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
Kojto 99:dbbf35b96557 174 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
Kojto 99:dbbf35b96557 175 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
Kojto 99:dbbf35b96557 176 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
Kojto 99:dbbf35b96557 177 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
Kojto 99:dbbf35b96557 178 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
Kojto 99:dbbf35b96557 179
Kojto 99:dbbf35b96557 180 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
Kojto 99:dbbf35b96557 181 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
Kojto 99:dbbf35b96557 182 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
Kojto 99:dbbf35b96557 183 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
Kojto 99:dbbf35b96557 184 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
Kojto 99:dbbf35b96557 185 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
Kojto 99:dbbf35b96557 186 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
Kojto 99:dbbf35b96557 187 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
Kojto 99:dbbf35b96557 188 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
Kojto 99:dbbf35b96557 189 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
Kojto 99:dbbf35b96557 190 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
Kojto 99:dbbf35b96557 191 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
Kojto 99:dbbf35b96557 192 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
Kojto 99:dbbf35b96557 193 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
Kojto 99:dbbf35b96557 194 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
Kojto 99:dbbf35b96557 195 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
Kojto 99:dbbf35b96557 196 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
Kojto 99:dbbf35b96557 197 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
Kojto 99:dbbf35b96557 198 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
Kojto 99:dbbf35b96557 199 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
Kojto 99:dbbf35b96557 200 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
Kojto 99:dbbf35b96557 201 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
Kojto 99:dbbf35b96557 202 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
Kojto 99:dbbf35b96557 203 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
Kojto 99:dbbf35b96557 204 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
Kojto 99:dbbf35b96557 205 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
Kojto 99:dbbf35b96557 206 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
Kojto 99:dbbf35b96557 207 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
Kojto 99:dbbf35b96557 208 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
Kojto 99:dbbf35b96557 209 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
Kojto 99:dbbf35b96557 210 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
Kojto 99:dbbf35b96557 211 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
Kojto 99:dbbf35b96557 212 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
Kojto 99:dbbf35b96557 213 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
Kojto 99:dbbf35b96557 214 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
Kojto 99:dbbf35b96557 215 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
Kojto 99:dbbf35b96557 216 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
Kojto 99:dbbf35b96557 217 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
Kojto 99:dbbf35b96557 218 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
Kojto 99:dbbf35b96557 219 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
Kojto 99:dbbf35b96557 220 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
Kojto 99:dbbf35b96557 221 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
Kojto 99:dbbf35b96557 222 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
Kojto 99:dbbf35b96557 223 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
Kojto 99:dbbf35b96557 224 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
Kojto 99:dbbf35b96557 225 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
Kojto 99:dbbf35b96557 226 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
Kojto 99:dbbf35b96557 227 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
Kojto 99:dbbf35b96557 228 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
Kojto 99:dbbf35b96557 229 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
Kojto 99:dbbf35b96557 230 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
Kojto 99:dbbf35b96557 231 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
Kojto 99:dbbf35b96557 232 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
Kojto 99:dbbf35b96557 233 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
Kojto 99:dbbf35b96557 234 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
Kojto 99:dbbf35b96557 235 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
Kojto 99:dbbf35b96557 236 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
Kojto 99:dbbf35b96557 237 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
Kojto 99:dbbf35b96557 238 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
Kojto 99:dbbf35b96557 239 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
Kojto 99:dbbf35b96557 240 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
Kojto 99:dbbf35b96557 241 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
Kojto 99:dbbf35b96557 242 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
Kojto 99:dbbf35b96557 243 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
Kojto 99:dbbf35b96557 244
Kojto 99:dbbf35b96557 245 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
Kojto 99:dbbf35b96557 246 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
Kojto 99:dbbf35b96557 247 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
Kojto 99:dbbf35b96557 248 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
Kojto 99:dbbf35b96557 249 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
Kojto 99:dbbf35b96557 250 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
Kojto 99:dbbf35b96557 251 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
Kojto 99:dbbf35b96557 252 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
Kojto 99:dbbf35b96557 253 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
Kojto 99:dbbf35b96557 254 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
Kojto 99:dbbf35b96557 255 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
Kojto 99:dbbf35b96557 256 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
Kojto 99:dbbf35b96557 257 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
Kojto 99:dbbf35b96557 258 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
Kojto 99:dbbf35b96557 259 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
Kojto 99:dbbf35b96557 260 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
Kojto 99:dbbf35b96557 261 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
Kojto 99:dbbf35b96557 262 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
Kojto 99:dbbf35b96557 263 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
Kojto 99:dbbf35b96557 264 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
Kojto 99:dbbf35b96557 265 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
Kojto 99:dbbf35b96557 266 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
Kojto 99:dbbf35b96557 267 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
Kojto 99:dbbf35b96557 268 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
Kojto 99:dbbf35b96557 269 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
Kojto 99:dbbf35b96557 270 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
Kojto 99:dbbf35b96557 271 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
Kojto 99:dbbf35b96557 272 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
Kojto 99:dbbf35b96557 273 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
Kojto 99:dbbf35b96557 274 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
Kojto 99:dbbf35b96557 275 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
Kojto 99:dbbf35b96557 276 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
Kojto 99:dbbf35b96557 277 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
Kojto 99:dbbf35b96557 278 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
Kojto 99:dbbf35b96557 279 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17
Kojto 99:dbbf35b96557 280 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
Kojto 99:dbbf35b96557 281 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18
Kojto 99:dbbf35b96557 282 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
Kojto 99:dbbf35b96557 283 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19
Kojto 99:dbbf35b96557 284 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
Kojto 99:dbbf35b96557 285 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20
Kojto 99:dbbf35b96557 286 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
Kojto 99:dbbf35b96557 287 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21
Kojto 99:dbbf35b96557 288 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
Kojto 99:dbbf35b96557 289 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22
Kojto 99:dbbf35b96557 290 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
Kojto 99:dbbf35b96557 291 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23
Kojto 99:dbbf35b96557 292 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
Kojto 99:dbbf35b96557 293 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24
Kojto 99:dbbf35b96557 294 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
Kojto 99:dbbf35b96557 295 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25
Kojto 99:dbbf35b96557 296 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
Kojto 99:dbbf35b96557 297 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26
Kojto 99:dbbf35b96557 298 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
Kojto 99:dbbf35b96557 299 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27
Kojto 99:dbbf35b96557 300 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
Kojto 99:dbbf35b96557 301 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28
Kojto 99:dbbf35b96557 302 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
Kojto 99:dbbf35b96557 303 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29
Kojto 99:dbbf35b96557 304 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
Kojto 99:dbbf35b96557 305 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30
Kojto 99:dbbf35b96557 306 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
Kojto 99:dbbf35b96557 307 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31
Kojto 99:dbbf35b96557 308 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
Kojto 99:dbbf35b96557 309
Kojto 99:dbbf35b96557 310 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
Kojto 99:dbbf35b96557 311 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
Kojto 99:dbbf35b96557 312 #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS 28
Kojto 99:dbbf35b96557 313 #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS))
Kojto 99:dbbf35b96557 314
Kojto 99:dbbf35b96557 315 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
Kojto 99:dbbf35b96557 316 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
Kojto 99:dbbf35b96557 317 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
Kojto 99:dbbf35b96557 318 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
Kojto 99:dbbf35b96557 319
Kojto 99:dbbf35b96557 320 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
Kojto 99:dbbf35b96557 321 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
Kojto 99:dbbf35b96557 322 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
Kojto 99:dbbf35b96557 323 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
Kojto 99:dbbf35b96557 324
Kojto 99:dbbf35b96557 325 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 0
Kojto 99:dbbf35b96557 326 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
Kojto 99:dbbf35b96557 327 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 1
Kojto 99:dbbf35b96557 328 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
Kojto 99:dbbf35b96557 329 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 2
Kojto 99:dbbf35b96557 330 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
Kojto 99:dbbf35b96557 331 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 3
Kojto 99:dbbf35b96557 332 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
Kojto 99:dbbf35b96557 333 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 4
Kojto 99:dbbf35b96557 334 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
Kojto 99:dbbf35b96557 335 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 5
Kojto 99:dbbf35b96557 336 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
Kojto 99:dbbf35b96557 337 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
Kojto 99:dbbf35b96557 338 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
Kojto 99:dbbf35b96557 339 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 7
Kojto 99:dbbf35b96557 340 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
Kojto 99:dbbf35b96557 341 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 8
Kojto 99:dbbf35b96557 342 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
Kojto 99:dbbf35b96557 343 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS 9
Kojto 99:dbbf35b96557 344 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS))
Kojto 99:dbbf35b96557 345 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS 10
Kojto 99:dbbf35b96557 346 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS))
Kojto 99:dbbf35b96557 347 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS 11
Kojto 99:dbbf35b96557 348 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS))
Kojto 99:dbbf35b96557 349 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS 12
Kojto 99:dbbf35b96557 350 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS))
Kojto 99:dbbf35b96557 351 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS 13
Kojto 99:dbbf35b96557 352 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS))
Kojto 99:dbbf35b96557 353 #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS 14
Kojto 99:dbbf35b96557 354 #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS))
Kojto 99:dbbf35b96557 355 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 15
Kojto 99:dbbf35b96557 356 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
Kojto 99:dbbf35b96557 357 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 16
Kojto 99:dbbf35b96557 358 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
Kojto 99:dbbf35b96557 359 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS 17
Kojto 99:dbbf35b96557 360 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS))
Kojto 99:dbbf35b96557 361 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS 18
Kojto 99:dbbf35b96557 362 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS))
Kojto 99:dbbf35b96557 363 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS 19
Kojto 99:dbbf35b96557 364 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS))
Kojto 99:dbbf35b96557 365 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 20
Kojto 99:dbbf35b96557 366 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
Kojto 99:dbbf35b96557 367 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 21
Kojto 99:dbbf35b96557 368 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
Kojto 99:dbbf35b96557 369 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
Kojto 99:dbbf35b96557 370 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
Kojto 99:dbbf35b96557 371 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 23
Kojto 99:dbbf35b96557 372 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
Kojto 99:dbbf35b96557 373 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 24
Kojto 99:dbbf35b96557 374 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
Kojto 99:dbbf35b96557 375 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 25
Kojto 99:dbbf35b96557 376 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
Kojto 99:dbbf35b96557 377
Kojto 99:dbbf35b96557 378 #ifdef __cplusplus
Kojto 99:dbbf35b96557 379 }
Kojto 99:dbbf35b96557 380 #endif
Kojto 99:dbbf35b96557 381
Kojto 99:dbbf35b96557 382 /**
Kojto 99:dbbf35b96557 383 * @}
Kojto 99:dbbf35b96557 384 */
Kojto 99:dbbf35b96557 385
Kojto 99:dbbf35b96557 386 #endif /* _MXC_PWRMAN_REGS_H_ */