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TARGET_MAX32600MBED/adc_regs.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
101:7cff1c4259d7 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /*******************************************************************************
Kojto 101:7cff1c4259d7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Kojto 101:7cff1c4259d7 3 *
Kojto 101:7cff1c4259d7 4 * Permission is hereby granted, free of charge, to any person obtaining a
Kojto 101:7cff1c4259d7 5 * copy of this software and associated documentation files (the "Software"),
Kojto 101:7cff1c4259d7 6 * to deal in the Software without restriction, including without limitation
Kojto 101:7cff1c4259d7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Kojto 101:7cff1c4259d7 8 * and/or sell copies of the Software, and to permit persons to whom the
Kojto 101:7cff1c4259d7 9 * Software is furnished to do so, subject to the following conditions:
Kojto 101:7cff1c4259d7 10 *
Kojto 101:7cff1c4259d7 11 * The above copyright notice and this permission notice shall be included
Kojto 101:7cff1c4259d7 12 * in all copies or substantial portions of the Software.
Kojto 101:7cff1c4259d7 13 *
Kojto 101:7cff1c4259d7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Kojto 101:7cff1c4259d7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Kojto 101:7cff1c4259d7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Kojto 101:7cff1c4259d7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Kojto 101:7cff1c4259d7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Kojto 101:7cff1c4259d7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Kojto 101:7cff1c4259d7 20 * OTHER DEALINGS IN THE SOFTWARE.
Kojto 101:7cff1c4259d7 21 *
Kojto 101:7cff1c4259d7 22 * Except as contained in this notice, the name of Maxim Integrated
Kojto 101:7cff1c4259d7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Kojto 101:7cff1c4259d7 24 * Products, Inc. Branding Policy.
Kojto 101:7cff1c4259d7 25 *
Kojto 101:7cff1c4259d7 26 * The mere transfer of this software does not imply any licenses
Kojto 101:7cff1c4259d7 27 * of trade secrets, proprietary technology, copyrights, patents,
Kojto 101:7cff1c4259d7 28 * trademarks, maskwork rights, or any other form of intellectual
Kojto 101:7cff1c4259d7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Kojto 101:7cff1c4259d7 30 * ownership rights.
Kojto 101:7cff1c4259d7 31 *******************************************************************************
Kojto 101:7cff1c4259d7 32 */
Kojto 101:7cff1c4259d7 33
Kojto 101:7cff1c4259d7 34 #ifndef _MXC_ADC_REGS_H
Kojto 101:7cff1c4259d7 35 #define _MXC_ADC_REGS_H
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 38 extern "C" {
Kojto 101:7cff1c4259d7 39 #endif
Kojto 101:7cff1c4259d7 40
Kojto 101:7cff1c4259d7 41 #include <stdint.h>
Kojto 101:7cff1c4259d7 42
Kojto 101:7cff1c4259d7 43 /**
Kojto 101:7cff1c4259d7 44 * @file adc_regs.h
Kojto 101:7cff1c4259d7 45 * @addtogroup adc ADC
Kojto 101:7cff1c4259d7 46 * @{
Kojto 101:7cff1c4259d7 47 */
Kojto 101:7cff1c4259d7 48
Kojto 101:7cff1c4259d7 49 /**
Kojto 101:7cff1c4259d7 50 * @brief Defines ADC Modes.
Kojto 101:7cff1c4259d7 51 */
Kojto 101:7cff1c4259d7 52 typedef enum {
Kojto 101:7cff1c4259d7 53 /** Single Mode Full Rate */
Kojto 101:7cff1c4259d7 54 MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
Kojto 101:7cff1c4259d7 55 /** Single Mode Low Power */
Kojto 101:7cff1c4259d7 56 MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
Kojto 101:7cff1c4259d7 57 /** Continuous Mode Full Rate */
Kojto 101:7cff1c4259d7 58 MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
Kojto 101:7cff1c4259d7 59 /** Continuous Mode Low Power */
Kojto 101:7cff1c4259d7 60 MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
Kojto 101:7cff1c4259d7 61 /** Single Mode Full Rate with Scan Enabled */
Kojto 101:7cff1c4259d7 62 MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
Kojto 101:7cff1c4259d7 63 /** Single Mode Low Power with Scan Enabled */
Kojto 101:7cff1c4259d7 64 MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
Kojto 101:7cff1c4259d7 65 /** Continuous Mode Full Rate with Scan Enabled */
Kojto 101:7cff1c4259d7 66 MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
Kojto 101:7cff1c4259d7 67 /** Continuous Mode Low Power with Scan Enabled */
Kojto 101:7cff1c4259d7 68 MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
Kojto 101:7cff1c4259d7 69 } mxc_adc_mode_t;
Kojto 101:7cff1c4259d7 70
Kojto 101:7cff1c4259d7 71 /**
Kojto 101:7cff1c4259d7 72 * @brief Defines ADC Range Control.
Kojto 101:7cff1c4259d7 73 */
Kojto 101:7cff1c4259d7 74 typedef enum {
Kojto 101:7cff1c4259d7 75 /** Bi-polar Operation (-Vref/2 -> Vref/2) */
Kojto 101:7cff1c4259d7 76 MXC_E_ADC_RANGE_HALF = 0,
Kojto 101:7cff1c4259d7 77 /** Bi-polar Operation (-Vref -> Vref) */
Kojto 101:7cff1c4259d7 78 MXC_E_ADC_RANGE_FULL
Kojto 101:7cff1c4259d7 79 } mxc_adc_range_t;
Kojto 101:7cff1c4259d7 80
Kojto 101:7cff1c4259d7 81 /**
Kojto 101:7cff1c4259d7 82 * @brief Defines ADC Bipolar operation.
Kojto 101:7cff1c4259d7 83 */
Kojto 101:7cff1c4259d7 84 typedef enum {
Kojto 101:7cff1c4259d7 85 /** Uni-polar operation (0 -> Vref) */
Kojto 101:7cff1c4259d7 86 MXC_E_ADC_BI_POL_UNIPOLAR = 0,
Kojto 101:7cff1c4259d7 87 /** Bi-polar operation see ADC Range Control */
Kojto 101:7cff1c4259d7 88 MXC_E_ADC_BI_POL_BIPOLAR
Kojto 101:7cff1c4259d7 89 } mxc_adc_bi_pol_t;
Kojto 101:7cff1c4259d7 90
Kojto 101:7cff1c4259d7 91 /**
Kojto 101:7cff1c4259d7 92 * @brief Defines Decimation Filter Modes.
Kojto 101:7cff1c4259d7 93 */
Kojto 101:7cff1c4259d7 94 typedef enum {
Kojto 101:7cff1c4259d7 95 /** Decimation Filter ByPassed */
Kojto 101:7cff1c4259d7 96 MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
Kojto 101:7cff1c4259d7 97 /** Output Average Only*/
Kojto 101:7cff1c4259d7 98 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
Kojto 101:7cff1c4259d7 99 /** Output Average and Raw Data (Test Mode Only) */
Kojto 101:7cff1c4259d7 100 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
Kojto 101:7cff1c4259d7 101 } mxc_adc_avg_mode_t;
Kojto 101:7cff1c4259d7 102
Kojto 101:7cff1c4259d7 103 /**
Kojto 101:7cff1c4259d7 104 * @brief Defines ADC StartMode Modes.
Kojto 101:7cff1c4259d7 105 */
Kojto 101:7cff1c4259d7 106 typedef enum {
Kojto 101:7cff1c4259d7 107 /** StarMode via Software */
Kojto 101:7cff1c4259d7 108 MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
Kojto 101:7cff1c4259d7 109 /** StarMode via PulseTrain */
Kojto 101:7cff1c4259d7 110 MXC_E_ADC_STRT_MODE_PULSETRAIN
Kojto 101:7cff1c4259d7 111 } mxc_adc_strt_mode_t;
Kojto 101:7cff1c4259d7 112
Kojto 101:7cff1c4259d7 113 /**
Kojto 101:7cff1c4259d7 114 * @brief Defines Mux Channel Select for the Positive Input to the ADC.
Kojto 101:7cff1c4259d7 115 */
Kojto 101:7cff1c4259d7 116 typedef enum {
Kojto 101:7cff1c4259d7 117 /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */
Kojto 101:7cff1c4259d7 118 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
Kojto 101:7cff1c4259d7 119 /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */
Kojto 101:7cff1c4259d7 120 MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
Kojto 101:7cff1c4259d7 121 /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
Kojto 101:7cff1c4259d7 122 MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
Kojto 101:7cff1c4259d7 123 /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
Kojto 101:7cff1c4259d7 124 MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
Kojto 101:7cff1c4259d7 125 /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
Kojto 101:7cff1c4259d7 126 MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
Kojto 101:7cff1c4259d7 127 /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */
Kojto 101:7cff1c4259d7 128 MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
Kojto 101:7cff1c4259d7 129 /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */
Kojto 101:7cff1c4259d7 130 MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
Kojto 101:7cff1c4259d7 131 /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */
Kojto 101:7cff1c4259d7 132 MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
Kojto 101:7cff1c4259d7 133 /** Single Mode Input AIN8+ */
Kojto 101:7cff1c4259d7 134 MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
Kojto 101:7cff1c4259d7 135 /** Single Mode Input AIN9+ */
Kojto 101:7cff1c4259d7 136 MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
Kojto 101:7cff1c4259d7 137 /** Single Mode Input AIN10+ */
Kojto 101:7cff1c4259d7 138 MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
Kojto 101:7cff1c4259d7 139 /** Single Mode Input AIN11+ */
Kojto 101:7cff1c4259d7 140 MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
Kojto 101:7cff1c4259d7 141 /** Single Mode Input AIN12+ */
Kojto 101:7cff1c4259d7 142 MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
Kojto 101:7cff1c4259d7 143 /** Single Mode Input AIN13+ */
Kojto 101:7cff1c4259d7 144 MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
Kojto 101:7cff1c4259d7 145 /** Single Mode Input AIN14+ */
Kojto 101:7cff1c4259d7 146 MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
Kojto 101:7cff1c4259d7 147 /** Single Mode Input AIN15+ */
Kojto 101:7cff1c4259d7 148 MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
Kojto 101:7cff1c4259d7 149 /** Positive Input VSSADC */
Kojto 101:7cff1c4259d7 150 MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
Kojto 101:7cff1c4259d7 151 /** Positive Input TMON_R */
Kojto 101:7cff1c4259d7 152 MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
Kojto 101:7cff1c4259d7 153 /** Positive Input VDDA/4 */
Kojto 101:7cff1c4259d7 154 MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
Kojto 101:7cff1c4259d7 155 /** Positive Input PWRMAN_TST */
Kojto 101:7cff1c4259d7 156 MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
Kojto 101:7cff1c4259d7 157 /** Positive Input Ain0Div */
Kojto 101:7cff1c4259d7 158 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
Kojto 101:7cff1c4259d7 159 /** Positive Input OpAmp OUTA */
Kojto 101:7cff1c4259d7 160 MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
Kojto 101:7cff1c4259d7 161 /** Positive Input OpAmp OUTB */
Kojto 101:7cff1c4259d7 162 MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
Kojto 101:7cff1c4259d7 163 /** Positive Input OpAmp OUTC */
Kojto 101:7cff1c4259d7 164 MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
Kojto 101:7cff1c4259d7 165 /** Positive Input OpAmp OUTD */
Kojto 101:7cff1c4259d7 166 MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
Kojto 101:7cff1c4259d7 167 /** Positive INA+ */
Kojto 101:7cff1c4259d7 168 MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
Kojto 101:7cff1c4259d7 169 /** Positive SNO_or */
Kojto 101:7cff1c4259d7 170 MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
Kojto 101:7cff1c4259d7 171 /** Positive SCM_or */
Kojto 101:7cff1c4259d7 172 MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
Kojto 101:7cff1c4259d7 173 /** Positive TPROBE_sense */
Kojto 101:7cff1c4259d7 174 MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
Kojto 101:7cff1c4259d7 175 /** Positive VREFDAC */
Kojto 101:7cff1c4259d7 176 MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
Kojto 101:7cff1c4259d7 177 /** Positive VREFADJ */
Kojto 101:7cff1c4259d7 178 MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
Kojto 101:7cff1c4259d7 179 /** Positive Vdd3xtal */
Kojto 101:7cff1c4259d7 180 MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
Kojto 101:7cff1c4259d7 181 } mxc_adc_pga_mux_ch_sel_t;
Kojto 101:7cff1c4259d7 182
Kojto 101:7cff1c4259d7 183 /**
Kojto 101:7cff1c4259d7 184 * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
Kojto 101:7cff1c4259d7 185 */
Kojto 101:7cff1c4259d7 186 typedef enum {
Kojto 101:7cff1c4259d7 187 /** Differential Mode Disabled */
Kojto 101:7cff1c4259d7 188 MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
Kojto 101:7cff1c4259d7 189 /** Differential Mode Enabled */
Kojto 101:7cff1c4259d7 190 MXC_E_ADC_PGA_MUX_DIFF_ENABLE
Kojto 101:7cff1c4259d7 191 } mxc_adc_pga_mux_diff_t;
Kojto 101:7cff1c4259d7 192
Kojto 101:7cff1c4259d7 193 /**
Kojto 101:7cff1c4259d7 194 * @brief Defines the PGA Gain Options.
Kojto 101:7cff1c4259d7 195 */
Kojto 101:7cff1c4259d7 196 typedef enum {
Kojto 101:7cff1c4259d7 197 /** PGA Gain = 1 */
Kojto 101:7cff1c4259d7 198 MXC_E_ADC_PGA_GAIN_1 = 0,
Kojto 101:7cff1c4259d7 199 /** PGA Gain = 2 */
Kojto 101:7cff1c4259d7 200 MXC_E_ADC_PGA_GAIN_2,
Kojto 101:7cff1c4259d7 201 /** PGA Gain = 4 */
Kojto 101:7cff1c4259d7 202 MXC_E_ADC_PGA_GAIN_4,
Kojto 101:7cff1c4259d7 203 /** PGA Gain = 8 */
Kojto 101:7cff1c4259d7 204 MXC_E_ADC_PGA_GAIN_8,
Kojto 101:7cff1c4259d7 205 } mxc_adc_pga_gain_t;
Kojto 101:7cff1c4259d7 206
Kojto 101:7cff1c4259d7 207 /**
Kojto 101:7cff1c4259d7 208 * @brief Defines the Switch Control Mode.
Kojto 101:7cff1c4259d7 209 */
Kojto 101:7cff1c4259d7 210 typedef enum {
Kojto 101:7cff1c4259d7 211 /** Switch Control Mode = Software */
Kojto 101:7cff1c4259d7 212 MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
Kojto 101:7cff1c4259d7 213 /** Switch Control Mode = Pulse Train */
Kojto 101:7cff1c4259d7 214 MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
Kojto 101:7cff1c4259d7 215 } mxc_adc_spst_sw_ctrl_t;
Kojto 101:7cff1c4259d7 216
Kojto 101:7cff1c4259d7 217 /**
Kojto 101:7cff1c4259d7 218 * @brief Defines the number of channels to scan when Scan Mode is enabled.
Kojto 101:7cff1c4259d7 219 */
Kojto 101:7cff1c4259d7 220 typedef enum {
Kojto 101:7cff1c4259d7 221 /** Number of Channels to Scan = 1 */
Kojto 101:7cff1c4259d7 222 MXC_E_ADC_SCAN_CNT_1 = 0,
Kojto 101:7cff1c4259d7 223 /** Number of Channels to Scan = 2 */
Kojto 101:7cff1c4259d7 224 MXC_E_ADC_SCAN_CNT_2,
Kojto 101:7cff1c4259d7 225 /** Number of Channels to Scan = 3 */
Kojto 101:7cff1c4259d7 226 MXC_E_ADC_SCAN_CNT_3,
Kojto 101:7cff1c4259d7 227 /** Number of Channels to Scan = 4 */
Kojto 101:7cff1c4259d7 228 MXC_E_ADC_SCAN_CNT_4,
Kojto 101:7cff1c4259d7 229 /** Number of Channels to Scan = 5 */
Kojto 101:7cff1c4259d7 230 MXC_E_ADC_SCAN_CNT_5,
Kojto 101:7cff1c4259d7 231 /** Number of Channels to Scan = 6 */
Kojto 101:7cff1c4259d7 232 MXC_E_ADC_SCAN_CNT_6,
Kojto 101:7cff1c4259d7 233 /** Number of Channels to Scan = 7 */
Kojto 101:7cff1c4259d7 234 MXC_E_ADC_SCAN_CNT_7,
Kojto 101:7cff1c4259d7 235 /** Number of Channels to Scan = 8 */
Kojto 101:7cff1c4259d7 236 MXC_E_ADC_SCAN_CNT_8,
Kojto 101:7cff1c4259d7 237 } mxc_adc_scan_cnt_t;
Kojto 101:7cff1c4259d7 238
Kojto 101:7cff1c4259d7 239 /* Offset Register Description
Kojto 101:7cff1c4259d7 240 ====== =================================================== */
Kojto 101:7cff1c4259d7 241 typedef struct {
Kojto 101:7cff1c4259d7 242 __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */
Kojto 101:7cff1c4259d7 243 __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */
Kojto 101:7cff1c4259d7 244 __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */
Kojto 101:7cff1c4259d7 245 __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */
Kojto 101:7cff1c4259d7 246 __IO uint32_t limit; /* 0x0010 ADC Limit Settings */
Kojto 101:7cff1c4259d7 247 __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */
Kojto 101:7cff1c4259d7 248 __IO uint32_t out; /* 0x0018 ADC Output Register */
Kojto 101:7cff1c4259d7 249 } mxc_adc_regs_t;
Kojto 101:7cff1c4259d7 250
Kojto 101:7cff1c4259d7 251 /* Offset Register Description
Kojto 101:7cff1c4259d7 252 ====== =================================================== */
Kojto 101:7cff1c4259d7 253 typedef struct {
Kojto 101:7cff1c4259d7 254 __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */
Kojto 101:7cff1c4259d7 255 __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */
Kojto 101:7cff1c4259d7 256 __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */
Kojto 101:7cff1c4259d7 257 __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */
Kojto 101:7cff1c4259d7 258 __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */
Kojto 101:7cff1c4259d7 259 } mxc_adccfg_regs_t;
Kojto 101:7cff1c4259d7 260
Kojto 101:7cff1c4259d7 261 typedef struct {
Kojto 101:7cff1c4259d7 262 __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */
Kojto 101:7cff1c4259d7 263 } mxc_adc_fifo_regs_t;
Kojto 101:7cff1c4259d7 264
Kojto 101:7cff1c4259d7 265 /*
Kojto 101:7cff1c4259d7 266 Register offsets for module ADC, ADCCFG, ADC_FIFO
Kojto 101:7cff1c4259d7 267 */
Kojto 101:7cff1c4259d7 268 #define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
Kojto 101:7cff1c4259d7 269 #define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL)
Kojto 101:7cff1c4259d7 270 #define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL)
Kojto 101:7cff1c4259d7 271 #define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL)
Kojto 101:7cff1c4259d7 272 #define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL)
Kojto 101:7cff1c4259d7 273 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL)
Kojto 101:7cff1c4259d7 274 #define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL)
Kojto 101:7cff1c4259d7 275
Kojto 101:7cff1c4259d7 276 #define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL)
Kojto 101:7cff1c4259d7 277 #define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL)
Kojto 101:7cff1c4259d7 278 #define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL)
Kojto 101:7cff1c4259d7 279 #define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL)
Kojto 101:7cff1c4259d7 280 #define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL)
Kojto 101:7cff1c4259d7 281 #define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL)
Kojto 101:7cff1c4259d7 282
Kojto 101:7cff1c4259d7 283 /*
Kojto 101:7cff1c4259d7 284 Field positions and masks for module ADC.
Kojto 101:7cff1c4259d7 285 */
Kojto 101:7cff1c4259d7 286 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0
Kojto 101:7cff1c4259d7 287 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
Kojto 101:7cff1c4259d7 288 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5
Kojto 101:7cff1c4259d7 289 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
Kojto 101:7cff1c4259d7 290 #define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6
Kojto 101:7cff1c4259d7 291 #define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
Kojto 101:7cff1c4259d7 292 #define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7
Kojto 101:7cff1c4259d7 293 #define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
Kojto 101:7cff1c4259d7 294 #define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8
Kojto 101:7cff1c4259d7 295 #define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
Kojto 101:7cff1c4259d7 296 #define MXC_F_ADC_CTRL0_ADC_DV_POS 9
Kojto 101:7cff1c4259d7 297 #define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
Kojto 101:7cff1c4259d7 298 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10
Kojto 101:7cff1c4259d7 299 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
Kojto 101:7cff1c4259d7 300 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11
Kojto 101:7cff1c4259d7 301 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
Kojto 101:7cff1c4259d7 302 #define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12
Kojto 101:7cff1c4259d7 303 #define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
Kojto 101:7cff1c4259d7 304 #define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13
Kojto 101:7cff1c4259d7 305 #define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
Kojto 101:7cff1c4259d7 306 #define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14
Kojto 101:7cff1c4259d7 307 #define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
Kojto 101:7cff1c4259d7 308 #define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15
Kojto 101:7cff1c4259d7 309 #define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
Kojto 101:7cff1c4259d7 310 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18
Kojto 101:7cff1c4259d7 311 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
Kojto 101:7cff1c4259d7 312 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19
Kojto 101:7cff1c4259d7 313 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
Kojto 101:7cff1c4259d7 314 #define MXC_F_ADC_CTRL0_AVG_MODE_POS 20
Kojto 101:7cff1c4259d7 315 #define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
Kojto 101:7cff1c4259d7 316 #define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22
Kojto 101:7cff1c4259d7 317 #define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
Kojto 101:7cff1c4259d7 318 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24
Kojto 101:7cff1c4259d7 319 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
Kojto 101:7cff1c4259d7 320 #define MXC_F_ADC_CTRL0_ADC_MODE_POS 28
Kojto 101:7cff1c4259d7 321 #define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
Kojto 101:7cff1c4259d7 322
Kojto 101:7cff1c4259d7 323 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0
Kojto 101:7cff1c4259d7 324 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
Kojto 101:7cff1c4259d7 325 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2
Kojto 101:7cff1c4259d7 326 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
Kojto 101:7cff1c4259d7 327 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3
Kojto 101:7cff1c4259d7 328 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
Kojto 101:7cff1c4259d7 329 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4
Kojto 101:7cff1c4259d7 330 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
Kojto 101:7cff1c4259d7 331 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5
Kojto 101:7cff1c4259d7 332 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
Kojto 101:7cff1c4259d7 333 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6
Kojto 101:7cff1c4259d7 334 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
Kojto 101:7cff1c4259d7 335 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8
Kojto 101:7cff1c4259d7 336 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
Kojto 101:7cff1c4259d7 337 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13
Kojto 101:7cff1c4259d7 338 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
Kojto 101:7cff1c4259d7 339 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14
Kojto 101:7cff1c4259d7 340 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
Kojto 101:7cff1c4259d7 341 #define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15
Kojto 101:7cff1c4259d7 342 #define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
Kojto 101:7cff1c4259d7 343 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20
Kojto 101:7cff1c4259d7 344 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
Kojto 101:7cff1c4259d7 345 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24
Kojto 101:7cff1c4259d7 346 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
Kojto 101:7cff1c4259d7 347
Kojto 101:7cff1c4259d7 348 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0
Kojto 101:7cff1c4259d7 349 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
Kojto 101:7cff1c4259d7 350 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16
Kojto 101:7cff1c4259d7 351 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
Kojto 101:7cff1c4259d7 352
Kojto 101:7cff1c4259d7 353 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0
Kojto 101:7cff1c4259d7 354 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
Kojto 101:7cff1c4259d7 355 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4
Kojto 101:7cff1c4259d7 356 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
Kojto 101:7cff1c4259d7 357 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8
Kojto 101:7cff1c4259d7 358 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
Kojto 101:7cff1c4259d7 359 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12
Kojto 101:7cff1c4259d7 360 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
Kojto 101:7cff1c4259d7 361 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16
Kojto 101:7cff1c4259d7 362 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
Kojto 101:7cff1c4259d7 363
Kojto 101:7cff1c4259d7 364 #define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0
Kojto 101:7cff1c4259d7 365 #define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
Kojto 101:7cff1c4259d7 366 #define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16
Kojto 101:7cff1c4259d7 367 #define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
Kojto 101:7cff1c4259d7 368
Kojto 101:7cff1c4259d7 369 #define MXC_F_ADC_INTR_FIFO_AF_POS 6
Kojto 101:7cff1c4259d7 370 #define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
Kojto 101:7cff1c4259d7 371 #define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7
Kojto 101:7cff1c4259d7 372 #define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
Kojto 101:7cff1c4259d7 373 #define MXC_F_ADC_INTR_HI_RNG_IF_POS 8
Kojto 101:7cff1c4259d7 374 #define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
Kojto 101:7cff1c4259d7 375 #define MXC_F_ADC_INTR_LO_RNG_IF_POS 9
Kojto 101:7cff1c4259d7 376 #define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
Kojto 101:7cff1c4259d7 377 #define MXC_F_ADC_INTR_DONE_IF_POS 10
Kojto 101:7cff1c4259d7 378 #define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
Kojto 101:7cff1c4259d7 379 #define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11
Kojto 101:7cff1c4259d7 380 #define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
Kojto 101:7cff1c4259d7 381 #define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12
Kojto 101:7cff1c4259d7 382 #define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
Kojto 101:7cff1c4259d7 383 #define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13
Kojto 101:7cff1c4259d7 384 #define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
Kojto 101:7cff1c4259d7 385 #define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14
Kojto 101:7cff1c4259d7 386 #define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
Kojto 101:7cff1c4259d7 387 #define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15
Kojto 101:7cff1c4259d7 388 #define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
Kojto 101:7cff1c4259d7 389 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16
Kojto 101:7cff1c4259d7 390 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
Kojto 101:7cff1c4259d7 391 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17
Kojto 101:7cff1c4259d7 392 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
Kojto 101:7cff1c4259d7 393 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18
Kojto 101:7cff1c4259d7 394 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
Kojto 101:7cff1c4259d7 395 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19
Kojto 101:7cff1c4259d7 396 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
Kojto 101:7cff1c4259d7 397 #define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23
Kojto 101:7cff1c4259d7 398 #define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
Kojto 101:7cff1c4259d7 399 #define MXC_F_ADC_INTR_HI_RNG_IE_POS 24
Kojto 101:7cff1c4259d7 400 #define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
Kojto 101:7cff1c4259d7 401 #define MXC_F_ADC_INTR_LO_RNG_IE_POS 25
Kojto 101:7cff1c4259d7 402 #define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
Kojto 101:7cff1c4259d7 403 #define MXC_F_ADC_INTR_DONE_IE_POS 26
Kojto 101:7cff1c4259d7 404 #define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
Kojto 101:7cff1c4259d7 405 #define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27
Kojto 101:7cff1c4259d7 406 #define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
Kojto 101:7cff1c4259d7 407 #define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28
Kojto 101:7cff1c4259d7 408 #define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
Kojto 101:7cff1c4259d7 409 #define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29
Kojto 101:7cff1c4259d7 410 #define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
Kojto 101:7cff1c4259d7 411 #define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30
Kojto 101:7cff1c4259d7 412 #define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
Kojto 101:7cff1c4259d7 413 #define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31
Kojto 101:7cff1c4259d7 414 #define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
Kojto 101:7cff1c4259d7 415
Kojto 101:7cff1c4259d7 416 #define MXC_F_ADC_OUT_DATA_REG_POS 0
Kojto 101:7cff1c4259d7 417 #define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
Kojto 101:7cff1c4259d7 418
Kojto 101:7cff1c4259d7 419 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16
Kojto 101:7cff1c4259d7 420 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
Kojto 101:7cff1c4259d7 421
Kojto 101:7cff1c4259d7 422 #define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0
Kojto 101:7cff1c4259d7 423 #define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
Kojto 101:7cff1c4259d7 424 #define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8
Kojto 101:7cff1c4259d7 425 #define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
Kojto 101:7cff1c4259d7 426 #define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16
Kojto 101:7cff1c4259d7 427 #define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
Kojto 101:7cff1c4259d7 428 #define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24
Kojto 101:7cff1c4259d7 429 #define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
Kojto 101:7cff1c4259d7 430
Kojto 101:7cff1c4259d7 431 #define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0
Kojto 101:7cff1c4259d7 432 #define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
Kojto 101:7cff1c4259d7 433 #define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8
Kojto 101:7cff1c4259d7 434 #define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
Kojto 101:7cff1c4259d7 435 #define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16
Kojto 101:7cff1c4259d7 436 #define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
Kojto 101:7cff1c4259d7 437 #define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24
Kojto 101:7cff1c4259d7 438 #define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
Kojto 101:7cff1c4259d7 439
Kojto 101:7cff1c4259d7 440 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
Kojto 101:7cff1c4259d7 441 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
Kojto 101:7cff1c4259d7 442 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
Kojto 101:7cff1c4259d7 443 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
Kojto 101:7cff1c4259d7 444 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
Kojto 101:7cff1c4259d7 445 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
Kojto 101:7cff1c4259d7 446 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
Kojto 101:7cff1c4259d7 447 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
Kojto 101:7cff1c4259d7 448 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
Kojto 101:7cff1c4259d7 449 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
Kojto 101:7cff1c4259d7 450
Kojto 101:7cff1c4259d7 451 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
Kojto 101:7cff1c4259d7 452 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
Kojto 101:7cff1c4259d7 453 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
Kojto 101:7cff1c4259d7 454 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
Kojto 101:7cff1c4259d7 455 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
Kojto 101:7cff1c4259d7 456 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
Kojto 101:7cff1c4259d7 457
Kojto 101:7cff1c4259d7 458 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 459 }
Kojto 101:7cff1c4259d7 460 #endif
Kojto 101:7cff1c4259d7 461
Kojto 101:7cff1c4259d7 462 /**
Kojto 101:7cff1c4259d7 463 * @}
Kojto 101:7cff1c4259d7 464 */
Kojto 101:7cff1c4259d7 465
Kojto 101:7cff1c4259d7 466 #endif /* _MXC_ADC_REGS_H */