Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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Fork of mbed by mbed official

TARGET_LPC1114/core_cm0.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
110:165afa46840b 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 66:9c8f0e3462fb 1 /**************************************************************************//**
bogdanm 66:9c8f0e3462fb 2 * @file core_cm0.h
bogdanm 66:9c8f0e3462fb 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
bogdanm 66:9c8f0e3462fb 6 *
bogdanm 66:9c8f0e3462fb 7 * @note
bogdanm 66:9c8f0e3462fb 8 *
bogdanm 66:9c8f0e3462fb 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 66:9c8f0e3462fb 11
bogdanm 66:9c8f0e3462fb 12 All rights reserved.
bogdanm 66:9c8f0e3462fb 13 Redistribution and use in source and binary forms, with or without
bogdanm 66:9c8f0e3462fb 14 modification, are permitted provided that the following conditions are met:
bogdanm 66:9c8f0e3462fb 15 - Redistributions of source code must retain the above copyright
bogdanm 66:9c8f0e3462fb 16 notice, this list of conditions and the following disclaimer.
bogdanm 66:9c8f0e3462fb 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 66:9c8f0e3462fb 18 notice, this list of conditions and the following disclaimer in the
bogdanm 66:9c8f0e3462fb 19 documentation and/or other materials provided with the distribution.
bogdanm 66:9c8f0e3462fb 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 66:9c8f0e3462fb 21 to endorse or promote products derived from this software without
bogdanm 66:9c8f0e3462fb 22 specific prior written permission.
bogdanm 66:9c8f0e3462fb 23 *
bogdanm 66:9c8f0e3462fb 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 66:9c8f0e3462fb 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 66:9c8f0e3462fb 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 66:9c8f0e3462fb 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 66:9c8f0e3462fb 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 66:9c8f0e3462fb 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 66:9c8f0e3462fb 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 66:9c8f0e3462fb 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 66:9c8f0e3462fb 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 66:9c8f0e3462fb 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 66:9c8f0e3462fb 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 66:9c8f0e3462fb 35 ---------------------------------------------------------------------------*/
bogdanm 66:9c8f0e3462fb 36
bogdanm 66:9c8f0e3462fb 37
bogdanm 66:9c8f0e3462fb 38 #if defined ( __ICCARM__ )
bogdanm 66:9c8f0e3462fb 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 66:9c8f0e3462fb 40 #endif
bogdanm 66:9c8f0e3462fb 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
bogdanm 66:9c8f0e3462fb 45 #ifdef __cplusplus
bogdanm 66:9c8f0e3462fb 46 extern "C" {
bogdanm 66:9c8f0e3462fb 47 #endif
bogdanm 66:9c8f0e3462fb 48
bogdanm 66:9c8f0e3462fb 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 66:9c8f0e3462fb 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 66:9c8f0e3462fb 51
bogdanm 66:9c8f0e3462fb 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 66:9c8f0e3462fb 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 66:9c8f0e3462fb 54
bogdanm 66:9c8f0e3462fb 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 66:9c8f0e3462fb 56 Unions are used for effective representation of core registers.
bogdanm 66:9c8f0e3462fb 57
bogdanm 66:9c8f0e3462fb 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 66:9c8f0e3462fb 59 Function-like macros are used to allow more efficient code.
bogdanm 66:9c8f0e3462fb 60 */
bogdanm 66:9c8f0e3462fb 61
bogdanm 66:9c8f0e3462fb 62
bogdanm 66:9c8f0e3462fb 63 /*******************************************************************************
bogdanm 66:9c8f0e3462fb 64 * CMSIS definitions
bogdanm 66:9c8f0e3462fb 65 ******************************************************************************/
bogdanm 66:9c8f0e3462fb 66 /** \ingroup Cortex_M0
bogdanm 66:9c8f0e3462fb 67 @{
bogdanm 66:9c8f0e3462fb 68 */
bogdanm 66:9c8f0e3462fb 69
bogdanm 66:9c8f0e3462fb 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 66:9c8f0e3462fb 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
bogdanm 66:9c8f0e3462fb 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 66:9c8f0e3462fb 75
bogdanm 66:9c8f0e3462fb 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 66:9c8f0e3462fb 77
bogdanm 66:9c8f0e3462fb 78
bogdanm 66:9c8f0e3462fb 79 #if defined ( __CC_ARM )
bogdanm 66:9c8f0e3462fb 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 66:9c8f0e3462fb 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 66:9c8f0e3462fb 82 #define __STATIC_INLINE static __inline
bogdanm 66:9c8f0e3462fb 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
bogdanm 66:9c8f0e3462fb 89 #elif defined ( __ICCARM__ )
bogdanm 66:9c8f0e3462fb 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 66:9c8f0e3462fb 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 66:9c8f0e3462fb 92 #define __STATIC_INLINE static inline
bogdanm 66:9c8f0e3462fb 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 66:9c8f0e3462fb 96 #define __STATIC_INLINE static inline
bogdanm 66:9c8f0e3462fb 97
bogdanm 66:9c8f0e3462fb 98 #elif defined ( __TASKING__ )
bogdanm 66:9c8f0e3462fb 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 66:9c8f0e3462fb 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 66:9c8f0e3462fb 101 #define __STATIC_INLINE static inline
bogdanm 66:9c8f0e3462fb 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
bogdanm 66:9c8f0e3462fb 109 #endif
bogdanm 66:9c8f0e3462fb 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
bogdanm 66:9c8f0e3462fb 113 */
bogdanm 66:9c8f0e3462fb 114 #define __FPU_USED 0
bogdanm 66:9c8f0e3462fb 115
bogdanm 66:9c8f0e3462fb 116 #if defined ( __CC_ARM )
bogdanm 66:9c8f0e3462fb 117 #if defined __TARGET_FPU_VFP
bogdanm 66:9c8f0e3462fb 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 66:9c8f0e3462fb 119 #endif
bogdanm 66:9c8f0e3462fb 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
bogdanm 66:9c8f0e3462fb 126 #elif defined ( __ICCARM__ )
bogdanm 66:9c8f0e3462fb 127 #if defined __ARMVFP__
bogdanm 66:9c8f0e3462fb 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 66:9c8f0e3462fb 129 #endif
bogdanm 66:9c8f0e3462fb 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
bogdanm 66:9c8f0e3462fb 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 66:9c8f0e3462fb 134 #endif
bogdanm 66:9c8f0e3462fb 135
bogdanm 66:9c8f0e3462fb 136 #elif defined ( __TASKING__ )
bogdanm 66:9c8f0e3462fb 137 #if defined __FPU_VFP__
bogdanm 66:9c8f0e3462fb 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 66:9c8f0e3462fb 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
bogdanm 66:9c8f0e3462fb 145 #endif
bogdanm 66:9c8f0e3462fb 146
bogdanm 66:9c8f0e3462fb 147 #include <stdint.h> /* standard types definitions */
bogdanm 66:9c8f0e3462fb 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 66:9c8f0e3462fb 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 66:9c8f0e3462fb 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
bogdanm 66:9c8f0e3462fb 155 #endif /* __CORE_CM0_H_GENERIC */
bogdanm 66:9c8f0e3462fb 156
bogdanm 66:9c8f0e3462fb 157 #ifndef __CMSIS_GENERIC
bogdanm 66:9c8f0e3462fb 158
bogdanm 66:9c8f0e3462fb 159 #ifndef __CORE_CM0_H_DEPENDANT
bogdanm 66:9c8f0e3462fb 160 #define __CORE_CM0_H_DEPENDANT
bogdanm 66:9c8f0e3462fb 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
bogdanm 66:9c8f0e3462fb 166 /* check device defines and use defaults */
bogdanm 66:9c8f0e3462fb 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 66:9c8f0e3462fb 168 #ifndef __CM0_REV
bogdanm 66:9c8f0e3462fb 169 #define __CM0_REV 0x0000
bogdanm 66:9c8f0e3462fb 170 #warning "__CM0_REV not defined in device header file; using default!"
bogdanm 66:9c8f0e3462fb 171 #endif
bogdanm 66:9c8f0e3462fb 172
bogdanm 66:9c8f0e3462fb 173 #ifndef __NVIC_PRIO_BITS
bogdanm 66:9c8f0e3462fb 174 #define __NVIC_PRIO_BITS 2
bogdanm 66:9c8f0e3462fb 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 66:9c8f0e3462fb 176 #endif
bogdanm 66:9c8f0e3462fb 177
bogdanm 66:9c8f0e3462fb 178 #ifndef __Vendor_SysTickConfig
bogdanm 66:9c8f0e3462fb 179 #define __Vendor_SysTickConfig 0
bogdanm 66:9c8f0e3462fb 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 66:9c8f0e3462fb 181 #endif
bogdanm 66:9c8f0e3462fb 182 #endif
bogdanm 66:9c8f0e3462fb 183
bogdanm 66:9c8f0e3462fb 184 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 66:9c8f0e3462fb 185 /**
bogdanm 66:9c8f0e3462fb 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 66:9c8f0e3462fb 187
bogdanm 66:9c8f0e3462fb 188 <strong>IO Type Qualifiers</strong> are used
bogdanm 66:9c8f0e3462fb 189 \li to specify the access to peripheral variables.
bogdanm 66:9c8f0e3462fb 190 \li for automatic generation of peripheral register debug information.
bogdanm 66:9c8f0e3462fb 191 */
bogdanm 66:9c8f0e3462fb 192 #ifdef __cplusplus
bogdanm 66:9c8f0e3462fb 193 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 66:9c8f0e3462fb 194 #else
bogdanm 66:9c8f0e3462fb 195 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 66:9c8f0e3462fb 196 #endif
bogdanm 66:9c8f0e3462fb 197 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 66:9c8f0e3462fb 198 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 66:9c8f0e3462fb 199
bogdanm 66:9c8f0e3462fb 200 /*@} end of group Cortex_M0 */
bogdanm 66:9c8f0e3462fb 201
bogdanm 66:9c8f0e3462fb 202
bogdanm 66:9c8f0e3462fb 203
bogdanm 66:9c8f0e3462fb 204 /*******************************************************************************
bogdanm 66:9c8f0e3462fb 205 * Register Abstraction
bogdanm 66:9c8f0e3462fb 206 Core Register contain:
bogdanm 66:9c8f0e3462fb 207 - Core Register
bogdanm 66:9c8f0e3462fb 208 - Core NVIC Register
bogdanm 66:9c8f0e3462fb 209 - Core SCB Register
bogdanm 66:9c8f0e3462fb 210 - Core SysTick Register
bogdanm 66:9c8f0e3462fb 211 ******************************************************************************/
bogdanm 66:9c8f0e3462fb 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 66:9c8f0e3462fb 213 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 66:9c8f0e3462fb 214 */
bogdanm 66:9c8f0e3462fb 215
bogdanm 66:9c8f0e3462fb 216 /** \ingroup CMSIS_core_register
bogdanm 66:9c8f0e3462fb 217 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 66:9c8f0e3462fb 218 \brief Core Register type definitions.
bogdanm 66:9c8f0e3462fb 219 @{
bogdanm 66:9c8f0e3462fb 220 */
bogdanm 66:9c8f0e3462fb 221
bogdanm 66:9c8f0e3462fb 222 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 66:9c8f0e3462fb 223 */
bogdanm 66:9c8f0e3462fb 224 typedef union
bogdanm 66:9c8f0e3462fb 225 {
bogdanm 66:9c8f0e3462fb 226 struct
bogdanm 66:9c8f0e3462fb 227 {
Kojto 110:165afa46840b 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
bogdanm 66:9c8f0e3462fb 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 66:9c8f0e3462fb 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 66:9c8f0e3462fb 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 66:9c8f0e3462fb 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 66:9c8f0e3462fb 233 } b; /*!< Structure used for bit access */
bogdanm 66:9c8f0e3462fb 234 uint32_t w; /*!< Type used for word access */
bogdanm 66:9c8f0e3462fb 235 } APSR_Type;
bogdanm 66:9c8f0e3462fb 236
Kojto 110:165afa46840b 237 /* APSR Register Definitions */
Kojto 110:165afa46840b 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 240
Kojto 110:165afa46840b 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 243
Kojto 110:165afa46840b 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 246
Kojto 110:165afa46840b 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 249
bogdanm 66:9c8f0e3462fb 250
bogdanm 66:9c8f0e3462fb 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 66:9c8f0e3462fb 252 */
bogdanm 66:9c8f0e3462fb 253 typedef union
bogdanm 66:9c8f0e3462fb 254 {
bogdanm 66:9c8f0e3462fb 255 struct
bogdanm 66:9c8f0e3462fb 256 {
bogdanm 66:9c8f0e3462fb 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 66:9c8f0e3462fb 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 66:9c8f0e3462fb 259 } b; /*!< Structure used for bit access */
bogdanm 66:9c8f0e3462fb 260 uint32_t w; /*!< Type used for word access */
bogdanm 66:9c8f0e3462fb 261 } IPSR_Type;
bogdanm 66:9c8f0e3462fb 262
Kojto 110:165afa46840b 263 /* IPSR Register Definitions */
Kojto 110:165afa46840b 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 266
bogdanm 66:9c8f0e3462fb 267
bogdanm 66:9c8f0e3462fb 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 66:9c8f0e3462fb 269 */
bogdanm 66:9c8f0e3462fb 270 typedef union
bogdanm 66:9c8f0e3462fb 271 {
bogdanm 66:9c8f0e3462fb 272 struct
bogdanm 66:9c8f0e3462fb 273 {
bogdanm 66:9c8f0e3462fb 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 66:9c8f0e3462fb 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 66:9c8f0e3462fb 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
bogdanm 66:9c8f0e3462fb 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 66:9c8f0e3462fb 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 66:9c8f0e3462fb 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 66:9c8f0e3462fb 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 66:9c8f0e3462fb 282 } b; /*!< Structure used for bit access */
bogdanm 66:9c8f0e3462fb 283 uint32_t w; /*!< Type used for word access */
bogdanm 66:9c8f0e3462fb 284 } xPSR_Type;
bogdanm 66:9c8f0e3462fb 285
Kojto 110:165afa46840b 286 /* xPSR Register Definitions */
Kojto 110:165afa46840b 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 289
Kojto 110:165afa46840b 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 292
Kojto 110:165afa46840b 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 295
Kojto 110:165afa46840b 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 298
Kojto 110:165afa46840b 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 301
Kojto 110:165afa46840b 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 304
bogdanm 66:9c8f0e3462fb 305
bogdanm 66:9c8f0e3462fb 306 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 66:9c8f0e3462fb 307 */
bogdanm 66:9c8f0e3462fb 308 typedef union
bogdanm 66:9c8f0e3462fb 309 {
bogdanm 66:9c8f0e3462fb 310 struct
bogdanm 66:9c8f0e3462fb 311 {
Kojto 110:165afa46840b 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
bogdanm 66:9c8f0e3462fb 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 66:9c8f0e3462fb 315 } b; /*!< Structure used for bit access */
bogdanm 66:9c8f0e3462fb 316 uint32_t w; /*!< Type used for word access */
bogdanm 66:9c8f0e3462fb 317 } CONTROL_Type;
bogdanm 66:9c8f0e3462fb 318
Kojto 110:165afa46840b 319 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 322
bogdanm 66:9c8f0e3462fb 323 /*@} end of group CMSIS_CORE */
bogdanm 66:9c8f0e3462fb 324
bogdanm 66:9c8f0e3462fb 325
bogdanm 66:9c8f0e3462fb 326 /** \ingroup CMSIS_core_register
bogdanm 66:9c8f0e3462fb 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 66:9c8f0e3462fb 328 \brief Type definitions for the NVIC Registers
bogdanm 66:9c8f0e3462fb 329 @{
bogdanm 66:9c8f0e3462fb 330 */
bogdanm 66:9c8f0e3462fb 331
bogdanm 66:9c8f0e3462fb 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 66:9c8f0e3462fb 333 */
bogdanm 66:9c8f0e3462fb 334 typedef struct
bogdanm 66:9c8f0e3462fb 335 {
bogdanm 66:9c8f0e3462fb 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 66:9c8f0e3462fb 337 uint32_t RESERVED0[31];
bogdanm 66:9c8f0e3462fb 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 66:9c8f0e3462fb 339 uint32_t RSERVED1[31];
bogdanm 66:9c8f0e3462fb 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 66:9c8f0e3462fb 341 uint32_t RESERVED2[31];
bogdanm 66:9c8f0e3462fb 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 66:9c8f0e3462fb 343 uint32_t RESERVED3[31];
bogdanm 66:9c8f0e3462fb 344 uint32_t RESERVED4[64];
bogdanm 66:9c8f0e3462fb 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 66:9c8f0e3462fb 346 } NVIC_Type;
bogdanm 66:9c8f0e3462fb 347
bogdanm 66:9c8f0e3462fb 348 /*@} end of group CMSIS_NVIC */
bogdanm 66:9c8f0e3462fb 349
bogdanm 66:9c8f0e3462fb 350
bogdanm 66:9c8f0e3462fb 351 /** \ingroup CMSIS_core_register
bogdanm 66:9c8f0e3462fb 352 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 66:9c8f0e3462fb 353 \brief Type definitions for the System Control Block Registers
bogdanm 66:9c8f0e3462fb 354 @{
bogdanm 66:9c8f0e3462fb 355 */
bogdanm 66:9c8f0e3462fb 356
bogdanm 66:9c8f0e3462fb 357 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 66:9c8f0e3462fb 358 */
bogdanm 66:9c8f0e3462fb 359 typedef struct
bogdanm 66:9c8f0e3462fb 360 {
bogdanm 66:9c8f0e3462fb 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 66:9c8f0e3462fb 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 66:9c8f0e3462fb 363 uint32_t RESERVED0;
bogdanm 66:9c8f0e3462fb 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 66:9c8f0e3462fb 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 66:9c8f0e3462fb 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 66:9c8f0e3462fb 367 uint32_t RESERVED1;
bogdanm 66:9c8f0e3462fb 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 66:9c8f0e3462fb 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 66:9c8f0e3462fb 370 } SCB_Type;
bogdanm 66:9c8f0e3462fb 371
bogdanm 66:9c8f0e3462fb 372 /* SCB CPUID Register Definitions */
bogdanm 66:9c8f0e3462fb 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 66:9c8f0e3462fb 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 66:9c8f0e3462fb 375
bogdanm 66:9c8f0e3462fb 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 66:9c8f0e3462fb 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 66:9c8f0e3462fb 378
bogdanm 66:9c8f0e3462fb 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 66:9c8f0e3462fb 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 66:9c8f0e3462fb 381
bogdanm 66:9c8f0e3462fb 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 66:9c8f0e3462fb 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 66:9c8f0e3462fb 384
bogdanm 66:9c8f0e3462fb 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 66:9c8f0e3462fb 387
bogdanm 66:9c8f0e3462fb 388 /* SCB Interrupt Control State Register Definitions */
bogdanm 66:9c8f0e3462fb 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 66:9c8f0e3462fb 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 66:9c8f0e3462fb 391
bogdanm 66:9c8f0e3462fb 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 66:9c8f0e3462fb 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 66:9c8f0e3462fb 394
bogdanm 66:9c8f0e3462fb 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 66:9c8f0e3462fb 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 66:9c8f0e3462fb 397
bogdanm 66:9c8f0e3462fb 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 66:9c8f0e3462fb 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 66:9c8f0e3462fb 400
bogdanm 66:9c8f0e3462fb 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 66:9c8f0e3462fb 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 66:9c8f0e3462fb 403
bogdanm 66:9c8f0e3462fb 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 66:9c8f0e3462fb 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 66:9c8f0e3462fb 406
bogdanm 66:9c8f0e3462fb 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 66:9c8f0e3462fb 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 66:9c8f0e3462fb 409
bogdanm 66:9c8f0e3462fb 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 66:9c8f0e3462fb 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 66:9c8f0e3462fb 412
bogdanm 66:9c8f0e3462fb 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 66:9c8f0e3462fb 415
bogdanm 66:9c8f0e3462fb 416 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 66:9c8f0e3462fb 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 66:9c8f0e3462fb 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 66:9c8f0e3462fb 419
bogdanm 66:9c8f0e3462fb 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 66:9c8f0e3462fb 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 66:9c8f0e3462fb 422
bogdanm 66:9c8f0e3462fb 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 66:9c8f0e3462fb 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 66:9c8f0e3462fb 425
bogdanm 66:9c8f0e3462fb 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 66:9c8f0e3462fb 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 66:9c8f0e3462fb 428
bogdanm 66:9c8f0e3462fb 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 66:9c8f0e3462fb 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 66:9c8f0e3462fb 431
bogdanm 66:9c8f0e3462fb 432 /* SCB System Control Register Definitions */
bogdanm 66:9c8f0e3462fb 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 66:9c8f0e3462fb 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 66:9c8f0e3462fb 435
bogdanm 66:9c8f0e3462fb 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 66:9c8f0e3462fb 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 66:9c8f0e3462fb 438
bogdanm 66:9c8f0e3462fb 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 66:9c8f0e3462fb 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 66:9c8f0e3462fb 441
bogdanm 66:9c8f0e3462fb 442 /* SCB Configuration Control Register Definitions */
bogdanm 66:9c8f0e3462fb 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 66:9c8f0e3462fb 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 66:9c8f0e3462fb 445
bogdanm 66:9c8f0e3462fb 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 66:9c8f0e3462fb 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 66:9c8f0e3462fb 448
bogdanm 66:9c8f0e3462fb 449 /* SCB System Handler Control and State Register Definitions */
bogdanm 66:9c8f0e3462fb 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 66:9c8f0e3462fb 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 66:9c8f0e3462fb 452
bogdanm 66:9c8f0e3462fb 453 /*@} end of group CMSIS_SCB */
bogdanm 66:9c8f0e3462fb 454
bogdanm 66:9c8f0e3462fb 455
bogdanm 66:9c8f0e3462fb 456 /** \ingroup CMSIS_core_register
bogdanm 66:9c8f0e3462fb 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 66:9c8f0e3462fb 458 \brief Type definitions for the System Timer Registers.
bogdanm 66:9c8f0e3462fb 459 @{
bogdanm 66:9c8f0e3462fb 460 */
bogdanm 66:9c8f0e3462fb 461
bogdanm 66:9c8f0e3462fb 462 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 66:9c8f0e3462fb 463 */
bogdanm 66:9c8f0e3462fb 464 typedef struct
bogdanm 66:9c8f0e3462fb 465 {
bogdanm 66:9c8f0e3462fb 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 66:9c8f0e3462fb 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 66:9c8f0e3462fb 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 66:9c8f0e3462fb 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 66:9c8f0e3462fb 470 } SysTick_Type;
bogdanm 66:9c8f0e3462fb 471
bogdanm 66:9c8f0e3462fb 472 /* SysTick Control / Status Register Definitions */
bogdanm 66:9c8f0e3462fb 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 66:9c8f0e3462fb 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 66:9c8f0e3462fb 475
bogdanm 66:9c8f0e3462fb 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 66:9c8f0e3462fb 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 66:9c8f0e3462fb 478
bogdanm 66:9c8f0e3462fb 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 66:9c8f0e3462fb 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 66:9c8f0e3462fb 481
bogdanm 66:9c8f0e3462fb 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 66:9c8f0e3462fb 484
bogdanm 66:9c8f0e3462fb 485 /* SysTick Reload Register Definitions */
bogdanm 66:9c8f0e3462fb 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 66:9c8f0e3462fb 488
bogdanm 66:9c8f0e3462fb 489 /* SysTick Current Register Definitions */
bogdanm 66:9c8f0e3462fb 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 66:9c8f0e3462fb 492
bogdanm 66:9c8f0e3462fb 493 /* SysTick Calibration Register Definitions */
bogdanm 66:9c8f0e3462fb 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 66:9c8f0e3462fb 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 66:9c8f0e3462fb 496
bogdanm 66:9c8f0e3462fb 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 66:9c8f0e3462fb 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 66:9c8f0e3462fb 499
bogdanm 66:9c8f0e3462fb 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 66:9c8f0e3462fb 502
bogdanm 66:9c8f0e3462fb 503 /*@} end of group CMSIS_SysTick */
bogdanm 66:9c8f0e3462fb 504
bogdanm 66:9c8f0e3462fb 505
bogdanm 66:9c8f0e3462fb 506 /** \ingroup CMSIS_core_register
bogdanm 66:9c8f0e3462fb 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 66:9c8f0e3462fb 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 66:9c8f0e3462fb 509 are only accessible over DAP and not via processor. Therefore
bogdanm 66:9c8f0e3462fb 510 they are not covered by the Cortex-M0 header file.
bogdanm 66:9c8f0e3462fb 511 @{
bogdanm 66:9c8f0e3462fb 512 */
bogdanm 66:9c8f0e3462fb 513 /*@} end of group CMSIS_CoreDebug */
bogdanm 66:9c8f0e3462fb 514
bogdanm 66:9c8f0e3462fb 515
bogdanm 66:9c8f0e3462fb 516 /** \ingroup CMSIS_core_register
bogdanm 66:9c8f0e3462fb 517 \defgroup CMSIS_core_base Core Definitions
bogdanm 66:9c8f0e3462fb 518 \brief Definitions for base addresses, unions, and structures.
bogdanm 66:9c8f0e3462fb 519 @{
bogdanm 66:9c8f0e3462fb 520 */
bogdanm 66:9c8f0e3462fb 521
bogdanm 66:9c8f0e3462fb 522 /* Memory mapping of Cortex-M0 Hardware */
bogdanm 66:9c8f0e3462fb 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 66:9c8f0e3462fb 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 66:9c8f0e3462fb 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 66:9c8f0e3462fb 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 66:9c8f0e3462fb 527
bogdanm 66:9c8f0e3462fb 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 66:9c8f0e3462fb 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 66:9c8f0e3462fb 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 66:9c8f0e3462fb 531
bogdanm 66:9c8f0e3462fb 532
bogdanm 66:9c8f0e3462fb 533 /*@} */
bogdanm 66:9c8f0e3462fb 534
bogdanm 66:9c8f0e3462fb 535
bogdanm 66:9c8f0e3462fb 536
bogdanm 66:9c8f0e3462fb 537 /*******************************************************************************
bogdanm 66:9c8f0e3462fb 538 * Hardware Abstraction Layer
bogdanm 66:9c8f0e3462fb 539 Core Function Interface contains:
bogdanm 66:9c8f0e3462fb 540 - Core NVIC Functions
bogdanm 66:9c8f0e3462fb 541 - Core SysTick Functions
bogdanm 66:9c8f0e3462fb 542 - Core Register Access Functions
bogdanm 66:9c8f0e3462fb 543 ******************************************************************************/
bogdanm 66:9c8f0e3462fb 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 66:9c8f0e3462fb 545 */
bogdanm 66:9c8f0e3462fb 546
bogdanm 66:9c8f0e3462fb 547
bogdanm 66:9c8f0e3462fb 548
bogdanm 66:9c8f0e3462fb 549 /* ########################## NVIC functions #################################### */
bogdanm 66:9c8f0e3462fb 550 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 66:9c8f0e3462fb 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 66:9c8f0e3462fb 552 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 66:9c8f0e3462fb 553 @{
bogdanm 66:9c8f0e3462fb 554 */
bogdanm 66:9c8f0e3462fb 555
bogdanm 66:9c8f0e3462fb 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 66:9c8f0e3462fb 557 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
bogdanm 66:9c8f0e3462fb 561
bogdanm 66:9c8f0e3462fb 562
bogdanm 66:9c8f0e3462fb 563 /** \brief Enable External Interrupt
bogdanm 66:9c8f0e3462fb 564
bogdanm 66:9c8f0e3462fb 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 66:9c8f0e3462fb 566
bogdanm 66:9c8f0e3462fb 567 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 66:9c8f0e3462fb 568 */
bogdanm 66:9c8f0e3462fb 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 66:9c8f0e3462fb 570 {
Kojto 110:165afa46840b 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 66:9c8f0e3462fb 572 }
bogdanm 66:9c8f0e3462fb 573
bogdanm 66:9c8f0e3462fb 574
bogdanm 66:9c8f0e3462fb 575 /** \brief Disable External Interrupt
bogdanm 66:9c8f0e3462fb 576
bogdanm 66:9c8f0e3462fb 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 66:9c8f0e3462fb 578
bogdanm 66:9c8f0e3462fb 579 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 66:9c8f0e3462fb 580 */
bogdanm 66:9c8f0e3462fb 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 66:9c8f0e3462fb 582 {
Kojto 110:165afa46840b 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 66:9c8f0e3462fb 584 }
bogdanm 66:9c8f0e3462fb 585
bogdanm 66:9c8f0e3462fb 586
bogdanm 66:9c8f0e3462fb 587 /** \brief Get Pending Interrupt
bogdanm 66:9c8f0e3462fb 588
bogdanm 66:9c8f0e3462fb 589 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 66:9c8f0e3462fb 590 for the specified interrupt.
bogdanm 66:9c8f0e3462fb 591
bogdanm 66:9c8f0e3462fb 592 \param [in] IRQn Interrupt number.
bogdanm 66:9c8f0e3462fb 593
bogdanm 66:9c8f0e3462fb 594 \return 0 Interrupt status is not pending.
bogdanm 66:9c8f0e3462fb 595 \return 1 Interrupt status is pending.
bogdanm 66:9c8f0e3462fb 596 */
bogdanm 66:9c8f0e3462fb 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 66:9c8f0e3462fb 598 {
Kojto 110:165afa46840b 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 66:9c8f0e3462fb 600 }
bogdanm 66:9c8f0e3462fb 601
bogdanm 66:9c8f0e3462fb 602
bogdanm 66:9c8f0e3462fb 603 /** \brief Set Pending Interrupt
bogdanm 66:9c8f0e3462fb 604
bogdanm 66:9c8f0e3462fb 605 The function sets the pending bit of an external interrupt.
bogdanm 66:9c8f0e3462fb 606
bogdanm 66:9c8f0e3462fb 607 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 66:9c8f0e3462fb 608 */
bogdanm 66:9c8f0e3462fb 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 66:9c8f0e3462fb 610 {
Kojto 110:165afa46840b 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 66:9c8f0e3462fb 612 }
bogdanm 66:9c8f0e3462fb 613
bogdanm 66:9c8f0e3462fb 614
bogdanm 66:9c8f0e3462fb 615 /** \brief Clear Pending Interrupt
bogdanm 66:9c8f0e3462fb 616
bogdanm 66:9c8f0e3462fb 617 The function clears the pending bit of an external interrupt.
bogdanm 66:9c8f0e3462fb 618
bogdanm 66:9c8f0e3462fb 619 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 66:9c8f0e3462fb 620 */
bogdanm 66:9c8f0e3462fb 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 66:9c8f0e3462fb 622 {
Kojto 110:165afa46840b 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 66:9c8f0e3462fb 624 }
bogdanm 66:9c8f0e3462fb 625
bogdanm 66:9c8f0e3462fb 626
bogdanm 66:9c8f0e3462fb 627 /** \brief Set Interrupt Priority
bogdanm 66:9c8f0e3462fb 628
bogdanm 66:9c8f0e3462fb 629 The function sets the priority of an interrupt.
bogdanm 66:9c8f0e3462fb 630
bogdanm 66:9c8f0e3462fb 631 \note The priority cannot be set for every core interrupt.
bogdanm 66:9c8f0e3462fb 632
bogdanm 66:9c8f0e3462fb 633 \param [in] IRQn Interrupt number.
bogdanm 66:9c8f0e3462fb 634 \param [in] priority Priority to set.
bogdanm 66:9c8f0e3462fb 635 */
bogdanm 66:9c8f0e3462fb 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 66:9c8f0e3462fb 637 {
Kojto 110:165afa46840b 638 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 641 }
bogdanm 66:9c8f0e3462fb 642 else {
Kojto 110:165afa46840b 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 645 }
bogdanm 66:9c8f0e3462fb 646 }
bogdanm 66:9c8f0e3462fb 647
bogdanm 66:9c8f0e3462fb 648
bogdanm 66:9c8f0e3462fb 649 /** \brief Get Interrupt Priority
bogdanm 66:9c8f0e3462fb 650
bogdanm 66:9c8f0e3462fb 651 The function reads the priority of an interrupt. The interrupt
bogdanm 66:9c8f0e3462fb 652 number can be positive to specify an external (device specific)
bogdanm 66:9c8f0e3462fb 653 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 66:9c8f0e3462fb 654
bogdanm 66:9c8f0e3462fb 655
bogdanm 66:9c8f0e3462fb 656 \param [in] IRQn Interrupt number.
bogdanm 66:9c8f0e3462fb 657 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 66:9c8f0e3462fb 658 priority bits of the microcontroller.
bogdanm 66:9c8f0e3462fb 659 */
bogdanm 66:9c8f0e3462fb 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 66:9c8f0e3462fb 661 {
bogdanm 66:9c8f0e3462fb 662
Kojto 110:165afa46840b 663 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 665 }
bogdanm 66:9c8f0e3462fb 666 else {
Kojto 110:165afa46840b 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 668 }
bogdanm 66:9c8f0e3462fb 669 }
bogdanm 66:9c8f0e3462fb 670
bogdanm 66:9c8f0e3462fb 671
bogdanm 66:9c8f0e3462fb 672 /** \brief System Reset
bogdanm 66:9c8f0e3462fb 673
bogdanm 66:9c8f0e3462fb 674 The function initiates a system reset request to reset the MCU.
bogdanm 66:9c8f0e3462fb 675 */
bogdanm 66:9c8f0e3462fb 676 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 66:9c8f0e3462fb 677 {
bogdanm 66:9c8f0e3462fb 678 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 66:9c8f0e3462fb 679 buffered write are completed before reset */
Kojto 110:165afa46840b 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 66:9c8f0e3462fb 681 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 66:9c8f0e3462fb 682 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 683 while(1) { __NOP(); } /* wait until reset */
bogdanm 66:9c8f0e3462fb 684 }
bogdanm 66:9c8f0e3462fb 685
bogdanm 66:9c8f0e3462fb 686 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 66:9c8f0e3462fb 687
bogdanm 66:9c8f0e3462fb 688
bogdanm 66:9c8f0e3462fb 689
bogdanm 66:9c8f0e3462fb 690 /* ################################## SysTick function ############################################ */
bogdanm 66:9c8f0e3462fb 691 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 66:9c8f0e3462fb 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 66:9c8f0e3462fb 693 \brief Functions that configure the System.
bogdanm 66:9c8f0e3462fb 694 @{
bogdanm 66:9c8f0e3462fb 695 */
bogdanm 66:9c8f0e3462fb 696
bogdanm 66:9c8f0e3462fb 697 #if (__Vendor_SysTickConfig == 0)
bogdanm 66:9c8f0e3462fb 698
bogdanm 66:9c8f0e3462fb 699 /** \brief System Tick Configuration
bogdanm 66:9c8f0e3462fb 700
bogdanm 66:9c8f0e3462fb 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 66:9c8f0e3462fb 702 Counter is in free running mode to generate periodic interrupts.
bogdanm 66:9c8f0e3462fb 703
bogdanm 66:9c8f0e3462fb 704 \param [in] ticks Number of ticks between two interrupts.
bogdanm 66:9c8f0e3462fb 705
bogdanm 66:9c8f0e3462fb 706 \return 0 Function succeeded.
bogdanm 66:9c8f0e3462fb 707 \return 1 Function failed.
bogdanm 66:9c8f0e3462fb 708
bogdanm 66:9c8f0e3462fb 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 66:9c8f0e3462fb 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 66:9c8f0e3462fb 711 must contain a vendor-specific implementation of this function.
bogdanm 66:9c8f0e3462fb 712
bogdanm 66:9c8f0e3462fb 713 */
bogdanm 66:9c8f0e3462fb 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 66:9c8f0e3462fb 715 {
Kojto 110:165afa46840b 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
bogdanm 66:9c8f0e3462fb 717
Kojto 110:165afa46840b 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 66:9c8f0e3462fb 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 66:9c8f0e3462fb 722 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 724 return (0UL); /* Function successful */
bogdanm 66:9c8f0e3462fb 725 }
bogdanm 66:9c8f0e3462fb 726
bogdanm 66:9c8f0e3462fb 727 #endif
bogdanm 66:9c8f0e3462fb 728
bogdanm 66:9c8f0e3462fb 729 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 66:9c8f0e3462fb 730
bogdanm 66:9c8f0e3462fb 731
bogdanm 66:9c8f0e3462fb 732
bogdanm 66:9c8f0e3462fb 733
Kojto 110:165afa46840b 734 #ifdef __cplusplus
Kojto 110:165afa46840b 735 }
Kojto 110:165afa46840b 736 #endif
Kojto 110:165afa46840b 737
bogdanm 66:9c8f0e3462fb 738 #endif /* __CORE_CM0_H_DEPENDANT */
bogdanm 66:9c8f0e3462fb 739
bogdanm 66:9c8f0e3462fb 740 #endif /* __CMSIS_GENERIC */