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TARGET_DISCO_L053C8/stm32l0xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 99:dbbf35b96557

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	99:dbbf35b96557	1	/**
Kojto	99:dbbf35b96557	2	******************************************************************************
Kojto	99:dbbf35b96557	3	* @file stm32l0xx_hal_rcc.h
Kojto	99:dbbf35b96557	4	* @author MCD Application Team
Kojto	99:dbbf35b96557	5	* @version V1.2.0
Kojto	99:dbbf35b96557	6	* @date 06-February-2015
Kojto	99:dbbf35b96557	7	* @brief Header file of RCC HAL module.
Kojto	99:dbbf35b96557	8	******************************************************************************
Kojto	99:dbbf35b96557	9	* @attention
Kojto	99:dbbf35b96557	10	*
Kojto	99:dbbf35b96557	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	99:dbbf35b96557	12	*
Kojto	99:dbbf35b96557	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	99:dbbf35b96557	14	* are permitted provided that the following conditions are met:
Kojto	99:dbbf35b96557	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	99:dbbf35b96557	16	* this list of conditions and the following disclaimer.
Kojto	99:dbbf35b96557	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	99:dbbf35b96557	18	* this list of conditions and the following disclaimer in the documentation
Kojto	99:dbbf35b96557	19	* and/or other materials provided with the distribution.
Kojto	99:dbbf35b96557	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	99:dbbf35b96557	21	* may be used to endorse or promote products derived from this software
Kojto	99:dbbf35b96557	22	* without specific prior written permission.
Kojto	99:dbbf35b96557	23	*
Kojto	99:dbbf35b96557	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	99:dbbf35b96557	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	99:dbbf35b96557	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	99:dbbf35b96557	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	99:dbbf35b96557	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	99:dbbf35b96557	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	99:dbbf35b96557	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	99:dbbf35b96557	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	99:dbbf35b96557	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	99:dbbf35b96557	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	99:dbbf35b96557	34	*
Kojto	99:dbbf35b96557	35	******************************************************************************
Kojto	99:dbbf35b96557	36	*/
Kojto	99:dbbf35b96557	37
Kojto	99:dbbf35b96557	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	99:dbbf35b96557	39	#ifndef __STM32L0xx_HAL_RCC_H
Kojto	99:dbbf35b96557	40	#define __STM32L0xx_HAL_RCC_H
Kojto	99:dbbf35b96557	41
Kojto	99:dbbf35b96557	42	#ifdef __cplusplus
Kojto	99:dbbf35b96557	43	extern "C" {
Kojto	99:dbbf35b96557	44	#endif
Kojto	99:dbbf35b96557	45
Kojto	99:dbbf35b96557	46	/* Includes ------------------------------------------------------------------*/
Kojto	99:dbbf35b96557	47	#include "stm32l0xx_hal_def.h"
Kojto	99:dbbf35b96557	48
Kojto	99:dbbf35b96557	49	/** @addtogroup STM32L0xx_HAL_Driver
Kojto	99:dbbf35b96557	50	* @{
Kojto	99:dbbf35b96557	51	*/
Kojto	99:dbbf35b96557	52
Kojto	99:dbbf35b96557	53	/** @defgroup RCC RCC
Kojto	99:dbbf35b96557	54	* @{
Kojto	99:dbbf35b96557	55	*/
Kojto	99:dbbf35b96557	56
Kojto	99:dbbf35b96557	57	/* Exported types ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	58
Kojto	99:dbbf35b96557	59	/**
Kojto	99:dbbf35b96557	60	* @brief RCC PLL configuration structure definition
Kojto	99:dbbf35b96557	61	*/
Kojto	99:dbbf35b96557	62	typedef struct
Kojto	99:dbbf35b96557	63	{
Kojto	99:dbbf35b96557	64	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	99:dbbf35b96557	65	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	99:dbbf35b96557	66
Kojto	99:dbbf35b96557	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	99:dbbf35b96557	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	99:dbbf35b96557	69
Kojto	99:dbbf35b96557	70	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
Kojto	99:dbbf35b96557	71	This parameter must of @ref RCC_PLLMultiplication_Factor */
Kojto	99:dbbf35b96557	72
Kojto	99:dbbf35b96557	73	uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
Kojto	99:dbbf35b96557	74	This parameter must be a value of @ref RCC_PLLDivider_Factor */
Kojto	99:dbbf35b96557	75
Kojto	99:dbbf35b96557	76	}RCC_PLLInitTypeDef;
Kojto	99:dbbf35b96557	77
Kojto	99:dbbf35b96557	78	/**
Kojto	99:dbbf35b96557	79	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	99:dbbf35b96557	80	*/
Kojto	99:dbbf35b96557	81	typedef struct
Kojto	99:dbbf35b96557	82	{
Kojto	99:dbbf35b96557	83	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	99:dbbf35b96557	84	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	99:dbbf35b96557	85
Kojto	99:dbbf35b96557	86	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	99:dbbf35b96557	87	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	99:dbbf35b96557	88
Kojto	99:dbbf35b96557	89	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	99:dbbf35b96557	90	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	99:dbbf35b96557	91
Kojto	99:dbbf35b96557	92	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	99:dbbf35b96557	93	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	99:dbbf35b96557	94
Kojto	99:dbbf35b96557	95	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto	99:dbbf35b96557	96	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	99:dbbf35b96557	97
Kojto	99:dbbf35b96557	98	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	99:dbbf35b96557	99	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	99:dbbf35b96557	100
Kojto	99:dbbf35b96557	101	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	99:dbbf35b96557	102	uint32_t HSI48State; /*!< The new state of the HSI48.
Kojto	99:dbbf35b96557	103	This parameter can be a value of @ref RCC_HSI48_Config */
Kojto	99:dbbf35b96557	104	#endif
Kojto	99:dbbf35b96557	105
Kojto	99:dbbf35b96557	106	uint32_t MSIState; /*!< The new state of the MSI.
Kojto	99:dbbf35b96557	107	This parameter can be a value of @ref RCC_MSI_Config */
Kojto	99:dbbf35b96557	108
Kojto	99:dbbf35b96557	109	uint32_t MSICalibrationValue; /*!< The calibration trimming value.
Kojto	99:dbbf35b96557	110	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
Kojto	99:dbbf35b96557	111
Kojto	99:dbbf35b96557	112	uint32_t MSIClockRange; /*!< The MSI frequency range.
Kojto	99:dbbf35b96557	113	This parameter can be a value of @ref RCC_MSI_Clock_Range */
Kojto	99:dbbf35b96557	114
Kojto	99:dbbf35b96557	115	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	99:dbbf35b96557	116
Kojto	99:dbbf35b96557	117	}RCC_OscInitTypeDef;
Kojto	99:dbbf35b96557	118
Kojto	99:dbbf35b96557	119	/**
Kojto	99:dbbf35b96557	120	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	99:dbbf35b96557	121	*/
Kojto	99:dbbf35b96557	122	typedef struct
Kojto	99:dbbf35b96557	123	{
Kojto	99:dbbf35b96557	124	uint32_t ClockType; /*!< The clock to be configured.
Kojto	99:dbbf35b96557	125	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	99:dbbf35b96557	126
Kojto	99:dbbf35b96557	127	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	99:dbbf35b96557	128	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	99:dbbf35b96557	129
Kojto	99:dbbf35b96557	130	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	99:dbbf35b96557	131	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	99:dbbf35b96557	132
Kojto	99:dbbf35b96557	133	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	99:dbbf35b96557	134	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	99:dbbf35b96557	135
Kojto	99:dbbf35b96557	136	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	99:dbbf35b96557	137	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	99:dbbf35b96557	138
Kojto	99:dbbf35b96557	139	}RCC_ClkInitTypeDef;
Kojto	99:dbbf35b96557	140
Kojto	99:dbbf35b96557	141
Kojto	99:dbbf35b96557	142	/** @defgroup RCC_Private_Constants RCC Private constatnts
Kojto	99:dbbf35b96557	143	* @brief RCC registers bit address in the alias region
Kojto	99:dbbf35b96557	144	* @{
Kojto	99:dbbf35b96557	145	*/
Kojto	99:dbbf35b96557	146	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	99:dbbf35b96557	147	/* --- CR Register ---*/
Kojto	99:dbbf35b96557	148	/* Alias word address of HSION bit */
Kojto	99:dbbf35b96557	149	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto	99:dbbf35b96557	150	/* --- CFGR Register ---*/
Kojto	99:dbbf35b96557	151	/* Alias word address of I2SSRC bit */
Kojto	99:dbbf35b96557	152	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
Kojto	99:dbbf35b96557	153	/* --- CSR Register ---*/
Kojto	99:dbbf35b96557	154	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
Kojto	99:dbbf35b96557	155
Kojto	99:dbbf35b96557	156	/* CR register byte 3 (Bits[23:16]) base address */
Kojto	99:dbbf35b96557	157	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
Kojto	99:dbbf35b96557	158
Kojto	99:dbbf35b96557	159	/* CIER register byte 0 (Bits[0:8]) base address */
Kojto	99:dbbf35b96557	160	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
Kojto	99:dbbf35b96557	161
Kojto	99:dbbf35b96557	162	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto	99:dbbf35b96557	163	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	99:dbbf35b96557	164
Kojto	99:dbbf35b96557	165	/**
Kojto	99:dbbf35b96557	166	* @}
Kojto	99:dbbf35b96557	167	*/
Kojto	99:dbbf35b96557	168
Kojto	99:dbbf35b96557	169	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	99:dbbf35b96557	170	* @{
Kojto	99:dbbf35b96557	171	*/
Kojto	99:dbbf35b96557	172
Kojto	99:dbbf35b96557	173	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
Kojto	99:dbbf35b96557	174	* @{
Kojto	99:dbbf35b96557	175	*/
Kojto	99:dbbf35b96557	176	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	177	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	99:dbbf35b96557	178	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	179	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	99:dbbf35b96557	180	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	99:dbbf35b96557	181	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
Kojto	99:dbbf35b96557	182	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	99:dbbf35b96557	183	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
Kojto	99:dbbf35b96557	184	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
Kojto	99:dbbf35b96557	185	#else
Kojto	99:dbbf35b96557	186	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
Kojto	99:dbbf35b96557	187	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
Kojto	99:dbbf35b96557	188
Kojto	99:dbbf35b96557	189	/**
Kojto	99:dbbf35b96557	190	* @}
Kojto	99:dbbf35b96557	191	*/
Kojto	99:dbbf35b96557	192
Kojto	99:dbbf35b96557	193	/** @defgroup RCC_HSE_Config RCC HSE Config
Kojto	99:dbbf35b96557	194	* @{
Kojto	99:dbbf35b96557	195	*/
Kojto	99:dbbf35b96557	196	#define RCC_HSE_OFF ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	197	#define RCC_HSE_ON RCC_CR_HSEON
Kojto	99:dbbf35b96557	198	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
Kojto	99:dbbf35b96557	199
Kojto	99:dbbf35b96557	200	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
Kojto	99:dbbf35b96557	201	((__HSE__) == RCC_HSE_BYPASS))
Kojto	99:dbbf35b96557	202	/**
Kojto	99:dbbf35b96557	203	* @}
Kojto	99:dbbf35b96557	204	*/
Kojto	99:dbbf35b96557	205
Kojto	99:dbbf35b96557	206	/** @defgroup RCC_LSE_Config RCC LSE Config
Kojto	99:dbbf35b96557	207	* @{
Kojto	99:dbbf35b96557	208	*/
Kojto	99:dbbf35b96557	209	#define RCC_LSE_OFF ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	210	#define RCC_LSE_ON RCC_CSR_LSEON
Kojto	99:dbbf35b96557	211	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON))
Kojto	99:dbbf35b96557	212
Kojto	99:dbbf35b96557	213	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
Kojto	99:dbbf35b96557	214	((__LSE__) == RCC_LSE_BYPASS))
Kojto	99:dbbf35b96557	215	/**
Kojto	99:dbbf35b96557	216	* @}
Kojto	99:dbbf35b96557	217	*/
Kojto	99:dbbf35b96557	218
Kojto	99:dbbf35b96557	219
Kojto	99:dbbf35b96557	220
Kojto	99:dbbf35b96557	221	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
Kojto	99:dbbf35b96557	222	* @{
Kojto	99:dbbf35b96557	223	*/
Kojto	99:dbbf35b96557	224
Kojto	99:dbbf35b96557	225	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
Kojto	99:dbbf35b96557	226	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
Kojto	99:dbbf35b96557	227	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
Kojto	99:dbbf35b96557	228	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
Kojto	99:dbbf35b96557	229	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
Kojto	99:dbbf35b96557	230	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
Kojto	99:dbbf35b96557	231	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
Kojto	99:dbbf35b96557	232
Kojto	99:dbbf35b96557	233	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
Kojto	99:dbbf35b96557	234	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
Kojto	99:dbbf35b96557	235	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
Kojto	99:dbbf35b96557	236	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
Kojto	99:dbbf35b96557	237	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
Kojto	99:dbbf35b96557	238	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
Kojto	99:dbbf35b96557	239	((__RANGE__) == RCC_MSIRANGE_6))
Kojto	99:dbbf35b96557	240
Kojto	99:dbbf35b96557	241	/**
Kojto	99:dbbf35b96557	242	* @}
Kojto	99:dbbf35b96557	243	*/
Kojto	99:dbbf35b96557	244
Kojto	99:dbbf35b96557	245	/** @defgroup RCC_LSI_Config RCC LSI Config
Kojto	99:dbbf35b96557	246	* @{
Kojto	99:dbbf35b96557	247	*/
Kojto	99:dbbf35b96557	248	#define RCC_LSI_OFF ((uint8_t)0x00)
Kojto	99:dbbf35b96557	249	#define RCC_LSI_ON ((uint8_t)0x01)
Kojto	99:dbbf35b96557	250
Kojto	99:dbbf35b96557	251	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
Kojto	99:dbbf35b96557	252
Kojto	99:dbbf35b96557	253	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
Kojto	99:dbbf35b96557	254	/**
Kojto	99:dbbf35b96557	255	* @}
Kojto	99:dbbf35b96557	256	*/
Kojto	99:dbbf35b96557	257
Kojto	99:dbbf35b96557	258
Kojto	99:dbbf35b96557	259	/** @defgroup RCC_MSI_Config RCC MSI Config
Kojto	99:dbbf35b96557	260	* @{
Kojto	99:dbbf35b96557	261	*/
Kojto	99:dbbf35b96557	262	#define RCC_MSI_OFF ((uint8_t)0x00)
Kojto	99:dbbf35b96557	263	#define RCC_MSI_ON ((uint8_t)0x01)
Kojto	99:dbbf35b96557	264
Kojto	99:dbbf35b96557	265	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto	99:dbbf35b96557	266
Kojto	99:dbbf35b96557	267	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
Kojto	99:dbbf35b96557	268	/**
Kojto	99:dbbf35b96557	269	* @}
Kojto	99:dbbf35b96557	270	*/
Kojto	99:dbbf35b96557	271
Kojto	99:dbbf35b96557	272	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	99:dbbf35b96557	273	/** @defgroup RCC_HSI48_Config
Kojto	99:dbbf35b96557	274	* @{
Kojto	99:dbbf35b96557	275	*/
Kojto	99:dbbf35b96557	276	#define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto	99:dbbf35b96557	277	#define RCC_HSI48_ON ((uint8_t)0x01)
Kojto	99:dbbf35b96557	278
Kojto	99:dbbf35b96557	279	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
Kojto	99:dbbf35b96557	280	/**
Kojto	99:dbbf35b96557	281	* @}
Kojto	99:dbbf35b96557	282	*/
Kojto	99:dbbf35b96557	283	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
Kojto	99:dbbf35b96557	284
Kojto	99:dbbf35b96557	285	/** @defgroup RCC_PLL_Config RCC PLL Config
Kojto	99:dbbf35b96557	286	* @{
Kojto	99:dbbf35b96557	287	*/
Kojto	99:dbbf35b96557	288	#define RCC_PLL_NONE ((uint8_t)0x00)
Kojto	99:dbbf35b96557	289	#define RCC_PLL_OFF ((uint8_t)0x01)
Kojto	99:dbbf35b96557	290	#define RCC_PLL_ON ((uint8_t)0x02)
Kojto	99:dbbf35b96557	291
Kojto	99:dbbf35b96557	292	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| ((__PLL__) == RCC_PLL_ON))
Kojto	99:dbbf35b96557	293	/**
Kojto	99:dbbf35b96557	294	* @}
Kojto	99:dbbf35b96557	295	*/
Kojto	99:dbbf35b96557	296
Kojto	99:dbbf35b96557	297	/** @defgroup RCC_PLL_Clock_Source PCC PLL Clock Source
Kojto	99:dbbf35b96557	298	* @{
Kojto	99:dbbf35b96557	299	*/
Kojto	99:dbbf35b96557	300	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
Kojto	99:dbbf35b96557	301	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
Kojto	99:dbbf35b96557	302
Kojto	99:dbbf35b96557	303	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	99:dbbf35b96557	304	((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto	99:dbbf35b96557	305
Kojto	99:dbbf35b96557	306	/**
Kojto	99:dbbf35b96557	307	* @}
Kojto	99:dbbf35b96557	308	*/
Kojto	99:dbbf35b96557	309
Kojto	99:dbbf35b96557	310	/** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers
Kojto	99:dbbf35b96557	311	* @{
Kojto	99:dbbf35b96557	312	*/
Kojto	99:dbbf35b96557	313
Kojto	99:dbbf35b96557	314	#define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
Kojto	99:dbbf35b96557	315	#define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
Kojto	99:dbbf35b96557	316	#define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
Kojto	99:dbbf35b96557	317	#define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
Kojto	99:dbbf35b96557	318	#define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
Kojto	99:dbbf35b96557	319	#define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
Kojto	99:dbbf35b96557	320	#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
Kojto	99:dbbf35b96557	321	#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
Kojto	99:dbbf35b96557	322	#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
Kojto	99:dbbf35b96557	323	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) \|\| ((__MUL__) == RCC_PLLMUL_4) \|\| \
Kojto	99:dbbf35b96557	324	((__MUL__) == RCC_PLLMUL_6) \|\| ((__MUL__) == RCC_PLLMUL_8) \|\| \
Kojto	99:dbbf35b96557	325	((__MUL__) == RCC_PLLMUL_12) \|\| ((__MUL__) == RCC_PLLMUL_16) \|\| \
Kojto	99:dbbf35b96557	326	((__MUL__) == RCC_PLLMUL_24) \|\| ((__MUL__) == RCC_PLLMUL_32) \|\| \
Kojto	99:dbbf35b96557	327	((__MUL__) == RCC_PLLMUL_48))
Kojto	99:dbbf35b96557	328	/**
Kojto	99:dbbf35b96557	329	* @}
Kojto	99:dbbf35b96557	330	*/
Kojto	99:dbbf35b96557	331
Kojto	99:dbbf35b96557	332	/** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers
Kojto	99:dbbf35b96557	333	* @{
Kojto	99:dbbf35b96557	334	*/
Kojto	99:dbbf35b96557	335
Kojto	99:dbbf35b96557	336	#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
Kojto	99:dbbf35b96557	337	#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
Kojto	99:dbbf35b96557	338	#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
Kojto	99:dbbf35b96557	339	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) \|\| ((__DIV__) == RCC_PLLDIV_3) \|\| \
Kojto	99:dbbf35b96557	340	((__DIV__) == RCC_PLLDIV_4))
Kojto	99:dbbf35b96557	341	/**
Kojto	99:dbbf35b96557	342	* @}
Kojto	99:dbbf35b96557	343	*/
Kojto	99:dbbf35b96557	344
Kojto	99:dbbf35b96557	345	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto	99:dbbf35b96557	346	* @{
Kojto	99:dbbf35b96557	347	*/
Kojto	99:dbbf35b96557	348	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto	99:dbbf35b96557	349	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto	99:dbbf35b96557	350	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto	99:dbbf35b96557	351	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto	99:dbbf35b96557	352
Kojto	99:dbbf35b96557	353	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
Kojto	99:dbbf35b96557	354	/**
Kojto	99:dbbf35b96557	355	* @}
Kojto	99:dbbf35b96557	356	*/
Kojto	99:dbbf35b96557	357
Kojto	99:dbbf35b96557	358	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto	99:dbbf35b96557	359	* @{
Kojto	99:dbbf35b96557	360	*/
Kojto	99:dbbf35b96557	361	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
Kojto	99:dbbf35b96557	362	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto	99:dbbf35b96557	363	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto	99:dbbf35b96557	364	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto	99:dbbf35b96557	365
Kojto	99:dbbf35b96557	366	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	99:dbbf35b96557	367	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	99:dbbf35b96557	368	((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
Kojto	99:dbbf35b96557	369	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	99:dbbf35b96557	370	/**
Kojto	99:dbbf35b96557	371	* @}
Kojto	99:dbbf35b96557	372	*/
Kojto	99:dbbf35b96557	373
Kojto	99:dbbf35b96557	374	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto	99:dbbf35b96557	375	* @{
Kojto	99:dbbf35b96557	376	*/
Kojto	99:dbbf35b96557	377	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
Kojto	99:dbbf35b96557	378	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
Kojto	99:dbbf35b96557	379	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
Kojto	99:dbbf35b96557	380
Kojto	99:dbbf35b96557	381	/**
Kojto	99:dbbf35b96557	382	* @}
Kojto	99:dbbf35b96557	383	*/
Kojto	99:dbbf35b96557	384
Kojto	99:dbbf35b96557	385	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock SOurce
Kojto	99:dbbf35b96557	386	* @{
Kojto	99:dbbf35b96557	387	*/
Kojto	99:dbbf35b96557	388	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto	99:dbbf35b96557	389	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto	99:dbbf35b96557	390	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto	99:dbbf35b96557	391	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto	99:dbbf35b96557	392	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto	99:dbbf35b96557	393	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto	99:dbbf35b96557	394	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto	99:dbbf35b96557	395	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto	99:dbbf35b96557	396	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto	99:dbbf35b96557	397
Kojto	99:dbbf35b96557	398	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
Kojto	99:dbbf35b96557	399	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
Kojto	99:dbbf35b96557	400	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
Kojto	99:dbbf35b96557	401	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
Kojto	99:dbbf35b96557	402	((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto	99:dbbf35b96557	403	/**
Kojto	99:dbbf35b96557	404	* @}
Kojto	99:dbbf35b96557	405	*/
Kojto	99:dbbf35b96557	406
Kojto	99:dbbf35b96557	407	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 Clock Source
Kojto	99:dbbf35b96557	408	* @{
Kojto	99:dbbf35b96557	409	*/
Kojto	99:dbbf35b96557	410	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto	99:dbbf35b96557	411	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto	99:dbbf35b96557	412	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto	99:dbbf35b96557	413	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto	99:dbbf35b96557	414	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto	99:dbbf35b96557	415
Kojto	99:dbbf35b96557	416	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
Kojto	99:dbbf35b96557	417	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
Kojto	99:dbbf35b96557	418	((__PCLK__) == RCC_HCLK_DIV16))
Kojto	99:dbbf35b96557	419	/**
Kojto	99:dbbf35b96557	420	* @}
Kojto	99:dbbf35b96557	421	*/
Kojto	99:dbbf35b96557	422
Kojto	99:dbbf35b96557	423	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
Kojto	99:dbbf35b96557	424	* @{
Kojto	99:dbbf35b96557	425	*/
Kojto	99:dbbf35b96557	426	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	427	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
Kojto	99:dbbf35b96557	428	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
Kojto	99:dbbf35b96557	429	#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
Kojto	99:dbbf35b96557	430	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
Kojto	99:dbbf35b96557	431	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
Kojto	99:dbbf35b96557	432	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
Kojto	99:dbbf35b96557	433	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
Kojto	99:dbbf35b96557	434	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
Kojto	99:dbbf35b96557	435	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
Kojto	99:dbbf35b96557	436	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
Kojto	99:dbbf35b96557	437	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
Kojto	99:dbbf35b96557	438	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
Kojto	99:dbbf35b96557	439	/**
Kojto	99:dbbf35b96557	440	* @}
Kojto	99:dbbf35b96557	441	*/
Kojto	99:dbbf35b96557	442
Kojto	99:dbbf35b96557	443	/** @defgroup RCC_MCO_Clock_Source RCC MCo Clock Source
Kojto	99:dbbf35b96557	444	* @{
Kojto	99:dbbf35b96557	445	*/
Kojto	99:dbbf35b96557	446
Kojto	99:dbbf35b96557	447	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
Kojto	99:dbbf35b96557	448	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto	99:dbbf35b96557	449	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
Kojto	99:dbbf35b96557	450	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
Kojto	99:dbbf35b96557	451	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
Kojto	99:dbbf35b96557	452	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
Kojto	99:dbbf35b96557	453	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
Kojto	99:dbbf35b96557	454	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
Kojto	99:dbbf35b96557	455	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	99:dbbf35b96557	456	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
Kojto	99:dbbf35b96557	457	#endif
Kojto	99:dbbf35b96557	458
Kojto	99:dbbf35b96557	459	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	99:dbbf35b96557	460	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Kojto	99:dbbf35b96557	461	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
Kojto	99:dbbf35b96557	462	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
Kojto	99:dbbf35b96557	463	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
Kojto	99:dbbf35b96557	464	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
Kojto	99:dbbf35b96557	465	#else
Kojto	99:dbbf35b96557	466	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
Kojto	99:dbbf35b96557	467	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
Kojto	99:dbbf35b96557	468	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
Kojto	99:dbbf35b96557	469	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
Kojto	99:dbbf35b96557	470	#endif
Kojto	99:dbbf35b96557	471
Kojto	99:dbbf35b96557	472	/**
Kojto	99:dbbf35b96557	473	* @}
Kojto	99:dbbf35b96557	474	*/
Kojto	99:dbbf35b96557	475
Kojto	99:dbbf35b96557	476	/** @defgroup RCC_MCOPrescaler RCC MCO Prescaler
Kojto	99:dbbf35b96557	477	* @{
Kojto	99:dbbf35b96557	478	*/
Kojto	99:dbbf35b96557	479
Kojto	99:dbbf35b96557	480	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
Kojto	99:dbbf35b96557	481	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
Kojto	99:dbbf35b96557	482	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
Kojto	99:dbbf35b96557	483	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
Kojto	99:dbbf35b96557	484	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
Kojto	99:dbbf35b96557	485
Kojto	99:dbbf35b96557	486	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| \
Kojto	99:dbbf35b96557	487	((__DIV__) == RCC_MCODIV_2) \|\| \
Kojto	99:dbbf35b96557	488	((__DIV__) == RCC_MCODIV_4) \|\| \
Kojto	99:dbbf35b96557	489	((__DIV__) == RCC_MCODIV_8) \|\| \
Kojto	99:dbbf35b96557	490	((__DIV__) == RCC_MCODIV_16))
Kojto	99:dbbf35b96557	491	/**
Kojto	99:dbbf35b96557	492	* @}
Kojto	99:dbbf35b96557	493	*/
Kojto	99:dbbf35b96557	494
Kojto	99:dbbf35b96557	495	/** @defgroup RCC_MCO_Index RCC MCO Index
Kojto	99:dbbf35b96557	496	* @{
Kojto	99:dbbf35b96557	497	*/
Kojto	99:dbbf35b96557	498	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	499	#define RCC_MCO2 ((uint32_t)0x00000001)
Kojto	99:dbbf35b96557	500
Kojto	99:dbbf35b96557	501	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2))
Kojto	99:dbbf35b96557	502	/**
Kojto	99:dbbf35b96557	503	* @}
Kojto	99:dbbf35b96557	504	*/
Kojto	99:dbbf35b96557	505
Kojto	99:dbbf35b96557	506	/** @defgroup RCC_Interrupt RCC Interruptions
Kojto	99:dbbf35b96557	507	* @{
Kojto	99:dbbf35b96557	508	*/
Kojto	99:dbbf35b96557	509	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
Kojto	99:dbbf35b96557	510	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF
Kojto	99:dbbf35b96557	511	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
Kojto	99:dbbf35b96557	512	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF
Kojto	99:dbbf35b96557	513	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
Kojto	99:dbbf35b96557	514	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
Kojto	99:dbbf35b96557	515
Kojto	99:dbbf35b96557	516	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF
Kojto	99:dbbf35b96557	517	#define RCC_IT_CSS RCC_CIFR_CSSF
Kojto	99:dbbf35b96557	518	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	99:dbbf35b96557	519	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
Kojto	99:dbbf35b96557	520
Kojto	99:dbbf35b96557	521	#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	99:dbbf35b96557	522	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	99:dbbf35b96557	523	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	99:dbbf35b96557	524	((__IT__) == RCC_IT_HSI48RDY) \|\| ((__IT__) == RCC_IT_LSECSS))
Kojto	99:dbbf35b96557	525
Kojto	99:dbbf35b96557	526	#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	99:dbbf35b96557	527	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	99:dbbf35b96557	528	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	99:dbbf35b96557	529	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_HSI48RDY) \|\| \
Kojto	99:dbbf35b96557	530	((__IT__) == RCC_IT_LSECSS))
Kojto	99:dbbf35b96557	531
Kojto	99:dbbf35b96557	532	#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	99:dbbf35b96557	533	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	99:dbbf35b96557	534	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	99:dbbf35b96557	535	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_HSI48RDY) \|\| \
Kojto	99:dbbf35b96557	536	((__IT__) == RCC_IT_LSECSS))
Kojto	99:dbbf35b96557	537	#else
Kojto	99:dbbf35b96557	538	#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	99:dbbf35b96557	539	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	99:dbbf35b96557	540	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	99:dbbf35b96557	541	((__IT__) == RCC_IT_LSECSS))
Kojto	99:dbbf35b96557	542
Kojto	99:dbbf35b96557	543	#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	99:dbbf35b96557	544	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	99:dbbf35b96557	545	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	99:dbbf35b96557	546	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_LSECSS))
Kojto	99:dbbf35b96557	547
Kojto	99:dbbf35b96557	548
Kojto	99:dbbf35b96557	549	#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
Kojto	99:dbbf35b96557	550	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
Kojto	99:dbbf35b96557	551	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
Kojto	99:dbbf35b96557	552	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_LSECSS))
Kojto	99:dbbf35b96557	553
Kojto	99:dbbf35b96557	554	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
Kojto	99:dbbf35b96557	555	/**
Kojto	99:dbbf35b96557	556	* @}
Kojto	99:dbbf35b96557	557	*/
Kojto	99:dbbf35b96557	558
Kojto	99:dbbf35b96557	559	/** @defgroup RCC_Flag
Kojto	99:dbbf35b96557	560	* Elements values convention: 0XXYYYYYb
Kojto	99:dbbf35b96557	561	* - YYYYY : Flag position in the register
Kojto	99:dbbf35b96557	562	* - 0XX : Register index
Kojto	99:dbbf35b96557	563	* - 01: CR register
Kojto	99:dbbf35b96557	564	* - 10: CSR register
Kojto	99:dbbf35b96557	565	* - 11: CRRCR register
Kojto	99:dbbf35b96557	566	* @{
Kojto	99:dbbf35b96557	567	*/
Kojto	99:dbbf35b96557	568	/* Flags in the CR register */
Kojto	99:dbbf35b96557	569	#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
Kojto	99:dbbf35b96557	570	#define RCC_FLAG_HSIDIV ((uint8_t)0x24)
Kojto	99:dbbf35b96557	571	#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
Kojto	99:dbbf35b96557	572	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
Kojto	99:dbbf35b96557	573	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Kojto	99:dbbf35b96557	574
Kojto	99:dbbf35b96557	575	/* Flags in the CSR register */
Kojto	99:dbbf35b96557	576	#define RCC_FLAG_LSERDY ((uint8_t)0x49)
Kojto	99:dbbf35b96557	577	#define RCC_FLAG_LSECSS ((uint8_t)0x4E)
Kojto	99:dbbf35b96557	578	#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
Kojto	99:dbbf35b96557	579	#define RCC_FLAG_FWRST ((uint8_t)0x58)
Kojto	99:dbbf35b96557	580	#define RCC_FLAG_OBLRST ((uint8_t)0x59)
Kojto	99:dbbf35b96557	581	#define RCC_FLAG_PINRST ((uint8_t)0x5A)
Kojto	99:dbbf35b96557	582	#define RCC_FLAG_PORRST ((uint8_t)0x5B)
Kojto	99:dbbf35b96557	583	#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
Kojto	99:dbbf35b96557	584	#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
Kojto	99:dbbf35b96557	585	#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
Kojto	99:dbbf35b96557	586	#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
Kojto	99:dbbf35b96557	587
Kojto	99:dbbf35b96557	588	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	99:dbbf35b96557	589	/* Flags in the CRRCR register */
Kojto	99:dbbf35b96557	590	#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
Kojto	99:dbbf35b96557	591	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
Kojto	99:dbbf35b96557	592
Kojto	99:dbbf35b96557	593	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto	99:dbbf35b96557	594	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
Kojto	99:dbbf35b96557	595
Kojto	99:dbbf35b96557	596	/**
Kojto	99:dbbf35b96557	597	* @}
Kojto	99:dbbf35b96557	598	*/
Kojto	99:dbbf35b96557	599
Kojto	99:dbbf35b96557	600	/**
Kojto	99:dbbf35b96557	601	* @}
Kojto	99:dbbf35b96557	602	*/
Kojto	99:dbbf35b96557	603	/* Exported macro ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	604	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	99:dbbf35b96557	605	* @{
Kojto	99:dbbf35b96557	606	*/
Kojto	99:dbbf35b96557	607
Kojto	99:dbbf35b96557	608	/** @brief Enable or disable the AHB peripheral clock.
Kojto	99:dbbf35b96557	609	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	610	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	611	* using it.
Kojto	99:dbbf35b96557	612	*/
Kojto	99:dbbf35b96557	613	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	614	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	615	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	99:dbbf35b96557	616	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	617	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto	99:dbbf35b96557	618	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	619	} while(0)
Kojto	99:dbbf35b96557	620
Kojto	99:dbbf35b96557	621	#define __HAL_RCC_MIF_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	622	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	623	SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
Kojto	99:dbbf35b96557	624	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	625	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
Kojto	99:dbbf35b96557	626	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	627	} while(0)
Kojto	99:dbbf35b96557	628
Kojto	99:dbbf35b96557	629	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	630	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	631	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	99:dbbf35b96557	632	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	633	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto	99:dbbf35b96557	634	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	635	} while(0)
Kojto	99:dbbf35b96557	636
Kojto	99:dbbf35b96557	637
Kojto	99:dbbf35b96557	638	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN))
Kojto	99:dbbf35b96557	639	#define __HAL_RCC_MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN))
Kojto	99:dbbf35b96557	640	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN))
Kojto	99:dbbf35b96557	641
Kojto	99:dbbf35b96557	642
Kojto	99:dbbf35b96557	643	/** @brief Enable or disable the IOPORT peripheral clock.
Kojto	99:dbbf35b96557	644	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	645	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	646	* using it.
Kojto	99:dbbf35b96557	647	*/
Kojto	99:dbbf35b96557	648	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	649	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	650	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
Kojto	99:dbbf35b96557	651	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	652	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
Kojto	99:dbbf35b96557	653	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	654	} while(0)
Kojto	99:dbbf35b96557	655
Kojto	99:dbbf35b96557	656	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	657	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	658	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
Kojto	99:dbbf35b96557	659	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	660	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
Kojto	99:dbbf35b96557	661	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	662	} while(0)
Kojto	99:dbbf35b96557	663
Kojto	99:dbbf35b96557	664	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	665	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	666	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
Kojto	99:dbbf35b96557	667	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	668	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
Kojto	99:dbbf35b96557	669	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	670	} while(0)
Kojto	99:dbbf35b96557	671
Kojto	99:dbbf35b96557	672	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	673	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	674	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
Kojto	99:dbbf35b96557	675	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	676	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
Kojto	99:dbbf35b96557	677	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	678	} while(0)
Kojto	99:dbbf35b96557	679
Kojto	99:dbbf35b96557	680	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto	99:dbbf35b96557	681	__IO uint32_t tmpreg; \
Kojto	99:dbbf35b96557	682	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
Kojto	99:dbbf35b96557	683	/* Delay after an RCC peripheral clock enabling */ \
Kojto	99:dbbf35b96557	684	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
Kojto	99:dbbf35b96557	685	UNUSED(tmpreg); \
Kojto	99:dbbf35b96557	686	} while(0)
Kojto	99:dbbf35b96557	687
Kojto	99:dbbf35b96557	688
Kojto	99:dbbf35b96557	689	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN))
Kojto	99:dbbf35b96557	690	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN))
Kojto	99:dbbf35b96557	691	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN))
Kojto	99:dbbf35b96557	692	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN))
Kojto	99:dbbf35b96557	693	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN))
Kojto	99:dbbf35b96557	694
Kojto	99:dbbf35b96557	695
Kojto	99:dbbf35b96557	696	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	99:dbbf35b96557	697	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	698	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	699	* using it.
Kojto	99:dbbf35b96557	700	*/
Kojto	99:dbbf35b96557	701	#define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
Kojto	99:dbbf35b96557	702	#define __HAL_RCC_PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
Kojto	99:dbbf35b96557	703
Kojto	99:dbbf35b96557	704	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN))
Kojto	99:dbbf35b96557	705	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN))
Kojto	99:dbbf35b96557	706
Kojto	99:dbbf35b96557	707	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	99:dbbf35b96557	708	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	99:dbbf35b96557	709	* is disabled and the application software has to enable this clock before
Kojto	99:dbbf35b96557	710	* using it.
Kojto	99:dbbf35b96557	711	*/
Kojto	99:dbbf35b96557	712	#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
Kojto	99:dbbf35b96557	713	#define __HAL_RCC_DBGMCU_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_DBGMCUEN))
Kojto	99:dbbf35b96557	714
Kojto	99:dbbf35b96557	715	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN))
Kojto	99:dbbf35b96557	716	#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN))
Kojto	99:dbbf35b96557	717
Kojto	99:dbbf35b96557	718	/** @brief Force or release AHB peripheral reset.
Kojto	99:dbbf35b96557	719	*/
Kojto	99:dbbf35b96557	720	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto	99:dbbf35b96557	721	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
Kojto	99:dbbf35b96557	722	#define __HAL_RCC_MIF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_MIFRST))
Kojto	99:dbbf35b96557	723	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
Kojto	99:dbbf35b96557	724
Kojto	99:dbbf35b96557	725	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto	99:dbbf35b96557	726	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST))
Kojto	99:dbbf35b96557	727	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST))
Kojto	99:dbbf35b96557	728	#define __HAL_RCC_MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST))
Kojto	99:dbbf35b96557	729
Kojto	99:dbbf35b96557	730
Kojto	99:dbbf35b96557	731	/** @brief Force or release IOPORT peripheral reset.
Kojto	99:dbbf35b96557	732	*/
Kojto	99:dbbf35b96557	733	#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
Kojto	99:dbbf35b96557	734	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOARST))
Kojto	99:dbbf35b96557	735	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOBRST))
Kojto	99:dbbf35b96557	736	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOCRST))
Kojto	99:dbbf35b96557	737	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIODRST))
Kojto	99:dbbf35b96557	738	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOHRST))
Kojto	99:dbbf35b96557	739
Kojto	99:dbbf35b96557	740	#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
Kojto	99:dbbf35b96557	741	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST))
Kojto	99:dbbf35b96557	742	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST))
Kojto	99:dbbf35b96557	743	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST))
Kojto	99:dbbf35b96557	744	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST))
Kojto	99:dbbf35b96557	745	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST))
Kojto	99:dbbf35b96557	746
Kojto	99:dbbf35b96557	747	/** @brief Force or release APB1 peripheral reset.
Kojto	99:dbbf35b96557	748	*/
Kojto	99:dbbf35b96557	749	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	99:dbbf35b96557	750	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	99:dbbf35b96557	751	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	99:dbbf35b96557	752
Kojto	99:dbbf35b96557	753	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	99:dbbf35b96557	754	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST))
Kojto	99:dbbf35b96557	755	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST))
Kojto	99:dbbf35b96557	756
Kojto	99:dbbf35b96557	757	/** @brief Force or release APB2 peripheral reset.
Kojto	99:dbbf35b96557	758	*/
Kojto	99:dbbf35b96557	759	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	99:dbbf35b96557	760	#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
Kojto	99:dbbf35b96557	761	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	99:dbbf35b96557	762
Kojto	99:dbbf35b96557	763	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	99:dbbf35b96557	764	#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST))
Kojto	99:dbbf35b96557	765	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST))
Kojto	99:dbbf35b96557	766
Kojto	99:dbbf35b96557	767	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	768	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	769	* power consumption.
Kojto	99:dbbf35b96557	770	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	771	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto	99:dbbf35b96557	772	*/
Kojto	99:dbbf35b96557	773	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_CRCSMEN))
Kojto	99:dbbf35b96557	774	#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_MIFSMEN))
Kojto	99:dbbf35b96557	775	#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_SRAMSMEN))
Kojto	99:dbbf35b96557	776	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_DMA1SMEN))
Kojto	99:dbbf35b96557	777
Kojto	99:dbbf35b96557	778	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN))
Kojto	99:dbbf35b96557	779	#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN))
Kojto	99:dbbf35b96557	780	#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN))
Kojto	99:dbbf35b96557	781	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN))
Kojto	99:dbbf35b96557	782
Kojto	99:dbbf35b96557	783	/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	784	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	785	* power consumption.
Kojto	99:dbbf35b96557	786	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	787	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto	99:dbbf35b96557	788	*/
Kojto	99:dbbf35b96557	789
Kojto	99:dbbf35b96557	790	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOASMEN))
Kojto	99:dbbf35b96557	791	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOBSMEN))
Kojto	99:dbbf35b96557	792	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOCSMEN))
Kojto	99:dbbf35b96557	793	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIODSMEN))
Kojto	99:dbbf35b96557	794	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOHSMEN))
Kojto	99:dbbf35b96557	795
Kojto	99:dbbf35b96557	796	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN))
Kojto	99:dbbf35b96557	797	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN))
Kojto	99:dbbf35b96557	798	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN))
Kojto	99:dbbf35b96557	799	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN))
Kojto	99:dbbf35b96557	800	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN))
Kojto	99:dbbf35b96557	801
Kojto	99:dbbf35b96557	802	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	803	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	804	* power consumption.
Kojto	99:dbbf35b96557	805	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	806	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto	99:dbbf35b96557	807	*/
Kojto	99:dbbf35b96557	808	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_WWDGSMEN))
Kojto	99:dbbf35b96557	809	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_PWRSMEN))
Kojto	99:dbbf35b96557	810
Kojto	99:dbbf35b96557	811	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN))
Kojto	99:dbbf35b96557	812	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN))
Kojto	99:dbbf35b96557	813
Kojto	99:dbbf35b96557	814	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	99:dbbf35b96557	815	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	99:dbbf35b96557	816	* power consumption.
Kojto	99:dbbf35b96557	817	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	99:dbbf35b96557	818	* @note By default, all peripheral actiated clocks remain enabled during SLEEP mode.
Kojto	99:dbbf35b96557	819	*/
Kojto	99:dbbf35b96557	820	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SYSCFGSMEN))
Kojto	99:dbbf35b96557	821	#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_DBGMCUSMEN))
Kojto	99:dbbf35b96557	822
Kojto	99:dbbf35b96557	823	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN))
Kojto	99:dbbf35b96557	824	#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN))
Kojto	99:dbbf35b96557	825
Kojto	99:dbbf35b96557	826	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
Kojto	99:dbbf35b96557	827	* @note After enabling the HSI, the application software should wait on
Kojto	99:dbbf35b96557	828	* HSIRDY flag to be set indicating that HSI clock is stable and can
Kojto	99:dbbf35b96557	829	* be used to clock the PLL and/or system clock.
Kojto	99:dbbf35b96557	830	* @note HSI can not be stopped if it is used directly or through the PLL
Kojto	99:dbbf35b96557	831	* as system clock. In this case, you have to select another source
Kojto	99:dbbf35b96557	832	* of the system clock then stop the HSI.
Kojto	99:dbbf35b96557	833	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	99:dbbf35b96557	834	* @param __STATE__: specifies the new state of the HSI.
Kojto	99:dbbf35b96557	835	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	836	* @arg RCC_HSI_OFF: turn OFF the HSI oscillator
Kojto	99:dbbf35b96557	837	* @arg RCC_HSI_ON: turn ON the HSI oscillator
Kojto	99:dbbf35b96557	838	* @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
Kojto	99:dbbf35b96557	839	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	99:dbbf35b96557	840	* clock cycles.
Kojto	99:dbbf35b96557	841	*/
Kojto	99:dbbf35b96557	842	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
Kojto	99:dbbf35b96557	843	MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
Kojto	99:dbbf35b96557	844
Kojto	99:dbbf35b96557	845	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	99:dbbf35b96557	846	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	99:dbbf35b96557	847	* It is used (enabled by hardware) as system clock source after startup
Kojto	99:dbbf35b96557	848	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto	99:dbbf35b96557	849	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	99:dbbf35b96557	850	* Security System CSS is enabled).
Kojto	99:dbbf35b96557	851	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	99:dbbf35b96557	852	* you have to select another source of the system clock then stop the HSI.
Kojto	99:dbbf35b96557	853	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	99:dbbf35b96557	854	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	99:dbbf35b96557	855	* system clock source.
Kojto	99:dbbf35b96557	856	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	99:dbbf35b96557	857	* clock cycles.
Kojto	99:dbbf35b96557	858	*/
Kojto	99:dbbf35b96557	859	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto	99:dbbf35b96557	860	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto	99:dbbf35b96557	861
Kojto	99:dbbf35b96557	862	/**
Kojto	99:dbbf35b96557	863	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
Kojto	99:dbbf35b96557	864	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	99:dbbf35b96557	865	* It is used (enabled by hardware) as system clock source after
Kojto	99:dbbf35b96557	866	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
Kojto	99:dbbf35b96557	867	* of failure of the HSE used directly or indirectly as system clock
Kojto	99:dbbf35b96557	868	* (if the Clock Security System CSS is enabled).
Kojto	99:dbbf35b96557	869	* @note MSI can not be stopped if it is used as system clock source.
Kojto	99:dbbf35b96557	870	* In this case, you have to select another source of the system
Kojto	99:dbbf35b96557	871	* clock then stop the MSI.
Kojto	99:dbbf35b96557	872	* @note After enabling the MSI, the application software should wait on
Kojto	99:dbbf35b96557	873	* MSIRDY flag to be set indicating that MSI clock is stable and can
Kojto	99:dbbf35b96557	874	* be used as system clock source.
Kojto	99:dbbf35b96557	875	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
Kojto	99:dbbf35b96557	876	* clock cycles.
Kojto	99:dbbf35b96557	877	*/
Kojto	99:dbbf35b96557	878	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
Kojto	99:dbbf35b96557	879	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
Kojto	99:dbbf35b96557	880
Kojto	99:dbbf35b96557	881	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	99:dbbf35b96557	882	* @note The calibration is used to compensate for the variations in voltage
Kojto	99:dbbf35b96557	883	* and temperature that influence the frequency of the internal HSI RC.
Kojto	99:dbbf35b96557	884	* @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto	99:dbbf35b96557	885	* This parameter must be a number between 0 and 0x1F.
Kojto	99:dbbf35b96557	886	*/
Kojto	99:dbbf35b96557	887	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
Kojto	99:dbbf35b96557	888	RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
Kojto	99:dbbf35b96557	889
Kojto	99:dbbf35b96557	890	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
Kojto	99:dbbf35b96557	891	* @note The calibration is used to compensate for the variations in voltage
Kojto	99:dbbf35b96557	892	* and temperature that influence the frequency of the internal MSI RC.
Kojto	99:dbbf35b96557	893	* Refer to the Application Note AN3300 for more details on how to
Kojto	99:dbbf35b96557	894	* calibrate the MSI.
Kojto	99:dbbf35b96557	895	* @param __MSICalibrationValue__: specifies the calibration trimming value.
Kojto	99:dbbf35b96557	896	* This parameter must be a number between 0 and 0xFF.
Kojto	99:dbbf35b96557	897	*/
Kojto	99:dbbf35b96557	898	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
Kojto	99:dbbf35b96557	899	RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
Kojto	99:dbbf35b96557	900
Kojto	99:dbbf35b96557	901	/**
Kojto	99:dbbf35b96557	902	* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
Kojto	99:dbbf35b96557	903	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
Kojto	99:dbbf35b96557	904	* around 2.097 MHz. The MSI clock does not change after wake-up from
Kojto	99:dbbf35b96557	905	* STOP mode.
Kojto	99:dbbf35b96557	906	* @note The MSI clock range can be modified on the fly.
Kojto	99:dbbf35b96557	907	* @param RCC_MSIRange: specifies the MSI Clock range.
Kojto	99:dbbf35b96557	908	* This parameter must be one of the following values:
Kojto	99:dbbf35b96557	909	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
Kojto	99:dbbf35b96557	910	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
Kojto	99:dbbf35b96557	911	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
Kojto	99:dbbf35b96557	912	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
Kojto	99:dbbf35b96557	913	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
Kojto	99:dbbf35b96557	914	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
Kojto	99:dbbf35b96557	915	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
Kojto	99:dbbf35b96557	916	*/
Kojto	99:dbbf35b96557	917	#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
Kojto	99:dbbf35b96557	918	RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
Kojto	99:dbbf35b96557	919
Kojto	99:dbbf35b96557	920	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	99:dbbf35b96557	921	* @note After enabling the LSI, the application software should wait on
Kojto	99:dbbf35b96557	922	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	99:dbbf35b96557	923	* be used to clock the IWDG and/or the RTC.
Kojto	99:dbbf35b96557	924	* @note LSI can not be disabled if the IWDG is running.
Kojto	99:dbbf35b96557	925	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	99:dbbf35b96557	926	* clock cycles.
Kojto	99:dbbf35b96557	927	*/
Kojto	99:dbbf35b96557	928	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	99:dbbf35b96557	929	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	99:dbbf35b96557	930
Kojto	99:dbbf35b96557	931	/**
Kojto	99:dbbf35b96557	932	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	99:dbbf35b96557	933	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto	99:dbbf35b96557	934	* software should wait on HSERDY flag to be set indicating that HSE clock
Kojto	99:dbbf35b96557	935	* is stable and can be used to clock the PLL and/or system clock.
Kojto	99:dbbf35b96557	936	* @note HSE state can not be changed if it is used directly or through the
Kojto	99:dbbf35b96557	937	* PLL as system clock. In this case, you have to select another source
Kojto	99:dbbf35b96557	938	* of the system clock then change the HSE state (ex. disable it).
Kojto	99:dbbf35b96557	939	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	99:dbbf35b96557	940	* @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto	99:dbbf35b96557	941	* was previously enabled you have to enable it again after calling this
Kojto	99:dbbf35b96557	942	* function.
Kojto	99:dbbf35b96557	943	* @param __STATE__: specifies the new state of the HSE.
Kojto	99:dbbf35b96557	944	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	945	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	99:dbbf35b96557	946	* 6 HSE oscillator clock cycles.
Kojto	99:dbbf35b96557	947	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto	99:dbbf35b96557	948	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto	99:dbbf35b96557	949	*/
Kojto	99:dbbf35b96557	950	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto	99:dbbf35b96557	951	do { \
Kojto	99:dbbf35b96557	952	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	99:dbbf35b96557	953	if((__STATE__) == RCC_HSE_ON) \
Kojto	99:dbbf35b96557	954	{ \
Kojto	99:dbbf35b96557	955	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	99:dbbf35b96557	956	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	99:dbbf35b96557	957	} \
Kojto	99:dbbf35b96557	958	else if((__STATE__) == RCC_HSE_BYPASS) \
Kojto	99:dbbf35b96557	959	{ \
Kojto	99:dbbf35b96557	960	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	99:dbbf35b96557	961	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	99:dbbf35b96557	962	} \
Kojto	99:dbbf35b96557	963	else \
Kojto	99:dbbf35b96557	964	{ \
Kojto	99:dbbf35b96557	965	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	99:dbbf35b96557	966	} \
Kojto	99:dbbf35b96557	967	} while(0)
Kojto	99:dbbf35b96557	968
Kojto	99:dbbf35b96557	969	/**
Kojto	99:dbbf35b96557	970	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	99:dbbf35b96557	971	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	99:dbbf35b96557	972	* this domain after reset, you have to enable write access using
Kojto	99:dbbf35b96557	973	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	99:dbbf35b96557	974	* (to be done once after reset).
Kojto	99:dbbf35b96557	975	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto	99:dbbf35b96557	976	* software should wait on LSERDY flag to be set indicating that LSE clock
Kojto	99:dbbf35b96557	977	* is stable and can be used to clock the RTC.
Kojto	99:dbbf35b96557	978	* @param __STATE__: specifies the new state of the LSE.
Kojto	99:dbbf35b96557	979	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	980	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto	99:dbbf35b96557	981	* 6 LSE oscillator clock cycles.
Kojto	99:dbbf35b96557	982	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto	99:dbbf35b96557	983	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto	99:dbbf35b96557	984	*/
Kojto	99:dbbf35b96557	985	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto	99:dbbf35b96557	986	do { \
Kojto	99:dbbf35b96557	987	if((__STATE__) == RCC_LSE_ON) \
Kojto	99:dbbf35b96557	988	{ \
Kojto	99:dbbf35b96557	989	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	99:dbbf35b96557	990	} \
Kojto	99:dbbf35b96557	991	else if((__STATE__) == RCC_LSE_OFF) \
Kojto	99:dbbf35b96557	992	{ \
Kojto	99:dbbf35b96557	993	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	99:dbbf35b96557	994	} \
Kojto	99:dbbf35b96557	995	else if((__STATE__) == RCC_LSE_BYPASS) \
Kojto	99:dbbf35b96557	996	{ \
Kojto	99:dbbf35b96557	997	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	99:dbbf35b96557	998	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Kojto	99:dbbf35b96557	999	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	99:dbbf35b96557	1000	} \
Kojto	99:dbbf35b96557	1001	else \
Kojto	99:dbbf35b96557	1002	{ \
Kojto	99:dbbf35b96557	1003	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto	99:dbbf35b96557	1004	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Kojto	99:dbbf35b96557	1005	} \
Kojto	99:dbbf35b96557	1006	} while(0)
Kojto	99:dbbf35b96557	1007
Kojto	99:dbbf35b96557	1008	/** @brief Macros to enable or disable the the RTC clock.
Kojto	99:dbbf35b96557	1009	* @note These macros must be used only after the RTC clock source was selected.
Kojto	99:dbbf35b96557	1010	*/
Kojto	99:dbbf35b96557	1011	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
Kojto	99:dbbf35b96557	1012	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
Kojto	99:dbbf35b96557	1013
Kojto	99:dbbf35b96557	1014	/**
Kojto	99:dbbf35b96557	1015	* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
Kojto	99:dbbf35b96557	1016	* @note As the RTC clock configuration bits are in the RTC domain and write
Kojto	99:dbbf35b96557	1017	* access is denied to this domain after reset, you have to enable write
Kojto	99:dbbf35b96557	1018	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
Kojto	99:dbbf35b96557	1019	* the RTC clock source (to be done once after reset).
Kojto	99:dbbf35b96557	1020	* @note Once the RTC clock is configured it cannot be changed unless the RTC
Kojto	99:dbbf35b96557	1021	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
Kojto	99:dbbf35b96557	1022	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
Kojto	99:dbbf35b96557	1023	*
Kojto	99:dbbf35b96557	1024	* @param RCC_RTCCLKSource: specifies the RTC clock source.
Kojto	99:dbbf35b96557	1025	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	1026	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	99:dbbf35b96557	1027	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	99:dbbf35b96557	1028	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
Kojto	99:dbbf35b96557	1029	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
Kojto	99:dbbf35b96557	1030	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
Kojto	99:dbbf35b96557	1031	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
Kojto	99:dbbf35b96557	1032	*
Kojto	99:dbbf35b96557	1033	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto	99:dbbf35b96557	1034	* work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto	99:dbbf35b96557	1035	* However, when the HSE clock is used as RTC clock source, the RTC
Kojto	99:dbbf35b96557	1036	* cannot be used in STOP and STANDBY modes.
Kojto	99:dbbf35b96557	1037	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto	99:dbbf35b96557	1038	* RTC clock source).
Kojto	99:dbbf35b96557	1039	*/
Kojto	99:dbbf35b96557	1040	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
Kojto	99:dbbf35b96557	1041	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTCCLKSource__) & 0xFFFCFFFF)) : CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
Kojto	99:dbbf35b96557	1042
Kojto	99:dbbf35b96557	1043	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto	99:dbbf35b96557	1044	MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)(__RTCCLKSource__)); \
Kojto	99:dbbf35b96557	1045	} while (0)
Kojto	99:dbbf35b96557	1046
Kojto	99:dbbf35b96557	1047	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
Kojto	99:dbbf35b96557	1048
Kojto	99:dbbf35b96557	1049	/** @brief Macros to force or release the Backup domain reset.
Kojto	99:dbbf35b96557	1050	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	99:dbbf35b96557	1051	* and the RTC clock source selection in RCC_CSR register.
Kojto	99:dbbf35b96557	1052	* @note The BKPSRAM is not affected by this reset.
Kojto	99:dbbf35b96557	1053	*/
Kojto	99:dbbf35b96557	1054	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
Kojto	99:dbbf35b96557	1055	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
Kojto	99:dbbf35b96557	1056
Kojto	99:dbbf35b96557	1057	/** @brief Macros to enable or disable the main PLL.
Kojto	99:dbbf35b96557	1058	* @note After enabling the main PLL, the application software should wait on
Kojto	99:dbbf35b96557	1059	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	99:dbbf35b96557	1060	* be used as system clock source.
Kojto	99:dbbf35b96557	1061	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	99:dbbf35b96557	1062	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	99:dbbf35b96557	1063	*/
Kojto	99:dbbf35b96557	1064	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	99:dbbf35b96557	1065	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	99:dbbf35b96557	1066
Kojto	99:dbbf35b96557	1067	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	99:dbbf35b96557	1068	* @note This function must be used only when the main PLL is disabled.
Kojto	99:dbbf35b96557	1069	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	99:dbbf35b96557	1070	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	1071	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	1072	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	99:dbbf35b96557	1073	* @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
Kojto	99:dbbf35b96557	1074	* This parameter must be one of the following values:
Kojto	99:dbbf35b96557	1075	* @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
Kojto	99:dbbf35b96557	1076	* @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
Kojto	99:dbbf35b96557	1077	* @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
Kojto	99:dbbf35b96557	1078	* @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
Kojto	99:dbbf35b96557	1079	* @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
Kojto	99:dbbf35b96557	1080	* @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
Kojto	99:dbbf35b96557	1081	* @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
Kojto	99:dbbf35b96557	1082	* @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
Kojto	99:dbbf35b96557	1083	* @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
Kojto	99:dbbf35b96557	1084	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
Kojto	99:dbbf35b96557	1085	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
Kojto	99:dbbf35b96557	1086	* in Range 3.
Kojto	99:dbbf35b96557	1087	* @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
Kojto	99:dbbf35b96557	1088	* This parameter must be one of the following values:
Kojto	99:dbbf35b96557	1089	* @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
Kojto	99:dbbf35b96557	1090	* @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
Kojto	99:dbbf35b96557	1091	* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
Kojto	99:dbbf35b96557	1092	*/
Kojto	99:dbbf35b96557	1093
Kojto	99:dbbf35b96557	1094	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__ ,__PLLDIV__ ) \
Kojto	99:dbbf35b96557	1095	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\| (__PLLDIV__)\| (__RCC_PLLSource__)))
Kojto	99:dbbf35b96557	1096
Kojto	99:dbbf35b96557	1097	/** @brief Macro to get the clock source used as system clock.
Kojto	99:dbbf35b96557	1098	* @retval The clock source used as system clock. The returned value can be one
Kojto	99:dbbf35b96557	1099	* of the following:
Kojto	99:dbbf35b96557	1100	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
Kojto	99:dbbf35b96557	1101	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
Kojto	99:dbbf35b96557	1102	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
Kojto	99:dbbf35b96557	1103	*/
Kojto	99:dbbf35b96557	1104	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto	99:dbbf35b96557	1105
Kojto	99:dbbf35b96557	1106	/** @brief Macro to get the oscillator used as PLL clock source.
Kojto	99:dbbf35b96557	1107	* @retval The oscillator used as PLL clock source. The returned value can be one
Kojto	99:dbbf35b96557	1108	* of the following:
Kojto	99:dbbf35b96557	1109	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto	99:dbbf35b96557	1110	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto	99:dbbf35b96557	1111	*/
Kojto	99:dbbf35b96557	1112	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
Kojto	99:dbbf35b96557	1113
Kojto	99:dbbf35b96557	1114	/** @defgroup RCC_Flags_Interrupts_Management
Kojto	99:dbbf35b96557	1115	* @brief macros to manage the specified RCC Flags and interrupts.
Kojto	99:dbbf35b96557	1116	* @{
Kojto	99:dbbf35b96557	1117	*/
Kojto	99:dbbf35b96557	1118
Kojto	99:dbbf35b96557	1119	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
Kojto	99:dbbf35b96557	1120	* the selected interrupts).
Kojto	99:dbbf35b96557	1121	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
Kojto	99:dbbf35b96557	1122	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
Kojto	99:dbbf35b96557	1123	* automatically generated. The NMI will be executed indefinitely, and
Kojto	99:dbbf35b96557	1124	* since NMI has higher priority than any other IRQ (and main program)
Kojto	99:dbbf35b96557	1125	* the application will be stacked in the NMI ISR unless the CSS interrupt
Kojto	99:dbbf35b96557	1126	* pending bit is cleared.
Kojto	99:dbbf35b96557	1127	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	99:dbbf35b96557	1128	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	1129	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	99:dbbf35b96557	1130	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	99:dbbf35b96557	1131	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	99:dbbf35b96557	1132	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	99:dbbf35b96557	1133	* @arg RCC_IT_PLLRDY: PLL ready interrupt
Kojto	99:dbbf35b96557	1134	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	99:dbbf35b96557	1135	* @arg RCC_IT_LSECSS: LSE CSS interrupt
Kojto	99:dbbf35b96557	1136	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
Kojto	99:dbbf35b96557	1137	*/
Kojto	99:dbbf35b96557	1138	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (RCC->CIER \|= (__INTERRUPT__))
Kojto	99:dbbf35b96557	1139
Kojto	99:dbbf35b96557	1140	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
Kojto	99:dbbf35b96557	1141	* the selected interrupts).
Kojto	99:dbbf35b96557	1142	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
Kojto	99:dbbf35b96557	1143	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
Kojto	99:dbbf35b96557	1144	* automatically generated. The NMI will be executed indefinitely, and
Kojto	99:dbbf35b96557	1145	* since NMI has higher priority than any other IRQ (and main program)
Kojto	99:dbbf35b96557	1146	* the application will be stacked in the NMI ISR unless the CSS interrupt
Kojto	99:dbbf35b96557	1147	* pending bit is cleared.
Kojto	99:dbbf35b96557	1148	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	99:dbbf35b96557	1149	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	1150	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	99:dbbf35b96557	1151	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	99:dbbf35b96557	1152	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	99:dbbf35b96557	1153	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	99:dbbf35b96557	1154	* @arg RCC_IT_PLLRDY: PLL ready interrupt
Kojto	99:dbbf35b96557	1155	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	99:dbbf35b96557	1156	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
Kojto	99:dbbf35b96557	1157	* @arg RCC_IT_LSECSS: LSE CSS interrupt
Kojto	99:dbbf35b96557	1158
Kojto	99:dbbf35b96557	1159	*/
Kojto	99:dbbf35b96557	1160	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (RCC->CIER &= ~(__INTERRUPT__))
Kojto	99:dbbf35b96557	1161
Kojto	99:dbbf35b96557	1162	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto	99:dbbf35b96557	1163	* bits to clear the selected interrupt pending bits.
Kojto	99:dbbf35b96557	1164	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	99:dbbf35b96557	1165	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	1166	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	99:dbbf35b96557	1167	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	99:dbbf35b96557	1168	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	99:dbbf35b96557	1169	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	99:dbbf35b96557	1170	* @arg RCC_IT_PLLRDY: PLL ready interrupt
Kojto	99:dbbf35b96557	1171	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	99:dbbf35b96557	1172	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
Kojto	99:dbbf35b96557	1173	* @arg RCC_IT_LSECSS: LSE CSS interrupt
Kojto	99:dbbf35b96557	1174	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	99:dbbf35b96557	1175	*/
Kojto	99:dbbf35b96557	1176	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
Kojto	99:dbbf35b96557	1177
Kojto	99:dbbf35b96557	1178	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	99:dbbf35b96557	1179	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	99:dbbf35b96557	1180	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	1181	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	99:dbbf35b96557	1182	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	99:dbbf35b96557	1183	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	99:dbbf35b96557	1184	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	99:dbbf35b96557	1185	* @arg RCC_IT_PLLRDY: PLL ready interrupt
Kojto	99:dbbf35b96557	1186	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	99:dbbf35b96557	1187	* @arg RCC_IT_LSECSS: LSE CSS interrupt
Kojto	99:dbbf35b96557	1188	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	99:dbbf35b96557	1189	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	99:dbbf35b96557	1190	*/
Kojto	99:dbbf35b96557	1191	#define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	99:dbbf35b96557	1192
Kojto	99:dbbf35b96557	1193	/** @brief Set RMVF bit to clear the reset flags.
Kojto	99:dbbf35b96557	1194	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto	99:dbbf35b96557	1195	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
Kojto	99:dbbf35b96557	1196	*/
Kojto	99:dbbf35b96557	1197	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
Kojto	99:dbbf35b96557	1198
Kojto	99:dbbf35b96557	1199	/** @brief Check RCC flag is set or not.
Kojto	99:dbbf35b96557	1200	* @param __FLAG__: specifies the flag to check.
Kojto	99:dbbf35b96557	1201	* This parameter can be one of the following values:
Kojto	99:dbbf35b96557	1202	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Kojto	99:dbbf35b96557	1203	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
Kojto	99:dbbf35b96557	1204	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
Kojto	99:dbbf35b96557	1205	* @arg RCC_FLAG_PLLRDY: PLL clock ready
Kojto	99:dbbf35b96557	1206	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
Kojto	99:dbbf35b96557	1207	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
Kojto	99:dbbf35b96557	1208	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Kojto	99:dbbf35b96557	1209	* @arg RCC_FLAG_FWRST: Firewall reset
Kojto	99:dbbf35b96557	1210	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
Kojto	99:dbbf35b96557	1211	* @arg RCC_FLAG_PINRST: Pin reset
Kojto	99:dbbf35b96557	1212	* @arg RCC_FLAG_PORRST: POR/PDR reset
Kojto	99:dbbf35b96557	1213	* @arg RCC_FLAG_SFTRST: Software reset
Kojto	99:dbbf35b96557	1214	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
Kojto	99:dbbf35b96557	1215	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
Kojto	99:dbbf35b96557	1216	* @arg RCC_FLAG_LPWRRST: Low Power reset
Kojto	99:dbbf35b96557	1217	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	99:dbbf35b96557	1218	*/
Kojto	99:dbbf35b96557	1219	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	99:dbbf35b96557	1220	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
Kojto	99:dbbf35b96557	1221	RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
Kojto	99:dbbf35b96557	1222
Kojto	99:dbbf35b96557	1223	/**
Kojto	99:dbbf35b96557	1224	* @}
Kojto	99:dbbf35b96557	1225	*/
Kojto	99:dbbf35b96557	1226
Kojto	99:dbbf35b96557	1227	/**
Kojto	99:dbbf35b96557	1228	* @}
Kojto	99:dbbf35b96557	1229	*/
Kojto	99:dbbf35b96557	1230
Kojto	99:dbbf35b96557	1231	/* Include RCC HAL Extension module */
Kojto	99:dbbf35b96557	1232	#include "stm32l0xx_hal_rcc_ex.h"
Kojto	99:dbbf35b96557	1233
Kojto	99:dbbf35b96557	1234	/** @defgroup RCC_Exported_Functions RCC Exported Functions
Kojto	99:dbbf35b96557	1235	* @{
Kojto	99:dbbf35b96557	1236	*/
Kojto	99:dbbf35b96557	1237
Kojto	99:dbbf35b96557	1238	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto	99:dbbf35b96557	1239	* @{
Kojto	99:dbbf35b96557	1240	*/
Kojto	99:dbbf35b96557	1241	void HAL_RCC_DeInit(void);
Kojto	99:dbbf35b96557	1242	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	99:dbbf35b96557	1243	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	99:dbbf35b96557	1244	/**
Kojto	99:dbbf35b96557	1245	* @}
Kojto	99:dbbf35b96557	1246	*/
Kojto	99:dbbf35b96557	1247
Kojto	99:dbbf35b96557	1248	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
Kojto	99:dbbf35b96557	1249	* @{
Kojto	99:dbbf35b96557	1250	*/
Kojto	99:dbbf35b96557	1251	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	99:dbbf35b96557	1252	void HAL_RCC_EnableCSS(void);
Kojto	99:dbbf35b96557	1253	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	99:dbbf35b96557	1254	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	99:dbbf35b96557	1255	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	99:dbbf35b96557	1256	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	99:dbbf35b96557	1257	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	99:dbbf35b96557	1258	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	99:dbbf35b96557	1259	/* CSS NMI IRQ handler */
Kojto	99:dbbf35b96557	1260	void HAL_RCC_NMI_IRQHandler(void);
Kojto	99:dbbf35b96557	1261
Kojto	99:dbbf35b96557	1262	/* User Callbacks in non blocking mode (IT mode) */
Kojto	99:dbbf35b96557	1263	void HAL_RCC_CSSCallback(void);
Kojto	99:dbbf35b96557	1264	/**
Kojto	99:dbbf35b96557	1265	* @}
Kojto	99:dbbf35b96557	1266	*/
Kojto	99:dbbf35b96557	1267
Kojto	99:dbbf35b96557	1268	/**
Kojto	99:dbbf35b96557	1269	* @}
Kojto	99:dbbf35b96557	1270	*/
Kojto	99:dbbf35b96557	1271
Kojto	99:dbbf35b96557	1272	/**
Kojto	99:dbbf35b96557	1273	* @}
Kojto	99:dbbf35b96557	1274	*/
Kojto	99:dbbf35b96557	1275
Kojto	99:dbbf35b96557	1276	/**
Kojto	99:dbbf35b96557	1277	* @}
Kojto	99:dbbf35b96557	1278	*/
Kojto	99:dbbf35b96557	1279
Kojto	99:dbbf35b96557	1280	#ifdef __cplusplus
Kojto	99:dbbf35b96557	1281	}
Kojto	99:dbbf35b96557	1282	#endif
Kojto	99:dbbf35b96557	1283
Kojto	99:dbbf35b96557	1284	#endif /* __STM32l0xx_HAL_RCC_H */
Kojto	99:dbbf35b96557	1285
Kojto	99:dbbf35b96557	1286	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	99:dbbf35b96557	1287

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_DISCO_L053C8/stm32l0xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

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