Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_DISCO_F469NI/stm32f469xx.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
110:165afa46840b 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 110:165afa46840b 1 /**
Kojto 110:165afa46840b 2 ******************************************************************************
Kojto 110:165afa46840b 3 * @file stm32f469xx.h
Kojto 110:165afa46840b 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V2.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
Kojto 110:165afa46840b 7 * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File.
Kojto 110:165afa46840b 8 *
Kojto 110:165afa46840b 9 * This file contains:
Kojto 110:165afa46840b 10 * - Data structures and the address mapping for all peripherals
Kojto 110:165afa46840b 11 * - Peripheral's registers declarations and bits definition
Kojto 110:165afa46840b 12 * - Macros to access peripheral’s registers hardware
Kojto 110:165afa46840b 13 *
Kojto 110:165afa46840b 14 ******************************************************************************
Kojto 110:165afa46840b 15 * @attention
Kojto 110:165afa46840b 16 *
Kojto 110:165afa46840b 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 110:165afa46840b 18 *
Kojto 110:165afa46840b 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 110:165afa46840b 20 * are permitted provided that the following conditions are met:
Kojto 110:165afa46840b 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 110:165afa46840b 22 * this list of conditions and the following disclaimer.
Kojto 110:165afa46840b 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 110:165afa46840b 24 * this list of conditions and the following disclaimer in the documentation
Kojto 110:165afa46840b 25 * and/or other materials provided with the distribution.
Kojto 110:165afa46840b 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 110:165afa46840b 27 * may be used to endorse or promote products derived from this software
Kojto 110:165afa46840b 28 * without specific prior written permission.
Kojto 110:165afa46840b 29 *
Kojto 110:165afa46840b 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 110:165afa46840b 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 110:165afa46840b 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 110:165afa46840b 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 110:165afa46840b 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 110:165afa46840b 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 110:165afa46840b 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 110:165afa46840b 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 110:165afa46840b 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 110:165afa46840b 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 110:165afa46840b 40 *
Kojto 110:165afa46840b 41 ******************************************************************************
Kojto 110:165afa46840b 42 */
Kojto 110:165afa46840b 43
Kojto 110:165afa46840b 44 /** @addtogroup CMSIS_Device
Kojto 110:165afa46840b 45 * @{
Kojto 110:165afa46840b 46 */
Kojto 110:165afa46840b 47
Kojto 110:165afa46840b 48 /** @addtogroup stm32f469xx
Kojto 110:165afa46840b 49 * @{
Kojto 110:165afa46840b 50 */
Kojto 110:165afa46840b 51
Kojto 110:165afa46840b 52 #ifndef __STM32F469xx_H
Kojto 110:165afa46840b 53 #define __STM32F469xx_H
Kojto 110:165afa46840b 54
Kojto 110:165afa46840b 55 #ifdef __cplusplus
Kojto 110:165afa46840b 56 extern "C" {
Kojto 110:165afa46840b 57 #endif /* __cplusplus */
Kojto 110:165afa46840b 58
Kojto 110:165afa46840b 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 110:165afa46840b 60 * @{
Kojto 110:165afa46840b 61 */
Kojto 110:165afa46840b 62
Kojto 110:165afa46840b 63 /**
Kojto 110:165afa46840b 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
Kojto 110:165afa46840b 65 */
Kojto 110:165afa46840b 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
Kojto 110:165afa46840b 67 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
Kojto 110:165afa46840b 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
Kojto 110:165afa46840b 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 110:165afa46840b 70 #define __FPU_PRESENT 1 /*!< FPU present */
Kojto 110:165afa46840b 71
Kojto 110:165afa46840b 72 /**
Kojto 110:165afa46840b 73 * @}
Kojto 110:165afa46840b 74 */
Kojto 110:165afa46840b 75
Kojto 110:165afa46840b 76 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 110:165afa46840b 77 * @{
Kojto 110:165afa46840b 78 */
Kojto 110:165afa46840b 79
Kojto 110:165afa46840b 80 /**
Kojto 110:165afa46840b 81 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
Kojto 110:165afa46840b 82 * in @ref Library_configuration_section
Kojto 110:165afa46840b 83 */
Kojto 110:165afa46840b 84 typedef enum
Kojto 110:165afa46840b 85 {
Kojto 110:165afa46840b 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
Kojto 110:165afa46840b 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 110:165afa46840b 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
Kojto 110:165afa46840b 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Kojto 110:165afa46840b 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
Kojto 110:165afa46840b 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
Kojto 110:165afa46840b 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
Kojto 110:165afa46840b 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
Kojto 110:165afa46840b 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
Kojto 110:165afa46840b 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 110:165afa46840b 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 110:165afa46840b 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 110:165afa46840b 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 110:165afa46840b 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
Kojto 110:165afa46840b 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 110:165afa46840b 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 110:165afa46840b 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 110:165afa46840b 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 110:165afa46840b 104 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 110:165afa46840b 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 110:165afa46840b 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 110:165afa46840b 107 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
Kojto 110:165afa46840b 108 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
Kojto 110:165afa46840b 109 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
Kojto 110:165afa46840b 110 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
Kojto 110:165afa46840b 111 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
Kojto 110:165afa46840b 112 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
Kojto 110:165afa46840b 113 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
Kojto 110:165afa46840b 114 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
Kojto 110:165afa46840b 115 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
Kojto 110:165afa46840b 116 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
Kojto 110:165afa46840b 117 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
Kojto 110:165afa46840b 118 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
Kojto 110:165afa46840b 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 110:165afa46840b 120 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
Kojto 110:165afa46840b 121 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
Kojto 110:165afa46840b 122 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
Kojto 110:165afa46840b 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 110:165afa46840b 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 110:165afa46840b 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 110:165afa46840b 126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 110:165afa46840b 127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 110:165afa46840b 128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 110:165afa46840b 129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 110:165afa46840b 130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 110:165afa46840b 131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 110:165afa46840b 132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 110:165afa46840b 133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 110:165afa46840b 134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 110:165afa46840b 135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
Kojto 110:165afa46840b 136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 110:165afa46840b 137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
Kojto 110:165afa46840b 138 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
Kojto 110:165afa46840b 139 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
Kojto 110:165afa46840b 140 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
Kojto 110:165afa46840b 141 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
Kojto 110:165afa46840b 142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
Kojto 110:165afa46840b 143 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
Kojto 110:165afa46840b 144 FMC_IRQn = 48, /*!< FMC global Interrupt */
Kojto 110:165afa46840b 145 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
Kojto 110:165afa46840b 146 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
Kojto 110:165afa46840b 147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
Kojto 110:165afa46840b 148 UART4_IRQn = 52, /*!< UART4 global Interrupt */
Kojto 110:165afa46840b 149 UART5_IRQn = 53, /*!< UART5 global Interrupt */
Kojto 110:165afa46840b 150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
Kojto 110:165afa46840b 151 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
Kojto 110:165afa46840b 152 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
Kojto 110:165afa46840b 153 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
Kojto 110:165afa46840b 154 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
Kojto 110:165afa46840b 155 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
Kojto 110:165afa46840b 156 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
Kojto 110:165afa46840b 157 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
Kojto 110:165afa46840b 158 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
Kojto 110:165afa46840b 159 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
Kojto 110:165afa46840b 160 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
Kojto 110:165afa46840b 161 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
Kojto 110:165afa46840b 162 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
Kojto 110:165afa46840b 163 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
Kojto 110:165afa46840b 164 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
Kojto 110:165afa46840b 165 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
Kojto 110:165afa46840b 166 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
Kojto 110:165afa46840b 167 USART6_IRQn = 71, /*!< USART6 global interrupt */
Kojto 110:165afa46840b 168 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
Kojto 110:165afa46840b 169 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
Kojto 110:165afa46840b 170 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
Kojto 110:165afa46840b 171 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
Kojto 110:165afa46840b 172 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
Kojto 110:165afa46840b 173 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
Kojto 110:165afa46840b 174 DCMI_IRQn = 78, /*!< DCMI global interrupt */
Kojto 110:165afa46840b 175 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
Kojto 110:165afa46840b 176 FPU_IRQn = 81, /*!< FPU global interrupt */
Kojto 110:165afa46840b 177 UART7_IRQn = 82, /*!< UART7 global interrupt */
Kojto 110:165afa46840b 178 UART8_IRQn = 83, /*!< UART8 global interrupt */
Kojto 110:165afa46840b 179 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
Kojto 110:165afa46840b 180 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
Kojto 110:165afa46840b 181 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
Kojto 110:165afa46840b 182 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
Kojto 110:165afa46840b 183 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
Kojto 110:165afa46840b 184 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
Kojto 110:165afa46840b 185 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
Kojto 110:165afa46840b 186 QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
Kojto 110:165afa46840b 187 DSI_IRQn = 92 /*!< DSI global Interrupt */
Kojto 110:165afa46840b 188 } IRQn_Type;
Kojto 110:165afa46840b 189
Kojto 110:165afa46840b 190 /**
Kojto 110:165afa46840b 191 * @}
Kojto 110:165afa46840b 192 */
Kojto 110:165afa46840b 193
Kojto 110:165afa46840b 194 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Kojto 110:165afa46840b 195 #include "system_stm32f4xx.h"
Kojto 110:165afa46840b 196 #include <stdint.h>
Kojto 110:165afa46840b 197
Kojto 110:165afa46840b 198 /** @addtogroup Peripheral_registers_structures
Kojto 110:165afa46840b 199 * @{
Kojto 110:165afa46840b 200 */
Kojto 110:165afa46840b 201
Kojto 110:165afa46840b 202 /**
Kojto 110:165afa46840b 203 * @brief Analog to Digital Converter
Kojto 110:165afa46840b 204 */
Kojto 110:165afa46840b 205
Kojto 110:165afa46840b 206 typedef struct
Kojto 110:165afa46840b 207 {
Kojto 110:165afa46840b 208 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
Kojto 110:165afa46840b 209 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
Kojto 110:165afa46840b 210 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
Kojto 110:165afa46840b 211 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
Kojto 110:165afa46840b 212 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
Kojto 110:165afa46840b 213 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
Kojto 110:165afa46840b 214 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
Kojto 110:165afa46840b 215 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
Kojto 110:165afa46840b 216 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
Kojto 110:165afa46840b 217 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
Kojto 110:165afa46840b 218 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
Kojto 110:165afa46840b 219 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
Kojto 110:165afa46840b 220 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
Kojto 110:165afa46840b 221 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
Kojto 110:165afa46840b 222 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
Kojto 110:165afa46840b 223 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
Kojto 110:165afa46840b 224 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
Kojto 110:165afa46840b 225 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
Kojto 110:165afa46840b 226 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
Kojto 110:165afa46840b 227 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
Kojto 110:165afa46840b 228 } ADC_TypeDef;
Kojto 110:165afa46840b 229
Kojto 110:165afa46840b 230 typedef struct
Kojto 110:165afa46840b 231 {
Kojto 110:165afa46840b 232 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
Kojto 110:165afa46840b 233 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
Kojto 110:165afa46840b 234 __IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto 110:165afa46840b 235 AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto 110:165afa46840b 236 } ADC_Common_TypeDef;
Kojto 110:165afa46840b 237
Kojto 110:165afa46840b 238
Kojto 110:165afa46840b 239 /**
Kojto 110:165afa46840b 240 * @brief Controller Area Network TxMailBox
Kojto 110:165afa46840b 241 */
Kojto 110:165afa46840b 242
Kojto 110:165afa46840b 243 typedef struct
Kojto 110:165afa46840b 244 {
Kojto 110:165afa46840b 245 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 110:165afa46840b 246 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 110:165afa46840b 247 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 110:165afa46840b 248 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 110:165afa46840b 249 } CAN_TxMailBox_TypeDef;
Kojto 110:165afa46840b 250
Kojto 110:165afa46840b 251 /**
Kojto 110:165afa46840b 252 * @brief Controller Area Network FIFOMailBox
Kojto 110:165afa46840b 253 */
Kojto 110:165afa46840b 254
Kojto 110:165afa46840b 255 typedef struct
Kojto 110:165afa46840b 256 {
Kojto 110:165afa46840b 257 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 110:165afa46840b 258 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 110:165afa46840b 259 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 110:165afa46840b 260 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 110:165afa46840b 261 } CAN_FIFOMailBox_TypeDef;
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 /**
Kojto 110:165afa46840b 264 * @brief Controller Area Network FilterRegister
Kojto 110:165afa46840b 265 */
Kojto 110:165afa46840b 266
Kojto 110:165afa46840b 267 typedef struct
Kojto 110:165afa46840b 268 {
Kojto 110:165afa46840b 269 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 110:165afa46840b 270 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 110:165afa46840b 271 } CAN_FilterRegister_TypeDef;
Kojto 110:165afa46840b 272
Kojto 110:165afa46840b 273 /**
Kojto 110:165afa46840b 274 * @brief Controller Area Network
Kojto 110:165afa46840b 275 */
Kojto 110:165afa46840b 276
Kojto 110:165afa46840b 277 typedef struct
Kojto 110:165afa46840b 278 {
Kojto 110:165afa46840b 279 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 110:165afa46840b 280 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 110:165afa46840b 281 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 110:165afa46840b 282 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 110:165afa46840b 283 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 110:165afa46840b 284 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 110:165afa46840b 285 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 110:165afa46840b 286 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 110:165afa46840b 287 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 110:165afa46840b 288 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 110:165afa46840b 289 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 110:165afa46840b 290 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 110:165afa46840b 291 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 110:165afa46840b 292 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 110:165afa46840b 293 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 110:165afa46840b 294 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 110:165afa46840b 295 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 110:165afa46840b 296 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 110:165afa46840b 297 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 110:165afa46840b 298 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 110:165afa46840b 299 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 110:165afa46840b 300 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 110:165afa46840b 301 } CAN_TypeDef;
Kojto 110:165afa46840b 302
Kojto 110:165afa46840b 303 /**
Kojto 110:165afa46840b 304 * @brief CRC calculation unit
Kojto 110:165afa46840b 305 */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 typedef struct
Kojto 110:165afa46840b 308 {
Kojto 110:165afa46840b 309 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 110:165afa46840b 310 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 110:165afa46840b 311 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 110:165afa46840b 312 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 110:165afa46840b 313 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 110:165afa46840b 314 } CRC_TypeDef;
Kojto 110:165afa46840b 315
Kojto 110:165afa46840b 316 /**
Kojto 110:165afa46840b 317 * @brief Digital to Analog Converter
Kojto 110:165afa46840b 318 */
Kojto 110:165afa46840b 319
Kojto 110:165afa46840b 320 typedef struct
Kojto 110:165afa46840b 321 {
Kojto 110:165afa46840b 322 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 110:165afa46840b 323 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 110:165afa46840b 324 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 110:165afa46840b 325 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 110:165afa46840b 326 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 110:165afa46840b 327 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 110:165afa46840b 328 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 110:165afa46840b 329 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 110:165afa46840b 330 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 110:165afa46840b 331 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 110:165afa46840b 332 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 110:165afa46840b 333 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 110:165afa46840b 334 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 110:165afa46840b 335 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 110:165afa46840b 336 } DAC_TypeDef;
Kojto 110:165afa46840b 337
Kojto 110:165afa46840b 338 /**
Kojto 110:165afa46840b 339 * @brief Debug MCU
Kojto 110:165afa46840b 340 */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 typedef struct
Kojto 110:165afa46840b 343 {
Kojto 110:165afa46840b 344 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 110:165afa46840b 345 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 110:165afa46840b 346 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 110:165afa46840b 347 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 110:165afa46840b 348 }DBGMCU_TypeDef;
Kojto 110:165afa46840b 349
Kojto 110:165afa46840b 350 /**
Kojto 110:165afa46840b 351 * @brief DCMI
Kojto 110:165afa46840b 352 */
Kojto 110:165afa46840b 353
Kojto 110:165afa46840b 354 typedef struct
Kojto 110:165afa46840b 355 {
Kojto 110:165afa46840b 356 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
Kojto 110:165afa46840b 357 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
Kojto 110:165afa46840b 358 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
Kojto 110:165afa46840b 359 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
Kojto 110:165afa46840b 360 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
Kojto 110:165afa46840b 361 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
Kojto 110:165afa46840b 362 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
Kojto 110:165afa46840b 363 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
Kojto 110:165afa46840b 364 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
Kojto 110:165afa46840b 365 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
Kojto 110:165afa46840b 366 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
Kojto 110:165afa46840b 367 } DCMI_TypeDef;
Kojto 110:165afa46840b 368
Kojto 110:165afa46840b 369 /**
Kojto 110:165afa46840b 370 * @brief DMA Controller
Kojto 110:165afa46840b 371 */
Kojto 110:165afa46840b 372
Kojto 110:165afa46840b 373 typedef struct
Kojto 110:165afa46840b 374 {
Kojto 110:165afa46840b 375 __IO uint32_t CR; /*!< DMA stream x configuration register */
Kojto 110:165afa46840b 376 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
Kojto 110:165afa46840b 377 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
Kojto 110:165afa46840b 378 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
Kojto 110:165afa46840b 379 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
Kojto 110:165afa46840b 380 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
Kojto 110:165afa46840b 381 } DMA_Stream_TypeDef;
Kojto 110:165afa46840b 382
Kojto 110:165afa46840b 383 typedef struct
Kojto 110:165afa46840b 384 {
Kojto 110:165afa46840b 385 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
Kojto 110:165afa46840b 386 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
Kojto 110:165afa46840b 387 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
Kojto 110:165afa46840b 388 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
Kojto 110:165afa46840b 389 } DMA_TypeDef;
Kojto 110:165afa46840b 390
Kojto 110:165afa46840b 391 /**
Kojto 110:165afa46840b 392 * @brief DMA2D Controller
Kojto 110:165afa46840b 393 */
Kojto 110:165afa46840b 394
Kojto 110:165afa46840b 395 typedef struct
Kojto 110:165afa46840b 396 {
Kojto 110:165afa46840b 397 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
Kojto 110:165afa46840b 398 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
Kojto 110:165afa46840b 399 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
Kojto 110:165afa46840b 400 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
Kojto 110:165afa46840b 401 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
Kojto 110:165afa46840b 402 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
Kojto 110:165afa46840b 403 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
Kojto 110:165afa46840b 404 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
Kojto 110:165afa46840b 405 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
Kojto 110:165afa46840b 406 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
Kojto 110:165afa46840b 407 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
Kojto 110:165afa46840b 408 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
Kojto 110:165afa46840b 409 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
Kojto 110:165afa46840b 410 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
Kojto 110:165afa46840b 411 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
Kojto 110:165afa46840b 412 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
Kojto 110:165afa46840b 413 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
Kojto 110:165afa46840b 414 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
Kojto 110:165afa46840b 415 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
Kojto 110:165afa46840b 416 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
Kojto 110:165afa46840b 417 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
Kojto 110:165afa46840b 418 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
Kojto 110:165afa46840b 419 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
Kojto 110:165afa46840b 420 } DMA2D_TypeDef;
Kojto 110:165afa46840b 421
Kojto 110:165afa46840b 422 /**
Kojto 110:165afa46840b 423 * @brief DSI Controller
Kojto 110:165afa46840b 424 */
Kojto 110:165afa46840b 425
Kojto 110:165afa46840b 426 typedef struct
Kojto 110:165afa46840b 427 {
Kojto 110:165afa46840b 428 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
Kojto 110:165afa46840b 429 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
Kojto 110:165afa46840b 430 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
Kojto 110:165afa46840b 431 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
Kojto 110:165afa46840b 432 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
Kojto 110:165afa46840b 433 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
Kojto 110:165afa46840b 434 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
Kojto 110:165afa46840b 435 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
Kojto 110:165afa46840b 436 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
Kojto 110:165afa46840b 437 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
Kojto 110:165afa46840b 438 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
Kojto 110:165afa46840b 439 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
Kojto 110:165afa46840b 440 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
Kojto 110:165afa46840b 441 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
Kojto 110:165afa46840b 442 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
Kojto 110:165afa46840b 443 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
Kojto 110:165afa46840b 444 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
Kojto 110:165afa46840b 445 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
Kojto 110:165afa46840b 446 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
Kojto 110:165afa46840b 447 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
Kojto 110:165afa46840b 448 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
Kojto 110:165afa46840b 449 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
Kojto 110:165afa46840b 450 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
Kojto 110:165afa46840b 451 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
Kojto 110:165afa46840b 452 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
Kojto 110:165afa46840b 453 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
Kojto 110:165afa46840b 454 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
Kojto 110:165afa46840b 455 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
Kojto 110:165afa46840b 456 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
Kojto 110:165afa46840b 457 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
Kojto 110:165afa46840b 458 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
Kojto 110:165afa46840b 459 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
Kojto 110:165afa46840b 460 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
Kojto 110:165afa46840b 461 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
Kojto 110:165afa46840b 462 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
Kojto 110:165afa46840b 463 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
Kojto 110:165afa46840b 464 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
Kojto 110:165afa46840b 465 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
Kojto 110:165afa46840b 466 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
Kojto 110:165afa46840b 467 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
Kojto 110:165afa46840b 468 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
Kojto 110:165afa46840b 469 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
Kojto 110:165afa46840b 470 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
Kojto 110:165afa46840b 471 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
Kojto 110:165afa46840b 472 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
Kojto 110:165afa46840b 473 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
Kojto 110:165afa46840b 474 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
Kojto 110:165afa46840b 475 uint32_t RESERVED5; /*!< Reserved, 0x114 */
Kojto 110:165afa46840b 476 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
Kojto 110:165afa46840b 477 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
Kojto 110:165afa46840b 478 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
Kojto 110:165afa46840b 479 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
Kojto 110:165afa46840b 480 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
Kojto 110:165afa46840b 481 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
Kojto 110:165afa46840b 482 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
Kojto 110:165afa46840b 483 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
Kojto 110:165afa46840b 484 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
Kojto 110:165afa46840b 485 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
Kojto 110:165afa46840b 486 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
Kojto 110:165afa46840b 487 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
Kojto 110:165afa46840b 488 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
Kojto 110:165afa46840b 489 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
Kojto 110:165afa46840b 490 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
Kojto 110:165afa46840b 491 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
Kojto 110:165afa46840b 492 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
Kojto 110:165afa46840b 493 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
Kojto 110:165afa46840b 494 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
Kojto 110:165afa46840b 495 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
Kojto 110:165afa46840b 496 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
Kojto 110:165afa46840b 497 uint32_t RESERVED9; /*!< Reserved, 0x414 */
Kojto 110:165afa46840b 498 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
Kojto 110:165afa46840b 499 uint32_t RESERVED10; /*!< Reserved, 0x42C */
Kojto 110:165afa46840b 500 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
Kojto 110:165afa46840b 501 } DSI_TypeDef;
Kojto 110:165afa46840b 502
Kojto 110:165afa46840b 503 /**
Kojto 110:165afa46840b 504 * @brief Ethernet MAC
Kojto 110:165afa46840b 505 */
Kojto 110:165afa46840b 506
Kojto 110:165afa46840b 507 typedef struct
Kojto 110:165afa46840b 508 {
Kojto 110:165afa46840b 509 __IO uint32_t MACCR;
Kojto 110:165afa46840b 510 __IO uint32_t MACFFR;
Kojto 110:165afa46840b 511 __IO uint32_t MACHTHR;
Kojto 110:165afa46840b 512 __IO uint32_t MACHTLR;
Kojto 110:165afa46840b 513 __IO uint32_t MACMIIAR;
Kojto 110:165afa46840b 514 __IO uint32_t MACMIIDR;
Kojto 110:165afa46840b 515 __IO uint32_t MACFCR;
Kojto 110:165afa46840b 516 __IO uint32_t MACVLANTR; /* 8 */
Kojto 110:165afa46840b 517 uint32_t RESERVED0[2];
Kojto 110:165afa46840b 518 __IO uint32_t MACRWUFFR; /* 11 */
Kojto 110:165afa46840b 519 __IO uint32_t MACPMTCSR;
Kojto 110:165afa46840b 520 uint32_t RESERVED1[2];
Kojto 110:165afa46840b 521 __IO uint32_t MACSR; /* 15 */
Kojto 110:165afa46840b 522 __IO uint32_t MACIMR;
Kojto 110:165afa46840b 523 __IO uint32_t MACA0HR;
Kojto 110:165afa46840b 524 __IO uint32_t MACA0LR;
Kojto 110:165afa46840b 525 __IO uint32_t MACA1HR;
Kojto 110:165afa46840b 526 __IO uint32_t MACA1LR;
Kojto 110:165afa46840b 527 __IO uint32_t MACA2HR;
Kojto 110:165afa46840b 528 __IO uint32_t MACA2LR;
Kojto 110:165afa46840b 529 __IO uint32_t MACA3HR;
Kojto 110:165afa46840b 530 __IO uint32_t MACA3LR; /* 24 */
Kojto 110:165afa46840b 531 uint32_t RESERVED2[40];
Kojto 110:165afa46840b 532 __IO uint32_t MMCCR; /* 65 */
Kojto 110:165afa46840b 533 __IO uint32_t MMCRIR;
Kojto 110:165afa46840b 534 __IO uint32_t MMCTIR;
Kojto 110:165afa46840b 535 __IO uint32_t MMCRIMR;
Kojto 110:165afa46840b 536 __IO uint32_t MMCTIMR; /* 69 */
Kojto 110:165afa46840b 537 uint32_t RESERVED3[14];
Kojto 110:165afa46840b 538 __IO uint32_t MMCTGFSCCR; /* 84 */
Kojto 110:165afa46840b 539 __IO uint32_t MMCTGFMSCCR;
Kojto 110:165afa46840b 540 uint32_t RESERVED4[5];
Kojto 110:165afa46840b 541 __IO uint32_t MMCTGFCR;
Kojto 110:165afa46840b 542 uint32_t RESERVED5[10];
Kojto 110:165afa46840b 543 __IO uint32_t MMCRFCECR;
Kojto 110:165afa46840b 544 __IO uint32_t MMCRFAECR;
Kojto 110:165afa46840b 545 uint32_t RESERVED6[10];
Kojto 110:165afa46840b 546 __IO uint32_t MMCRGUFCR;
Kojto 110:165afa46840b 547 uint32_t RESERVED7[334];
Kojto 110:165afa46840b 548 __IO uint32_t PTPTSCR;
Kojto 110:165afa46840b 549 __IO uint32_t PTPSSIR;
Kojto 110:165afa46840b 550 __IO uint32_t PTPTSHR;
Kojto 110:165afa46840b 551 __IO uint32_t PTPTSLR;
Kojto 110:165afa46840b 552 __IO uint32_t PTPTSHUR;
Kojto 110:165afa46840b 553 __IO uint32_t PTPTSLUR;
Kojto 110:165afa46840b 554 __IO uint32_t PTPTSAR;
Kojto 110:165afa46840b 555 __IO uint32_t PTPTTHR;
Kojto 110:165afa46840b 556 __IO uint32_t PTPTTLR;
Kojto 110:165afa46840b 557 __IO uint32_t RESERVED8;
Kojto 110:165afa46840b 558 __IO uint32_t PTPTSSR;
Kojto 110:165afa46840b 559 uint32_t RESERVED9[565];
Kojto 110:165afa46840b 560 __IO uint32_t DMABMR;
Kojto 110:165afa46840b 561 __IO uint32_t DMATPDR;
Kojto 110:165afa46840b 562 __IO uint32_t DMARPDR;
Kojto 110:165afa46840b 563 __IO uint32_t DMARDLAR;
Kojto 110:165afa46840b 564 __IO uint32_t DMATDLAR;
Kojto 110:165afa46840b 565 __IO uint32_t DMASR;
Kojto 110:165afa46840b 566 __IO uint32_t DMAOMR;
Kojto 110:165afa46840b 567 __IO uint32_t DMAIER;
Kojto 110:165afa46840b 568 __IO uint32_t DMAMFBOCR;
Kojto 110:165afa46840b 569 __IO uint32_t DMARSWTR;
Kojto 110:165afa46840b 570 uint32_t RESERVED10[8];
Kojto 110:165afa46840b 571 __IO uint32_t DMACHTDR;
Kojto 110:165afa46840b 572 __IO uint32_t DMACHRDR;
Kojto 110:165afa46840b 573 __IO uint32_t DMACHTBAR;
Kojto 110:165afa46840b 574 __IO uint32_t DMACHRBAR;
Kojto 110:165afa46840b 575 } ETH_TypeDef;
Kojto 110:165afa46840b 576
Kojto 110:165afa46840b 577 /**
Kojto 110:165afa46840b 578 * @brief External Interrupt/Event Controller
Kojto 110:165afa46840b 579 */
Kojto 110:165afa46840b 580
Kojto 110:165afa46840b 581 typedef struct
Kojto 110:165afa46840b 582 {
Kojto 110:165afa46840b 583 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 110:165afa46840b 584 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
Kojto 110:165afa46840b 585 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
Kojto 110:165afa46840b 586 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 110:165afa46840b 587 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 110:165afa46840b 588 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
Kojto 110:165afa46840b 589 } EXTI_TypeDef;
Kojto 110:165afa46840b 590
Kojto 110:165afa46840b 591 /**
Kojto 110:165afa46840b 592 * @brief FLASH Registers
Kojto 110:165afa46840b 593 */
Kojto 110:165afa46840b 594
Kojto 110:165afa46840b 595 typedef struct
Kojto 110:165afa46840b 596 {
Kojto 110:165afa46840b 597 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 110:165afa46840b 598 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
Kojto 110:165afa46840b 599 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
Kojto 110:165afa46840b 600 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
Kojto 110:165afa46840b 601 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
Kojto 110:165afa46840b 602 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
Kojto 110:165afa46840b 603 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
Kojto 110:165afa46840b 604 } FLASH_TypeDef;
Kojto 110:165afa46840b 605
Kojto 110:165afa46840b 606 /**
Kojto 110:165afa46840b 607 * @brief Flexible Memory Controller
Kojto 110:165afa46840b 608 */
Kojto 110:165afa46840b 609
Kojto 110:165afa46840b 610 typedef struct
Kojto 110:165afa46840b 611 {
Kojto 110:165afa46840b 612 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
Kojto 110:165afa46840b 613 } FMC_Bank1_TypeDef;
Kojto 110:165afa46840b 614
Kojto 110:165afa46840b 615 /**
Kojto 110:165afa46840b 616 * @brief Flexible Memory Controller Bank1E
Kojto 110:165afa46840b 617 */
Kojto 110:165afa46840b 618
Kojto 110:165afa46840b 619 typedef struct
Kojto 110:165afa46840b 620 {
Kojto 110:165afa46840b 621 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
Kojto 110:165afa46840b 622 } FMC_Bank1E_TypeDef;
Kojto 110:165afa46840b 623
Kojto 110:165afa46840b 624 /**
Kojto 110:165afa46840b 625 * @brief Flexible Memory Controller Bank3
Kojto 110:165afa46840b 626 */
Kojto 110:165afa46840b 627
Kojto 110:165afa46840b 628 typedef struct
Kojto 110:165afa46840b 629 {
Kojto 110:165afa46840b 630 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
Kojto 110:165afa46840b 631 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
Kojto 110:165afa46840b 632 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
Kojto 110:165afa46840b 633 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
Kojto 110:165afa46840b 634 uint32_t RESERVED; /*!< Reserved, 0x90 */
Kojto 110:165afa46840b 635 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
Kojto 110:165afa46840b 636 } FMC_Bank3_TypeDef;
Kojto 110:165afa46840b 637
Kojto 110:165afa46840b 638 /**
Kojto 110:165afa46840b 639 * @brief Flexible Memory Controller Bank5_6
Kojto 110:165afa46840b 640 */
Kojto 110:165afa46840b 641
Kojto 110:165afa46840b 642 typedef struct
Kojto 110:165afa46840b 643 {
Kojto 110:165afa46840b 644 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
Kojto 110:165afa46840b 645 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
Kojto 110:165afa46840b 646 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
Kojto 110:165afa46840b 647 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
Kojto 110:165afa46840b 648 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
Kojto 110:165afa46840b 649 } FMC_Bank5_6_TypeDef;
Kojto 110:165afa46840b 650
Kojto 110:165afa46840b 651 /**
Kojto 110:165afa46840b 652 * @brief General Purpose I/O
Kojto 110:165afa46840b 653 */
Kojto 110:165afa46840b 654
Kojto 110:165afa46840b 655 typedef struct
Kojto 110:165afa46840b 656 {
Kojto 110:165afa46840b 657 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 110:165afa46840b 658 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 110:165afa46840b 659 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 110:165afa46840b 660 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 110:165afa46840b 661 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 110:165afa46840b 662 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 110:165afa46840b 663 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
Kojto 110:165afa46840b 664 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 110:165afa46840b 665 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 110:165afa46840b 666 } GPIO_TypeDef;
Kojto 110:165afa46840b 667
Kojto 110:165afa46840b 668 /**
Kojto 110:165afa46840b 669 * @brief System configuration controller
Kojto 110:165afa46840b 670 */
Kojto 110:165afa46840b 671
Kojto 110:165afa46840b 672 typedef struct
Kojto 110:165afa46840b 673 {
Kojto 110:165afa46840b 674 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 110:165afa46840b 675 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
Kojto 110:165afa46840b 676 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 110:165afa46840b 677 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
Kojto 110:165afa46840b 678 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
Kojto 110:165afa46840b 679 } SYSCFG_TypeDef;
Kojto 110:165afa46840b 680
Kojto 110:165afa46840b 681 /**
Kojto 110:165afa46840b 682 * @brief Inter-integrated Circuit Interface
Kojto 110:165afa46840b 683 */
Kojto 110:165afa46840b 684
Kojto 110:165afa46840b 685 typedef struct
Kojto 110:165afa46840b 686 {
Kojto 110:165afa46840b 687 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 110:165afa46840b 688 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 110:165afa46840b 689 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
Kojto 110:165afa46840b 690 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
Kojto 110:165afa46840b 691 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
Kojto 110:165afa46840b 692 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
Kojto 110:165afa46840b 693 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
Kojto 110:165afa46840b 694 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
Kojto 110:165afa46840b 695 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
Kojto 110:165afa46840b 696 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
Kojto 110:165afa46840b 697 } I2C_TypeDef;
Kojto 110:165afa46840b 698
Kojto 110:165afa46840b 699 /**
Kojto 110:165afa46840b 700 * @brief Independent WATCHDOG
Kojto 110:165afa46840b 701 */
Kojto 110:165afa46840b 702
Kojto 110:165afa46840b 703 typedef struct
Kojto 110:165afa46840b 704 {
Kojto 110:165afa46840b 705 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 110:165afa46840b 706 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 110:165afa46840b 707 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 110:165afa46840b 708 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 110:165afa46840b 709 } IWDG_TypeDef;
Kojto 110:165afa46840b 710
Kojto 110:165afa46840b 711 /**
Kojto 110:165afa46840b 712 * @brief LCD-TFT Display Controller
Kojto 110:165afa46840b 713 */
Kojto 110:165afa46840b 714
Kojto 110:165afa46840b 715 typedef struct
Kojto 110:165afa46840b 716 {
Kojto 110:165afa46840b 717 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
Kojto 110:165afa46840b 718 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
Kojto 110:165afa46840b 719 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
Kojto 110:165afa46840b 720 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
Kojto 110:165afa46840b 721 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
Kojto 110:165afa46840b 722 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
Kojto 110:165afa46840b 723 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
Kojto 110:165afa46840b 724 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
Kojto 110:165afa46840b 725 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
Kojto 110:165afa46840b 726 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
Kojto 110:165afa46840b 727 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
Kojto 110:165afa46840b 728 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
Kojto 110:165afa46840b 729 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
Kojto 110:165afa46840b 730 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
Kojto 110:165afa46840b 731 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
Kojto 110:165afa46840b 732 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
Kojto 110:165afa46840b 733 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
Kojto 110:165afa46840b 734 } LTDC_TypeDef;
Kojto 110:165afa46840b 735
Kojto 110:165afa46840b 736 /**
Kojto 110:165afa46840b 737 * @brief LCD-TFT Display layer x Controller
Kojto 110:165afa46840b 738 */
Kojto 110:165afa46840b 739
Kojto 110:165afa46840b 740 typedef struct
Kojto 110:165afa46840b 741 {
Kojto 110:165afa46840b 742 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
Kojto 110:165afa46840b 743 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
Kojto 110:165afa46840b 744 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
Kojto 110:165afa46840b 745 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
Kojto 110:165afa46840b 746 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
Kojto 110:165afa46840b 747 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
Kojto 110:165afa46840b 748 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
Kojto 110:165afa46840b 749 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
Kojto 110:165afa46840b 750 uint32_t RESERVED0[2]; /*!< Reserved */
Kojto 110:165afa46840b 751 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
Kojto 110:165afa46840b 752 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
Kojto 110:165afa46840b 753 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
Kojto 110:165afa46840b 754 uint32_t RESERVED1[3]; /*!< Reserved */
Kojto 110:165afa46840b 755 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
Kojto 110:165afa46840b 756
Kojto 110:165afa46840b 757 } LTDC_Layer_TypeDef;
Kojto 110:165afa46840b 758
Kojto 110:165afa46840b 759 /**
Kojto 110:165afa46840b 760 * @brief Power Control
Kojto 110:165afa46840b 761 */
Kojto 110:165afa46840b 762
Kojto 110:165afa46840b 763 typedef struct
Kojto 110:165afa46840b 764 {
Kojto 110:165afa46840b 765 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 110:165afa46840b 766 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 110:165afa46840b 767 } PWR_TypeDef;
Kojto 110:165afa46840b 768
Kojto 110:165afa46840b 769 /**
Kojto 110:165afa46840b 770 * @brief Reset and Clock Control
Kojto 110:165afa46840b 771 */
Kojto 110:165afa46840b 772
Kojto 110:165afa46840b 773 typedef struct
Kojto 110:165afa46840b 774 {
Kojto 110:165afa46840b 775 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 110:165afa46840b 776 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
Kojto 110:165afa46840b 777 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
Kojto 110:165afa46840b 778 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
Kojto 110:165afa46840b 779 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
Kojto 110:165afa46840b 780 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
Kojto 110:165afa46840b 781 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
Kojto 110:165afa46840b 782 uint32_t RESERVED0; /*!< Reserved, 0x1C */
Kojto 110:165afa46840b 783 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
Kojto 110:165afa46840b 784 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
Kojto 110:165afa46840b 785 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
Kojto 110:165afa46840b 786 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
Kojto 110:165afa46840b 787 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
Kojto 110:165afa46840b 788 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
Kojto 110:165afa46840b 789 uint32_t RESERVED2; /*!< Reserved, 0x3C */
Kojto 110:165afa46840b 790 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
Kojto 110:165afa46840b 791 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
Kojto 110:165afa46840b 792 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
Kojto 110:165afa46840b 793 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
Kojto 110:165afa46840b 794 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
Kojto 110:165afa46840b 795 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
Kojto 110:165afa46840b 796 uint32_t RESERVED4; /*!< Reserved, 0x5C */
Kojto 110:165afa46840b 797 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
Kojto 110:165afa46840b 798 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
Kojto 110:165afa46840b 799 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
Kojto 110:165afa46840b 800 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
Kojto 110:165afa46840b 801 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
Kojto 110:165afa46840b 802 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
Kojto 110:165afa46840b 803 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
Kojto 110:165afa46840b 804 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
Kojto 110:165afa46840b 805 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
Kojto 110:165afa46840b 806 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
Kojto 110:165afa46840b 807
Kojto 110:165afa46840b 808 } RCC_TypeDef;
Kojto 110:165afa46840b 809
Kojto 110:165afa46840b 810 /**
Kojto 110:165afa46840b 811 * @brief Real-Time Clock
Kojto 110:165afa46840b 812 */
Kojto 110:165afa46840b 813
Kojto 110:165afa46840b 814 typedef struct
Kojto 110:165afa46840b 815 {
Kojto 110:165afa46840b 816 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 110:165afa46840b 817 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 110:165afa46840b 818 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 110:165afa46840b 819 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 110:165afa46840b 820 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 110:165afa46840b 821 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 110:165afa46840b 822 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
Kojto 110:165afa46840b 823 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 110:165afa46840b 824 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 110:165afa46840b 825 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 110:165afa46840b 826 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 110:165afa46840b 827 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 110:165afa46840b 828 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 110:165afa46840b 829 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 110:165afa46840b 830 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 110:165afa46840b 831 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 110:165afa46840b 832 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 110:165afa46840b 833 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 110:165afa46840b 834 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 110:165afa46840b 835 uint32_t RESERVED7; /*!< Reserved, 0x4C */
Kojto 110:165afa46840b 836 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
Kojto 110:165afa46840b 837 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 110:165afa46840b 838 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 110:165afa46840b 839 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 110:165afa46840b 840 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 110:165afa46840b 841 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 110:165afa46840b 842 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 110:165afa46840b 843 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 110:165afa46840b 844 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 110:165afa46840b 845 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 110:165afa46840b 846 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 110:165afa46840b 847 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 110:165afa46840b 848 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 110:165afa46840b 849 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 110:165afa46840b 850 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 110:165afa46840b 851 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 110:165afa46840b 852 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 110:165afa46840b 853 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 110:165afa46840b 854 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 110:165afa46840b 855 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 110:165afa46840b 856 } RTC_TypeDef;
Kojto 110:165afa46840b 857
Kojto 110:165afa46840b 858 /**
Kojto 110:165afa46840b 859 * @brief Serial Audio Interface
Kojto 110:165afa46840b 860 */
Kojto 110:165afa46840b 861
Kojto 110:165afa46840b 862 typedef struct
Kojto 110:165afa46840b 863 {
Kojto 110:165afa46840b 864 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
Kojto 110:165afa46840b 865 } SAI_TypeDef;
Kojto 110:165afa46840b 866
Kojto 110:165afa46840b 867 typedef struct
Kojto 110:165afa46840b 868 {
Kojto 110:165afa46840b 869 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
Kojto 110:165afa46840b 870 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
Kojto 110:165afa46840b 871 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
Kojto 110:165afa46840b 872 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
Kojto 110:165afa46840b 873 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
Kojto 110:165afa46840b 874 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
Kojto 110:165afa46840b 875 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
Kojto 110:165afa46840b 876 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
Kojto 110:165afa46840b 877 } SAI_Block_TypeDef;
Kojto 110:165afa46840b 878
Kojto 110:165afa46840b 879 /**
Kojto 110:165afa46840b 880 * @brief SD host Interface
Kojto 110:165afa46840b 881 */
Kojto 110:165afa46840b 882
Kojto 110:165afa46840b 883 typedef struct
Kojto 110:165afa46840b 884 {
Kojto 110:165afa46840b 885 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
Kojto 110:165afa46840b 886 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
Kojto 110:165afa46840b 887 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
Kojto 110:165afa46840b 888 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
Kojto 110:165afa46840b 889 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
Kojto 110:165afa46840b 890 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
Kojto 110:165afa46840b 891 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
Kojto 110:165afa46840b 892 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
Kojto 110:165afa46840b 893 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
Kojto 110:165afa46840b 894 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
Kojto 110:165afa46840b 895 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
Kojto 110:165afa46840b 896 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
Kojto 110:165afa46840b 897 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
Kojto 110:165afa46840b 898 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
Kojto 110:165afa46840b 899 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
Kojto 110:165afa46840b 900 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
Kojto 110:165afa46840b 901 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
Kojto 110:165afa46840b 902 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
Kojto 110:165afa46840b 903 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
Kojto 110:165afa46840b 904 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
Kojto 110:165afa46840b 905 } SDIO_TypeDef;
Kojto 110:165afa46840b 906
Kojto 110:165afa46840b 907 /**
Kojto 110:165afa46840b 908 * @brief Serial Peripheral Interface
Kojto 110:165afa46840b 909 */
Kojto 110:165afa46840b 910
Kojto 110:165afa46840b 911 typedef struct
Kojto 110:165afa46840b 912 {
Kojto 110:165afa46840b 913 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 110:165afa46840b 914 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
Kojto 110:165afa46840b 915 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
Kojto 110:165afa46840b 916 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 110:165afa46840b 917 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 110:165afa46840b 918 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 110:165afa46840b 919 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 110:165afa46840b 920 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 110:165afa46840b 921 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 110:165afa46840b 922 } SPI_TypeDef;
Kojto 110:165afa46840b 923
Kojto 110:165afa46840b 924 /**
Kojto 110:165afa46840b 925 * @brief QUAD Serial Peripheral Interface
Kojto 110:165afa46840b 926 */
Kojto 110:165afa46840b 927
Kojto 110:165afa46840b 928 typedef struct
Kojto 110:165afa46840b 929 {
Kojto 110:165afa46840b 930 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
Kojto 110:165afa46840b 931 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
Kojto 110:165afa46840b 932 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
Kojto 110:165afa46840b 933 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
Kojto 110:165afa46840b 934 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
Kojto 110:165afa46840b 935 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
Kojto 110:165afa46840b 936 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
Kojto 110:165afa46840b 937 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
Kojto 110:165afa46840b 938 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
Kojto 110:165afa46840b 939 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
Kojto 110:165afa46840b 940 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
Kojto 110:165afa46840b 941 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
Kojto 110:165afa46840b 942 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
Kojto 110:165afa46840b 943 } QUADSPI_TypeDef;
Kojto 110:165afa46840b 944
Kojto 110:165afa46840b 945 /**
Kojto 110:165afa46840b 946 * @brief TIM
Kojto 110:165afa46840b 947 */
Kojto 110:165afa46840b 948
Kojto 110:165afa46840b 949 typedef struct
Kojto 110:165afa46840b 950 {
Kojto 110:165afa46840b 951 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 110:165afa46840b 952 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 110:165afa46840b 953 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 110:165afa46840b 954 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 110:165afa46840b 955 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 110:165afa46840b 956 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 110:165afa46840b 957 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 110:165afa46840b 958 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 110:165afa46840b 959 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 110:165afa46840b 960 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 110:165afa46840b 961 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 110:165afa46840b 962 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 110:165afa46840b 963 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 110:165afa46840b 964 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 110:165afa46840b 965 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 110:165afa46840b 966 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 110:165afa46840b 967 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 110:165afa46840b 968 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 110:165afa46840b 969 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 110:165afa46840b 970 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 110:165afa46840b 971 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 110:165afa46840b 972 } TIM_TypeDef;
Kojto 110:165afa46840b 973
Kojto 110:165afa46840b 974 /**
Kojto 110:165afa46840b 975 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 110:165afa46840b 976 */
Kojto 110:165afa46840b 977
Kojto 110:165afa46840b 978 typedef struct
Kojto 110:165afa46840b 979 {
Kojto 110:165afa46840b 980 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
Kojto 110:165afa46840b 981 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
Kojto 110:165afa46840b 982 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
Kojto 110:165afa46840b 983 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
Kojto 110:165afa46840b 984 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
Kojto 110:165afa46840b 985 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
Kojto 110:165afa46840b 986 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
Kojto 110:165afa46840b 987 } USART_TypeDef;
Kojto 110:165afa46840b 988
Kojto 110:165afa46840b 989 /**
Kojto 110:165afa46840b 990 * @brief Window WATCHDOG
Kojto 110:165afa46840b 991 */
Kojto 110:165afa46840b 992
Kojto 110:165afa46840b 993 typedef struct
Kojto 110:165afa46840b 994 {
Kojto 110:165afa46840b 995 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 110:165afa46840b 996 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 110:165afa46840b 997 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 110:165afa46840b 998 } WWDG_TypeDef;
Kojto 110:165afa46840b 999
Kojto 110:165afa46840b 1000 /**
Kojto 110:165afa46840b 1001 * @brief RNG
Kojto 110:165afa46840b 1002 */
Kojto 110:165afa46840b 1003
Kojto 110:165afa46840b 1004 typedef struct
Kojto 110:165afa46840b 1005 {
Kojto 110:165afa46840b 1006 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
Kojto 110:165afa46840b 1007 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
Kojto 110:165afa46840b 1008 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
Kojto 110:165afa46840b 1009 } RNG_TypeDef;
Kojto 110:165afa46840b 1010
Kojto 110:165afa46840b 1011
Kojto 110:165afa46840b 1012 /**
Kojto 110:165afa46840b 1013 * @brief USB_OTG_Core_Registers
Kojto 110:165afa46840b 1014 */
Kojto 110:165afa46840b 1015 typedef struct
Kojto 110:165afa46840b 1016 {
Kojto 110:165afa46840b 1017 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
Kojto 110:165afa46840b 1018 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
Kojto 110:165afa46840b 1019 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
Kojto 110:165afa46840b 1020 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
Kojto 110:165afa46840b 1021 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
Kojto 110:165afa46840b 1022 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
Kojto 110:165afa46840b 1023 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
Kojto 110:165afa46840b 1024 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
Kojto 110:165afa46840b 1025 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
Kojto 110:165afa46840b 1026 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
Kojto 110:165afa46840b 1027 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
Kojto 110:165afa46840b 1028 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
Kojto 110:165afa46840b 1029 uint32_t Reserved30[2]; /*!< Reserved 030h */
Kojto 110:165afa46840b 1030 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
Kojto 110:165afa46840b 1031 __IO uint32_t CID; /*!< User ID Register 03Ch */
Kojto 110:165afa46840b 1032 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
Kojto 110:165afa46840b 1033 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
Kojto 110:165afa46840b 1034 uint32_t Reserved6; /*!< Reserved 050h */
Kojto 110:165afa46840b 1035 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
Kojto 110:165afa46840b 1036 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
Kojto 110:165afa46840b 1037 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
Kojto 110:165afa46840b 1038 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
Kojto 110:165afa46840b 1039 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
Kojto 110:165afa46840b 1040 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
Kojto 110:165afa46840b 1041 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
Kojto 110:165afa46840b 1042 } USB_OTG_GlobalTypeDef;
Kojto 110:165afa46840b 1043
Kojto 110:165afa46840b 1044 /**
Kojto 110:165afa46840b 1045 * @brief USB_OTG_device_Registers
Kojto 110:165afa46840b 1046 */
Kojto 110:165afa46840b 1047 typedef struct
Kojto 110:165afa46840b 1048 {
Kojto 110:165afa46840b 1049 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
Kojto 110:165afa46840b 1050 __IO uint32_t DCTL; /*!< dev Control Register 804h */
Kojto 110:165afa46840b 1051 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
Kojto 110:165afa46840b 1052 uint32_t Reserved0C; /*!< Reserved 80Ch */
Kojto 110:165afa46840b 1053 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
Kojto 110:165afa46840b 1054 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
Kojto 110:165afa46840b 1055 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
Kojto 110:165afa46840b 1056 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
Kojto 110:165afa46840b 1057 uint32_t Reserved20; /*!< Reserved 820h */
Kojto 110:165afa46840b 1058 uint32_t Reserved9; /*!< Reserved 824h */
Kojto 110:165afa46840b 1059 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
Kojto 110:165afa46840b 1060 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
Kojto 110:165afa46840b 1061 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
Kojto 110:165afa46840b 1062 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
Kojto 110:165afa46840b 1063 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
Kojto 110:165afa46840b 1064 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
Kojto 110:165afa46840b 1065 uint32_t Reserved40; /*!< dedicated EP mask 840h */
Kojto 110:165afa46840b 1066 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
Kojto 110:165afa46840b 1067 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
Kojto 110:165afa46840b 1068 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
Kojto 110:165afa46840b 1069 } USB_OTG_DeviceTypeDef;
Kojto 110:165afa46840b 1070
Kojto 110:165afa46840b 1071 /**
Kojto 110:165afa46840b 1072 * @brief USB_OTG_IN_Endpoint-Specific_Register
Kojto 110:165afa46840b 1073 */
Kojto 110:165afa46840b 1074 typedef struct
Kojto 110:165afa46840b 1075 {
Kojto 110:165afa46840b 1076 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
Kojto 110:165afa46840b 1077 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
Kojto 110:165afa46840b 1078 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
Kojto 110:165afa46840b 1079 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
Kojto 110:165afa46840b 1080 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
Kojto 110:165afa46840b 1081 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
Kojto 110:165afa46840b 1082 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
Kojto 110:165afa46840b 1083 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto 110:165afa46840b 1084 } USB_OTG_INEndpointTypeDef;
Kojto 110:165afa46840b 1085
Kojto 110:165afa46840b 1086 /**
Kojto 110:165afa46840b 1087 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
Kojto 110:165afa46840b 1088 */
Kojto 110:165afa46840b 1089 typedef struct
Kojto 110:165afa46840b 1090 {
Kojto 110:165afa46840b 1091 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
Kojto 110:165afa46840b 1092 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
Kojto 110:165afa46840b 1093 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
Kojto 110:165afa46840b 1094 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
Kojto 110:165afa46840b 1095 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
Kojto 110:165afa46840b 1096 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
Kojto 110:165afa46840b 1097 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
Kojto 110:165afa46840b 1098 } USB_OTG_OUTEndpointTypeDef;
Kojto 110:165afa46840b 1099
Kojto 110:165afa46840b 1100 /**
Kojto 110:165afa46840b 1101 * @brief USB_OTG_Host_Mode_Register_Structures
Kojto 110:165afa46840b 1102 */
Kojto 110:165afa46840b 1103 typedef struct
Kojto 110:165afa46840b 1104 {
Kojto 110:165afa46840b 1105 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
Kojto 110:165afa46840b 1106 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
Kojto 110:165afa46840b 1107 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
Kojto 110:165afa46840b 1108 uint32_t Reserved40C; /*!< Reserved 40Ch */
Kojto 110:165afa46840b 1109 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
Kojto 110:165afa46840b 1110 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
Kojto 110:165afa46840b 1111 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
Kojto 110:165afa46840b 1112 } USB_OTG_HostTypeDef;
Kojto 110:165afa46840b 1113
Kojto 110:165afa46840b 1114 /**
Kojto 110:165afa46840b 1115 * @brief USB_OTG_Host_Channel_Specific_Registers
Kojto 110:165afa46840b 1116 */
Kojto 110:165afa46840b 1117 typedef struct
Kojto 110:165afa46840b 1118 {
Kojto 110:165afa46840b 1119 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
Kojto 110:165afa46840b 1120 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
Kojto 110:165afa46840b 1121 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
Kojto 110:165afa46840b 1122 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
Kojto 110:165afa46840b 1123 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
Kojto 110:165afa46840b 1124 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
Kojto 110:165afa46840b 1125 uint32_t Reserved[2]; /*!< Reserved */
Kojto 110:165afa46840b 1126 } USB_OTG_HostChannelTypeDef;
Kojto 110:165afa46840b 1127
Kojto 110:165afa46840b 1128 /**
Kojto 110:165afa46840b 1129 * @}
Kojto 110:165afa46840b 1130 */
Kojto 110:165afa46840b 1131
Kojto 110:165afa46840b 1132 /** @addtogroup Peripheral_memory_map
Kojto 110:165afa46840b 1133 * @{
Kojto 110:165afa46840b 1134 */
Kojto 110:165afa46840b 1135 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
Kojto 110:165afa46840b 1136 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
Kojto 110:165afa46840b 1137 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(160 KB) base address in the alias region */
Kojto 110:165afa46840b 1138 #define SRAM2_BASE ((uint32_t)0x20028000) /*!< SRAM2(32 KB) base address in the alias region */
Kojto 110:165afa46840b 1139 #define SRAM3_BASE ((uint32_t)0x20030000) /*!< SRAM3(128 KB) base address in the alias region */
Kojto 110:165afa46840b 1140 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 110:165afa46840b 1141 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
Kojto 110:165afa46840b 1142 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
Kojto 110:165afa46840b 1143 #define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
Kojto 110:165afa46840b 1144 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
Kojto 110:165afa46840b 1145 #define SRAM2_BB_BASE ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */
Kojto 110:165afa46840b 1146 #define SRAM3_BB_BASE ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */
Kojto 110:165afa46840b 1147 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
Kojto 110:165afa46840b 1148 #define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
Kojto 110:165afa46840b 1149 #define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
Kojto 110:165afa46840b 1150 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
Kojto 110:165afa46840b 1151
Kojto 110:165afa46840b 1152 /* Legacy defines */
Kojto 110:165afa46840b 1153 #define SRAM_BASE SRAM1_BASE
Kojto 110:165afa46840b 1154 #define SRAM_BB_BASE SRAM1_BB_BASE
Kojto 110:165afa46840b 1155
Kojto 110:165afa46840b 1156
Kojto 110:165afa46840b 1157 /*!< Peripheral memory map */
Kojto 110:165afa46840b 1158 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 110:165afa46840b 1159 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
Kojto 110:165afa46840b 1160 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 110:165afa46840b 1161 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
Kojto 110:165afa46840b 1162
Kojto 110:165afa46840b 1163 /*!< APB1 peripherals */
Kojto 110:165afa46840b 1164 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
Kojto 110:165afa46840b 1165 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
Kojto 110:165afa46840b 1166 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
Kojto 110:165afa46840b 1167 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
Kojto 110:165afa46840b 1168 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
Kojto 110:165afa46840b 1169 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
Kojto 110:165afa46840b 1170 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
Kojto 110:165afa46840b 1171 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
Kojto 110:165afa46840b 1172 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
Kojto 110:165afa46840b 1173 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
Kojto 110:165afa46840b 1174 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
Kojto 110:165afa46840b 1175 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
Kojto 110:165afa46840b 1176 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
Kojto 110:165afa46840b 1177 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
Kojto 110:165afa46840b 1178 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
Kojto 110:165afa46840b 1179 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
Kojto 110:165afa46840b 1180 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
Kojto 110:165afa46840b 1181 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
Kojto 110:165afa46840b 1182 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
Kojto 110:165afa46840b 1183 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
Kojto 110:165afa46840b 1184 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
Kojto 110:165afa46840b 1185 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
Kojto 110:165afa46840b 1186 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
Kojto 110:165afa46840b 1187 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
Kojto 110:165afa46840b 1188 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
Kojto 110:165afa46840b 1189 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
Kojto 110:165afa46840b 1190 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
Kojto 110:165afa46840b 1191 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
Kojto 110:165afa46840b 1192 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
Kojto 110:165afa46840b 1193
Kojto 110:165afa46840b 1194 /*!< APB2 peripherals */
Kojto 110:165afa46840b 1195 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
Kojto 110:165afa46840b 1196 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
Kojto 110:165afa46840b 1197 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
Kojto 110:165afa46840b 1198 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
Kojto 110:165afa46840b 1199 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
Kojto 110:165afa46840b 1200 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
Kojto 110:165afa46840b 1201 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
Kojto 110:165afa46840b 1202 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
Kojto 110:165afa46840b 1203 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
Kojto 110:165afa46840b 1204 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
Kojto 110:165afa46840b 1205 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
Kojto 110:165afa46840b 1206 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
Kojto 110:165afa46840b 1207 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
Kojto 110:165afa46840b 1208 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
Kojto 110:165afa46840b 1209 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
Kojto 110:165afa46840b 1210 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
Kojto 110:165afa46840b 1211 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
Kojto 110:165afa46840b 1212 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
Kojto 110:165afa46840b 1213 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
Kojto 110:165afa46840b 1214 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
Kojto 110:165afa46840b 1215 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
Kojto 110:165afa46840b 1216 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
Kojto 110:165afa46840b 1217 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
Kojto 110:165afa46840b 1218 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
Kojto 110:165afa46840b 1219 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00)
Kojto 110:165afa46840b 1220
Kojto 110:165afa46840b 1221 /*!< AHB1 peripherals */
Kojto 110:165afa46840b 1222 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
Kojto 110:165afa46840b 1223 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
Kojto 110:165afa46840b 1224 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
Kojto 110:165afa46840b 1225 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
Kojto 110:165afa46840b 1226 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
Kojto 110:165afa46840b 1227 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
Kojto 110:165afa46840b 1228 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
Kojto 110:165afa46840b 1229 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
Kojto 110:165afa46840b 1230 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
Kojto 110:165afa46840b 1231 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
Kojto 110:165afa46840b 1232 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
Kojto 110:165afa46840b 1233 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
Kojto 110:165afa46840b 1234 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
Kojto 110:165afa46840b 1235 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
Kojto 110:165afa46840b 1236 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
Kojto 110:165afa46840b 1237 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
Kojto 110:165afa46840b 1238 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
Kojto 110:165afa46840b 1239 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
Kojto 110:165afa46840b 1240 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
Kojto 110:165afa46840b 1241 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
Kojto 110:165afa46840b 1242 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
Kojto 110:165afa46840b 1243 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
Kojto 110:165afa46840b 1244 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
Kojto 110:165afa46840b 1245 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
Kojto 110:165afa46840b 1246 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
Kojto 110:165afa46840b 1247 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
Kojto 110:165afa46840b 1248 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
Kojto 110:165afa46840b 1249 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
Kojto 110:165afa46840b 1250 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
Kojto 110:165afa46840b 1251 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
Kojto 110:165afa46840b 1252 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
Kojto 110:165afa46840b 1253 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
Kojto 110:165afa46840b 1254 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
Kojto 110:165afa46840b 1255 #define ETH_MAC_BASE (ETH_BASE)
Kojto 110:165afa46840b 1256 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
Kojto 110:165afa46840b 1257 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
Kojto 110:165afa46840b 1258 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
Kojto 110:165afa46840b 1259 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
Kojto 110:165afa46840b 1260
Kojto 110:165afa46840b 1261 /*!< AHB2 peripherals */
Kojto 110:165afa46840b 1262 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
Kojto 110:165afa46840b 1263 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
Kojto 110:165afa46840b 1264
Kojto 110:165afa46840b 1265 /*!< FMC Bankx registers base address */
Kojto 110:165afa46840b 1266 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
Kojto 110:165afa46840b 1267 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
Kojto 110:165afa46840b 1268 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
Kojto 110:165afa46840b 1269 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
Kojto 110:165afa46840b 1270
Kojto 110:165afa46840b 1271 /*!< Debug MCU registers base address */
Kojto 110:165afa46840b 1272 #define DBGMCU_BASE ((uint32_t )0xE0042000)
Kojto 110:165afa46840b 1273
Kojto 110:165afa46840b 1274 /*!< USB registers base address */
Kojto 110:165afa46840b 1275 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
Kojto 110:165afa46840b 1276 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
Kojto 110:165afa46840b 1277
Kojto 110:165afa46840b 1278 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
Kojto 110:165afa46840b 1279 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
Kojto 110:165afa46840b 1280 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
Kojto 110:165afa46840b 1281 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
Kojto 110:165afa46840b 1282 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
Kojto 110:165afa46840b 1283 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
Kojto 110:165afa46840b 1284 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
Kojto 110:165afa46840b 1285 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
Kojto 110:165afa46840b 1286 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
Kojto 110:165afa46840b 1287 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
Kojto 110:165afa46840b 1288 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
Kojto 110:165afa46840b 1289 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
Kojto 110:165afa46840b 1290
Kojto 110:165afa46840b 1291 /**
Kojto 110:165afa46840b 1292 * @}
Kojto 110:165afa46840b 1293 */
Kojto 110:165afa46840b 1294
Kojto 110:165afa46840b 1295 /** @addtogroup Peripheral_declaration
Kojto 110:165afa46840b 1296 * @{
Kojto 110:165afa46840b 1297 */
Kojto 110:165afa46840b 1298 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 110:165afa46840b 1299 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 110:165afa46840b 1300 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 110:165afa46840b 1301 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto 110:165afa46840b 1302 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 110:165afa46840b 1303 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 110:165afa46840b 1304 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
Kojto 110:165afa46840b 1305 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
Kojto 110:165afa46840b 1306 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 110:165afa46840b 1307 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 110:165afa46840b 1308 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 110:165afa46840b 1309 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 110:165afa46840b 1310 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
Kojto 110:165afa46840b 1311 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 110:165afa46840b 1312 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 110:165afa46840b 1313 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
Kojto 110:165afa46840b 1314 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 110:165afa46840b 1315 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 110:165afa46840b 1316 #define UART4 ((USART_TypeDef *) UART4_BASE)
Kojto 110:165afa46840b 1317 #define UART5 ((USART_TypeDef *) UART5_BASE)
Kojto 110:165afa46840b 1318 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 110:165afa46840b 1319 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 110:165afa46840b 1320 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto 110:165afa46840b 1321 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto 110:165afa46840b 1322 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
Kojto 110:165afa46840b 1323 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 110:165afa46840b 1324 #define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto 110:165afa46840b 1325 #define UART7 ((USART_TypeDef *) UART7_BASE)
Kojto 110:165afa46840b 1326 #define UART8 ((USART_TypeDef *) UART8_BASE)
Kojto 110:165afa46840b 1327 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 110:165afa46840b 1328 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
Kojto 110:165afa46840b 1329 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 110:165afa46840b 1330 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 110:165afa46840b 1331 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 110:165afa46840b 1332 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 110:165afa46840b 1333 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto 110:165afa46840b 1334 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
Kojto 110:165afa46840b 1335 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
Kojto 110:165afa46840b 1336 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 110:165afa46840b 1337 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto 110:165afa46840b 1338 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 110:165afa46840b 1339 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 110:165afa46840b 1340 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto 110:165afa46840b 1341 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto 110:165afa46840b 1342 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto 110:165afa46840b 1343 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
Kojto 110:165afa46840b 1344 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
Kojto 110:165afa46840b 1345 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
Kojto 110:165afa46840b 1346 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
Kojto 110:165afa46840b 1347 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
Kojto 110:165afa46840b 1348 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
Kojto 110:165afa46840b 1349 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
Kojto 110:165afa46840b 1350 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
Kojto 110:165afa46840b 1351 #define DSI ((DSI_TypeDef *)DSI_BASE)
Kojto 110:165afa46840b 1352
Kojto 110:165afa46840b 1353 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 110:165afa46840b 1354 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 110:165afa46840b 1355 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 110:165afa46840b 1356 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 110:165afa46840b 1357 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 110:165afa46840b 1358 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 110:165afa46840b 1359 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Kojto 110:165afa46840b 1360 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 110:165afa46840b 1361 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
Kojto 110:165afa46840b 1362 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
Kojto 110:165afa46840b 1363 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
Kojto 110:165afa46840b 1364 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 110:165afa46840b 1365 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 110:165afa46840b 1366 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 110:165afa46840b 1367 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 110:165afa46840b 1368 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto 110:165afa46840b 1369 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto 110:165afa46840b 1370 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto 110:165afa46840b 1371 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto 110:165afa46840b 1372 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto 110:165afa46840b 1373 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto 110:165afa46840b 1374 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto 110:165afa46840b 1375 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto 110:165afa46840b 1376 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 110:165afa46840b 1377 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto 110:165afa46840b 1378 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto 110:165afa46840b 1379 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto 110:165afa46840b 1380 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto 110:165afa46840b 1381 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto 110:165afa46840b 1382 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto 110:165afa46840b 1383 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto 110:165afa46840b 1384 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto 110:165afa46840b 1385 #define ETH ((ETH_TypeDef *) ETH_BASE)
Kojto 110:165afa46840b 1386 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
Kojto 110:165afa46840b 1387 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
Kojto 110:165afa46840b 1388 #define RNG ((RNG_TypeDef *) RNG_BASE)
Kojto 110:165afa46840b 1389 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
Kojto 110:165afa46840b 1390 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
Kojto 110:165afa46840b 1391 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
Kojto 110:165afa46840b 1392 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
Kojto 110:165afa46840b 1393 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
Kojto 110:165afa46840b 1394
Kojto 110:165afa46840b 1395 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 110:165afa46840b 1396
Kojto 110:165afa46840b 1397 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto 110:165afa46840b 1398 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
Kojto 110:165afa46840b 1399
Kojto 110:165afa46840b 1400 /**
Kojto 110:165afa46840b 1401 * @}
Kojto 110:165afa46840b 1402 */
Kojto 110:165afa46840b 1403
Kojto 110:165afa46840b 1404 /** @addtogroup Exported_constants
Kojto 110:165afa46840b 1405 * @{
Kojto 110:165afa46840b 1406 */
Kojto 110:165afa46840b 1407
Kojto 110:165afa46840b 1408 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 110:165afa46840b 1409 * @{
Kojto 110:165afa46840b 1410 */
Kojto 110:165afa46840b 1411
Kojto 110:165afa46840b 1412 /******************************************************************************/
Kojto 110:165afa46840b 1413 /* Peripheral Registers_Bits_Definition */
Kojto 110:165afa46840b 1414 /******************************************************************************/
Kojto 110:165afa46840b 1415
Kojto 110:165afa46840b 1416 /******************************************************************************/
Kojto 110:165afa46840b 1417 /* */
Kojto 110:165afa46840b 1418 /* Analog to Digital Converter */
Kojto 110:165afa46840b 1419 /* */
Kojto 110:165afa46840b 1420 /******************************************************************************/
Kojto 110:165afa46840b 1421 /******************** Bit definition for ADC_SR register ********************/
Kojto 110:165afa46840b 1422 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
Kojto 110:165afa46840b 1423 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
Kojto 110:165afa46840b 1424 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
Kojto 110:165afa46840b 1425 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
Kojto 110:165afa46840b 1426 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
Kojto 110:165afa46840b 1427 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
Kojto 110:165afa46840b 1428
Kojto 110:165afa46840b 1429 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 110:165afa46840b 1430 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 110:165afa46840b 1431 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 1432 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 1433 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 1434 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 1435 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 1436 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
Kojto 110:165afa46840b 1437 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
Kojto 110:165afa46840b 1438 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
Kojto 110:165afa46840b 1439 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
Kojto 110:165afa46840b 1440 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
Kojto 110:165afa46840b 1441 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
Kojto 110:165afa46840b 1442 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
Kojto 110:165afa46840b 1443 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
Kojto 110:165afa46840b 1444 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 110:165afa46840b 1445 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 110:165afa46840b 1446 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 110:165afa46840b 1447 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 110:165afa46840b 1448 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
Kojto 110:165afa46840b 1449 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
Kojto 110:165afa46840b 1450 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
Kojto 110:165afa46840b 1451 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 1452 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 1453 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
Kojto 110:165afa46840b 1454
Kojto 110:165afa46840b 1455 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 110:165afa46840b 1456 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
Kojto 110:165afa46840b 1457 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
Kojto 110:165afa46840b 1458 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
Kojto 110:165afa46840b 1459 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
Kojto 110:165afa46840b 1460 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
Kojto 110:165afa46840b 1461 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
Kojto 110:165afa46840b 1462 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
Kojto 110:165afa46840b 1463 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 1464 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 1465 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 1466 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 1467 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
Kojto 110:165afa46840b 1468 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 1469 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 1470 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
Kojto 110:165afa46840b 1471 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
Kojto 110:165afa46840b 1472 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 1473 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 1474 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 1475 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 1476 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
Kojto 110:165afa46840b 1477 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 110:165afa46840b 1478 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 110:165afa46840b 1479 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
Kojto 110:165afa46840b 1480
Kojto 110:165afa46840b 1481 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 110:165afa46840b 1482 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 110:165afa46840b 1483 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 1484 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 1485 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 1486 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 110:165afa46840b 1487 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 110:165afa46840b 1488 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 110:165afa46840b 1489 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 110:165afa46840b 1490 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 110:165afa46840b 1491 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 110:165afa46840b 1492 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 110:165afa46840b 1493 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 110:165afa46840b 1494 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 110:165afa46840b 1495 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 110:165afa46840b 1496 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 110:165afa46840b 1497 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 110:165afa46840b 1498 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 110:165afa46840b 1499 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 110:165afa46840b 1500 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 110:165afa46840b 1501 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 110:165afa46840b 1502 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 110:165afa46840b 1503 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 110:165afa46840b 1504 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 110:165afa46840b 1505 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 110:165afa46840b 1506 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 110:165afa46840b 1507 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 110:165afa46840b 1508 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 110:165afa46840b 1509 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 110:165afa46840b 1510 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 110:165afa46840b 1511 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 110:165afa46840b 1512 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 110:165afa46840b 1513 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 110:165afa46840b 1514 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
Kojto 110:165afa46840b 1515 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 1516 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 1517 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 1518
Kojto 110:165afa46840b 1519 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 110:165afa46840b 1520 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 110:165afa46840b 1521 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 1522 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 1523 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 1524 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 110:165afa46840b 1525 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 110:165afa46840b 1526 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 110:165afa46840b 1527 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 110:165afa46840b 1528 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 110:165afa46840b 1529 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 110:165afa46840b 1530 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 110:165afa46840b 1531 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 110:165afa46840b 1532 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 110:165afa46840b 1533 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 110:165afa46840b 1534 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 110:165afa46840b 1535 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 110:165afa46840b 1536 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 110:165afa46840b 1537 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 110:165afa46840b 1538 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 110:165afa46840b 1539 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 110:165afa46840b 1540 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 110:165afa46840b 1541 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 110:165afa46840b 1542 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 110:165afa46840b 1543 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 110:165afa46840b 1544 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 110:165afa46840b 1545 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 110:165afa46840b 1546 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 110:165afa46840b 1547 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 110:165afa46840b 1548 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 110:165afa46840b 1549 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 110:165afa46840b 1550 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 110:165afa46840b 1551 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 110:165afa46840b 1552 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 110:165afa46840b 1553 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 1554 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 1555 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 1556 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 110:165afa46840b 1557 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
Kojto 110:165afa46840b 1558 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
Kojto 110:165afa46840b 1559 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
Kojto 110:165afa46840b 1560
Kojto 110:165afa46840b 1561 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 110:165afa46840b 1562 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
Kojto 110:165afa46840b 1563
Kojto 110:165afa46840b 1564 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 110:165afa46840b 1565 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
Kojto 110:165afa46840b 1566
Kojto 110:165afa46840b 1567 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 110:165afa46840b 1568 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
Kojto 110:165afa46840b 1569
Kojto 110:165afa46840b 1570 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 110:165afa46840b 1571 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
Kojto 110:165afa46840b 1572
Kojto 110:165afa46840b 1573 /******************* Bit definition for ADC_HTR register ********************/
Kojto 110:165afa46840b 1574 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
Kojto 110:165afa46840b 1575
Kojto 110:165afa46840b 1576 /******************* Bit definition for ADC_LTR register ********************/
Kojto 110:165afa46840b 1577 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
Kojto 110:165afa46840b 1578
Kojto 110:165afa46840b 1579 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 110:165afa46840b 1580 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 110:165afa46840b 1581 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 1582 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 1583 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 1584 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 1585 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 1586 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 110:165afa46840b 1587 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 110:165afa46840b 1588 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 110:165afa46840b 1589 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 110:165afa46840b 1590 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 110:165afa46840b 1591 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 110:165afa46840b 1592 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 110:165afa46840b 1593 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 110:165afa46840b 1594 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 110:165afa46840b 1595 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 110:165afa46840b 1596 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 110:165afa46840b 1597 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 110:165afa46840b 1598 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 110:165afa46840b 1599 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 110:165afa46840b 1600 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 110:165afa46840b 1601 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 110:165afa46840b 1602 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 110:165afa46840b 1603 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 110:165afa46840b 1604 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
Kojto 110:165afa46840b 1605 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 1606 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 1607 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 1608 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 110:165afa46840b 1609
Kojto 110:165afa46840b 1610 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 110:165afa46840b 1611 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 110:165afa46840b 1612 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 1613 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 1614 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 1615 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 1616 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 1617 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 110:165afa46840b 1618 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 110:165afa46840b 1619 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 110:165afa46840b 1620 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 110:165afa46840b 1621 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 110:165afa46840b 1622 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 110:165afa46840b 1623 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 110:165afa46840b 1624 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 110:165afa46840b 1625 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 110:165afa46840b 1626 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 110:165afa46840b 1627 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 110:165afa46840b 1628 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 110:165afa46840b 1629 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 110:165afa46840b 1630 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 110:165afa46840b 1631 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 110:165afa46840b 1632 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 110:165afa46840b 1633 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 110:165afa46840b 1634 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 110:165afa46840b 1635 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 110:165afa46840b 1636 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 1637 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 1638 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 1639 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 110:165afa46840b 1640 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 110:165afa46840b 1641 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 110:165afa46840b 1642 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 110:165afa46840b 1643 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 110:165afa46840b 1644 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 110:165afa46840b 1645 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 110:165afa46840b 1646 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 110:165afa46840b 1647
Kojto 110:165afa46840b 1648 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 110:165afa46840b 1649 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 110:165afa46840b 1650 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 1651 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 1652 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 1653 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 1654 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 1655 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 110:165afa46840b 1656 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 110:165afa46840b 1657 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 110:165afa46840b 1658 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 110:165afa46840b 1659 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 110:165afa46840b 1660 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 110:165afa46840b 1661 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 110:165afa46840b 1662 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 110:165afa46840b 1663 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 110:165afa46840b 1664 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 110:165afa46840b 1665 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 110:165afa46840b 1666 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 110:165afa46840b 1667 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 110:165afa46840b 1668 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 110:165afa46840b 1669 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 110:165afa46840b 1670 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 110:165afa46840b 1671 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 110:165afa46840b 1672 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 110:165afa46840b 1673 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 110:165afa46840b 1674 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 1675 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 1676 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 1677 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 110:165afa46840b 1678 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 110:165afa46840b 1679 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 110:165afa46840b 1680 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 110:165afa46840b 1681 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 110:165afa46840b 1682 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 110:165afa46840b 1683 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 110:165afa46840b 1684 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 110:165afa46840b 1685
Kojto 110:165afa46840b 1686 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 110:165afa46840b 1687 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 110:165afa46840b 1688 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 1689 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 1690 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 1691 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 1692 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 1693 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 110:165afa46840b 1694 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 110:165afa46840b 1695 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 110:165afa46840b 1696 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 110:165afa46840b 1697 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 110:165afa46840b 1698 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 110:165afa46840b 1699 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 110:165afa46840b 1700 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 110:165afa46840b 1701 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 110:165afa46840b 1702 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 110:165afa46840b 1703 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 110:165afa46840b 1704 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 110:165afa46840b 1705 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 110:165afa46840b 1706 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 110:165afa46840b 1707 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 110:165afa46840b 1708 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 110:165afa46840b 1709 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 110:165afa46840b 1710 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 110:165afa46840b 1711 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
Kojto 110:165afa46840b 1712 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 1713 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 1714
Kojto 110:165afa46840b 1715 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 110:165afa46840b 1716 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 110:165afa46840b 1717
Kojto 110:165afa46840b 1718 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 110:165afa46840b 1719 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 110:165afa46840b 1720
Kojto 110:165afa46840b 1721 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 110:165afa46840b 1722 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 110:165afa46840b 1723
Kojto 110:165afa46840b 1724 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 110:165afa46840b 1725 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 110:165afa46840b 1726
Kojto 110:165afa46840b 1727 /******************** Bit definition for ADC_DR register ********************/
Kojto 110:165afa46840b 1728 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
Kojto 110:165afa46840b 1729 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
Kojto 110:165afa46840b 1730
Kojto 110:165afa46840b 1731 /******************* Bit definition for ADC_CSR register ********************/
Kojto 110:165afa46840b 1732 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
Kojto 110:165afa46840b 1733 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
Kojto 110:165afa46840b 1734 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
Kojto 110:165afa46840b 1735 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
Kojto 110:165afa46840b 1736 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
Kojto 110:165afa46840b 1737 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
Kojto 110:165afa46840b 1738 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
Kojto 110:165afa46840b 1739 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
Kojto 110:165afa46840b 1740 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
Kojto 110:165afa46840b 1741 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
Kojto 110:165afa46840b 1742 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
Kojto 110:165afa46840b 1743 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
Kojto 110:165afa46840b 1744 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
Kojto 110:165afa46840b 1745 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
Kojto 110:165afa46840b 1746 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
Kojto 110:165afa46840b 1747 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
Kojto 110:165afa46840b 1748 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
Kojto 110:165afa46840b 1749 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
Kojto 110:165afa46840b 1750
Kojto 110:165afa46840b 1751 /******************* Bit definition for ADC_CCR register ********************/
Kojto 110:165afa46840b 1752 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
Kojto 110:165afa46840b 1753 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 1754 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 1755 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 1756 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 1757 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 1758 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
Kojto 110:165afa46840b 1759 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 1760 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 1761 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 1762 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 1763 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
Kojto 110:165afa46840b 1764 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
Kojto 110:165afa46840b 1765 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 110:165afa46840b 1766 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 110:165afa46840b 1767 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
Kojto 110:165afa46840b 1768 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 1769 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 1770 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
Kojto 110:165afa46840b 1771 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
Kojto 110:165afa46840b 1772
Kojto 110:165afa46840b 1773 /******************* Bit definition for ADC_CDR register ********************/
Kojto 110:165afa46840b 1774 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
Kojto 110:165afa46840b 1775 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
Kojto 110:165afa46840b 1776
Kojto 110:165afa46840b 1777 /******************************************************************************/
Kojto 110:165afa46840b 1778 /* */
Kojto 110:165afa46840b 1779 /* Controller Area Network */
Kojto 110:165afa46840b 1780 /* */
Kojto 110:165afa46840b 1781 /******************************************************************************/
Kojto 110:165afa46840b 1782 /*!<CAN control and status registers */
Kojto 110:165afa46840b 1783 /******************* Bit definition for CAN_MCR register ********************/
Kojto 110:165afa46840b 1784 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
Kojto 110:165afa46840b 1785 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
Kojto 110:165afa46840b 1786 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
Kojto 110:165afa46840b 1787 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
Kojto 110:165afa46840b 1788 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
Kojto 110:165afa46840b 1789 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
Kojto 110:165afa46840b 1790 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
Kojto 110:165afa46840b 1791 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
Kojto 110:165afa46840b 1792 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
Kojto 110:165afa46840b 1793 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
Kojto 110:165afa46840b 1794 /******************* Bit definition for CAN_MSR register ********************/
Kojto 110:165afa46840b 1795 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
Kojto 110:165afa46840b 1796 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
Kojto 110:165afa46840b 1797 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
Kojto 110:165afa46840b 1798 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
Kojto 110:165afa46840b 1799 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
Kojto 110:165afa46840b 1800 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
Kojto 110:165afa46840b 1801 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
Kojto 110:165afa46840b 1802 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
Kojto 110:165afa46840b 1803 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
Kojto 110:165afa46840b 1804
Kojto 110:165afa46840b 1805 /******************* Bit definition for CAN_TSR register ********************/
Kojto 110:165afa46840b 1806 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
Kojto 110:165afa46840b 1807 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
Kojto 110:165afa46840b 1808 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
Kojto 110:165afa46840b 1809 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
Kojto 110:165afa46840b 1810 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
Kojto 110:165afa46840b 1811 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
Kojto 110:165afa46840b 1812 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
Kojto 110:165afa46840b 1813 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
Kojto 110:165afa46840b 1814 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
Kojto 110:165afa46840b 1815 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
Kojto 110:165afa46840b 1816 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
Kojto 110:165afa46840b 1817 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
Kojto 110:165afa46840b 1818 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
Kojto 110:165afa46840b 1819 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
Kojto 110:165afa46840b 1820 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
Kojto 110:165afa46840b 1821 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
Kojto 110:165afa46840b 1822
Kojto 110:165afa46840b 1823 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
Kojto 110:165afa46840b 1824 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
Kojto 110:165afa46840b 1825 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
Kojto 110:165afa46840b 1826 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
Kojto 110:165afa46840b 1827
Kojto 110:165afa46840b 1828 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
Kojto 110:165afa46840b 1829 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 110:165afa46840b 1830 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 110:165afa46840b 1831 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 110:165afa46840b 1832
Kojto 110:165afa46840b 1833 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 110:165afa46840b 1834 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
Kojto 110:165afa46840b 1835 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
Kojto 110:165afa46840b 1836 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
Kojto 110:165afa46840b 1837 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
Kojto 110:165afa46840b 1838
Kojto 110:165afa46840b 1839 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 110:165afa46840b 1840 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
Kojto 110:165afa46840b 1841 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
Kojto 110:165afa46840b 1842 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
Kojto 110:165afa46840b 1843 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
Kojto 110:165afa46840b 1844
Kojto 110:165afa46840b 1845 /******************** Bit definition for CAN_IER register *******************/
Kojto 110:165afa46840b 1846 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 110:165afa46840b 1847 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
Kojto 110:165afa46840b 1848 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
Kojto 110:165afa46840b 1849 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
Kojto 110:165afa46840b 1850 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
Kojto 110:165afa46840b 1851 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
Kojto 110:165afa46840b 1852 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
Kojto 110:165afa46840b 1853 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
Kojto 110:165afa46840b 1854 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
Kojto 110:165afa46840b 1855 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
Kojto 110:165afa46840b 1856 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
Kojto 110:165afa46840b 1857 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
Kojto 110:165afa46840b 1858 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
Kojto 110:165afa46840b 1859 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
Kojto 110:165afa46840b 1860 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
Kojto 110:165afa46840b 1861 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
Kojto 110:165afa46840b 1862 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
Kojto 110:165afa46840b 1863 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
Kojto 110:165afa46840b 1864 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
Kojto 110:165afa46840b 1865
Kojto 110:165afa46840b 1866
Kojto 110:165afa46840b 1867 /******************** Bit definition for CAN_ESR register *******************/
Kojto 110:165afa46840b 1868 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
Kojto 110:165afa46840b 1869 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
Kojto 110:165afa46840b 1870 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
Kojto 110:165afa46840b 1871
Kojto 110:165afa46840b 1872 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
Kojto 110:165afa46840b 1873 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 1874 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 1875 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 1876
Kojto 110:165afa46840b 1877 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 110:165afa46840b 1878 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
Kojto 110:165afa46840b 1879
Kojto 110:165afa46840b 1880 /******************* Bit definition for CAN_BTR register ********************/
Kojto 110:165afa46840b 1881 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
Kojto 110:165afa46840b 1882 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
Kojto 110:165afa46840b 1883 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 1884 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 1885 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 1886 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 1887 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
Kojto 110:165afa46840b 1888 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 1889 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 1890 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 1891 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
Kojto 110:165afa46840b 1892 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 1893 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 1894 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
Kojto 110:165afa46840b 1895 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
Kojto 110:165afa46840b 1896
Kojto 110:165afa46840b 1897
Kojto 110:165afa46840b 1898 /*!<Mailbox registers */
Kojto 110:165afa46840b 1899 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 110:165afa46840b 1900 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 110:165afa46840b 1901 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 110:165afa46840b 1902 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 110:165afa46840b 1903 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 110:165afa46840b 1904 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 110:165afa46840b 1905
Kojto 110:165afa46840b 1906 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 110:165afa46840b 1907 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 110:165afa46840b 1908 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 110:165afa46840b 1909 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 110:165afa46840b 1910
Kojto 110:165afa46840b 1911 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 110:165afa46840b 1912 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 110:165afa46840b 1913 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 110:165afa46840b 1914 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 110:165afa46840b 1915 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 110:165afa46840b 1916
Kojto 110:165afa46840b 1917 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 110:165afa46840b 1918 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 110:165afa46840b 1919 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 110:165afa46840b 1920 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 110:165afa46840b 1921 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 110:165afa46840b 1922
Kojto 110:165afa46840b 1923 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 110:165afa46840b 1924 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 110:165afa46840b 1925 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 110:165afa46840b 1926 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 110:165afa46840b 1927 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 110:165afa46840b 1928 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 110:165afa46840b 1929
Kojto 110:165afa46840b 1930 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 110:165afa46840b 1931 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 110:165afa46840b 1932 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 110:165afa46840b 1933 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 110:165afa46840b 1934
Kojto 110:165afa46840b 1935 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 110:165afa46840b 1936 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 110:165afa46840b 1937 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 110:165afa46840b 1938 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 110:165afa46840b 1939 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 110:165afa46840b 1940
Kojto 110:165afa46840b 1941 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 110:165afa46840b 1942 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 110:165afa46840b 1943 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 110:165afa46840b 1944 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 110:165afa46840b 1945 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 110:165afa46840b 1946
Kojto 110:165afa46840b 1947 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 110:165afa46840b 1948 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 110:165afa46840b 1949 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 110:165afa46840b 1950 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 110:165afa46840b 1951 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 110:165afa46840b 1952 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 110:165afa46840b 1953
Kojto 110:165afa46840b 1954 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 110:165afa46840b 1955 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 110:165afa46840b 1956 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 110:165afa46840b 1957 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 110:165afa46840b 1958
Kojto 110:165afa46840b 1959 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 110:165afa46840b 1960 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 110:165afa46840b 1961 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 110:165afa46840b 1962 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 110:165afa46840b 1963 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 110:165afa46840b 1964
Kojto 110:165afa46840b 1965 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 110:165afa46840b 1966 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 110:165afa46840b 1967 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 110:165afa46840b 1968 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 110:165afa46840b 1969 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 110:165afa46840b 1970
Kojto 110:165afa46840b 1971 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 110:165afa46840b 1972 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 110:165afa46840b 1973 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 110:165afa46840b 1974 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 110:165afa46840b 1975 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 110:165afa46840b 1976
Kojto 110:165afa46840b 1977 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 110:165afa46840b 1978 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 110:165afa46840b 1979 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 110:165afa46840b 1980 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 110:165afa46840b 1981
Kojto 110:165afa46840b 1982 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 110:165afa46840b 1983 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 110:165afa46840b 1984 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 110:165afa46840b 1985 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 110:165afa46840b 1986 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 110:165afa46840b 1987
Kojto 110:165afa46840b 1988 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 110:165afa46840b 1989 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 110:165afa46840b 1990 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 110:165afa46840b 1991 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 110:165afa46840b 1992 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 110:165afa46840b 1993
Kojto 110:165afa46840b 1994 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 110:165afa46840b 1995 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 110:165afa46840b 1996 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 110:165afa46840b 1997 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 110:165afa46840b 1998 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 110:165afa46840b 1999
Kojto 110:165afa46840b 2000 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 110:165afa46840b 2001 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 110:165afa46840b 2002 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 110:165afa46840b 2003 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 110:165afa46840b 2004
Kojto 110:165afa46840b 2005 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 110:165afa46840b 2006 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 110:165afa46840b 2007 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 110:165afa46840b 2008 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 110:165afa46840b 2009 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 110:165afa46840b 2010
Kojto 110:165afa46840b 2011 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 110:165afa46840b 2012 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 110:165afa46840b 2013 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 110:165afa46840b 2014 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 110:165afa46840b 2015 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 110:165afa46840b 2016
Kojto 110:165afa46840b 2017 /*!<CAN filter registers */
Kojto 110:165afa46840b 2018 /******************* Bit definition for CAN_FMR register ********************/
Kojto 110:165afa46840b 2019 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
Kojto 110:165afa46840b 2020 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
Kojto 110:165afa46840b 2021
Kojto 110:165afa46840b 2022 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 110:165afa46840b 2023 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
Kojto 110:165afa46840b 2024 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
Kojto 110:165afa46840b 2025 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
Kojto 110:165afa46840b 2026 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
Kojto 110:165afa46840b 2027 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
Kojto 110:165afa46840b 2028 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
Kojto 110:165afa46840b 2029 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
Kojto 110:165afa46840b 2030 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
Kojto 110:165afa46840b 2031 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
Kojto 110:165afa46840b 2032 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
Kojto 110:165afa46840b 2033 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
Kojto 110:165afa46840b 2034 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
Kojto 110:165afa46840b 2035 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
Kojto 110:165afa46840b 2036 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
Kojto 110:165afa46840b 2037 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
Kojto 110:165afa46840b 2038 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
Kojto 110:165afa46840b 2039 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
Kojto 110:165afa46840b 2040 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
Kojto 110:165afa46840b 2041 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
Kojto 110:165afa46840b 2042 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
Kojto 110:165afa46840b 2043 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
Kojto 110:165afa46840b 2044 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
Kojto 110:165afa46840b 2045 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
Kojto 110:165afa46840b 2046 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
Kojto 110:165afa46840b 2047 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
Kojto 110:165afa46840b 2048 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
Kojto 110:165afa46840b 2049 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
Kojto 110:165afa46840b 2050 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
Kojto 110:165afa46840b 2051 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
Kojto 110:165afa46840b 2052
Kojto 110:165afa46840b 2053 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 110:165afa46840b 2054 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
Kojto 110:165afa46840b 2055 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
Kojto 110:165afa46840b 2056 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
Kojto 110:165afa46840b 2057 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
Kojto 110:165afa46840b 2058 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
Kojto 110:165afa46840b 2059 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
Kojto 110:165afa46840b 2060 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
Kojto 110:165afa46840b 2061 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
Kojto 110:165afa46840b 2062 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
Kojto 110:165afa46840b 2063 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
Kojto 110:165afa46840b 2064 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
Kojto 110:165afa46840b 2065 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
Kojto 110:165afa46840b 2066 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
Kojto 110:165afa46840b 2067 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
Kojto 110:165afa46840b 2068 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
Kojto 110:165afa46840b 2069 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
Kojto 110:165afa46840b 2070 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
Kojto 110:165afa46840b 2071 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
Kojto 110:165afa46840b 2072 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
Kojto 110:165afa46840b 2073 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
Kojto 110:165afa46840b 2074 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
Kojto 110:165afa46840b 2075 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
Kojto 110:165afa46840b 2076 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
Kojto 110:165afa46840b 2077 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
Kojto 110:165afa46840b 2078 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
Kojto 110:165afa46840b 2079 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
Kojto 110:165afa46840b 2080 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
Kojto 110:165afa46840b 2081 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
Kojto 110:165afa46840b 2082 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
Kojto 110:165afa46840b 2083
Kojto 110:165afa46840b 2084 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 110:165afa46840b 2085 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
Kojto 110:165afa46840b 2086 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
Kojto 110:165afa46840b 2087 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
Kojto 110:165afa46840b 2088 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
Kojto 110:165afa46840b 2089 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
Kojto 110:165afa46840b 2090 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
Kojto 110:165afa46840b 2091 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
Kojto 110:165afa46840b 2092 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
Kojto 110:165afa46840b 2093 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
Kojto 110:165afa46840b 2094 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
Kojto 110:165afa46840b 2095 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
Kojto 110:165afa46840b 2096 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
Kojto 110:165afa46840b 2097 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
Kojto 110:165afa46840b 2098 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
Kojto 110:165afa46840b 2099 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
Kojto 110:165afa46840b 2100 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
Kojto 110:165afa46840b 2101 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
Kojto 110:165afa46840b 2102 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
Kojto 110:165afa46840b 2103 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
Kojto 110:165afa46840b 2104 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
Kojto 110:165afa46840b 2105 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
Kojto 110:165afa46840b 2106 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
Kojto 110:165afa46840b 2107 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
Kojto 110:165afa46840b 2108 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
Kojto 110:165afa46840b 2109 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
Kojto 110:165afa46840b 2110 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
Kojto 110:165afa46840b 2111 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
Kojto 110:165afa46840b 2112 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
Kojto 110:165afa46840b 2113 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
Kojto 110:165afa46840b 2114
Kojto 110:165afa46840b 2115 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 110:165afa46840b 2116 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
Kojto 110:165afa46840b 2117 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
Kojto 110:165afa46840b 2118 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
Kojto 110:165afa46840b 2119 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
Kojto 110:165afa46840b 2120 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
Kojto 110:165afa46840b 2121 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
Kojto 110:165afa46840b 2122 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
Kojto 110:165afa46840b 2123 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
Kojto 110:165afa46840b 2124 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
Kojto 110:165afa46840b 2125 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
Kojto 110:165afa46840b 2126 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
Kojto 110:165afa46840b 2127 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
Kojto 110:165afa46840b 2128 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
Kojto 110:165afa46840b 2129 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
Kojto 110:165afa46840b 2130 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
Kojto 110:165afa46840b 2131 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
Kojto 110:165afa46840b 2132 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
Kojto 110:165afa46840b 2133 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
Kojto 110:165afa46840b 2134 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
Kojto 110:165afa46840b 2135 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
Kojto 110:165afa46840b 2136 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
Kojto 110:165afa46840b 2137 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
Kojto 110:165afa46840b 2138 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
Kojto 110:165afa46840b 2139 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
Kojto 110:165afa46840b 2140 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
Kojto 110:165afa46840b 2141 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
Kojto 110:165afa46840b 2142 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
Kojto 110:165afa46840b 2143 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
Kojto 110:165afa46840b 2144 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
Kojto 110:165afa46840b 2145
Kojto 110:165afa46840b 2146
Kojto 110:165afa46840b 2147 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 110:165afa46840b 2148 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2149 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2150 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2151 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2152 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2153 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2154 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2155 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2156 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2157 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2158 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2159 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2160 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2161 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2162 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2163 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2164 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2165 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2166 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2167 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2168 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2169 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2170 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2171 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2172 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2173 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2174 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2175 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2176 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2177 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2178 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2179 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2180
Kojto 110:165afa46840b 2181 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 110:165afa46840b 2182 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2183 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2184 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2185 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2186 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2187 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2188 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2189 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2190 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2191 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2192 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2193 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2194 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2195 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2196 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2197 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2198 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2199 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2200 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2201 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2202 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2203 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2204 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2205 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2206 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2207 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2208 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2209 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2210 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2211 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2212 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2213 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2214
Kojto 110:165afa46840b 2215 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 110:165afa46840b 2216 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2217 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2218 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2219 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2220 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2221 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2222 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2223 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2224 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2225 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2226 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2227 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2228 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2229 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2230 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2231 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2232 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2233 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2234 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2235 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2236 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2237 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2238 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2239 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2240 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2241 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2242 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2243 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2244 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2245 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2246 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2247 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2248
Kojto 110:165afa46840b 2249 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 110:165afa46840b 2250 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2251 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2252 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2253 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2254 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2255 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2256 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2257 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2258 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2259 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2260 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2261 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2262 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2263 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2264 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2265 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2266 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2267 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2268 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2269 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2270 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2271 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2272 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2273 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2274 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2275 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2276 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2277 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2278 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2279 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2280 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2281 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2282
Kojto 110:165afa46840b 2283 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 110:165afa46840b 2284 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2285 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2286 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2287 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2288 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2289 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2290 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2291 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2292 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2293 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2294 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2295 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2296 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2297 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2298 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2299 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2300 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2301 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2302 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2303 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2304 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2305 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2306 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2307 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2308 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2309 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2310 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2311 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2312 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2313 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2314 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2315 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2316
Kojto 110:165afa46840b 2317 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 110:165afa46840b 2318 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2319 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2320 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2321 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2322 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2323 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2324 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2325 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2326 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2327 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2328 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2329 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2330 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2331 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2332 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2333 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2334 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2335 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2336 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2337 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2338 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2339 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2340 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2341 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2342 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2343 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2344 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2345 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2346 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2347 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2348 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2349 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2350
Kojto 110:165afa46840b 2351 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 110:165afa46840b 2352 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2353 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2354 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2355 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2356 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2357 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2358 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2359 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2360 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2361 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2362 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2363 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2364 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2365 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2366 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2367 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2368 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2369 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2370 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2371 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2372 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2373 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2374 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2375 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2376 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2377 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2378 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2379 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2380 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2381 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2382 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2383 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2384
Kojto 110:165afa46840b 2385 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 110:165afa46840b 2386 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2387 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2388 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2389 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2390 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2391 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2392 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2393 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2394 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2395 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2396 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2397 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2398 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2399 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2400 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2401 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2402 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2403 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2404 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2405 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2406 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2407 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2408 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2409 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2410 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2411 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2412 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2413 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2414 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2415 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2416 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2417 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2418
Kojto 110:165afa46840b 2419 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 110:165afa46840b 2420 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2421 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2422 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2423 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2424 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2425 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2426 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2427 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2428 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2429 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2430 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2431 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2432 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2433 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2434 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2435 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2436 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2437 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2438 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2439 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2440 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2441 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2442 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2443 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2444 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2445 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2446 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2447 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2448 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2449 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2450 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2451 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2452
Kojto 110:165afa46840b 2453 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 110:165afa46840b 2454 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2455 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2456 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2457 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2458 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2459 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2460 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2461 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2462 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2463 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2464 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2465 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2466 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2467 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2468 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2469 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2470 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2471 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2472 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2473 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2474 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2475 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2476 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2477 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2478 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2479 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2480 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2481 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2482 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2483 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2484 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2485 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2486
Kojto 110:165afa46840b 2487 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 110:165afa46840b 2488 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2489 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2490 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2491 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2492 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2493 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2494 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2495 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2496 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2497 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2498 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2499 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2500 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2501 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2502 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2503 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2504 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2505 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2506 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2507 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2508 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2509 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2510 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2511 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2512 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2513 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2514 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2515 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2516 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2517 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2518 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2519 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2520
Kojto 110:165afa46840b 2521 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 110:165afa46840b 2522 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2523 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2524 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2525 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2526 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2527 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2528 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2529 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2530 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2531 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2532 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2533 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2534 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2535 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2536 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2537 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2538 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2539 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2540 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2541 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2542 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2543 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2544 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2545 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2546 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2547 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2548 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2549 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2550 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2551 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2552 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2553 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2554
Kojto 110:165afa46840b 2555 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 110:165afa46840b 2556 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2557 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2558 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2559 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2560 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2561 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2562 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2563 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2564 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2565 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2566 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2567 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2568 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2569 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2570 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2571 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2572 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2573 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2574 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2575 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2576 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2577 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2578 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2579 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2580 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2581 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2582 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2583 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2584 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2585 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2586 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2587 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2588
Kojto 110:165afa46840b 2589 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 110:165afa46840b 2590 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2591 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2592 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2593 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2594 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2595 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2596 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2597 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2598 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2599 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2600 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2601 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2602 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2603 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2604 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2605 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2606 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2607 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2608 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2609 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2610 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2611 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2612 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2613 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2614 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2615 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2616 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2617 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2618 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2619 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2620 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2621 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2622
Kojto 110:165afa46840b 2623 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 110:165afa46840b 2624 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2625 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2626 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2627 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2628 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2629 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2630 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2631 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2632 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2633 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2634 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2635 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2636 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2637 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2638 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2639 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2640 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2641 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2642 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2643 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2644 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2645 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2646 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2647 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2648 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2649 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2650 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2651 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2652 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2653 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2654 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2655 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2656
Kojto 110:165afa46840b 2657 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 110:165afa46840b 2658 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2659 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2660 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2661 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2662 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2663 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2664 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2665 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2666 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2667 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2668 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2669 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2670 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2671 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2672 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2673 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2674 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2675 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2676 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2677 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2678 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2679 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2680 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2681 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2682 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2683 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2684 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2685 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2686 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2687 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2688 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2689 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2690
Kojto 110:165afa46840b 2691 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 110:165afa46840b 2692 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2693 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2694 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2695 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2696 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2697 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2698 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2699 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2700 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2701 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2702 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2703 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2704 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2705 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2706 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2707 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2708 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2709 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2710 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2711 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2712 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2713 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2714 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2715 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2716 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2717 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2718 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2719 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2720 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2721 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2722 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2723 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2724
Kojto 110:165afa46840b 2725 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 110:165afa46840b 2726 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2727 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2728 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2729 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2730 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2731 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2732 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2733 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2734 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2735 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2736 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2737 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2738 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2739 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2740 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2741 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2742 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2743 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2744 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2745 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2746 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2747 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2748 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2749 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2750 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2751 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2752 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2753 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2754 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2755 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2756 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2757 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2758
Kojto 110:165afa46840b 2759 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 110:165afa46840b 2760 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2761 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2762 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2763 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2764 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2765 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2766 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2767 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2768 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2769 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2770 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2771 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2772 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2773 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2774 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2775 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2776 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2777 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2778 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2779 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2780 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2781 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2782 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2783 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2784 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2785 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2786 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2787 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2788 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2789 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2790 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2791 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2792
Kojto 110:165afa46840b 2793 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 110:165afa46840b 2794 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2795 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2796 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2797 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2798 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2799 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2800 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2801 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2802 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2803 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2804 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2805 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2806 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2807 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2808 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2809 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2810 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2811 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2812 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2813 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2814 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2815 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2816 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2817 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2818 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2819 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2820 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2821 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2822 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2823 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2824 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2825 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2826
Kojto 110:165afa46840b 2827 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 110:165afa46840b 2828 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2829 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2830 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2831 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2832 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2833 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2834 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2835 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2836 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2837 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2838 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2839 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2840 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2841 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2842 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2843 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2844 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2845 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2846 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2847 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2848 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2849 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2850 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2851 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2852 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2853 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2854 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2855 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2856 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2857 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2858 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2859 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2860
Kojto 110:165afa46840b 2861 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 110:165afa46840b 2862 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2863 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2864 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2865 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2866 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2867 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2868 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2869 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2870 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2871 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2872 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2873 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2874 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2875 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2876 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2877 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2878 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2879 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2880 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2881 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2882 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2883 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2884 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2885 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2886 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2887 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2888 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2889 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2890 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2891 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2892 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2893 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2894
Kojto 110:165afa46840b 2895 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 110:165afa46840b 2896 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2897 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2898 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2899 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2900 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2901 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2902 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2903 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2904 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2905 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2906 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2907 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2908 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2909 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2910 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2911 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2912 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2913 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2914 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2915 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2916 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2917 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2918 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2919 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2920 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2921 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2922 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2923 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2924 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2925 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2926 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2927 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2928
Kojto 110:165afa46840b 2929 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 110:165afa46840b 2930 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2931 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2932 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2933 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2934 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2935 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2936 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2937 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2938 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2939 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2940 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2941 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2942 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2943 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2944 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2945 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2946 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2947 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2948 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2949 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2950 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2951 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2952 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2953 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2954 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2955 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2956 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2957 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2958 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2959 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2960 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2961 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2962
Kojto 110:165afa46840b 2963 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 110:165afa46840b 2964 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2965 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 2966 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 2967 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 2968 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 2969 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 2970 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 2971 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 2972 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 2973 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 2974 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 2975 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 2976 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 2977 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 2978 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 2979 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 2980 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 2981 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 2982 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 2983 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 2984 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 2985 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 2986 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 2987 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 2988 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 2989 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 2990 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 2991 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 2992 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 2993 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 2994 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 2995 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 2996
Kojto 110:165afa46840b 2997 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 110:165afa46840b 2998 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 2999 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 3000 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 3001 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 3002 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 3003 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 3004 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 3005 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 3006 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 3007 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 3008 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 3009 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 3010 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 3011 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 3012 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 3013 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 3014 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 3015 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 3016 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 3017 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 3018 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 3019 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 3020 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 3021 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 3022 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 3023 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 3024 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 3025 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 3026 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 3027 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 3028 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 3029 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 3030
Kojto 110:165afa46840b 3031 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 110:165afa46840b 3032 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 3033 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 3034 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 3035 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 3036 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 3037 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 3038 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 3039 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 3040 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 3041 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 3042 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 3043 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 3044 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 3045 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 3046 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 3047 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 3048 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 3049 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 3050 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 3051 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 3052 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 3053 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 3054 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 3055 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 3056 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 3057 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 3058 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 3059 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 3060 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 3061 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 3062 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 3063 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 3064
Kojto 110:165afa46840b 3065 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 110:165afa46840b 3066 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 110:165afa46840b 3067 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 110:165afa46840b 3068 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 110:165afa46840b 3069 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 110:165afa46840b 3070 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 110:165afa46840b 3071 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 110:165afa46840b 3072 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 110:165afa46840b 3073 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 110:165afa46840b 3074 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 110:165afa46840b 3075 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 110:165afa46840b 3076 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 110:165afa46840b 3077 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 110:165afa46840b 3078 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 110:165afa46840b 3079 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 110:165afa46840b 3080 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 110:165afa46840b 3081 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 110:165afa46840b 3082 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 110:165afa46840b 3083 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 110:165afa46840b 3084 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 110:165afa46840b 3085 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 110:165afa46840b 3086 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 110:165afa46840b 3087 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 110:165afa46840b 3088 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 110:165afa46840b 3089 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 110:165afa46840b 3090 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 110:165afa46840b 3091 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 110:165afa46840b 3092 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 110:165afa46840b 3093 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 110:165afa46840b 3094 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 110:165afa46840b 3095 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 110:165afa46840b 3096 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 110:165afa46840b 3097 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 110:165afa46840b 3098
Kojto 110:165afa46840b 3099 /******************************************************************************/
Kojto 110:165afa46840b 3100 /* */
Kojto 110:165afa46840b 3101 /* CRC calculation unit */
Kojto 110:165afa46840b 3102 /* */
Kojto 110:165afa46840b 3103 /******************************************************************************/
Kojto 110:165afa46840b 3104 /******************* Bit definition for CRC_DR register *********************/
Kojto 110:165afa46840b 3105 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 110:165afa46840b 3106
Kojto 110:165afa46840b 3107
Kojto 110:165afa46840b 3108 /******************* Bit definition for CRC_IDR register ********************/
Kojto 110:165afa46840b 3109 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 110:165afa46840b 3110
Kojto 110:165afa46840b 3111
Kojto 110:165afa46840b 3112 /******************** Bit definition for CRC_CR register ********************/
Kojto 110:165afa46840b 3113 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
Kojto 110:165afa46840b 3114
Kojto 110:165afa46840b 3115
Kojto 110:165afa46840b 3116 /******************************************************************************/
Kojto 110:165afa46840b 3117 /* */
Kojto 110:165afa46840b 3118 /* Digital to Analog Converter */
Kojto 110:165afa46840b 3119 /* */
Kojto 110:165afa46840b 3120 /******************************************************************************/
Kojto 110:165afa46840b 3121 /******************** Bit definition for DAC_CR register ********************/
Kojto 110:165afa46840b 3122 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
Kojto 110:165afa46840b 3123 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
Kojto 110:165afa46840b 3124 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
Kojto 110:165afa46840b 3125
Kojto 110:165afa46840b 3126 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 110:165afa46840b 3127 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 110:165afa46840b 3128 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 110:165afa46840b 3129 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 110:165afa46840b 3130
Kojto 110:165afa46840b 3131 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 110:165afa46840b 3132 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 110:165afa46840b 3133 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 110:165afa46840b 3134
Kojto 110:165afa46840b 3135 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 110:165afa46840b 3136 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 3137 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 3138 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 3139 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 3140
Kojto 110:165afa46840b 3141 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
Kojto 110:165afa46840b 3142 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
Kojto 110:165afa46840b 3143 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
Kojto 110:165afa46840b 3144 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
Kojto 110:165afa46840b 3145
Kojto 110:165afa46840b 3146 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 110:165afa46840b 3147 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
Kojto 110:165afa46840b 3148 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
Kojto 110:165afa46840b 3149 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
Kojto 110:165afa46840b 3150
Kojto 110:165afa46840b 3151 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 110:165afa46840b 3152 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 110:165afa46840b 3153 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 110:165afa46840b 3154
Kojto 110:165afa46840b 3155 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 110:165afa46840b 3156 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 3157 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 3158 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 3159 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 3160
Kojto 110:165afa46840b 3161 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
Kojto 110:165afa46840b 3162
Kojto 110:165afa46840b 3163 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 110:165afa46840b 3164 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
Kojto 110:165afa46840b 3165 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
Kojto 110:165afa46840b 3166
Kojto 110:165afa46840b 3167 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 110:165afa46840b 3168 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
Kojto 110:165afa46840b 3169
Kojto 110:165afa46840b 3170 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 110:165afa46840b 3171 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
Kojto 110:165afa46840b 3172
Kojto 110:165afa46840b 3173 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 110:165afa46840b 3174 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
Kojto 110:165afa46840b 3175
Kojto 110:165afa46840b 3176 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 110:165afa46840b 3177 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
Kojto 110:165afa46840b 3178
Kojto 110:165afa46840b 3179 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 110:165afa46840b 3180 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
Kojto 110:165afa46840b 3181
Kojto 110:165afa46840b 3182 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 110:165afa46840b 3183 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
Kojto 110:165afa46840b 3184
Kojto 110:165afa46840b 3185 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 110:165afa46840b 3186 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
Kojto 110:165afa46840b 3187 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
Kojto 110:165afa46840b 3188
Kojto 110:165afa46840b 3189 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 110:165afa46840b 3190 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
Kojto 110:165afa46840b 3191 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
Kojto 110:165afa46840b 3192
Kojto 110:165afa46840b 3193 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 110:165afa46840b 3194 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
Kojto 110:165afa46840b 3195 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
Kojto 110:165afa46840b 3196
Kojto 110:165afa46840b 3197 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 110:165afa46840b 3198 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
Kojto 110:165afa46840b 3199
Kojto 110:165afa46840b 3200 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 110:165afa46840b 3201 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
Kojto 110:165afa46840b 3202
Kojto 110:165afa46840b 3203 /******************** Bit definition for DAC_SR register ********************/
Kojto 110:165afa46840b 3204 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
Kojto 110:165afa46840b 3205 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
Kojto 110:165afa46840b 3206
Kojto 110:165afa46840b 3207 /******************************************************************************/
Kojto 110:165afa46840b 3208 /* */
Kojto 110:165afa46840b 3209 /* Debug MCU */
Kojto 110:165afa46840b 3210 /* */
Kojto 110:165afa46840b 3211 /******************************************************************************/
Kojto 110:165afa46840b 3212
Kojto 110:165afa46840b 3213 /******************************************************************************/
Kojto 110:165afa46840b 3214 /* */
Kojto 110:165afa46840b 3215 /* DCMI */
Kojto 110:165afa46840b 3216 /* */
Kojto 110:165afa46840b 3217 /******************************************************************************/
Kojto 110:165afa46840b 3218 /******************** Bits definition for DCMI_CR register ******************/
Kojto 110:165afa46840b 3219 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3220 #define DCMI_CR_CM ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3221 #define DCMI_CR_CROP ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3222 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3223 #define DCMI_CR_ESS ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3224 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3225 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3226 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3227 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3228 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3229 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3230 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3231 #define DCMI_CR_OUTEN ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3232 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
Kojto 110:165afa46840b 3233 #define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3234 #define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 3235 #define DCMI_CR_OEBS ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3236 #define DCMI_CR_LSM ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3237 #define DCMI_CR_OELS ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3238
Kojto 110:165afa46840b 3239 /******************** Bits definition for DCMI_SR register ******************/
Kojto 110:165afa46840b 3240 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3241 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3242 #define DCMI_SR_FNE ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3243
Kojto 110:165afa46840b 3244 /******************** Bits definition for DCMI_RISR register ****************/
Kojto 110:165afa46840b 3245 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3246 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3247 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3248 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3249 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3250
Kojto 110:165afa46840b 3251 /******************** Bits definition for DCMI_IER register *****************/
Kojto 110:165afa46840b 3252 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3253 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3254 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3255 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3256 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3257
Kojto 110:165afa46840b 3258 /******************** Bits definition for DCMI_MISR register ****************/
Kojto 110:165afa46840b 3259 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3260 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3261 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3262 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3263 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3264
Kojto 110:165afa46840b 3265 /******************** Bits definition for DCMI_ICR register *****************/
Kojto 110:165afa46840b 3266 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3267 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3268 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3269 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3270 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3271
Kojto 110:165afa46840b 3272 /******************************************************************************/
Kojto 110:165afa46840b 3273 /* */
Kojto 110:165afa46840b 3274 /* DMA Controller */
Kojto 110:165afa46840b 3275 /* */
Kojto 110:165afa46840b 3276 /******************************************************************************/
Kojto 110:165afa46840b 3277 /******************** Bits definition for DMA_SxCR register *****************/
Kojto 110:165afa46840b 3278 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
Kojto 110:165afa46840b 3279 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 3280 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 3281 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 3282 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
Kojto 110:165afa46840b 3283 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 3284 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 3285 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
Kojto 110:165afa46840b 3286 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 3287 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 3288 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3289 #define DMA_SxCR_CT ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3290 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3291 #define DMA_SxCR_PL ((uint32_t)0x00030000)
Kojto 110:165afa46840b 3292 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3293 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 3294 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
Kojto 110:165afa46840b 3295 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
Kojto 110:165afa46840b 3296 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3297 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 3298 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
Kojto 110:165afa46840b 3299 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3300 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3301 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3302 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3303 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3304 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
Kojto 110:165afa46840b 3305 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3306 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3307 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3308 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3309 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3310 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3311 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3312 #define DMA_SxCR_EN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3313
Kojto 110:165afa46840b 3314 /******************** Bits definition for DMA_SxCNDTR register **************/
Kojto 110:165afa46840b 3315 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
Kojto 110:165afa46840b 3316 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3317 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3318 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3319 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3320 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3321 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3322 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3323 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3324 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3325 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3326 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3327 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3328 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3329 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3330 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 3331 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 3332
Kojto 110:165afa46840b 3333 /******************** Bits definition for DMA_SxFCR register ****************/
Kojto 110:165afa46840b 3334 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3335 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
Kojto 110:165afa46840b 3336 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3337 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3338 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3339 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3340 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
Kojto 110:165afa46840b 3341 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3342 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3343
Kojto 110:165afa46840b 3344 /******************** Bits definition for DMA_LISR register *****************/
Kojto 110:165afa46840b 3345 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 3346 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 3347 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 3348 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 3349 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 3350 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 3351 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3352 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3353 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3354 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3355 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3356 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3357 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3358 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3359 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3360 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3361 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3362 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3363 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3364 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3365
Kojto 110:165afa46840b 3366 /******************** Bits definition for DMA_HISR register *****************/
Kojto 110:165afa46840b 3367 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 3368 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 3369 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 3370 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 3371 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 3372 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 3373 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3374 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3375 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3376 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3377 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3378 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3379 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3380 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3381 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3382 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3383 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3384 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3385 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3386 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3387
Kojto 110:165afa46840b 3388 /******************** Bits definition for DMA_LIFCR register ****************/
Kojto 110:165afa46840b 3389 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 3390 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 3391 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 3392 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 3393 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 3394 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 3395 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3396 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3397 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3398 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3399 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3400 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3401 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3402 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3403 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3404 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3405 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3406 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3407 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3408 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3409
Kojto 110:165afa46840b 3410 /******************** Bits definition for DMA_HIFCR register ****************/
Kojto 110:165afa46840b 3411 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 3412 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 3413 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 3414 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 3415 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 3416 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 3417 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3418 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3419 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3420 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3421 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3422 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3423 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3424 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3425 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3426 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3427 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3428 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3429 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3430 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3431
Kojto 110:165afa46840b 3432
Kojto 110:165afa46840b 3433 /******************************************************************************/
Kojto 110:165afa46840b 3434 /* */
Kojto 110:165afa46840b 3435 /* AHB Master DMA2D Controller (DMA2D) */
Kojto 110:165afa46840b 3436 /* */
Kojto 110:165afa46840b 3437 /******************************************************************************/
Kojto 110:165afa46840b 3438
Kojto 110:165afa46840b 3439 /******************** Bit definition for DMA2D_CR register ******************/
Kojto 110:165afa46840b 3440
Kojto 110:165afa46840b 3441 #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
Kojto 110:165afa46840b 3442 #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
Kojto 110:165afa46840b 3443 #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
Kojto 110:165afa46840b 3444 #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
Kojto 110:165afa46840b 3445 #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
Kojto 110:165afa46840b 3446 #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
Kojto 110:165afa46840b 3447 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
Kojto 110:165afa46840b 3448 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
Kojto 110:165afa46840b 3449 #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
Kojto 110:165afa46840b 3450 #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
Kojto 110:165afa46840b 3451
Kojto 110:165afa46840b 3452 /******************** Bit definition for DMA2D_ISR register *****************/
Kojto 110:165afa46840b 3453
Kojto 110:165afa46840b 3454 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
Kojto 110:165afa46840b 3455 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
Kojto 110:165afa46840b 3456 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
Kojto 110:165afa46840b 3457 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
Kojto 110:165afa46840b 3458 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
Kojto 110:165afa46840b 3459 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
Kojto 110:165afa46840b 3460
Kojto 110:165afa46840b 3461 /******************** Bit definition for DMA2D_IFSR register ****************/
Kojto 110:165afa46840b 3462
Kojto 110:165afa46840b 3463 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
Kojto 110:165afa46840b 3464 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
Kojto 110:165afa46840b 3465 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
Kojto 110:165afa46840b 3466 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
Kojto 110:165afa46840b 3467 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
Kojto 110:165afa46840b 3468 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
Kojto 110:165afa46840b 3469
Kojto 110:165afa46840b 3470 /******************** Bit definition for DMA2D_FGMAR register ***************/
Kojto 110:165afa46840b 3471
Kojto 110:165afa46840b 3472 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 110:165afa46840b 3473
Kojto 110:165afa46840b 3474 /******************** Bit definition for DMA2D_FGOR register ****************/
Kojto 110:165afa46840b 3475
Kojto 110:165afa46840b 3476 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
Kojto 110:165afa46840b 3477
Kojto 110:165afa46840b 3478 /******************** Bit definition for DMA2D_BGMAR register ***************/
Kojto 110:165afa46840b 3479
Kojto 110:165afa46840b 3480 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 110:165afa46840b 3481
Kojto 110:165afa46840b 3482 /******************** Bit definition for DMA2D_BGOR register ****************/
Kojto 110:165afa46840b 3483
Kojto 110:165afa46840b 3484 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
Kojto 110:165afa46840b 3485
Kojto 110:165afa46840b 3486 /******************** Bit definition for DMA2D_FGPFCCR register *************/
Kojto 110:165afa46840b 3487
Kojto 110:165afa46840b 3488 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
Kojto 110:165afa46840b 3489 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
Kojto 110:165afa46840b 3490 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
Kojto 110:165afa46840b 3491 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
Kojto 110:165afa46840b 3492 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
Kojto 110:165afa46840b 3493 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
Kojto 110:165afa46840b 3494
Kojto 110:165afa46840b 3495 /******************** Bit definition for DMA2D_FGCOLR register **************/
Kojto 110:165afa46840b 3496
Kojto 110:165afa46840b 3497 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
Kojto 110:165afa46840b 3498 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
Kojto 110:165afa46840b 3499 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
Kojto 110:165afa46840b 3500
Kojto 110:165afa46840b 3501 /******************** Bit definition for DMA2D_BGPFCCR register *************/
Kojto 110:165afa46840b 3502
Kojto 110:165afa46840b 3503 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
Kojto 110:165afa46840b 3504 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
Kojto 110:165afa46840b 3505 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
Kojto 110:165afa46840b 3506 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
Kojto 110:165afa46840b 3507 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
Kojto 110:165afa46840b 3508 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
Kojto 110:165afa46840b 3509
Kojto 110:165afa46840b 3510 /******************** Bit definition for DMA2D_BGCOLR register **************/
Kojto 110:165afa46840b 3511
Kojto 110:165afa46840b 3512 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
Kojto 110:165afa46840b 3513 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
Kojto 110:165afa46840b 3514 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
Kojto 110:165afa46840b 3515
Kojto 110:165afa46840b 3516 /******************** Bit definition for DMA2D_FGCMAR register **************/
Kojto 110:165afa46840b 3517
Kojto 110:165afa46840b 3518 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 110:165afa46840b 3519
Kojto 110:165afa46840b 3520 /******************** Bit definition for DMA2D_BGCMAR register **************/
Kojto 110:165afa46840b 3521
Kojto 110:165afa46840b 3522 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 110:165afa46840b 3523
Kojto 110:165afa46840b 3524 /******************** Bit definition for DMA2D_OPFCCR register **************/
Kojto 110:165afa46840b 3525
Kojto 110:165afa46840b 3526 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
Kojto 110:165afa46840b 3527
Kojto 110:165afa46840b 3528 /******************** Bit definition for DMA2D_OCOLR register ***************/
Kojto 110:165afa46840b 3529
Kojto 110:165afa46840b 3530 /*!<Mode_ARGB8888/RGB888 */
Kojto 110:165afa46840b 3531
Kojto 110:165afa46840b 3532 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
Kojto 110:165afa46840b 3533 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
Kojto 110:165afa46840b 3534 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
Kojto 110:165afa46840b 3535 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
Kojto 110:165afa46840b 3536
Kojto 110:165afa46840b 3537 /*!<Mode_RGB565 */
Kojto 110:165afa46840b 3538 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
Kojto 110:165afa46840b 3539 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
Kojto 110:165afa46840b 3540 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
Kojto 110:165afa46840b 3541
Kojto 110:165afa46840b 3542 /*!<Mode_ARGB1555 */
Kojto 110:165afa46840b 3543 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
Kojto 110:165afa46840b 3544 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
Kojto 110:165afa46840b 3545 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
Kojto 110:165afa46840b 3546 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
Kojto 110:165afa46840b 3547
Kojto 110:165afa46840b 3548 /*!<Mode_ARGB4444 */
Kojto 110:165afa46840b 3549 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
Kojto 110:165afa46840b 3550 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
Kojto 110:165afa46840b 3551 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
Kojto 110:165afa46840b 3552 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
Kojto 110:165afa46840b 3553
Kojto 110:165afa46840b 3554 /******************** Bit definition for DMA2D_OMAR register ****************/
Kojto 110:165afa46840b 3555
Kojto 110:165afa46840b 3556 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 110:165afa46840b 3557
Kojto 110:165afa46840b 3558 /******************** Bit definition for DMA2D_OOR register *****************/
Kojto 110:165afa46840b 3559
Kojto 110:165afa46840b 3560 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
Kojto 110:165afa46840b 3561
Kojto 110:165afa46840b 3562 /******************** Bit definition for DMA2D_NLR register *****************/
Kojto 110:165afa46840b 3563
Kojto 110:165afa46840b 3564 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
Kojto 110:165afa46840b 3565 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
Kojto 110:165afa46840b 3566
Kojto 110:165afa46840b 3567 /******************** Bit definition for DMA2D_LWR register *****************/
Kojto 110:165afa46840b 3568
Kojto 110:165afa46840b 3569 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
Kojto 110:165afa46840b 3570
Kojto 110:165afa46840b 3571 /******************** Bit definition for DMA2D_AMTCR register ***************/
Kojto 110:165afa46840b 3572
Kojto 110:165afa46840b 3573 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
Kojto 110:165afa46840b 3574 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
Kojto 110:165afa46840b 3575
Kojto 110:165afa46840b 3576
Kojto 110:165afa46840b 3577 /******************** Bit definition for DMA2D_FGCLUT register **************/
Kojto 110:165afa46840b 3578
Kojto 110:165afa46840b 3579 /******************** Bit definition for DMA2D_BGCLUT register **************/
Kojto 110:165afa46840b 3580
Kojto 110:165afa46840b 3581
Kojto 110:165afa46840b 3582 /******************************************************************************/
Kojto 110:165afa46840b 3583 /* */
Kojto 110:165afa46840b 3584 /* Display Serial Interface (DSI) */
Kojto 110:165afa46840b 3585 /* */
Kojto 110:165afa46840b 3586 /******************************************************************************/
Kojto 110:165afa46840b 3587 /******************* Bit definition for DSI_VR register *****************/
Kojto 110:165afa46840b 3588 #define DSI_VR ((uint32_t)0x3133302A) /*!< DSI Host Version */
Kojto 110:165afa46840b 3589
Kojto 110:165afa46840b 3590 /******************* Bit definition for DSI_CR register *****************/
Kojto 110:165afa46840b 3591 #define DSI_CR_EN ((uint32_t)0x00000001) /*!< DSI Host power up and reset */
Kojto 110:165afa46840b 3592
Kojto 110:165afa46840b 3593 /******************* Bit definition for DSI_CCR register ****************/
Kojto 110:165afa46840b 3594 #define DSI_CCR_TXECKDIV ((uint32_t)0x000000FF) /*!< TX Escape Clock Division */
Kojto 110:165afa46840b 3595 #define DSI_CCR_TXECKDIV0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3596 #define DSI_CCR_TXECKDIV1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3597 #define DSI_CCR_TXECKDIV2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3598 #define DSI_CCR_TXECKDIV3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3599 #define DSI_CCR_TXECKDIV4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3600 #define DSI_CCR_TXECKDIV5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3601 #define DSI_CCR_TXECKDIV6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3602 #define DSI_CCR_TXECKDIV7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3603
Kojto 110:165afa46840b 3604 #define DSI_CCR_TOCKDIV ((uint32_t)0x0000FF00) /*!< Timeout Clock Division */
Kojto 110:165afa46840b 3605 #define DSI_CCR_TOCKDIV0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3606 #define DSI_CCR_TOCKDIV1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3607 #define DSI_CCR_TOCKDIV2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3608 #define DSI_CCR_TOCKDIV3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3609 #define DSI_CCR_TOCKDIV4 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3610 #define DSI_CCR_TOCKDIV5 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3611 #define DSI_CCR_TOCKDIV6 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 3612 #define DSI_CCR_TOCKDIV7 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 3613
Kojto 110:165afa46840b 3614 /******************* Bit definition for DSI_LVCIDR register *************/
Kojto 110:165afa46840b 3615 #define DSI_LVCIDR_VCID ((uint32_t)0x00000003) /*!< Virtual Channel ID */
Kojto 110:165afa46840b 3616 #define DSI_LVCIDR_VCID0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3617 #define DSI_LVCIDR_VCID1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3618
Kojto 110:165afa46840b 3619 /******************* Bit definition for DSI_LCOLCR register *************/
Kojto 110:165afa46840b 3620 #define DSI_LCOLCR_COLC ((uint32_t)0x0000000F) /*!< Color Coding */
Kojto 110:165afa46840b 3621 #define DSI_LCOLCR_COLC0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3622 #define DSI_LCOLCR_COLC1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3623 #define DSI_LCOLCR_COLC2 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3624 #define DSI_LCOLCR_COLC3 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3625
Kojto 110:165afa46840b 3626 #define DSI_LCOLCR_LPE ((uint32_t)0x00000100) /*!< Loosly Packet Enable */
Kojto 110:165afa46840b 3627
Kojto 110:165afa46840b 3628 /******************* Bit definition for DSI_LPCR register ***************/
Kojto 110:165afa46840b 3629 #define DSI_LPCR_DEP ((uint32_t)0x00000001) /*!< Data Enable Polarity */
Kojto 110:165afa46840b 3630 #define DSI_LPCR_VSP ((uint32_t)0x00000002) /*!< VSYNC Polarity */
Kojto 110:165afa46840b 3631 #define DSI_LPCR_HSP ((uint32_t)0x00000004) /*!< HSYNC Polarity */
Kojto 110:165afa46840b 3632
Kojto 110:165afa46840b 3633 /******************* Bit definition for DSI_LPMCR register **************/
Kojto 110:165afa46840b 3634 #define DSI_LPMCR_VLPSIZE ((uint32_t)0x000000FF) /*!< VACT Largest Packet Size */
Kojto 110:165afa46840b 3635 #define DSI_LPMCR_VLPSIZE0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3636 #define DSI_LPMCR_VLPSIZE1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3637 #define DSI_LPMCR_VLPSIZE2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3638 #define DSI_LPMCR_VLPSIZE3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3639 #define DSI_LPMCR_VLPSIZE4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3640 #define DSI_LPMCR_VLPSIZE5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3641 #define DSI_LPMCR_VLPSIZE6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3642 #define DSI_LPMCR_VLPSIZE7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3643
Kojto 110:165afa46840b 3644 #define DSI_LPMCR_LPSIZE ((uint32_t)0x00FF0000) /*!< Largest Packet Size */
Kojto 110:165afa46840b 3645 #define DSI_LPMCR_LPSIZE0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3646 #define DSI_LPMCR_LPSIZE1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 3647 #define DSI_LPMCR_LPSIZE2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3648 #define DSI_LPMCR_LPSIZE3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3649 #define DSI_LPMCR_LPSIZE4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3650 #define DSI_LPMCR_LPSIZE5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 3651 #define DSI_LPMCR_LPSIZE6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 3652 #define DSI_LPMCR_LPSIZE7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 3653
Kojto 110:165afa46840b 3654 /******************* Bit definition for DSI_PCR register ****************/
Kojto 110:165afa46840b 3655 #define DSI_PCR_ETTXE ((uint32_t)0x00000001) /*!< EoTp Transmission Enable */
Kojto 110:165afa46840b 3656 #define DSI_PCR_ETRXE ((uint32_t)0x00000002) /*!< EoTp Reception Enable */
Kojto 110:165afa46840b 3657 #define DSI_PCR_BTAE ((uint32_t)0x00000004) /*!< Bus Turn Around Enable */
Kojto 110:165afa46840b 3658 #define DSI_PCR_ECCRXE ((uint32_t)0x00000008) /*!< ECC Reception Enable */
Kojto 110:165afa46840b 3659 #define DSI_PCR_CRCRXE ((uint32_t)0x00000010) /*!< CRC Reception Enable */
Kojto 110:165afa46840b 3660
Kojto 110:165afa46840b 3661 /******************* Bit definition for DSI_GVCIDR register *************/
Kojto 110:165afa46840b 3662 #define DSI_GVCIDR_VCID ((uint32_t)0x00000003) /*!< Virtual Channel ID */
Kojto 110:165afa46840b 3663 #define DSI_GVCIDR_VCID0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3664 #define DSI_GVCIDR_VCID1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3665
Kojto 110:165afa46840b 3666 /******************* Bit definition for DSI_MCR register ****************/
Kojto 110:165afa46840b 3667 #define DSI_MCR_CMDM ((uint32_t)0x00000001) /*!< Command Mode */
Kojto 110:165afa46840b 3668
Kojto 110:165afa46840b 3669 /******************* Bit definition for DSI_VMCR register ***************/
Kojto 110:165afa46840b 3670 #define DSI_VMCR_VMT ((uint32_t)0x00000003) /*!< Video Mode Type */
Kojto 110:165afa46840b 3671 #define DSI_VMCR_VMT0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3672 #define DSI_VMCR_VMT1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3673
Kojto 110:165afa46840b 3674 #define DSI_VMCR_LPVSAE ((uint32_t)0x00000100) /*!< Low-Power Vertical Sync Active Enable */
Kojto 110:165afa46840b 3675 #define DSI_VMCR_LPVBPE ((uint32_t)0x00000200) /*!< Low-power Vertical Back-Porch Enable */
Kojto 110:165afa46840b 3676 #define DSI_VMCR_LPVFPE ((uint32_t)0x00000400) /*!< Low-power Vertical Front-porch Enable */
Kojto 110:165afa46840b 3677 #define DSI_VMCR_LPVAE ((uint32_t)0x00000800) /*!< Low-Power Vertical Active Enable */
Kojto 110:165afa46840b 3678 #define DSI_VMCR_LPHBPE ((uint32_t)0x00001000) /*!< Low-Power Horizontal Back-Porch Enable */
Kojto 110:165afa46840b 3679 #define DSI_VMCR_LPHFPE ((uint32_t)0x00002000) /*!< Low-Power Horizontal Front-Porch Enable */
Kojto 110:165afa46840b 3680 #define DSI_VMCR_FBTAAE ((uint32_t)0x00004000) /*!< Frame Bus-Turn-Around Acknowledge Enable */
Kojto 110:165afa46840b 3681 #define DSI_VMCR_LPCE ((uint32_t)0x00008000) /*!< Low-Power Command Enable */
Kojto 110:165afa46840b 3682 #define DSI_VMCR_PGE ((uint32_t)0x00010000) /*!< Pattern Generator Enable */
Kojto 110:165afa46840b 3683 #define DSI_VMCR_PGM ((uint32_t)0x00100000) /*!< Pattern Generator Mode */
Kojto 110:165afa46840b 3684 #define DSI_VMCR_PGO ((uint32_t)0x01000000) /*!< Pattern Generator Orientation */
Kojto 110:165afa46840b 3685
Kojto 110:165afa46840b 3686 /******************* Bit definition for DSI_VPCR register ***************/
Kojto 110:165afa46840b 3687 #define DSI_VPCR_VPSIZE ((uint32_t)0x00003FFF) /*!< Video Packet Size */
Kojto 110:165afa46840b 3688 #define DSI_VPCR_VPSIZE0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3689 #define DSI_VPCR_VPSIZE1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3690 #define DSI_VPCR_VPSIZE2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3691 #define DSI_VPCR_VPSIZE3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3692 #define DSI_VPCR_VPSIZE4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3693 #define DSI_VPCR_VPSIZE5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3694 #define DSI_VPCR_VPSIZE6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3695 #define DSI_VPCR_VPSIZE7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3696 #define DSI_VPCR_VPSIZE8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3697 #define DSI_VPCR_VPSIZE9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3698 #define DSI_VPCR_VPSIZE10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3699 #define DSI_VPCR_VPSIZE11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3700 #define DSI_VPCR_VPSIZE12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3701 #define DSI_VPCR_VPSIZE13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3702
Kojto 110:165afa46840b 3703 /******************* Bit definition for DSI_VCCR register ***************/
Kojto 110:165afa46840b 3704 #define DSI_VCCR_NUMC ((uint32_t)0x00001FFF) /*!< Number of Chunks */
Kojto 110:165afa46840b 3705 #define DSI_VCCR_NUMC0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3706 #define DSI_VCCR_NUMC1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3707 #define DSI_VCCR_NUMC2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3708 #define DSI_VCCR_NUMC3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3709 #define DSI_VCCR_NUMC4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3710 #define DSI_VCCR_NUMC5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3711 #define DSI_VCCR_NUMC6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3712 #define DSI_VCCR_NUMC7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3713 #define DSI_VCCR_NUMC8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3714 #define DSI_VCCR_NUMC9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3715 #define DSI_VCCR_NUMC10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3716 #define DSI_VCCR_NUMC11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3717 #define DSI_VCCR_NUMC12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3718
Kojto 110:165afa46840b 3719 /******************* Bit definition for DSI_VNPCR register **************/
Kojto 110:165afa46840b 3720 #define DSI_VNPCR_NPSIZE ((uint32_t)0x00001FFF) /*!< Null Packet Size */
Kojto 110:165afa46840b 3721 #define DSI_VNPCR_NPSIZE0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3722 #define DSI_VNPCR_NPSIZE1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3723 #define DSI_VNPCR_NPSIZE2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3724 #define DSI_VNPCR_NPSIZE3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3725 #define DSI_VNPCR_NPSIZE4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3726 #define DSI_VNPCR_NPSIZE5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3727 #define DSI_VNPCR_NPSIZE6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3728 #define DSI_VNPCR_NPSIZE7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3729 #define DSI_VNPCR_NPSIZE8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3730 #define DSI_VNPCR_NPSIZE9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3731 #define DSI_VNPCR_NPSIZE10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3732 #define DSI_VNPCR_NPSIZE11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3733 #define DSI_VNPCR_NPSIZE12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3734
Kojto 110:165afa46840b 3735 /******************* Bit definition for DSI_VHSACR register *************/
Kojto 110:165afa46840b 3736 #define DSI_VHSACR_HSA ((uint32_t)0x00000FFF) /*!< Horizontal Synchronism Active duration */
Kojto 110:165afa46840b 3737 #define DSI_VHSACR_HSA0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3738 #define DSI_VHSACR_HSA1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3739 #define DSI_VHSACR_HSA2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3740 #define DSI_VHSACR_HSA3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3741 #define DSI_VHSACR_HSA4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3742 #define DSI_VHSACR_HSA5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3743 #define DSI_VHSACR_HSA6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3744 #define DSI_VHSACR_HSA7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3745 #define DSI_VHSACR_HSA8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3746 #define DSI_VHSACR_HSA9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3747 #define DSI_VHSACR_HSA10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3748 #define DSI_VHSACR_HSA11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3749
Kojto 110:165afa46840b 3750 /******************* Bit definition for DSI_VHBPCR register *************/
Kojto 110:165afa46840b 3751 #define DSI_VHBPCR_HBP ((uint32_t)0x00000FFF) /*!< Horizontal Back-Porch duration */
Kojto 110:165afa46840b 3752 #define DSI_VHBPCR_HBP0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3753 #define DSI_VHBPCR_HBP1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3754 #define DSI_VHBPCR_HBP2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3755 #define DSI_VHBPCR_HBP3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3756 #define DSI_VHBPCR_HBP4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3757 #define DSI_VHBPCR_HBP5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3758 #define DSI_VHBPCR_HBP6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3759 #define DSI_VHBPCR_HBP7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3760 #define DSI_VHBPCR_HBP8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3761 #define DSI_VHBPCR_HBP9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3762 #define DSI_VHBPCR_HBP10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3763 #define DSI_VHBPCR_HBP11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3764
Kojto 110:165afa46840b 3765 /******************* Bit definition for DSI_VLCR register ***************/
Kojto 110:165afa46840b 3766 #define DSI_VLCR_HLINE ((uint32_t)0x00007FFF) /*!< Horizontal Line duration */
Kojto 110:165afa46840b 3767 #define DSI_VLCR_HLINE0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3768 #define DSI_VLCR_HLINE1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3769 #define DSI_VLCR_HLINE2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3770 #define DSI_VLCR_HLINE3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3771 #define DSI_VLCR_HLINE4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3772 #define DSI_VLCR_HLINE5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3773 #define DSI_VLCR_HLINE6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3774 #define DSI_VLCR_HLINE7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3775 #define DSI_VLCR_HLINE8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3776 #define DSI_VLCR_HLINE9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3777 #define DSI_VLCR_HLINE10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3778 #define DSI_VLCR_HLINE11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3779 #define DSI_VLCR_HLINE12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3780 #define DSI_VLCR_HLINE13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3781 #define DSI_VLCR_HLINE14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 3782
Kojto 110:165afa46840b 3783 /******************* Bit definition for DSI_VVSACR register *************/
Kojto 110:165afa46840b 3784 #define DSI_VVSACR_VSA ((uint32_t)0x000003FF) /*!< Vertical Synchronism Active duration */
Kojto 110:165afa46840b 3785 #define DSI_VVSACR_VSA0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3786 #define DSI_VVSACR_VSA1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3787 #define DSI_VVSACR_VSA2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3788 #define DSI_VVSACR_VSA3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3789 #define DSI_VVSACR_VSA4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3790 #define DSI_VVSACR_VSA5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3791 #define DSI_VVSACR_VSA6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3792 #define DSI_VVSACR_VSA7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3793 #define DSI_VVSACR_VSA8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3794 #define DSI_VVSACR_VSA9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3795
Kojto 110:165afa46840b 3796 /******************* Bit definition for DSI_VVBPCR register *************/
Kojto 110:165afa46840b 3797 #define DSI_VVBPCR_VBP ((uint32_t)0x000003FF) /*!< Vertical Back-Porch duration */
Kojto 110:165afa46840b 3798 #define DSI_VVBPCR_VBP0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3799 #define DSI_VVBPCR_VBP1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3800 #define DSI_VVBPCR_VBP2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3801 #define DSI_VVBPCR_VBP3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3802 #define DSI_VVBPCR_VBP4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3803 #define DSI_VVBPCR_VBP5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3804 #define DSI_VVBPCR_VBP6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3805 #define DSI_VVBPCR_VBP7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3806 #define DSI_VVBPCR_VBP8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3807 #define DSI_VVBPCR_VBP9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3808
Kojto 110:165afa46840b 3809 /******************* Bit definition for DSI_VVFPCR register *************/
Kojto 110:165afa46840b 3810 #define DSI_VVFPCR_VFP ((uint32_t)0x000003FF) /*!< Vertical Front-Porch duration */
Kojto 110:165afa46840b 3811 #define DSI_VVFPCR_VFP0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3812 #define DSI_VVFPCR_VFP1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3813 #define DSI_VVFPCR_VFP2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3814 #define DSI_VVFPCR_VFP3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3815 #define DSI_VVFPCR_VFP4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3816 #define DSI_VVFPCR_VFP5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3817 #define DSI_VVFPCR_VFP6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3818 #define DSI_VVFPCR_VFP7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3819 #define DSI_VVFPCR_VFP8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3820 #define DSI_VVFPCR_VFP9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3821
Kojto 110:165afa46840b 3822 /******************* Bit definition for DSI_VVACR register **************/
Kojto 110:165afa46840b 3823 #define DSI_VVACR_VA ((uint32_t)0x00003FFF) /*!< Vertical Active duration */
Kojto 110:165afa46840b 3824 #define DSI_VVACR_VA0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3825 #define DSI_VVACR_VA1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3826 #define DSI_VVACR_VA2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3827 #define DSI_VVACR_VA3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3828 #define DSI_VVACR_VA4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3829 #define DSI_VVACR_VA5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3830 #define DSI_VVACR_VA6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3831 #define DSI_VVACR_VA7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3832 #define DSI_VVACR_VA8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3833 #define DSI_VVACR_VA9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3834 #define DSI_VVACR_VA10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3835 #define DSI_VVACR_VA11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3836 #define DSI_VVACR_VA12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3837 #define DSI_VVACR_VA13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3838
Kojto 110:165afa46840b 3839 /******************* Bit definition for DSI_LCCR register ***************/
Kojto 110:165afa46840b 3840 #define DSI_LCCR_CMDSIZE ((uint32_t)0x0000FFFF) /*!< Command Size */
Kojto 110:165afa46840b 3841 #define DSI_LCCR_CMDSIZE0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3842 #define DSI_LCCR_CMDSIZE1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3843 #define DSI_LCCR_CMDSIZE2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3844 #define DSI_LCCR_CMDSIZE3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3845 #define DSI_LCCR_CMDSIZE4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3846 #define DSI_LCCR_CMDSIZE5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3847 #define DSI_LCCR_CMDSIZE6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3848 #define DSI_LCCR_CMDSIZE7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3849 #define DSI_LCCR_CMDSIZE8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3850 #define DSI_LCCR_CMDSIZE9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3851 #define DSI_LCCR_CMDSIZE10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3852 #define DSI_LCCR_CMDSIZE11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3853 #define DSI_LCCR_CMDSIZE12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3854 #define DSI_LCCR_CMDSIZE13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3855 #define DSI_LCCR_CMDSIZE14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 3856 #define DSI_LCCR_CMDSIZE15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 3857
Kojto 110:165afa46840b 3858 /******************* Bit definition for DSI_CMCR register ***************/
Kojto 110:165afa46840b 3859 #define DSI_CMCR_TEARE ((uint32_t)0x00000001) /*!< Tearing Effect Acknowledge Request Enable */
Kojto 110:165afa46840b 3860 #define DSI_CMCR_ARE ((uint32_t)0x00000002) /*!< Acknowledge Request Enable */
Kojto 110:165afa46840b 3861 #define DSI_CMCR_GSW0TX ((uint32_t)0x00000100) /*!< Generic Short Write Zero parameters Transmission */
Kojto 110:165afa46840b 3862 #define DSI_CMCR_GSW1TX ((uint32_t)0x00000200) /*!< Generic Short Write One parameters Transmission */
Kojto 110:165afa46840b 3863 #define DSI_CMCR_GSW2TX ((uint32_t)0x00000400) /*!< Generic Short Write Two parameters Transmission */
Kojto 110:165afa46840b 3864 #define DSI_CMCR_GSR0TX ((uint32_t)0x00000800) /*!< Generic Short Read Zero parameters Transmission */
Kojto 110:165afa46840b 3865 #define DSI_CMCR_GSR1TX ((uint32_t)0x00001000) /*!< Generic Short Read One parameters Transmission */
Kojto 110:165afa46840b 3866 #define DSI_CMCR_GSR2TX ((uint32_t)0x00002000) /*!< Generic Short Read Two parameters Transmission */
Kojto 110:165afa46840b 3867 #define DSI_CMCR_GLWTX ((uint32_t)0x00004000) /*!< Generic Long Write Transmission */
Kojto 110:165afa46840b 3868 #define DSI_CMCR_DSW0TX ((uint32_t)0x00010000) /*!< DCS Short Write Zero parameter Transmission */
Kojto 110:165afa46840b 3869 #define DSI_CMCR_DSW1TX ((uint32_t)0x00020000) /*!< DCS Short Read One parameter Transmission */
Kojto 110:165afa46840b 3870 #define DSI_CMCR_DSR0TX ((uint32_t)0x00040000) /*!< DCS Short Read Zero parameter Transmission */
Kojto 110:165afa46840b 3871 #define DSI_CMCR_DLWTX ((uint32_t)0x00080000) /*!< DCS Long Write Transmission */
Kojto 110:165afa46840b 3872 #define DSI_CMCR_MRDPS ((uint32_t)0x01000000) /*!< Maximum Read Packet Size */
Kojto 110:165afa46840b 3873
Kojto 110:165afa46840b 3874 /******************* Bit definition for DSI_GHCR register ***************/
Kojto 110:165afa46840b 3875 #define DSI_GHCR_DT ((uint32_t)0x0000003F) /*!< Type */
Kojto 110:165afa46840b 3876 #define DSI_GHCR_DT0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3877 #define DSI_GHCR_DT1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3878 #define DSI_GHCR_DT2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3879 #define DSI_GHCR_DT3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3880 #define DSI_GHCR_DT4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3881 #define DSI_GHCR_DT5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3882
Kojto 110:165afa46840b 3883 #define DSI_GHCR_VCID ((uint32_t)0x000000C0) /*!< Channel */
Kojto 110:165afa46840b 3884 #define DSI_GHCR_VCID0 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3885 #define DSI_GHCR_VCID1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3886
Kojto 110:165afa46840b 3887 #define DSI_GHCR_WCLSB ((uint32_t)0x0000FF00) /*!< WordCount LSB */
Kojto 110:165afa46840b 3888 #define DSI_GHCR_WCLSB0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3889 #define DSI_GHCR_WCLSB1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3890 #define DSI_GHCR_WCLSB2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3891 #define DSI_GHCR_WCLSB3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3892 #define DSI_GHCR_WCLSB4 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3893 #define DSI_GHCR_WCLSB5 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3894 #define DSI_GHCR_WCLSB6 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 3895 #define DSI_GHCR_WCLSB7 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 3896
Kojto 110:165afa46840b 3897 #define DSI_GHCR_WCMSB ((uint32_t)0x00FF0000) /*!< WordCount MSB */
Kojto 110:165afa46840b 3898 #define DSI_GHCR_WCMSB0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3899 #define DSI_GHCR_WCMSB1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 3900 #define DSI_GHCR_WCMSB2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3901 #define DSI_GHCR_WCMSB3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3902 #define DSI_GHCR_WCMSB4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3903 #define DSI_GHCR_WCMSB5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 3904 #define DSI_GHCR_WCMSB6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 3905 #define DSI_GHCR_WCMSB7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 3906
Kojto 110:165afa46840b 3907 /******************* Bit definition for DSI_GPDR register ***************/
Kojto 110:165afa46840b 3908 #define DSI_GPDR_DATA1 ((uint32_t)0x000000FF) /*!< Payload Byte 1 */
Kojto 110:165afa46840b 3909 #define DSI_GPDR_DATA1_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3910 #define DSI_GPDR_DATA1_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3911 #define DSI_GPDR_DATA1_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3912 #define DSI_GPDR_DATA1_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3913 #define DSI_GPDR_DATA1_4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3914 #define DSI_GPDR_DATA1_5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3915 #define DSI_GPDR_DATA1_6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3916 #define DSI_GPDR_DATA1_7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3917
Kojto 110:165afa46840b 3918 #define DSI_GPDR_DATA2 ((uint32_t)0x0000FF00) /*!< Payload Byte 2 */
Kojto 110:165afa46840b 3919 #define DSI_GPDR_DATA2_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3920 #define DSI_GPDR_DATA2_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3921 #define DSI_GPDR_DATA2_2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3922 #define DSI_GPDR_DATA2_3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3923 #define DSI_GPDR_DATA2_4 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3924 #define DSI_GPDR_DATA2_5 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3925 #define DSI_GPDR_DATA2_6 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 3926 #define DSI_GPDR_DATA2_7 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 3927
Kojto 110:165afa46840b 3928 #define DSI_GPDR_DATA3 ((uint32_t)0x00FF0000) /*!< Payload Byte 3 */
Kojto 110:165afa46840b 3929 #define DSI_GPDR_DATA3_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3930 #define DSI_GPDR_DATA3_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 3931 #define DSI_GPDR_DATA3_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3932 #define DSI_GPDR_DATA3_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3933 #define DSI_GPDR_DATA3_4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3934 #define DSI_GPDR_DATA3_5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 3935 #define DSI_GPDR_DATA3_6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 3936 #define DSI_GPDR_DATA3_7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 3937
Kojto 110:165afa46840b 3938 #define DSI_GPDR_DATA4 ((uint32_t)0xFF000000) /*!< Payload Byte 4 */
Kojto 110:165afa46840b 3939 #define DSI_GPDR_DATA4_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 3940 #define DSI_GPDR_DATA4_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 3941 #define DSI_GPDR_DATA4_2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 3942 #define DSI_GPDR_DATA4_3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 3943 #define DSI_GPDR_DATA4_4 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 3944 #define DSI_GPDR_DATA4_5 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 3945 #define DSI_GPDR_DATA4_6 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 3946 #define DSI_GPDR_DATA4_7 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 3947
Kojto 110:165afa46840b 3948 /******************* Bit definition for DSI_GPSR register ***************/
Kojto 110:165afa46840b 3949 #define DSI_GPSR_CMDFE ((uint32_t)0x00000001) /*!< Command FIFO Empty */
Kojto 110:165afa46840b 3950 #define DSI_GPSR_CMDFF ((uint32_t)0x00000002) /*!< Command FIFO Full */
Kojto 110:165afa46840b 3951 #define DSI_GPSR_PWRFE ((uint32_t)0x00000004) /*!< Payload Write FIFO Empty */
Kojto 110:165afa46840b 3952 #define DSI_GPSR_PWRFF ((uint32_t)0x00000008) /*!< Payload Write FIFO Full */
Kojto 110:165afa46840b 3953 #define DSI_GPSR_PRDFE ((uint32_t)0x00000010) /*!< Payload Read FIFO Empty */
Kojto 110:165afa46840b 3954 #define DSI_GPSR_PRDFF ((uint32_t)0x00000020) /*!< Payload Read FIFO Full */
Kojto 110:165afa46840b 3955 #define DSI_GPSR_RCB ((uint32_t)0x00000040) /*!< Read Command Busy */
Kojto 110:165afa46840b 3956
Kojto 110:165afa46840b 3957 /******************* Bit definition for DSI_TCCR0 register **************/
Kojto 110:165afa46840b 3958 #define DSI_TCCR0_LPRX_TOCNT ((uint32_t)0x0000FFFF) /*!< Low-power Reception Timeout Counter */
Kojto 110:165afa46840b 3959 #define DSI_TCCR0_LPRX_TOCNT0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3960 #define DSI_TCCR0_LPRX_TOCNT1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3961 #define DSI_TCCR0_LPRX_TOCNT2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3962 #define DSI_TCCR0_LPRX_TOCNT3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 3963 #define DSI_TCCR0_LPRX_TOCNT4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 3964 #define DSI_TCCR0_LPRX_TOCNT5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 3965 #define DSI_TCCR0_LPRX_TOCNT6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 3966 #define DSI_TCCR0_LPRX_TOCNT7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 3967 #define DSI_TCCR0_LPRX_TOCNT8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 3968 #define DSI_TCCR0_LPRX_TOCNT9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 3969 #define DSI_TCCR0_LPRX_TOCNT10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 3970 #define DSI_TCCR0_LPRX_TOCNT11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 3971 #define DSI_TCCR0_LPRX_TOCNT12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 3972 #define DSI_TCCR0_LPRX_TOCNT13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 3973 #define DSI_TCCR0_LPRX_TOCNT14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 3974 #define DSI_TCCR0_LPRX_TOCNT15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 3975
Kojto 110:165afa46840b 3976 #define DSI_TCCR0_HSTX_TOCNT ((uint32_t)0xFFFF0000) /*!< High-Speed Transmission Timeout Counter */
Kojto 110:165afa46840b 3977 #define DSI_TCCR0_HSTX_TOCNT0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 3978 #define DSI_TCCR0_HSTX_TOCNT1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 3979 #define DSI_TCCR0_HSTX_TOCNT2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 3980 #define DSI_TCCR0_HSTX_TOCNT3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 3981 #define DSI_TCCR0_HSTX_TOCNT4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 3982 #define DSI_TCCR0_HSTX_TOCNT5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 3983 #define DSI_TCCR0_HSTX_TOCNT6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 3984 #define DSI_TCCR0_HSTX_TOCNT7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 3985 #define DSI_TCCR0_HSTX_TOCNT8 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 3986 #define DSI_TCCR0_HSTX_TOCNT9 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 3987 #define DSI_TCCR0_HSTX_TOCNT10 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 3988 #define DSI_TCCR0_HSTX_TOCNT11 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 3989 #define DSI_TCCR0_HSTX_TOCNT12 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 3990 #define DSI_TCCR0_HSTX_TOCNT13 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 3991 #define DSI_TCCR0_HSTX_TOCNT14 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 3992 #define DSI_TCCR0_HSTX_TOCNT15 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 3993
Kojto 110:165afa46840b 3994 /******************* Bit definition for DSI_TCCR1 register **************/
Kojto 110:165afa46840b 3995 #define DSI_TCCR1_HSRD_TOCNT ((uint32_t)0x0000FFFF) /*!< High-Speed Read Timeout Counter */
Kojto 110:165afa46840b 3996 #define DSI_TCCR1_HSRD_TOCNT0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 3997 #define DSI_TCCR1_HSRD_TOCNT1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 3998 #define DSI_TCCR1_HSRD_TOCNT2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 3999 #define DSI_TCCR1_HSRD_TOCNT3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4000 #define DSI_TCCR1_HSRD_TOCNT4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4001 #define DSI_TCCR1_HSRD_TOCNT5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4002 #define DSI_TCCR1_HSRD_TOCNT6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4003 #define DSI_TCCR1_HSRD_TOCNT7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4004 #define DSI_TCCR1_HSRD_TOCNT8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4005 #define DSI_TCCR1_HSRD_TOCNT9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4006 #define DSI_TCCR1_HSRD_TOCNT10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4007 #define DSI_TCCR1_HSRD_TOCNT11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4008 #define DSI_TCCR1_HSRD_TOCNT12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4009 #define DSI_TCCR1_HSRD_TOCNT13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4010 #define DSI_TCCR1_HSRD_TOCNT14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4011 #define DSI_TCCR1_HSRD_TOCNT15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4012
Kojto 110:165afa46840b 4013 /******************* Bit definition for DSI_TCCR2 register **************/
Kojto 110:165afa46840b 4014 #define DSI_TCCR2_LPRD_TOCNT ((uint32_t)0x0000FFFF) /*!< Low-Power Read Timeout Counter */
Kojto 110:165afa46840b 4015 #define DSI_TCCR2_LPRD_TOCNT0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4016 #define DSI_TCCR2_LPRD_TOCNT1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4017 #define DSI_TCCR2_LPRD_TOCNT2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4018 #define DSI_TCCR2_LPRD_TOCNT3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4019 #define DSI_TCCR2_LPRD_TOCNT4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4020 #define DSI_TCCR2_LPRD_TOCNT5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4021 #define DSI_TCCR2_LPRD_TOCNT6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4022 #define DSI_TCCR2_LPRD_TOCNT7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4023 #define DSI_TCCR2_LPRD_TOCNT8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4024 #define DSI_TCCR2_LPRD_TOCNT9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4025 #define DSI_TCCR2_LPRD_TOCNT10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4026 #define DSI_TCCR2_LPRD_TOCNT11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4027 #define DSI_TCCR2_LPRD_TOCNT12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4028 #define DSI_TCCR2_LPRD_TOCNT13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4029 #define DSI_TCCR2_LPRD_TOCNT14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4030 #define DSI_TCCR2_LPRD_TOCNT15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4031
Kojto 110:165afa46840b 4032 /******************* Bit definition for DSI_TCCR3 register **************/
Kojto 110:165afa46840b 4033 #define DSI_TCCR3_HSWR_TOCNT ((uint32_t)0x0000FFFF) /*!< High-Speed Write Timeout Counter */
Kojto 110:165afa46840b 4034 #define DSI_TCCR3_HSWR_TOCNT0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4035 #define DSI_TCCR3_HSWR_TOCNT1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4036 #define DSI_TCCR3_HSWR_TOCNT2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4037 #define DSI_TCCR3_HSWR_TOCNT3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4038 #define DSI_TCCR3_HSWR_TOCNT4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4039 #define DSI_TCCR3_HSWR_TOCNT5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4040 #define DSI_TCCR3_HSWR_TOCNT6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4041 #define DSI_TCCR3_HSWR_TOCNT7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4042 #define DSI_TCCR3_HSWR_TOCNT8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4043 #define DSI_TCCR3_HSWR_TOCNT9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4044 #define DSI_TCCR3_HSWR_TOCNT10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4045 #define DSI_TCCR3_HSWR_TOCNT11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4046 #define DSI_TCCR3_HSWR_TOCNT12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4047 #define DSI_TCCR3_HSWR_TOCNT13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4048 #define DSI_TCCR3_HSWR_TOCNT14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4049 #define DSI_TCCR3_HSWR_TOCNT15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4050
Kojto 110:165afa46840b 4051 #define DSI_TCCR3_PM ((uint32_t)0x01000000) /*!< Presp Mode */
Kojto 110:165afa46840b 4052
Kojto 110:165afa46840b 4053 /******************* Bit definition for DSI_TCCR4 register **************/
Kojto 110:165afa46840b 4054 #define DSI_TCCR4_LPWR_TOCNT ((uint32_t)0x0000FFFF) /*!< Low-Power Write Timeout Counter */
Kojto 110:165afa46840b 4055 #define DSI_TCCR4_LPWR_TOCNT0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4056 #define DSI_TCCR4_LPWR_TOCNT1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4057 #define DSI_TCCR4_LPWR_TOCNT2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4058 #define DSI_TCCR4_LPWR_TOCNT3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4059 #define DSI_TCCR4_LPWR_TOCNT4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4060 #define DSI_TCCR4_LPWR_TOCNT5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4061 #define DSI_TCCR4_LPWR_TOCNT6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4062 #define DSI_TCCR4_LPWR_TOCNT7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4063 #define DSI_TCCR4_LPWR_TOCNT8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4064 #define DSI_TCCR4_LPWR_TOCNT9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4065 #define DSI_TCCR4_LPWR_TOCNT10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4066 #define DSI_TCCR4_LPWR_TOCNT11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4067 #define DSI_TCCR4_LPWR_TOCNT12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4068 #define DSI_TCCR4_LPWR_TOCNT13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4069 #define DSI_TCCR4_LPWR_TOCNT14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4070 #define DSI_TCCR4_LPWR_TOCNT15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4071
Kojto 110:165afa46840b 4072 /******************* Bit definition for DSI_TCCR5 register **************/
Kojto 110:165afa46840b 4073 #define DSI_TCCR5_BTA_TOCNT ((uint32_t)0x0000FFFF) /*!< Bus-Turn-Around Timeout Counter */
Kojto 110:165afa46840b 4074 #define DSI_TCCR5_BTA_TOCNT0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4075 #define DSI_TCCR5_BTA_TOCNT1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4076 #define DSI_TCCR5_BTA_TOCNT2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4077 #define DSI_TCCR5_BTA_TOCNT3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4078 #define DSI_TCCR5_BTA_TOCNT4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4079 #define DSI_TCCR5_BTA_TOCNT5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4080 #define DSI_TCCR5_BTA_TOCNT6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4081 #define DSI_TCCR5_BTA_TOCNT7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4082 #define DSI_TCCR5_BTA_TOCNT8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4083 #define DSI_TCCR5_BTA_TOCNT9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4084 #define DSI_TCCR5_BTA_TOCNT10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4085 #define DSI_TCCR5_BTA_TOCNT11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4086 #define DSI_TCCR5_BTA_TOCNT12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4087 #define DSI_TCCR5_BTA_TOCNT13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4088 #define DSI_TCCR5_BTA_TOCNT14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4089 #define DSI_TCCR5_BTA_TOCNT15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4090
Kojto 110:165afa46840b 4091 /******************* Bit definition for DSI_TDCR register ***************/
Kojto 110:165afa46840b 4092 #define DSI_TDCR_3DM ((uint32_t)0x00000003) /*!< 3D Mode */
Kojto 110:165afa46840b 4093 #define DSI_TDCR_3DM0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4094 #define DSI_TDCR_3DM1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4095
Kojto 110:165afa46840b 4096 #define DSI_TDCR_3DF ((uint32_t)0x0000000C) /*!< 3D Format */
Kojto 110:165afa46840b 4097 #define DSI_TDCR_3DF0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4098 #define DSI_TDCR_3DF1 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4099
Kojto 110:165afa46840b 4100 #define DSI_TDCR_SVS ((uint32_t)0x00000010) /*!< Second VSYNC */
Kojto 110:165afa46840b 4101 #define DSI_TDCR_RF ((uint32_t)0x00000020) /*!< Right First */
Kojto 110:165afa46840b 4102 #define DSI_TDCR_S3DC ((uint32_t)0x00010000) /*!< Send 3D Control */
Kojto 110:165afa46840b 4103
Kojto 110:165afa46840b 4104 /******************* Bit definition for DSI_CLCR register ***************/
Kojto 110:165afa46840b 4105 #define DSI_CLCR_DPCC ((uint32_t)0x00000001) /*!< D-PHY Clock Control */
Kojto 110:165afa46840b 4106 #define DSI_CLCR_ACR ((uint32_t)0x00000002) /*!< Automatic Clocklane Control */
Kojto 110:165afa46840b 4107
Kojto 110:165afa46840b 4108 /******************* Bit definition for DSI_CLTCR register **************/
Kojto 110:165afa46840b 4109 #define DSI_CLTCR_LP2HS_TIME ((uint32_t)0x000003FF) /*!< Low-Power to High-Speed Time */
Kojto 110:165afa46840b 4110 #define DSI_CLTCR_LP2HS_TIME0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4111 #define DSI_CLTCR_LP2HS_TIME1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4112 #define DSI_CLTCR_LP2HS_TIME2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4113 #define DSI_CLTCR_LP2HS_TIME3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4114 #define DSI_CLTCR_LP2HS_TIME4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4115 #define DSI_CLTCR_LP2HS_TIME5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4116 #define DSI_CLTCR_LP2HS_TIME6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4117 #define DSI_CLTCR_LP2HS_TIME7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4118 #define DSI_CLTCR_LP2HS_TIME8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4119 #define DSI_CLTCR_LP2HS_TIME9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4120
Kojto 110:165afa46840b 4121 #define DSI_CLTCR_HS2LP_TIME ((uint32_t)0x03FF0000) /*!< High-Speed to Low-Power Time */
Kojto 110:165afa46840b 4122 #define DSI_CLTCR_HS2LP_TIME0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 4123 #define DSI_CLTCR_HS2LP_TIME1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 4124 #define DSI_CLTCR_HS2LP_TIME2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 4125 #define DSI_CLTCR_HS2LP_TIME3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 4126 #define DSI_CLTCR_HS2LP_TIME4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 4127 #define DSI_CLTCR_HS2LP_TIME5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 4128 #define DSI_CLTCR_HS2LP_TIME6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 4129 #define DSI_CLTCR_HS2LP_TIME7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 4130 #define DSI_CLTCR_HS2LP_TIME8 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 4131 #define DSI_CLTCR_HS2LP_TIME9 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 4132
Kojto 110:165afa46840b 4133 /******************* Bit definition for DSI_DLTCR register **************/
Kojto 110:165afa46840b 4134 #define DSI_DLTCR_MRD_TIME ((uint32_t)0x00007FFF) /*!< Maximum Read Time */
Kojto 110:165afa46840b 4135 #define DSI_DLTCR_MRD_TIME0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4136 #define DSI_DLTCR_MRD_TIME1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4137 #define DSI_DLTCR_MRD_TIME2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4138 #define DSI_DLTCR_MRD_TIME3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4139 #define DSI_DLTCR_MRD_TIME4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4140 #define DSI_DLTCR_MRD_TIME5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4141 #define DSI_DLTCR_MRD_TIME6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4142 #define DSI_DLTCR_MRD_TIME7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4143 #define DSI_DLTCR_MRD_TIME8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4144 #define DSI_DLTCR_MRD_TIME9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4145 #define DSI_DLTCR_MRD_TIME10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4146 #define DSI_DLTCR_MRD_TIME11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4147 #define DSI_DLTCR_MRD_TIME12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4148 #define DSI_DLTCR_MRD_TIME13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4149 #define DSI_DLTCR_MRD_TIME14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4150
Kojto 110:165afa46840b 4151 #define DSI_DLTCR_LP2HS_TIME ((uint32_t)0x00FF0000) /*!< Low-Power To High-Speed Time */
Kojto 110:165afa46840b 4152 #define DSI_DLTCR_LP2HS_TIME0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 4153 #define DSI_DLTCR_LP2HS_TIME1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 4154 #define DSI_DLTCR_LP2HS_TIME2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 4155 #define DSI_DLTCR_LP2HS_TIME3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 4156 #define DSI_DLTCR_LP2HS_TIME4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 4157 #define DSI_DLTCR_LP2HS_TIME5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 4158 #define DSI_DLTCR_LP2HS_TIME6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 4159 #define DSI_DLTCR_LP2HS_TIME7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 4160
Kojto 110:165afa46840b 4161 #define DSI_DLTCR_HS2LP_TIME ((uint32_t)0xFF000000) /*!< High-Speed To Low-Power Time */
Kojto 110:165afa46840b 4162 #define DSI_DLTCR_HS2LP_TIME0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 4163 #define DSI_DLTCR_HS2LP_TIME1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 4164 #define DSI_DLTCR_HS2LP_TIME2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 4165 #define DSI_DLTCR_HS2LP_TIME3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 4166 #define DSI_DLTCR_HS2LP_TIME4 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 4167 #define DSI_DLTCR_HS2LP_TIME5 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 4168 #define DSI_DLTCR_HS2LP_TIME6 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 4169 #define DSI_DLTCR_HS2LP_TIME7 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 4170
Kojto 110:165afa46840b 4171 /******************* Bit definition for DSI_PCTLR register **************/
Kojto 110:165afa46840b 4172 #define DSI_PCTLR_DEN ((uint32_t)0x00000002) /*!< Digital Enable */
Kojto 110:165afa46840b 4173 #define DSI_PCTLR_CKE ((uint32_t)0x00000004) /*!< Clock Enable */
Kojto 110:165afa46840b 4174
Kojto 110:165afa46840b 4175 /******************* Bit definition for DSI_PCONFR register *************/
Kojto 110:165afa46840b 4176 #define DSI_PCONFR_NL ((uint32_t)0x00000003) /*!< Number of Lanes */
Kojto 110:165afa46840b 4177 #define DSI_PCONFR_NL0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4178 #define DSI_PCONFR_NL1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4179
Kojto 110:165afa46840b 4180 #define DSI_PCONFR_SW_TIME ((uint32_t)0x0000FF00) /*!< Stop Wait Time */
Kojto 110:165afa46840b 4181 #define DSI_PCONFR_SW_TIME0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4182 #define DSI_PCONFR_SW_TIME1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4183 #define DSI_PCONFR_SW_TIME2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4184 #define DSI_PCONFR_SW_TIME3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4185 #define DSI_PCONFR_SW_TIME4 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4186 #define DSI_PCONFR_SW_TIME5 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4187 #define DSI_PCONFR_SW_TIME6 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4188 #define DSI_PCONFR_SW_TIME7 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4189
Kojto 110:165afa46840b 4190 /******************* Bit definition for DSI_PUCR register ***************/
Kojto 110:165afa46840b 4191 #define DSI_PUCR_URCL ((uint32_t)0x00000001) /*!< ULPS Request on Clock Lane */
Kojto 110:165afa46840b 4192 #define DSI_PUCR_UECL ((uint32_t)0x00000002) /*!< ULPS Exit on Clock Lane */
Kojto 110:165afa46840b 4193 #define DSI_PUCR_URDL ((uint32_t)0x00000004) /*!< ULPS Request on Data Lane */
Kojto 110:165afa46840b 4194 #define DSI_PUCR_UEDL ((uint32_t)0x00000008) /*!< ULPS Exit on Data Lane */
Kojto 110:165afa46840b 4195
Kojto 110:165afa46840b 4196 /******************* Bit definition for DSI_PTTCR register **************/
Kojto 110:165afa46840b 4197 #define DSI_PTTCR_TX_TRIG ((uint32_t)0x0000000F) /*!< Transmission Trigger */
Kojto 110:165afa46840b 4198 #define DSI_PTTCR_TX_TRIG0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4199 #define DSI_PTTCR_TX_TRIG1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4200 #define DSI_PTTCR_TX_TRIG2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4201 #define DSI_PTTCR_TX_TRIG3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4202
Kojto 110:165afa46840b 4203 /******************* Bit definition for DSI_PSR register ****************/
Kojto 110:165afa46840b 4204 #define DSI_PSR_PD ((uint32_t)0x00000002) /*!< PHY Direction */
Kojto 110:165afa46840b 4205 #define DSI_PSR_PSSC ((uint32_t)0x00000004) /*!< PHY Stop State Clock lane */
Kojto 110:165afa46840b 4206 #define DSI_PSR_UANC ((uint32_t)0x00000008) /*!< ULPS Active Not Clock lane */
Kojto 110:165afa46840b 4207 #define DSI_PSR_PSS0 ((uint32_t)0x00000010) /*!< PHY Stop State lane 0 */
Kojto 110:165afa46840b 4208 #define DSI_PSR_UAN0 ((uint32_t)0x00000020) /*!< ULPS Active Not lane 0 */
Kojto 110:165afa46840b 4209 #define DSI_PSR_RUE0 ((uint32_t)0x00000040) /*!< RX ULPS Escape lane 0 */
Kojto 110:165afa46840b 4210 #define DSI_PSR_PSS1 ((uint32_t)0x00000080) /*!< PHY Stop State lane 1 */
Kojto 110:165afa46840b 4211 #define DSI_PSR_UAN1 ((uint32_t)0x00000100) /*!< ULPS Active Not lane 1 */
Kojto 110:165afa46840b 4212
Kojto 110:165afa46840b 4213 /******************* Bit definition for DSI_ISR0 register ***************/
Kojto 110:165afa46840b 4214 #define DSI_ISR0_AE0 ((uint32_t)0x00000001) /*!< Acknowledge Error 0 */
Kojto 110:165afa46840b 4215 #define DSI_ISR0_AE1 ((uint32_t)0x00000002) /*!< Acknowledge Error 1 */
Kojto 110:165afa46840b 4216 #define DSI_ISR0_AE2 ((uint32_t)0x00000004) /*!< Acknowledge Error 2 */
Kojto 110:165afa46840b 4217 #define DSI_ISR0_AE3 ((uint32_t)0x00000008) /*!< Acknowledge Error 3 */
Kojto 110:165afa46840b 4218 #define DSI_ISR0_AE4 ((uint32_t)0x00000010) /*!< Acknowledge Error 4 */
Kojto 110:165afa46840b 4219 #define DSI_ISR0_AE5 ((uint32_t)0x00000020) /*!< Acknowledge Error 5 */
Kojto 110:165afa46840b 4220 #define DSI_ISR0_AE6 ((uint32_t)0x00000040) /*!< Acknowledge Error 6 */
Kojto 110:165afa46840b 4221 #define DSI_ISR0_AE7 ((uint32_t)0x00000080) /*!< Acknowledge Error 7 */
Kojto 110:165afa46840b 4222 #define DSI_ISR0_AE8 ((uint32_t)0x00000100) /*!< Acknowledge Error 8 */
Kojto 110:165afa46840b 4223 #define DSI_ISR0_AE9 ((uint32_t)0x00000200) /*!< Acknowledge Error 9 */
Kojto 110:165afa46840b 4224 #define DSI_ISR0_AE10 ((uint32_t)0x00000400) /*!< Acknowledge Error 10 */
Kojto 110:165afa46840b 4225 #define DSI_ISR0_AE11 ((uint32_t)0x00000800) /*!< Acknowledge Error 11 */
Kojto 110:165afa46840b 4226 #define DSI_ISR0_AE12 ((uint32_t)0x00001000) /*!< Acknowledge Error 12 */
Kojto 110:165afa46840b 4227 #define DSI_ISR0_AE13 ((uint32_t)0x00002000) /*!< Acknowledge Error 13 */
Kojto 110:165afa46840b 4228 #define DSI_ISR0_AE14 ((uint32_t)0x00004000) /*!< Acknowledge Error 14 */
Kojto 110:165afa46840b 4229 #define DSI_ISR0_AE15 ((uint32_t)0x00008000) /*!< Acknowledge Error 15 */
Kojto 110:165afa46840b 4230 #define DSI_ISR0_PE0 ((uint32_t)0x00010000) /*!< PHY Error 0 */
Kojto 110:165afa46840b 4231 #define DSI_ISR0_PE1 ((uint32_t)0x00020000) /*!< PHY Error 1 */
Kojto 110:165afa46840b 4232 #define DSI_ISR0_PE2 ((uint32_t)0x00040000) /*!< PHY Error 2 */
Kojto 110:165afa46840b 4233 #define DSI_ISR0_PE3 ((uint32_t)0x00080000) /*!< PHY Error 3 */
Kojto 110:165afa46840b 4234 #define DSI_ISR0_PE4 ((uint32_t)0x00100000) /*!< PHY Error 4 */
Kojto 110:165afa46840b 4235
Kojto 110:165afa46840b 4236 /******************* Bit definition for DSI_ISR1 register ***************/
Kojto 110:165afa46840b 4237 #define DSI_ISR1_TOHSTX ((uint32_t)0x00000001) /*!< Timeout High-Speed Transmission */
Kojto 110:165afa46840b 4238 #define DSI_ISR1_TOLPRX ((uint32_t)0x00000002) /*!< Timeout Low-Power Reception */
Kojto 110:165afa46840b 4239 #define DSI_ISR1_ECCSE ((uint32_t)0x00000004) /*!< ECC Single-bit Error */
Kojto 110:165afa46840b 4240 #define DSI_ISR1_ECCME ((uint32_t)0x00000008) /*!< ECC Multi-bit Error */
Kojto 110:165afa46840b 4241 #define DSI_ISR1_CRCE ((uint32_t)0x00000010) /*!< CRC Error */
Kojto 110:165afa46840b 4242 #define DSI_ISR1_PSE ((uint32_t)0x00000020) /*!< Packet Size Error */
Kojto 110:165afa46840b 4243 #define DSI_ISR1_EOTPE ((uint32_t)0x00000040) /*!< EoTp Error */
Kojto 110:165afa46840b 4244 #define DSI_ISR1_LPWRE ((uint32_t)0x00000080) /*!< LTDC Payload Write Error */
Kojto 110:165afa46840b 4245 #define DSI_ISR1_GCWRE ((uint32_t)0x00000100) /*!< Generic Command Write Error */
Kojto 110:165afa46840b 4246 #define DSI_ISR1_GPWRE ((uint32_t)0x00000200) /*!< Generic Payload Write Error */
Kojto 110:165afa46840b 4247 #define DSI_ISR1_GPTXE ((uint32_t)0x00000400) /*!< Generic Payload Transmit Error */
Kojto 110:165afa46840b 4248 #define DSI_ISR1_GPRDE ((uint32_t)0x00000800) /*!< Generic Payload Read Error */
Kojto 110:165afa46840b 4249 #define DSI_ISR1_GPRXE ((uint32_t)0x00001000) /*!< Generic Payload Receive Error */
Kojto 110:165afa46840b 4250
Kojto 110:165afa46840b 4251 /******************* Bit definition for DSI_IER0 register ***************/
Kojto 110:165afa46840b 4252 #define DSI_IER0_AE0IE ((uint32_t)0x00000001) /*!< Acknowledge Error 0 Interrupt Enable */
Kojto 110:165afa46840b 4253 #define DSI_IER0_AE1IE ((uint32_t)0x00000002) /*!< Acknowledge Error 1 Interrupt Enable */
Kojto 110:165afa46840b 4254 #define DSI_IER0_AE2IE ((uint32_t)0x00000004) /*!< Acknowledge Error 2 Interrupt Enable */
Kojto 110:165afa46840b 4255 #define DSI_IER0_AE3IE ((uint32_t)0x00000008) /*!< Acknowledge Error 3 Interrupt Enable */
Kojto 110:165afa46840b 4256 #define DSI_IER0_AE4IE ((uint32_t)0x00000010) /*!< Acknowledge Error 4 Interrupt Enable */
Kojto 110:165afa46840b 4257 #define DSI_IER0_AE5IE ((uint32_t)0x00000020) /*!< Acknowledge Error 5 Interrupt Enable */
Kojto 110:165afa46840b 4258 #define DSI_IER0_AE6IE ((uint32_t)0x00000040) /*!< Acknowledge Error 6 Interrupt Enable */
Kojto 110:165afa46840b 4259 #define DSI_IER0_AE7IE ((uint32_t)0x00000080) /*!< Acknowledge Error 7 Interrupt Enable */
Kojto 110:165afa46840b 4260 #define DSI_IER0_AE8IE ((uint32_t)0x00000100) /*!< Acknowledge Error 8 Interrupt Enable */
Kojto 110:165afa46840b 4261 #define DSI_IER0_AE9IE ((uint32_t)0x00000200) /*!< Acknowledge Error 9 Interrupt Enable */
Kojto 110:165afa46840b 4262 #define DSI_IER0_AE10IE ((uint32_t)0x00000400) /*!< Acknowledge Error 10 Interrupt Enable */
Kojto 110:165afa46840b 4263 #define DSI_IER0_AE11IE ((uint32_t)0x00000800) /*!< Acknowledge Error 11 Interrupt Enable */
Kojto 110:165afa46840b 4264 #define DSI_IER0_AE12IE ((uint32_t)0x00001000) /*!< Acknowledge Error 12 Interrupt Enable */
Kojto 110:165afa46840b 4265 #define DSI_IER0_AE13IE ((uint32_t)0x00002000) /*!< Acknowledge Error 13 Interrupt Enable */
Kojto 110:165afa46840b 4266 #define DSI_IER0_AE14IE ((uint32_t)0x00004000) /*!< Acknowledge Error 14 Interrupt Enable */
Kojto 110:165afa46840b 4267 #define DSI_IER0_AE15IE ((uint32_t)0x00008000) /*!< Acknowledge Error 15 Interrupt Enable */
Kojto 110:165afa46840b 4268 #define DSI_IER0_PE0IE ((uint32_t)0x00010000) /*!< PHY Error 0 Interrupt Enable */
Kojto 110:165afa46840b 4269 #define DSI_IER0_PE1IE ((uint32_t)0x00020000) /*!< PHY Error 1 Interrupt Enable */
Kojto 110:165afa46840b 4270 #define DSI_IER0_PE2IE ((uint32_t)0x00040000) /*!< PHY Error 2 Interrupt Enable */
Kojto 110:165afa46840b 4271 #define DSI_IER0_PE3IE ((uint32_t)0x00080000) /*!< PHY Error 3 Interrupt Enable */
Kojto 110:165afa46840b 4272 #define DSI_IER0_PE4IE ((uint32_t)0x00100000) /*!< PHY Error 4 Interrupt Enable */
Kojto 110:165afa46840b 4273
Kojto 110:165afa46840b 4274 /******************* Bit definition for DSI_IER1 register ***************/
Kojto 110:165afa46840b 4275 #define DSI_IER1_TOHSTXIE ((uint32_t)0x00000001) /*!< Timeout High-Speed Transmission Interrupt Enable */
Kojto 110:165afa46840b 4276 #define DSI_IER1_TOLPRXIE ((uint32_t)0x00000002) /*!< Timeout Low-Power Reception Interrupt Enable */
Kojto 110:165afa46840b 4277 #define DSI_IER1_ECCSEIE ((uint32_t)0x00000004) /*!< ECC Single-bit Error Interrupt Enable */
Kojto 110:165afa46840b 4278 #define DSI_IER1_ECCMEIE ((uint32_t)0x00000008) /*!< ECC Multi-bit Error Interrupt Enable */
Kojto 110:165afa46840b 4279 #define DSI_IER1_CRCEIE ((uint32_t)0x00000010) /*!< CRC Error Interrupt Enable */
Kojto 110:165afa46840b 4280 #define DSI_IER1_PSEIE ((uint32_t)0x00000020) /*!< Packet Size Error Interrupt Enable */
Kojto 110:165afa46840b 4281 #define DSI_IER1_EOTPEIE ((uint32_t)0x00000040) /*!< EoTp Error Interrupt Enable */
Kojto 110:165afa46840b 4282 #define DSI_IER1_LPWREIE ((uint32_t)0x00000080) /*!< LTDC Payload Write Error Interrupt Enable */
Kojto 110:165afa46840b 4283 #define DSI_IER1_GCWREIE ((uint32_t)0x00000100) /*!< Generic Command Write Error Interrupt Enable */
Kojto 110:165afa46840b 4284 #define DSI_IER1_GPWREIE ((uint32_t)0x00000200) /*!< Generic Payload Write Error Interrupt Enable */
Kojto 110:165afa46840b 4285 #define DSI_IER1_GPTXEIE ((uint32_t)0x00000400) /*!< Generic Payload Transmit Error Interrupt Enable */
Kojto 110:165afa46840b 4286 #define DSI_IER1_GPRDEIE ((uint32_t)0x00000800) /*!< Generic Payload Read Error Interrupt Enable */
Kojto 110:165afa46840b 4287 #define DSI_IER1_GPRXEIE ((uint32_t)0x00001000) /*!< Generic Payload Receive Error Interrupt Enable */
Kojto 110:165afa46840b 4288
Kojto 110:165afa46840b 4289 /******************* Bit definition for DSI_FIR0 register ***************/
Kojto 110:165afa46840b 4290 #define DSI_FIR0_FAE0 ((uint32_t)0x00000001) /*!< Force Acknowledge Error 0 */
Kojto 110:165afa46840b 4291 #define DSI_FIR0_FAE1 ((uint32_t)0x00000002) /*!< Force Acknowledge Error 1 */
Kojto 110:165afa46840b 4292 #define DSI_FIR0_FAE2 ((uint32_t)0x00000004) /*!< Force Acknowledge Error 2 */
Kojto 110:165afa46840b 4293 #define DSI_FIR0_FAE3 ((uint32_t)0x00000008) /*!< Force Acknowledge Error 3 */
Kojto 110:165afa46840b 4294 #define DSI_FIR0_FAE4 ((uint32_t)0x00000010) /*!< Force Acknowledge Error 4 */
Kojto 110:165afa46840b 4295 #define DSI_FIR0_FAE5 ((uint32_t)0x00000020) /*!< Force Acknowledge Error 5 */
Kojto 110:165afa46840b 4296 #define DSI_FIR0_FAE6 ((uint32_t)0x00000040) /*!< Force Acknowledge Error 6 */
Kojto 110:165afa46840b 4297 #define DSI_FIR0_FAE7 ((uint32_t)0x00000080) /*!< Force Acknowledge Error 7 */
Kojto 110:165afa46840b 4298 #define DSI_FIR0_FAE8 ((uint32_t)0x00000100) /*!< Force Acknowledge Error 8 */
Kojto 110:165afa46840b 4299 #define DSI_FIR0_FAE9 ((uint32_t)0x00000200) /*!< Force Acknowledge Error 9 */
Kojto 110:165afa46840b 4300 #define DSI_FIR0_FAE10 ((uint32_t)0x00000400) /*!< Force Acknowledge Error 10 */
Kojto 110:165afa46840b 4301 #define DSI_FIR0_FAE11 ((uint32_t)0x00000800) /*!< Force Acknowledge Error 11 */
Kojto 110:165afa46840b 4302 #define DSI_FIR0_FAE12 ((uint32_t)0x00001000) /*!< Force Acknowledge Error 12 */
Kojto 110:165afa46840b 4303 #define DSI_FIR0_FAE13 ((uint32_t)0x00002000) /*!< Force Acknowledge Error 13 */
Kojto 110:165afa46840b 4304 #define DSI_FIR0_FAE14 ((uint32_t)0x00004000) /*!< Force Acknowledge Error 14 */
Kojto 110:165afa46840b 4305 #define DSI_FIR0_FAE15 ((uint32_t)0x00008000) /*!< Force Acknowledge Error 15 */
Kojto 110:165afa46840b 4306 #define DSI_FIR0_FPE0 ((uint32_t)0x00010000) /*!< Force PHY Error 0 */
Kojto 110:165afa46840b 4307 #define DSI_FIR0_FPE1 ((uint32_t)0x00020000) /*!< Force PHY Error 1 */
Kojto 110:165afa46840b 4308 #define DSI_FIR0_FPE2 ((uint32_t)0x00040000) /*!< Force PHY Error 2 */
Kojto 110:165afa46840b 4309 #define DSI_FIR0_FPE3 ((uint32_t)0x00080000) /*!< Force PHY Error 3 */
Kojto 110:165afa46840b 4310 #define DSI_FIR0_FPE4 ((uint32_t)0x00100000) /*!< Force PHY Error 4 */
Kojto 110:165afa46840b 4311
Kojto 110:165afa46840b 4312 /******************* Bit definition for DSI_FIR1 register ***************/
Kojto 110:165afa46840b 4313 #define DSI_FIR1_FTOHSTX ((uint32_t)0x00000001) /*!< Force Timeout High-Speed Transmission */
Kojto 110:165afa46840b 4314 #define DSI_FIR1_FTOLPRX ((uint32_t)0x00000002) /*!< Force Timeout Low-Power Reception */
Kojto 110:165afa46840b 4315 #define DSI_FIR1_FECCSE ((uint32_t)0x00000004) /*!< Force ECC Single-bit Error */
Kojto 110:165afa46840b 4316 #define DSI_FIR1_FECCME ((uint32_t)0x00000008) /*!< Force ECC Multi-bit Error */
Kojto 110:165afa46840b 4317 #define DSI_FIR1_FCRCE ((uint32_t)0x00000010) /*!< Force CRC Error */
Kojto 110:165afa46840b 4318 #define DSI_FIR1_FPSE ((uint32_t)0x00000020) /*!< Force Packet Size Error */
Kojto 110:165afa46840b 4319 #define DSI_FIR1_FEOTPE ((uint32_t)0x00000040) /*!< Force EoTp Error */
Kojto 110:165afa46840b 4320 #define DSI_FIR1_FLPWRE ((uint32_t)0x00000080) /*!< Force LTDC Payload Write Error */
Kojto 110:165afa46840b 4321 #define DSI_FIR1_FGCWRE ((uint32_t)0x00000100) /*!< Force Generic Command Write Error */
Kojto 110:165afa46840b 4322 #define DSI_FIR1_FGPWRE ((uint32_t)0x00000200) /*!< Force Generic Payload Write Error */
Kojto 110:165afa46840b 4323 #define DSI_FIR1_FGPTXE ((uint32_t)0x00000400) /*!< Force Generic Payload Transmit Error */
Kojto 110:165afa46840b 4324 #define DSI_FIR1_FGPRDE ((uint32_t)0x00000800) /*!< Force Generic Payload Read Error */
Kojto 110:165afa46840b 4325 #define DSI_FIR1_FGPRXE ((uint32_t)0x00001000) /*!< Force Generic Payload Receive Error */
Kojto 110:165afa46840b 4326
Kojto 110:165afa46840b 4327 /******************* Bit definition for DSI_VSCR register ***************/
Kojto 110:165afa46840b 4328 #define DSI_VSCR_EN ((uint32_t)0x00000001) /*!< Enable */
Kojto 110:165afa46840b 4329 #define DSI_VSCR_UR ((uint32_t)0x00000100) /*!< Update Register */
Kojto 110:165afa46840b 4330
Kojto 110:165afa46840b 4331 /******************* Bit definition for DSI_LCVCIDR register ************/
Kojto 110:165afa46840b 4332 #define DSI_LCVCIDR_VCID ((uint32_t)0x00000003) /*!< Virtual Channel ID */
Kojto 110:165afa46840b 4333 #define DSI_LCVCIDR_VCID0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4334 #define DSI_LCVCIDR_VCID1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4335
Kojto 110:165afa46840b 4336 /******************* Bit definition for DSI_LCCCR register **************/
Kojto 110:165afa46840b 4337 #define DSI_LCCCR_COLC ((uint32_t)0x0000000F) /*!< Color Coding */
Kojto 110:165afa46840b 4338 #define DSI_LCCCR_COLC0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4339 #define DSI_LCCCR_COLC1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4340 #define DSI_LCCCR_COLC2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4341 #define DSI_LCCCR_COLC3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4342
Kojto 110:165afa46840b 4343 #define DSI_LCCCR_LPE ((uint32_t)0x00000100) /*!< Loosely Packed Enable */
Kojto 110:165afa46840b 4344
Kojto 110:165afa46840b 4345 /******************* Bit definition for DSI_LPMCCR register *************/
Kojto 110:165afa46840b 4346 #define DSI_LPMCCR_VLPSIZE ((uint32_t)0x000000FF) /*!< VACT Largest Packet Size */
Kojto 110:165afa46840b 4347 #define DSI_LPMCCR_VLPSIZE0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4348 #define DSI_LPMCCR_VLPSIZE1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4349 #define DSI_LPMCCR_VLPSIZE2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4350 #define DSI_LPMCCR_VLPSIZE3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4351 #define DSI_LPMCCR_VLPSIZE4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4352 #define DSI_LPMCCR_VLPSIZE5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4353 #define DSI_LPMCCR_VLPSIZE6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4354 #define DSI_LPMCCR_VLPSIZE7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4355
Kojto 110:165afa46840b 4356 #define DSI_LPMCCR_LPSIZE ((uint32_t)0x00FF0000) /*!< Largest Packet Size */
Kojto 110:165afa46840b 4357 #define DSI_LPMCCR_LPSIZE0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 4358 #define DSI_LPMCCR_LPSIZE1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 4359 #define DSI_LPMCCR_LPSIZE2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 4360 #define DSI_LPMCCR_LPSIZE3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 4361 #define DSI_LPMCCR_LPSIZE4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 4362 #define DSI_LPMCCR_LPSIZE5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 4363 #define DSI_LPMCCR_LPSIZE6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 4364 #define DSI_LPMCCR_LPSIZE7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 4365
Kojto 110:165afa46840b 4366 /******************* Bit definition for DSI_VMCCR register **************/
Kojto 110:165afa46840b 4367 #define DSI_VMCCR_VMT ((uint32_t)0x00000003) /*!< Video Mode Type */
Kojto 110:165afa46840b 4368 #define DSI_VMCCR_VMT0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4369 #define DSI_VMCCR_VMT1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4370
Kojto 110:165afa46840b 4371 #define DSI_VMCCR_LPVSAE ((uint32_t)0x00000100) /*!< Low-power Vertical Sync time Enable */
Kojto 110:165afa46840b 4372 #define DSI_VMCCR_LPVBPE ((uint32_t)0x00000200) /*!< Low-power Vertical Back-porch Enable */
Kojto 110:165afa46840b 4373 #define DSI_VMCCR_LPVFPE ((uint32_t)0x00000400) /*!< Low-power Vertical Front-porch Enable */
Kojto 110:165afa46840b 4374 #define DSI_VMCCR_LPVAE ((uint32_t)0x00000800) /*!< Low-power Vertical Active Enable */
Kojto 110:165afa46840b 4375 #define DSI_VMCCR_LPHBPE ((uint32_t)0x00001000) /*!< Low-power Horizontal Back-porch Enable */
Kojto 110:165afa46840b 4376 #define DSI_VMCCR_LPHFE ((uint32_t)0x00002000) /*!< Low-power Horizontal Front-porch Enable */
Kojto 110:165afa46840b 4377 #define DSI_VMCCR_FBTAAE ((uint32_t)0x00004000) /*!< Frame BTA Acknowledge Enable */
Kojto 110:165afa46840b 4378 #define DSI_VMCCR_LPCE ((uint32_t)0x00008000) /*!< Low-power Command Enable */
Kojto 110:165afa46840b 4379
Kojto 110:165afa46840b 4380 /******************* Bit definition for DSI_VPCCR register **************/
Kojto 110:165afa46840b 4381 #define DSI_VPCCR_VPSIZE ((uint32_t)0x00003FFF) /*!< Video Packet Size */
Kojto 110:165afa46840b 4382 #define DSI_VPCCR_VPSIZE0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4383 #define DSI_VPCCR_VPSIZE1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4384 #define DSI_VPCCR_VPSIZE2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4385 #define DSI_VPCCR_VPSIZE3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4386 #define DSI_VPCCR_VPSIZE4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4387 #define DSI_VPCCR_VPSIZE5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4388 #define DSI_VPCCR_VPSIZE6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4389 #define DSI_VPCCR_VPSIZE7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4390 #define DSI_VPCCR_VPSIZE8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4391 #define DSI_VPCCR_VPSIZE9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4392 #define DSI_VPCCR_VPSIZE10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4393 #define DSI_VPCCR_VPSIZE11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4394 #define DSI_VPCCR_VPSIZE12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4395 #define DSI_VPCCR_VPSIZE13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4396
Kojto 110:165afa46840b 4397 /******************* Bit definition for DSI_VCCCR register **************/
Kojto 110:165afa46840b 4398 #define DSI_VCCCR_NUMC ((uint32_t)0x00001FFF) /*!< Number of Chunks */
Kojto 110:165afa46840b 4399 #define DSI_VCCCR_NUMC0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4400 #define DSI_VCCCR_NUMC1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4401 #define DSI_VCCCR_NUMC2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4402 #define DSI_VCCCR_NUMC3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4403 #define DSI_VCCCR_NUMC4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4404 #define DSI_VCCCR_NUMC5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4405 #define DSI_VCCCR_NUMC6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4406 #define DSI_VCCCR_NUMC7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4407 #define DSI_VCCCR_NUMC8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4408 #define DSI_VCCCR_NUMC9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4409 #define DSI_VCCCR_NUMC10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4410 #define DSI_VCCCR_NUMC11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4411 #define DSI_VCCCR_NUMC12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4412
Kojto 110:165afa46840b 4413 /******************* Bit definition for DSI_VNPCCR register *************/
Kojto 110:165afa46840b 4414 #define DSI_VNPCCR_NPSIZE ((uint32_t)0x00001FFF) /*!< Number of Chunks */
Kojto 110:165afa46840b 4415 #define DSI_VNPCCR_NPSIZE0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4416 #define DSI_VNPCCR_NPSIZE1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4417 #define DSI_VNPCCR_NPSIZE2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4418 #define DSI_VNPCCR_NPSIZE3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4419 #define DSI_VNPCCR_NPSIZE4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4420 #define DSI_VNPCCR_NPSIZE5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4421 #define DSI_VNPCCR_NPSIZE6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4422 #define DSI_VNPCCR_NPSIZE7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4423 #define DSI_VNPCCR_NPSIZE8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4424 #define DSI_VNPCCR_NPSIZE9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4425 #define DSI_VNPCCR_NPSIZE10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4426 #define DSI_VNPCCR_NPSIZE11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4427 #define DSI_VNPCCR_NPSIZE12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4428
Kojto 110:165afa46840b 4429 /******************* Bit definition for DSI_VHSACCR register ************/
Kojto 110:165afa46840b 4430 #define DSI_VHSACCR_HSA ((uint32_t)0x00000FFF) /*!< Horizontal Synchronism Active duration */
Kojto 110:165afa46840b 4431 #define DSI_VHSACCR_HSA0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4432 #define DSI_VHSACCR_HSA1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4433 #define DSI_VHSACCR_HSA2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4434 #define DSI_VHSACCR_HSA3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4435 #define DSI_VHSACCR_HSA4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4436 #define DSI_VHSACCR_HSA5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4437 #define DSI_VHSACCR_HSA6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4438 #define DSI_VHSACCR_HSA7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4439 #define DSI_VHSACCR_HSA8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4440 #define DSI_VHSACCR_HSA9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4441 #define DSI_VHSACCR_HSA10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4442 #define DSI_VHSACCR_HSA11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4443
Kojto 110:165afa46840b 4444 /******************* Bit definition for DSI_VHBPCCR register ************/
Kojto 110:165afa46840b 4445 #define DSI_VHBPCCR_HBP ((uint32_t)0x00000FFF) /*!< Horizontal Back-Porch duration */
Kojto 110:165afa46840b 4446 #define DSI_VHBPCCR_HBP0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4447 #define DSI_VHBPCCR_HBP1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4448 #define DSI_VHBPCCR_HBP2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4449 #define DSI_VHBPCCR_HBP3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4450 #define DSI_VHBPCCR_HBP4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4451 #define DSI_VHBPCCR_HBP5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4452 #define DSI_VHBPCCR_HBP6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4453 #define DSI_VHBPCCR_HBP7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4454 #define DSI_VHBPCCR_HBP8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4455 #define DSI_VHBPCCR_HBP9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4456 #define DSI_VHBPCCR_HBP10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4457 #define DSI_VHBPCCR_HBP11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4458
Kojto 110:165afa46840b 4459 /******************* Bit definition for DSI_VLCCR register **************/
Kojto 110:165afa46840b 4460 #define DSI_VLCCR_HLINE ((uint32_t)0x00007FFF) /*!< Horizontal Line duration */
Kojto 110:165afa46840b 4461 #define DSI_VLCCR_HLINE0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4462 #define DSI_VLCCR_HLINE1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4463 #define DSI_VLCCR_HLINE2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4464 #define DSI_VLCCR_HLINE3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4465 #define DSI_VLCCR_HLINE4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4466 #define DSI_VLCCR_HLINE5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4467 #define DSI_VLCCR_HLINE6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4468 #define DSI_VLCCR_HLINE7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4469 #define DSI_VLCCR_HLINE8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4470 #define DSI_VLCCR_HLINE9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4471 #define DSI_VLCCR_HLINE10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4472 #define DSI_VLCCR_HLINE11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4473 #define DSI_VLCCR_HLINE12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4474 #define DSI_VLCCR_HLINE13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4475 #define DSI_VLCCR_HLINE14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4476
Kojto 110:165afa46840b 4477 /******************* Bit definition for DSI_VVSACCR register ***************/
Kojto 110:165afa46840b 4478 #define DSI_VVSACCR_VSA ((uint32_t)0x000003FF) /*!< Vertical Synchronism Active duration */
Kojto 110:165afa46840b 4479 #define DSI_VVSACCR_VSA0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4480 #define DSI_VVSACCR_VSA1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4481 #define DSI_VVSACCR_VSA2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4482 #define DSI_VVSACCR_VSA3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4483 #define DSI_VVSACCR_VSA4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4484 #define DSI_VVSACCR_VSA5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4485 #define DSI_VVSACCR_VSA6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4486 #define DSI_VVSACCR_VSA7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4487 #define DSI_VVSACCR_VSA8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4488 #define DSI_VVSACCR_VSA9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4489
Kojto 110:165afa46840b 4490 /******************* Bit definition for DSI_VVBPCCR register ************/
Kojto 110:165afa46840b 4491 #define DSI_VVBPCCR_VBP ((uint32_t)0x000003FF) /*!< Vertical Back-Porch duration */
Kojto 110:165afa46840b 4492 #define DSI_VVBPCCR_VBP0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4493 #define DSI_VVBPCCR_VBP1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4494 #define DSI_VVBPCCR_VBP2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4495 #define DSI_VVBPCCR_VBP3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4496 #define DSI_VVBPCCR_VBP4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4497 #define DSI_VVBPCCR_VBP5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4498 #define DSI_VVBPCCR_VBP6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4499 #define DSI_VVBPCCR_VBP7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4500 #define DSI_VVBPCCR_VBP8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4501 #define DSI_VVBPCCR_VBP9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4502
Kojto 110:165afa46840b 4503 /******************* Bit definition for DSI_VVFPCCR register ************/
Kojto 110:165afa46840b 4504 #define DSI_VVFPCCR_VFP ((uint32_t)0x000003FF) /*!< Vertical Front-Porch duration */
Kojto 110:165afa46840b 4505 #define DSI_VVFPCCR_VFP0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4506 #define DSI_VVFPCCR_VFP1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4507 #define DSI_VVFPCCR_VFP2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4508 #define DSI_VVFPCCR_VFP3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4509 #define DSI_VVFPCCR_VFP4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4510 #define DSI_VVFPCCR_VFP5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4511 #define DSI_VVFPCCR_VFP6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4512 #define DSI_VVFPCCR_VFP7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4513 #define DSI_VVFPCCR_VFP8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4514 #define DSI_VVFPCCR_VFP9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4515
Kojto 110:165afa46840b 4516 /******************* Bit definition for DSI_VVACCR register *************/
Kojto 110:165afa46840b 4517 #define DSI_VVACCR_VA ((uint32_t)0x00003FFF) /*!< Vertical Active duration */
Kojto 110:165afa46840b 4518 #define DSI_VVACCR_VA0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4519 #define DSI_VVACCR_VA1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4520 #define DSI_VVACCR_VA2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4521 #define DSI_VVACCR_VA3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4522 #define DSI_VVACCR_VA4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4523 #define DSI_VVACCR_VA5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4524 #define DSI_VVACCR_VA6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4525 #define DSI_VVACCR_VA7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4526 #define DSI_VVACCR_VA8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4527 #define DSI_VVACCR_VA9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4528 #define DSI_VVACCR_VA10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4529 #define DSI_VVACCR_VA11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4530 #define DSI_VVACCR_VA12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4531 #define DSI_VVACCR_VA13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4532
Kojto 110:165afa46840b 4533 /******************* Bit definition for DSI_TDCCR register **************/
Kojto 110:165afa46840b 4534 #define DSI_TDCCR_3DM ((uint32_t)0x00000003) /*!< 3D Mode */
Kojto 110:165afa46840b 4535 #define DSI_TDCCR_3DM0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4536 #define DSI_TDCCR_3DM1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4537
Kojto 110:165afa46840b 4538 #define DSI_TDCCR_3DF ((uint32_t)0x0000000C) /*!< 3D Format */
Kojto 110:165afa46840b 4539 #define DSI_TDCCR_3DF0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4540 #define DSI_TDCCR_3DF1 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4541
Kojto 110:165afa46840b 4542 #define DSI_TDCCR_SVS ((uint32_t)0x00000010) /*!< Second VSYNC */
Kojto 110:165afa46840b 4543 #define DSI_TDCCR_RF ((uint32_t)0x00000020) /*!< Right First */
Kojto 110:165afa46840b 4544 #define DSI_TDCCR_S3DC ((uint32_t)0x00010000) /*!< Send 3D Control */
Kojto 110:165afa46840b 4545
Kojto 110:165afa46840b 4546 /******************* Bit definition for DSI_WCFGR register ***************/
Kojto 110:165afa46840b 4547 #define DSI_WCFGR_DSIM ((uint32_t)0x00000001) /*!< DSI Mode */
Kojto 110:165afa46840b 4548 #define DSI_WCFGR_COLMUX ((uint32_t)0x0000000E) /*!< Color Multiplexing */
Kojto 110:165afa46840b 4549 #define DSI_WCFGR_COLMUX0 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4550 #define DSI_WCFGR_COLMUX1 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4551 #define DSI_WCFGR_COLMUX2 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4552
Kojto 110:165afa46840b 4553 #define DSI_WCFGR_TESRC ((uint32_t)0x00000010) /*!< Tearing Effect Source */
Kojto 110:165afa46840b 4554 #define DSI_WCFGR_TEPOL ((uint32_t)0x00000020) /*!< Tearing Effect Polarity */
Kojto 110:165afa46840b 4555 #define DSI_WCFGR_AR ((uint32_t)0x00000040) /*!< Automatic Refresh */
Kojto 110:165afa46840b 4556 #define DSI_WCFGR_VSPOL ((uint32_t)0x00000080) /*!< VSync Polarity */
Kojto 110:165afa46840b 4557
Kojto 110:165afa46840b 4558 /******************* Bit definition for DSI_WCR register *****************/
Kojto 110:165afa46840b 4559 #define DSI_WCR_COLM ((uint32_t)0x00000001) /*!< Color Mode */
Kojto 110:165afa46840b 4560 #define DSI_WCR_SHTDN ((uint32_t)0x00000002) /*!< Shutdown */
Kojto 110:165afa46840b 4561 #define DSI_WCR_LTDCEN ((uint32_t)0x00000004) /*!< LTDC Enable */
Kojto 110:165afa46840b 4562 #define DSI_WCR_DSIEN ((uint32_t)0x00000008) /*!< DSI Enable */
Kojto 110:165afa46840b 4563
Kojto 110:165afa46840b 4564 /******************* Bit definition for DSI_WIER register ****************/
Kojto 110:165afa46840b 4565 #define DSI_WIER_TEIE ((uint32_t)0x00000001) /*!< Tearing Effect Interrupt Enable */
Kojto 110:165afa46840b 4566 #define DSI_WIER_ERIE ((uint32_t)0x00000002) /*!< End of Refresh Interrupt Enable */
Kojto 110:165afa46840b 4567 #define DSI_WIER_PLLLIE ((uint32_t)0x00000200) /*!< PLL Lock Interrupt Enable */
Kojto 110:165afa46840b 4568 #define DSI_WIER_PLLUIE ((uint32_t)0x00000400) /*!< PLL Unlock Interrupt Enable */
Kojto 110:165afa46840b 4569 #define DSI_WIER_RRIE ((uint32_t)0x00002000) /*!< Regulator Ready Interrupt Enable */
Kojto 110:165afa46840b 4570
Kojto 110:165afa46840b 4571 /******************* Bit definition for DSI_WISR register ****************/
Kojto 110:165afa46840b 4572 #define DSI_WISR_TEIF ((uint32_t)0x00000001) /*!< Tearing Effect Interrupt Flag */
Kojto 110:165afa46840b 4573 #define DSI_WISR_ERIF ((uint32_t)0x00000002) /*!< End of Refresh Interrupt Flag */
Kojto 110:165afa46840b 4574 #define DSI_WISR_BUSY ((uint32_t)0x00000004) /*!< Busy Flag */
Kojto 110:165afa46840b 4575 #define DSI_WISR_PLLLS ((uint32_t)0x00000100) /*!< PLL Lock Status */
Kojto 110:165afa46840b 4576 #define DSI_WISR_PLLLIF ((uint32_t)0x00000200) /*!< PLL Lock Interrupt Flag */
Kojto 110:165afa46840b 4577 #define DSI_WISR_PLLUIF ((uint32_t)0x00000400) /*!< PLL Unlock Interrupt Flag */
Kojto 110:165afa46840b 4578 #define DSI_WISR_RRS ((uint32_t)0x00001000) /*!< Regulator Ready Flag */
Kojto 110:165afa46840b 4579 #define DSI_WISR_RRIF ((uint32_t)0x00002000) /*!< Regulator Ready Interrupt Flag */
Kojto 110:165afa46840b 4580
Kojto 110:165afa46840b 4581 /******************* Bit definition for DSI_WIFCR register ***************/
Kojto 110:165afa46840b 4582 #define DSI_WIFCR_CTEIF ((uint32_t)0x00000001) /*!< Clear Tearing Effect Interrupt Flag */
Kojto 110:165afa46840b 4583 #define DSI_WIFCR_CERIF ((uint32_t)0x00000002) /*!< Clear End of Refresh Interrupt Flag */
Kojto 110:165afa46840b 4584 #define DSI_WIFCR_CPLLLIF ((uint32_t)0x00000200) /*!< Clear PLL Lock Interrupt Flag */
Kojto 110:165afa46840b 4585 #define DSI_WIFCR_CPLLUIF ((uint32_t)0x00000400) /*!< Clear PLL Unlock Interrupt Flag */
Kojto 110:165afa46840b 4586 #define DSI_WIFCR_CRRIF ((uint32_t)0x00002000) /*!< Clear Regulator Ready Interrupt Flag */
Kojto 110:165afa46840b 4587
Kojto 110:165afa46840b 4588 /******************* Bit definition for DSI_WPCR0 register ***************/
Kojto 110:165afa46840b 4589 #define DSI_WPCR0_UIX4 ((uint32_t)0x0000003F) /*!< Unit Interval multiplied by 4 */
Kojto 110:165afa46840b 4590 #define DSI_WPCR0_UIX4_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4591 #define DSI_WPCR0_UIX4_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4592 #define DSI_WPCR0_UIX4_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4593 #define DSI_WPCR0_UIX4_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4594 #define DSI_WPCR0_UIX4_4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4595 #define DSI_WPCR0_UIX4_5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4596
Kojto 110:165afa46840b 4597 #define DSI_WPCR0_SWCL ((uint32_t)0x00000040) /*!< Swap pins on clock lane */
Kojto 110:165afa46840b 4598 #define DSI_WPCR0_SWDL0 ((uint32_t)0x00000080) /*!< Swap pins on data lane 1 */
Kojto 110:165afa46840b 4599 #define DSI_WPCR0_SWDL1 ((uint32_t)0x00000100) /*!< Swap pins on data lane 2 */
Kojto 110:165afa46840b 4600 #define DSI_WPCR0_HSICL ((uint32_t)0x00000200) /*!< Invert the high-speed data signal on clock lane */
Kojto 110:165afa46840b 4601 #define DSI_WPCR0_HSIDL0 ((uint32_t)0x00000400) /*!< Invert the high-speed data signal on lane 1 */
Kojto 110:165afa46840b 4602 #define DSI_WPCR0_HSIDL1 ((uint32_t)0x00000800) /*!< Invert the high-speed data signal on lane 2 */
Kojto 110:165afa46840b 4603 #define DSI_WPCR0_FTXSMCL ((uint32_t)0x00001000) /*!< Force clock lane in TX stop mode */
Kojto 110:165afa46840b 4604 #define DSI_WPCR0_FTXSMDL ((uint32_t)0x00002000) /*!< Force data lanes in TX stop mode */
Kojto 110:165afa46840b 4605 #define DSI_WPCR0_CDOFFDL ((uint32_t)0x00004000) /*!< Contention detection OFF */
Kojto 110:165afa46840b 4606 #define DSI_WPCR0_TDDL ((uint32_t)0x00010000) /*!< Turn Disable Data Lanes */
Kojto 110:165afa46840b 4607 #define DSI_WPCR0_PDEN ((uint32_t)0x00040000) /*!< Pull-Down Enable */
Kojto 110:165afa46840b 4608 #define DSI_WPCR0_TCLKPREPEN ((uint32_t)0x00080000) /*!< Timer for t-CLKPREP Enable */
Kojto 110:165afa46840b 4609 #define DSI_WPCR0_TCLKZEROEN ((uint32_t)0x00100000) /*!< Timer for t-CLKZERO Enable */
Kojto 110:165afa46840b 4610 #define DSI_WPCR0_THSPREPEN ((uint32_t)0x00200000) /*!< Timer for t-HSPREP Enable */
Kojto 110:165afa46840b 4611 #define DSI_WPCR0_THSTRAILEN ((uint32_t)0x00400000) /*!< Timer for t-HSTRAIL Enable */
Kojto 110:165afa46840b 4612 #define DSI_WPCR0_THSZEROEN ((uint32_t)0x00800000) /*!< Timer for t-HSZERO Enable */
Kojto 110:165afa46840b 4613 #define DSI_WPCR0_TLPXDEN ((uint32_t)0x01000000) /*!< Timer for t-LPXD Enable */
Kojto 110:165afa46840b 4614 #define DSI_WPCR0_THSEXITEN ((uint32_t)0x02000000) /*!< Timer for t-HSEXIT Enable */
Kojto 110:165afa46840b 4615 #define DSI_WPCR0_TLPXCEN ((uint32_t)0x04000000) /*!< Timer for t-LPXC Enable */
Kojto 110:165afa46840b 4616 #define DSI_WPCR0_TCLKPOSTEN ((uint32_t)0x08000000) /*!< Timer for t-CLKPOST Enable */
Kojto 110:165afa46840b 4617
Kojto 110:165afa46840b 4618 /******************* Bit definition for DSI_WPCR1 register ***************/
Kojto 110:165afa46840b 4619 #define DSI_WPCR1_HSTXDCL ((uint32_t)0x00000003) /*!< High-Speed Transmission Delay on Clock Lane */
Kojto 110:165afa46840b 4620 #define DSI_WPCR1_HSTXDCL0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4621 #define DSI_WPCR1_HSTXDCL1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4622
Kojto 110:165afa46840b 4623 #define DSI_WPCR1_HSTXDDL ((uint32_t)0x0000000C) /*!< High-Speed Transmission Delay on Data Lane */
Kojto 110:165afa46840b 4624 #define DSI_WPCR1_HSTXDDL0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4625 #define DSI_WPCR1_HSTXDDL1 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4626
Kojto 110:165afa46840b 4627 #define DSI_WPCR1_LPSRCCL ((uint32_t)0x000000C0) /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
Kojto 110:165afa46840b 4628 #define DSI_WPCR1_LPSRCCL0 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4629 #define DSI_WPCR1_LPSRCCL1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4630
Kojto 110:165afa46840b 4631 #define DSI_WPCR1_LPSRCDL ((uint32_t)0x00000300) /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
Kojto 110:165afa46840b 4632 #define DSI_WPCR1_LPSRCDL0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4633 #define DSI_WPCR1_LPSRCDL1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4634
Kojto 110:165afa46840b 4635 #define DSI_WPCR1_SDDC ((uint32_t)0x00001000) /*!< SDD Control */
Kojto 110:165afa46840b 4636
Kojto 110:165afa46840b 4637 #define DSI_WPCR1_LPRXVCDL ((uint32_t)0x0000C000) /*!< Low-Power Reception V-IL Compensation on Data Lanes */
Kojto 110:165afa46840b 4638 #define DSI_WPCR1_LPRXVCDL0 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4639 #define DSI_WPCR1_LPRXVCDL1 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4640
Kojto 110:165afa46840b 4641 #define DSI_WPCR1_HSTXSRCCL ((uint32_t)0x00030000) /*!< High-Speed Transmission Delay on Clock Lane */
Kojto 110:165afa46840b 4642 #define DSI_WPCR1_HSTXSRCCL0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 4643 #define DSI_WPCR1_HSTXSRCCL1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 4644
Kojto 110:165afa46840b 4645 #define DSI_WPCR1_HSTXSRCDL ((uint32_t)0x000C0000) /*!< High-Speed Transmission Delay on Data Lane */
Kojto 110:165afa46840b 4646 #define DSI_WPCR1_HSTXSRCDL0 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 4647 #define DSI_WPCR1_HSTXSRCDL1 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 4648
Kojto 110:165afa46840b 4649 #define DSI_WPCR1_FLPRXLPM ((uint32_t)0x00400000) /*!< Forces LP Receiver in Low-Power Mode */
Kojto 110:165afa46840b 4650
Kojto 110:165afa46840b 4651 #define DSI_WPCR1_LPRXFT ((uint32_t)0x06000000) /*!< Low-Power RX low-pass Filtering Tuning */
Kojto 110:165afa46840b 4652 #define DSI_WPCR1_LPRXFT0 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 4653 #define DSI_WPCR1_LPRXFT1 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 4654
Kojto 110:165afa46840b 4655 /******************* Bit definition for DSI_WPCR2 register ***************/
Kojto 110:165afa46840b 4656 #define DSI_WPCR2_TCLKPREP ((uint32_t)0x000000FF) /*!< t-CLKPREP */
Kojto 110:165afa46840b 4657 #define DSI_WPCR2_TCLKPREP0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4658 #define DSI_WPCR2_TCLKPREP1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4659 #define DSI_WPCR2_TCLKPREP2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4660 #define DSI_WPCR2_TCLKPREP3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4661 #define DSI_WPCR2_TCLKPREP4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4662 #define DSI_WPCR2_TCLKPREP5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4663 #define DSI_WPCR2_TCLKPREP6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4664 #define DSI_WPCR2_TCLKPREP7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4665
Kojto 110:165afa46840b 4666 #define DSI_WPCR2_TCLKZERO ((uint32_t)0x0000FF00) /*!< t-CLKZERO */
Kojto 110:165afa46840b 4667 #define DSI_WPCR2_TCLKZERO0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4668 #define DSI_WPCR2_TCLKZERO1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4669 #define DSI_WPCR2_TCLKZERO2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4670 #define DSI_WPCR2_TCLKZERO3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4671 #define DSI_WPCR2_TCLKZERO4 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4672 #define DSI_WPCR2_TCLKZERO5 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4673 #define DSI_WPCR2_TCLKZERO6 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4674 #define DSI_WPCR2_TCLKZERO7 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4675
Kojto 110:165afa46840b 4676 #define DSI_WPCR2_THSPREP ((uint32_t)0x00FF0000) /*!< t-HSPREP */
Kojto 110:165afa46840b 4677 #define DSI_WPCR2_THSPREP0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 4678 #define DSI_WPCR2_THSPREP1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 4679 #define DSI_WPCR2_THSPREP2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 4680 #define DSI_WPCR2_THSPREP3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 4681 #define DSI_WPCR2_THSPREP4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 4682 #define DSI_WPCR2_THSPREP5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 4683 #define DSI_WPCR2_THSPREP6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 4684 #define DSI_WPCR2_THSPREP7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 4685
Kojto 110:165afa46840b 4686 #define DSI_WPCR2_THSTRAIL ((uint32_t)0xFF000000) /*!< t-HSTRAIL */
Kojto 110:165afa46840b 4687 #define DSI_WPCR2_THSTRAIL0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 4688 #define DSI_WPCR2_THSTRAIL1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 4689 #define DSI_WPCR2_THSTRAIL2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 4690 #define DSI_WPCR2_THSTRAIL3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 4691 #define DSI_WPCR2_THSTRAIL4 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 4692 #define DSI_WPCR2_THSTRAIL5 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 4693 #define DSI_WPCR2_THSTRAIL6 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 4694 #define DSI_WPCR2_THSTRAIL7 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 4695
Kojto 110:165afa46840b 4696 /******************* Bit definition for DSI_WPCR3 register ***************/
Kojto 110:165afa46840b 4697 #define DSI_WPCR3_THSZERO ((uint32_t)0x000000FF) /*!< t-HSZERO */
Kojto 110:165afa46840b 4698 #define DSI_WPCR3_THSZERO0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4699 #define DSI_WPCR3_THSZERO1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4700 #define DSI_WPCR3_THSZERO2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4701 #define DSI_WPCR3_THSZERO3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4702 #define DSI_WPCR3_THSZERO4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4703 #define DSI_WPCR3_THSZERO5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4704 #define DSI_WPCR3_THSZERO6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4705 #define DSI_WPCR3_THSZERO7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4706
Kojto 110:165afa46840b 4707 #define DSI_WPCR3_TLPXD ((uint32_t)0x0000FF00) /*!< t-LPXD */
Kojto 110:165afa46840b 4708 #define DSI_WPCR3_TLPXD0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4709 #define DSI_WPCR3_TLPXD1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4710 #define DSI_WPCR3_TLPXD2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4711 #define DSI_WPCR3_TLPXD3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4712 #define DSI_WPCR3_TLPXD4 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4713 #define DSI_WPCR3_TLPXD5 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4714 #define DSI_WPCR3_TLPXD6 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4715 #define DSI_WPCR3_TLPXD7 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4716
Kojto 110:165afa46840b 4717 #define DSI_WPCR3_THSEXIT ((uint32_t)0x00FF0000) /*!< t-HSEXIT */
Kojto 110:165afa46840b 4718 #define DSI_WPCR3_THSEXIT0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 4719 #define DSI_WPCR3_THSEXIT1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 4720 #define DSI_WPCR3_THSEXIT2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 4721 #define DSI_WPCR3_THSEXIT3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 4722 #define DSI_WPCR3_THSEXIT4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 4723 #define DSI_WPCR3_THSEXIT5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 4724 #define DSI_WPCR3_THSEXIT6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 4725 #define DSI_WPCR3_THSEXIT7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 4726
Kojto 110:165afa46840b 4727 #define DSI_WPCR3_TLPXC ((uint32_t)0xFF000000) /*!< t-LPXC */
Kojto 110:165afa46840b 4728 #define DSI_WPCR3_TLPXC0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 4729 #define DSI_WPCR3_TLPXC1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 4730 #define DSI_WPCR3_TLPXC2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 4731 #define DSI_WPCR3_TLPXC3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 4732 #define DSI_WPCR3_TLPXC4 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 4733 #define DSI_WPCR3_TLPXC5 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 4734 #define DSI_WPCR3_TLPXC6 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 4735 #define DSI_WPCR3_TLPXC7 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 4736
Kojto 110:165afa46840b 4737 /******************* Bit definition for DSI_WPCR4 register ***************/
Kojto 110:165afa46840b 4738 #define DSI_WPCR4_TCLKPOST ((uint32_t)0x000000FF) /*!< t-CLKPOST */
Kojto 110:165afa46840b 4739 #define DSI_WPCR4_TCLKPOST0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4740 #define DSI_WPCR4_TCLKPOST1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4741 #define DSI_WPCR4_TCLKPOST2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4742 #define DSI_WPCR4_TCLKPOST3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4743 #define DSI_WPCR4_TCLKPOST4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4744 #define DSI_WPCR4_TCLKPOST5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4745 #define DSI_WPCR4_TCLKPOST6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4746 #define DSI_WPCR4_TCLKPOST7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4747
Kojto 110:165afa46840b 4748 /******************* Bit definition for DSI_WRPCR register ***************/
Kojto 110:165afa46840b 4749 #define DSI_WRPCR_PLLEN ((uint32_t)0x00000001) /*!< PLL Enable */
Kojto 110:165afa46840b 4750 #define DSI_WRPCR_PLL_NDIV ((uint32_t)0x000001FC) /*!< PLL Loop Division Factor */
Kojto 110:165afa46840b 4751 #define DSI_WRPCR_PLL_NDIV0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4752 #define DSI_WRPCR_PLL_NDIV1 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4753 #define DSI_WRPCR_PLL_NDIV2 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4754 #define DSI_WRPCR_PLL_NDIV3 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4755 #define DSI_WRPCR_PLL_NDIV4 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4756 #define DSI_WRPCR_PLL_NDIV5 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4757 #define DSI_WRPCR_PLL_NDIV6 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4758
Kojto 110:165afa46840b 4759 #define DSI_WRPCR_PLL_IDF ((uint32_t)0x00007800) /*!< PLL Input Division Factor */
Kojto 110:165afa46840b 4760 #define DSI_WRPCR_PLL_IDF0 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4761 #define DSI_WRPCR_PLL_IDF1 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4762 #define DSI_WRPCR_PLL_IDF2 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 4763 #define DSI_WRPCR_PLL_IDF3 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 4764
Kojto 110:165afa46840b 4765 #define DSI_WRPCR_PLL_ODF ((uint32_t)0x00030000) /*!< PLL Output Division Factor */
Kojto 110:165afa46840b 4766 #define DSI_WRPCR_PLL_ODF0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 4767 #define DSI_WRPCR_PLL_ODF1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 4768
Kojto 110:165afa46840b 4769 #define DSI_WRPCR_REGEN ((uint32_t)0x01000000) /*!< Regulator Enable */
Kojto 110:165afa46840b 4770
Kojto 110:165afa46840b 4771 /******************************************************************************/
Kojto 110:165afa46840b 4772 /* */
Kojto 110:165afa46840b 4773 /* External Interrupt/Event Controller */
Kojto 110:165afa46840b 4774 /* */
Kojto 110:165afa46840b 4775 /******************************************************************************/
Kojto 110:165afa46840b 4776 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 110:165afa46840b 4777 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 110:165afa46840b 4778 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 110:165afa46840b 4779 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 110:165afa46840b 4780 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 110:165afa46840b 4781 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 110:165afa46840b 4782 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 110:165afa46840b 4783 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 110:165afa46840b 4784 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 110:165afa46840b 4785 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 110:165afa46840b 4786 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 110:165afa46840b 4787 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 110:165afa46840b 4788 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 110:165afa46840b 4789 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 110:165afa46840b 4790 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 110:165afa46840b 4791 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 110:165afa46840b 4792 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 110:165afa46840b 4793 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 110:165afa46840b 4794 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 110:165afa46840b 4795 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
Kojto 110:165afa46840b 4796 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 110:165afa46840b 4797 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
Kojto 110:165afa46840b 4798 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Kojto 110:165afa46840b 4799 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Kojto 110:165afa46840b 4800
Kojto 110:165afa46840b 4801 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 110:165afa46840b 4802 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 110:165afa46840b 4803 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 110:165afa46840b 4804 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 110:165afa46840b 4805 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 110:165afa46840b 4806 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 110:165afa46840b 4807 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 110:165afa46840b 4808 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 110:165afa46840b 4809 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 110:165afa46840b 4810 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 110:165afa46840b 4811 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 110:165afa46840b 4812 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 110:165afa46840b 4813 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 110:165afa46840b 4814 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 110:165afa46840b 4815 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 110:165afa46840b 4816 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 110:165afa46840b 4817 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 110:165afa46840b 4818 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 110:165afa46840b 4819 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 110:165afa46840b 4820 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
Kojto 110:165afa46840b 4821 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 110:165afa46840b 4822 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
Kojto 110:165afa46840b 4823 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Kojto 110:165afa46840b 4824 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Kojto 110:165afa46840b 4825
Kojto 110:165afa46840b 4826 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 110:165afa46840b 4827 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 110:165afa46840b 4828 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 110:165afa46840b 4829 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 110:165afa46840b 4830 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 110:165afa46840b 4831 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 110:165afa46840b 4832 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 110:165afa46840b 4833 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 110:165afa46840b 4834 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 110:165afa46840b 4835 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 110:165afa46840b 4836 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 110:165afa46840b 4837 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 110:165afa46840b 4838 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 110:165afa46840b 4839 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 110:165afa46840b 4840 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 110:165afa46840b 4841 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 110:165afa46840b 4842 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 110:165afa46840b 4843 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 110:165afa46840b 4844 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 110:165afa46840b 4845 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
Kojto 110:165afa46840b 4846 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 110:165afa46840b 4847 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
Kojto 110:165afa46840b 4848 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
Kojto 110:165afa46840b 4849 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
Kojto 110:165afa46840b 4850
Kojto 110:165afa46840b 4851 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 110:165afa46840b 4852 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 110:165afa46840b 4853 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 110:165afa46840b 4854 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 110:165afa46840b 4855 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 110:165afa46840b 4856 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 110:165afa46840b 4857 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 110:165afa46840b 4858 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 110:165afa46840b 4859 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 110:165afa46840b 4860 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 110:165afa46840b 4861 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 110:165afa46840b 4862 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 110:165afa46840b 4863 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 110:165afa46840b 4864 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 110:165afa46840b 4865 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 110:165afa46840b 4866 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 110:165afa46840b 4867 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 110:165afa46840b 4868 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 110:165afa46840b 4869 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 110:165afa46840b 4870 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
Kojto 110:165afa46840b 4871 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 110:165afa46840b 4872 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
Kojto 110:165afa46840b 4873 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
Kojto 110:165afa46840b 4874 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
Kojto 110:165afa46840b 4875
Kojto 110:165afa46840b 4876 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 110:165afa46840b 4877 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 110:165afa46840b 4878 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 110:165afa46840b 4879 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 110:165afa46840b 4880 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 110:165afa46840b 4881 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 110:165afa46840b 4882 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 110:165afa46840b 4883 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 110:165afa46840b 4884 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 110:165afa46840b 4885 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 110:165afa46840b 4886 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 110:165afa46840b 4887 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 110:165afa46840b 4888 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 110:165afa46840b 4889 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 110:165afa46840b 4890 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 110:165afa46840b 4891 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 110:165afa46840b 4892 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 110:165afa46840b 4893 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 110:165afa46840b 4894 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 110:165afa46840b 4895 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
Kojto 110:165afa46840b 4896 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 110:165afa46840b 4897 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
Kojto 110:165afa46840b 4898 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
Kojto 110:165afa46840b 4899 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
Kojto 110:165afa46840b 4900
Kojto 110:165afa46840b 4901 /******************* Bit definition for EXTI_PR register ********************/
Kojto 110:165afa46840b 4902 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
Kojto 110:165afa46840b 4903 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
Kojto 110:165afa46840b 4904 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
Kojto 110:165afa46840b 4905 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
Kojto 110:165afa46840b 4906 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
Kojto 110:165afa46840b 4907 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
Kojto 110:165afa46840b 4908 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
Kojto 110:165afa46840b 4909 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
Kojto 110:165afa46840b 4910 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
Kojto 110:165afa46840b 4911 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
Kojto 110:165afa46840b 4912 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
Kojto 110:165afa46840b 4913 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
Kojto 110:165afa46840b 4914 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
Kojto 110:165afa46840b 4915 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
Kojto 110:165afa46840b 4916 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
Kojto 110:165afa46840b 4917 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
Kojto 110:165afa46840b 4918 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
Kojto 110:165afa46840b 4919 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
Kojto 110:165afa46840b 4920 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
Kojto 110:165afa46840b 4921 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
Kojto 110:165afa46840b 4922 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
Kojto 110:165afa46840b 4923 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
Kojto 110:165afa46840b 4924 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
Kojto 110:165afa46840b 4925
Kojto 110:165afa46840b 4926 /******************************************************************************/
Kojto 110:165afa46840b 4927 /* */
Kojto 110:165afa46840b 4928 /* FLASH */
Kojto 110:165afa46840b 4929 /* */
Kojto 110:165afa46840b 4930 /******************************************************************************/
Kojto 110:165afa46840b 4931 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 110:165afa46840b 4932 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
Kojto 110:165afa46840b 4933 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
Kojto 110:165afa46840b 4934 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4935 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4936 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
Kojto 110:165afa46840b 4937 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4938 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
Kojto 110:165afa46840b 4939 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
Kojto 110:165afa46840b 4940 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
Kojto 110:165afa46840b 4941 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4942 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
Kojto 110:165afa46840b 4943 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
Kojto 110:165afa46840b 4944 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
Kojto 110:165afa46840b 4945 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
Kojto 110:165afa46840b 4946 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
Kojto 110:165afa46840b 4947 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
Kojto 110:165afa46840b 4948 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
Kojto 110:165afa46840b 4949 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4950 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4951 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4952 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
Kojto 110:165afa46840b 4953 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
Kojto 110:165afa46840b 4954 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
Kojto 110:165afa46840b 4955 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
Kojto 110:165afa46840b 4956
Kojto 110:165afa46840b 4957 /******************* Bits definition for FLASH_SR register ******************/
Kojto 110:165afa46840b 4958 #define FLASH_SR_EOP ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4959 #define FLASH_SR_SOP ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4960 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4961 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4962 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4963 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4964 #define FLASH_SR_BSY ((uint32_t)0x00010000)
Kojto 110:165afa46840b 4965
Kojto 110:165afa46840b 4966 /******************* Bits definition for FLASH_CR register ******************/
Kojto 110:165afa46840b 4967 #define FLASH_CR_PG ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4968 #define FLASH_CR_SER ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4969 #define FLASH_CR_MER ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4970 #define FLASH_CR_MER1 FLASH_CR_MER
Kojto 110:165afa46840b 4971 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
Kojto 110:165afa46840b 4972 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4973 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4974 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4975 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4976 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4977 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
Kojto 110:165afa46840b 4978 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4979 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4980 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 4981 #define FLASH_CR_STRT ((uint32_t)0x00010000)
Kojto 110:165afa46840b 4982 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
Kojto 110:165afa46840b 4983 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
Kojto 110:165afa46840b 4984
Kojto 110:165afa46840b 4985 /******************* Bits definition for FLASH_OPTCR register ***************/
Kojto 110:165afa46840b 4986 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
Kojto 110:165afa46840b 4987 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
Kojto 110:165afa46840b 4988 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 4989 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 4990 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
Kojto 110:165afa46840b 4991 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 4992 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
Kojto 110:165afa46840b 4993 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
Kojto 110:165afa46840b 4994 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
Kojto 110:165afa46840b 4995 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
Kojto 110:165afa46840b 4996 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 4997 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 4998 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 4999 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 5000 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 5001 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 5002 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 5003 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 5004 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
Kojto 110:165afa46840b 5005 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 5006 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 5007 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 5008 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 5009 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 5010 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 5011 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 5012 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 5013 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 5014 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 5015 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 5016 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 5017 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
Kojto 110:165afa46840b 5018 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
Kojto 110:165afa46840b 5019
Kojto 110:165afa46840b 5020 /****************** Bits definition for FLASH_OPTCR1 register ***************/
Kojto 110:165afa46840b 5021 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
Kojto 110:165afa46840b 5022 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 5023 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 5024 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 5025 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 5026 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 5027 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 5028 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 5029 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 5030 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 5031 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 5032 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 5033 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 5034
Kojto 110:165afa46840b 5035 /******************************************************************************/
Kojto 110:165afa46840b 5036 /* */
Kojto 110:165afa46840b 5037 /* Flexible Memory Controller */
Kojto 110:165afa46840b 5038 /* */
Kojto 110:165afa46840b 5039 /******************************************************************************/
Kojto 110:165afa46840b 5040 /****************** Bit definition for FMC_BCR1 register *******************/
Kojto 110:165afa46840b 5041 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 110:165afa46840b 5042 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 110:165afa46840b 5043
Kojto 110:165afa46840b 5044 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 110:165afa46840b 5045 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 110:165afa46840b 5046 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 110:165afa46840b 5047
Kojto 110:165afa46840b 5048 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 110:165afa46840b 5049 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5050 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5051
Kojto 110:165afa46840b 5052 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 110:165afa46840b 5053 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 110:165afa46840b 5054 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 110:165afa46840b 5055 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 110:165afa46840b 5056 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 110:165afa46840b 5057 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 110:165afa46840b 5058 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 110:165afa46840b 5059 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 110:165afa46840b 5060 #define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
Kojto 110:165afa46840b 5061 #define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5062 #define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5063 #define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5064 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 110:165afa46840b 5065 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
Kojto 110:165afa46840b 5066 #define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
Kojto 110:165afa46840b 5067
Kojto 110:165afa46840b 5068 /****************** Bit definition for FMC_BCR2 register *******************/
Kojto 110:165afa46840b 5069 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 110:165afa46840b 5070 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 110:165afa46840b 5071
Kojto 110:165afa46840b 5072 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 110:165afa46840b 5073 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 110:165afa46840b 5074 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 110:165afa46840b 5075
Kojto 110:165afa46840b 5076 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 110:165afa46840b 5077 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5078 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5079
Kojto 110:165afa46840b 5080 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 110:165afa46840b 5081 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 110:165afa46840b 5082 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 110:165afa46840b 5083 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 110:165afa46840b 5084 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 110:165afa46840b 5085 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 110:165afa46840b 5086 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 110:165afa46840b 5087 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 110:165afa46840b 5088 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 110:165afa46840b 5089
Kojto 110:165afa46840b 5090 /****************** Bit definition for FMC_BCR3 register *******************/
Kojto 110:165afa46840b 5091 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 110:165afa46840b 5092 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 110:165afa46840b 5093
Kojto 110:165afa46840b 5094 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 110:165afa46840b 5095 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 110:165afa46840b 5096 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 110:165afa46840b 5097
Kojto 110:165afa46840b 5098 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 110:165afa46840b 5099 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5100 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5101
Kojto 110:165afa46840b 5102 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 110:165afa46840b 5103 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 110:165afa46840b 5104 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 110:165afa46840b 5105 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 110:165afa46840b 5106 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 110:165afa46840b 5107 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 110:165afa46840b 5108 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 110:165afa46840b 5109 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 110:165afa46840b 5110 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 110:165afa46840b 5111
Kojto 110:165afa46840b 5112 /****************** Bit definition for FMC_BCR4 register *******************/
Kojto 110:165afa46840b 5113 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 110:165afa46840b 5114 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 110:165afa46840b 5115
Kojto 110:165afa46840b 5116 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 110:165afa46840b 5117 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 110:165afa46840b 5118 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 110:165afa46840b 5119
Kojto 110:165afa46840b 5120 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 110:165afa46840b 5121 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5122 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5123
Kojto 110:165afa46840b 5124 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 110:165afa46840b 5125 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 110:165afa46840b 5126 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 110:165afa46840b 5127 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 110:165afa46840b 5128 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 110:165afa46840b 5129 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 110:165afa46840b 5130 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 110:165afa46840b 5131 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 110:165afa46840b 5132 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 110:165afa46840b 5133
Kojto 110:165afa46840b 5134 /****************** Bit definition for FMC_BTR1 register ******************/
Kojto 110:165afa46840b 5135 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 110:165afa46840b 5136 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5137 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5138 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5139 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5140
Kojto 110:165afa46840b 5141 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 110:165afa46840b 5142 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5143 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5144 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5145 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5146
Kojto 110:165afa46840b 5147 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 110:165afa46840b 5148 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5149 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5150 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5151 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5152 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5153 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5154 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5155 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5156
Kojto 110:165afa46840b 5157 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 110:165afa46840b 5158 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5159 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5160 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5161 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5162
Kojto 110:165afa46840b 5163 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 110:165afa46840b 5164 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 5165 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 5166 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 5167 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 110:165afa46840b 5168
Kojto 110:165afa46840b 5169 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 110:165afa46840b 5170 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5171 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5172 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 5173 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 5174
Kojto 110:165afa46840b 5175 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 110:165afa46840b 5176 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5177 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5178
Kojto 110:165afa46840b 5179 /****************** Bit definition for FMC_BTR2 register *******************/
Kojto 110:165afa46840b 5180 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 110:165afa46840b 5181 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5182 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5183 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5184 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5185
Kojto 110:165afa46840b 5186 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 110:165afa46840b 5187 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5188 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5189 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5190 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5191
Kojto 110:165afa46840b 5192 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 110:165afa46840b 5193 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5194 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5195 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5196 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5197 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5198 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5199 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5200 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5201
Kojto 110:165afa46840b 5202 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 110:165afa46840b 5203 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5204 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5205 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5206 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5207
Kojto 110:165afa46840b 5208 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 110:165afa46840b 5209 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 5210 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 5211 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 5212 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 110:165afa46840b 5213
Kojto 110:165afa46840b 5214 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 110:165afa46840b 5215 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5216 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5217 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 5218 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 5219
Kojto 110:165afa46840b 5220 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 110:165afa46840b 5221 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5222 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5223
Kojto 110:165afa46840b 5224 /******************* Bit definition for FMC_BTR3 register *******************/
Kojto 110:165afa46840b 5225 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 110:165afa46840b 5226 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5227 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5228 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5229 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5230
Kojto 110:165afa46840b 5231 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 110:165afa46840b 5232 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5233 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5234 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5235 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5236
Kojto 110:165afa46840b 5237 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 110:165afa46840b 5238 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5239 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5240 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5241 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5242 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5243 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5244 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5245 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5246
Kojto 110:165afa46840b 5247 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 110:165afa46840b 5248 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5249 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5250 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5251 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5252
Kojto 110:165afa46840b 5253 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 110:165afa46840b 5254 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 5255 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 5256 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 5257 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 110:165afa46840b 5258
Kojto 110:165afa46840b 5259 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 110:165afa46840b 5260 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5261 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5262 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 5263 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 5264
Kojto 110:165afa46840b 5265 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 110:165afa46840b 5266 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5267 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5268
Kojto 110:165afa46840b 5269 /****************** Bit definition for FMC_BTR4 register *******************/
Kojto 110:165afa46840b 5270 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 110:165afa46840b 5271 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5272 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5273 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5274 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5275
Kojto 110:165afa46840b 5276 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 110:165afa46840b 5277 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5278 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5279 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5280 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5281
Kojto 110:165afa46840b 5282 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 110:165afa46840b 5283 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5284 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5285 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5286 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5287 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5288 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5289 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5290 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5291
Kojto 110:165afa46840b 5292 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 110:165afa46840b 5293 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5294 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5295 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5296 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5297
Kojto 110:165afa46840b 5298 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 110:165afa46840b 5299 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 5300 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 5301 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 5302 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 110:165afa46840b 5303
Kojto 110:165afa46840b 5304 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 110:165afa46840b 5305 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5306 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5307 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 5308 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 5309
Kojto 110:165afa46840b 5310 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 110:165afa46840b 5311 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5312 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5313
Kojto 110:165afa46840b 5314 /****************** Bit definition for FMC_BWTR1 register ******************/
Kojto 110:165afa46840b 5315 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 110:165afa46840b 5316 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5317 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5318 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5319 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5320
Kojto 110:165afa46840b 5321 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 110:165afa46840b 5322 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5323 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5324 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5325 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5326
Kojto 110:165afa46840b 5327 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 110:165afa46840b 5328 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5329 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5330 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5331 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5332 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5333 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5334 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5335 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5336
Kojto 110:165afa46840b 5337 #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 110:165afa46840b 5338 #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5339 #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5340 #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5341 #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5342
Kojto 110:165afa46840b 5343 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 110:165afa46840b 5344 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5345 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5346
Kojto 110:165afa46840b 5347 /****************** Bit definition for FMC_BWTR2 register ******************/
Kojto 110:165afa46840b 5348 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 110:165afa46840b 5349 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5350 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5351 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5352 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5353
Kojto 110:165afa46840b 5354 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 110:165afa46840b 5355 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5356 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5357 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5358 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5359
Kojto 110:165afa46840b 5360 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 110:165afa46840b 5361 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5362 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5363 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5364 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5365 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5366 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5367 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5368 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5369
Kojto 110:165afa46840b 5370 #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 110:165afa46840b 5371 #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5372 #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5373 #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5374 #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5375
Kojto 110:165afa46840b 5376 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 110:165afa46840b 5377 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5378 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5379
Kojto 110:165afa46840b 5380 /****************** Bit definition for FMC_BWTR3 register ******************/
Kojto 110:165afa46840b 5381 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 110:165afa46840b 5382 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5383 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5384 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5385 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5386
Kojto 110:165afa46840b 5387 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 110:165afa46840b 5388 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5389 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5390 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5391 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5392
Kojto 110:165afa46840b 5393 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 110:165afa46840b 5394 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5395 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5396 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5397 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5398 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5399 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5400 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5401 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5402
Kojto 110:165afa46840b 5403 #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 110:165afa46840b 5404 #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5405 #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5406 #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5407 #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5408
Kojto 110:165afa46840b 5409 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 110:165afa46840b 5410 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5411 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5412
Kojto 110:165afa46840b 5413 /****************** Bit definition for FMC_BWTR4 register ******************/
Kojto 110:165afa46840b 5414 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 110:165afa46840b 5415 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5416 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5417 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5418 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5419
Kojto 110:165afa46840b 5420 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 110:165afa46840b 5421 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5422 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5423 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5424 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5425
Kojto 110:165afa46840b 5426 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 110:165afa46840b 5427 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5428 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5429 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5430 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5431 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5432 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5433 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5434 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5435
Kojto 110:165afa46840b 5436 #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 110:165afa46840b 5437 #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5438 #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5439 #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5440 #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5441
Kojto 110:165afa46840b 5442 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 110:165afa46840b 5443 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5444 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5445
Kojto 110:165afa46840b 5446 /****************** Bit definition for FMC_PCR register *******************/
Kojto 110:165afa46840b 5447 #define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
Kojto 110:165afa46840b 5448 #define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
Kojto 110:165afa46840b 5449 #define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
Kojto 110:165afa46840b 5450
Kojto 110:165afa46840b 5451 #define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
Kojto 110:165afa46840b 5452 #define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5453 #define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5454
Kojto 110:165afa46840b 5455 #define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
Kojto 110:165afa46840b 5456
Kojto 110:165afa46840b 5457 #define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
Kojto 110:165afa46840b 5458 #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 110:165afa46840b 5459 #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 110:165afa46840b 5460 #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 110:165afa46840b 5461 #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
Kojto 110:165afa46840b 5462
Kojto 110:165afa46840b 5463 #define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
Kojto 110:165afa46840b 5464 #define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 110:165afa46840b 5465 #define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 110:165afa46840b 5466 #define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 110:165afa46840b 5467 #define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 110:165afa46840b 5468
Kojto 110:165afa46840b 5469 #define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
Kojto 110:165afa46840b 5470 #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 110:165afa46840b 5471 #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 110:165afa46840b 5472 #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 110:165afa46840b 5473
Kojto 110:165afa46840b 5474 /******************* Bit definition for FMC_SR register *******************/
Kojto 110:165afa46840b 5475 #define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
Kojto 110:165afa46840b 5476 #define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
Kojto 110:165afa46840b 5477 #define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
Kojto 110:165afa46840b 5478 #define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
Kojto 110:165afa46840b 5479 #define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
Kojto 110:165afa46840b 5480 #define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
Kojto 110:165afa46840b 5481 #define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
Kojto 110:165afa46840b 5482
Kojto 110:165afa46840b 5483 /****************** Bit definition for FMC_PMEM register ******************/
Kojto 110:165afa46840b 5484 #define FMC_PMEM_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
Kojto 110:165afa46840b 5485 #define FMC_PMEM_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5486 #define FMC_PMEM_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5487 #define FMC_PMEM_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5488 #define FMC_PMEM_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5489 #define FMC_PMEM_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 5490 #define FMC_PMEM_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 110:165afa46840b 5491 #define FMC_PMEM_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 110:165afa46840b 5492 #define FMC_PMEM_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 110:165afa46840b 5493
Kojto 110:165afa46840b 5494 #define FMC_PMEM_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
Kojto 110:165afa46840b 5495 #define FMC_PMEM_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5496 #define FMC_PMEM_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5497 #define FMC_PMEM_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5498 #define FMC_PMEM_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5499 #define FMC_PMEM_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5500 #define FMC_PMEM_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5501 #define FMC_PMEM_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5502 #define FMC_PMEM_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5503
Kojto 110:165afa46840b 5504 #define FMC_PMEM_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
Kojto 110:165afa46840b 5505 #define FMC_PMEM_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5506 #define FMC_PMEM_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5507 #define FMC_PMEM_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5508 #define FMC_PMEM_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5509 #define FMC_PMEM_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 110:165afa46840b 5510 #define FMC_PMEM_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 110:165afa46840b 5511 #define FMC_PMEM_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 110:165afa46840b 5512 #define FMC_PMEM_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 110:165afa46840b 5513
Kojto 110:165afa46840b 5514 #define FMC_PMEM_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
Kojto 110:165afa46840b 5515 #define FMC_PMEM_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5516 #define FMC_PMEM_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5517 #define FMC_PMEM_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 5518 #define FMC_PMEM_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 5519 #define FMC_PMEM_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 110:165afa46840b 5520 #define FMC_PMEM_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 110:165afa46840b 5521 #define FMC_PMEM_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 110:165afa46840b 5522 #define FMC_PMEM_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 110:165afa46840b 5523
Kojto 110:165afa46840b 5524 /****************** Bit definition for FMC_PATT register ******************/
Kojto 110:165afa46840b 5525 #define FMC_PATT_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
Kojto 110:165afa46840b 5526 #define FMC_PATT_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5527 #define FMC_PATT_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5528 #define FMC_PATT_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5529 #define FMC_PATT_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5530 #define FMC_PATT_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 5531 #define FMC_PATT_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 110:165afa46840b 5532 #define FMC_PATT_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 110:165afa46840b 5533 #define FMC_PATT_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 110:165afa46840b 5534
Kojto 110:165afa46840b 5535 #define FMC_PATT_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
Kojto 110:165afa46840b 5536 #define FMC_PATT_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5537 #define FMC_PATT_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5538 #define FMC_PATT_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5539 #define FMC_PATT_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5540 #define FMC_PATT_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 5541 #define FMC_PATT_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 5542 #define FMC_PATT_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 5543 #define FMC_PATT_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 110:165afa46840b 5544
Kojto 110:165afa46840b 5545 #define FMC_PATT_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
Kojto 110:165afa46840b 5546 #define FMC_PATT_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5547 #define FMC_PATT_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5548 #define FMC_PATT_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5549 #define FMC_PATT_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 5550 #define FMC_PATT_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 110:165afa46840b 5551 #define FMC_PATT_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 110:165afa46840b 5552 #define FMC_PATT_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 110:165afa46840b 5553 #define FMC_PATT_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 110:165afa46840b 5554
Kojto 110:165afa46840b 5555 #define FMC_PATT_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
Kojto 110:165afa46840b 5556 #define FMC_PATT_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5557 #define FMC_PATT_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5558 #define FMC_PATT_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 5559 #define FMC_PATT_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 5560 #define FMC_PATT_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 110:165afa46840b 5561 #define FMC_PATT_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 110:165afa46840b 5562 #define FMC_PATT_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 110:165afa46840b 5563 #define FMC_PATT_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 110:165afa46840b 5564
Kojto 110:165afa46840b 5565 /****************** Bit definition for FMC_ECCR register ******************/
Kojto 110:165afa46840b 5566 #define FMC_ECCR_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
Kojto 110:165afa46840b 5567
Kojto 110:165afa46840b 5568 /****************** Bit definition for FMC_SDCR1 register ******************/
Kojto 110:165afa46840b 5569 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
Kojto 110:165afa46840b 5570 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5571 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5572
Kojto 110:165afa46840b 5573 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
Kojto 110:165afa46840b 5574 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 110:165afa46840b 5575 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 110:165afa46840b 5576
Kojto 110:165afa46840b 5577 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
Kojto 110:165afa46840b 5578 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5579 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5580
Kojto 110:165afa46840b 5581 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
Kojto 110:165afa46840b 5582
Kojto 110:165afa46840b 5583 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
Kojto 110:165afa46840b 5584 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 110:165afa46840b 5585 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 110:165afa46840b 5586
Kojto 110:165afa46840b 5587 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
Kojto 110:165afa46840b 5588
Kojto 110:165afa46840b 5589 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
Kojto 110:165afa46840b 5590 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 110:165afa46840b 5591 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 110:165afa46840b 5592
Kojto 110:165afa46840b 5593 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
Kojto 110:165afa46840b 5594
Kojto 110:165afa46840b 5595 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
Kojto 110:165afa46840b 5596 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 110:165afa46840b 5597 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 110:165afa46840b 5598
Kojto 110:165afa46840b 5599 /****************** Bit definition for FMC_SDCR2 register ******************/
Kojto 110:165afa46840b 5600 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
Kojto 110:165afa46840b 5601 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5602 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5603
Kojto 110:165afa46840b 5604 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
Kojto 110:165afa46840b 5605 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 110:165afa46840b 5606 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 110:165afa46840b 5607
Kojto 110:165afa46840b 5608 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
Kojto 110:165afa46840b 5609 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5610 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5611
Kojto 110:165afa46840b 5612 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
Kojto 110:165afa46840b 5613
Kojto 110:165afa46840b 5614 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
Kojto 110:165afa46840b 5615 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 110:165afa46840b 5616 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 110:165afa46840b 5617
Kojto 110:165afa46840b 5618 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
Kojto 110:165afa46840b 5619
Kojto 110:165afa46840b 5620 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
Kojto 110:165afa46840b 5621 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 110:165afa46840b 5622 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 110:165afa46840b 5623
Kojto 110:165afa46840b 5624 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
Kojto 110:165afa46840b 5625
Kojto 110:165afa46840b 5626 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
Kojto 110:165afa46840b 5627 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 110:165afa46840b 5628 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 110:165afa46840b 5629
Kojto 110:165afa46840b 5630 /****************** Bit definition for FMC_SDTR1 register ******************/
Kojto 110:165afa46840b 5631 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 110:165afa46840b 5632 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5633 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5634 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5635 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5636
Kojto 110:165afa46840b 5637 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 110:165afa46840b 5638 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5639 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5640 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5641 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5642
Kojto 110:165afa46840b 5643 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 110:165afa46840b 5644 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5645 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5646 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5647 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5648
Kojto 110:165afa46840b 5649 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 110:165afa46840b 5650 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 110:165afa46840b 5651 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 110:165afa46840b 5652 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 110:165afa46840b 5653
Kojto 110:165afa46840b 5654 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 110:165afa46840b 5655 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5656 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5657 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5658
Kojto 110:165afa46840b 5659 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 110:165afa46840b 5660 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 5661 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 5662 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 5663
Kojto 110:165afa46840b 5664 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
Kojto 110:165afa46840b 5665 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5666 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5667 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 5668
Kojto 110:165afa46840b 5669 /****************** Bit definition for FMC_SDTR2 register ******************/
Kojto 110:165afa46840b 5670 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 110:165afa46840b 5671 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5672 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5673 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5674 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 5675
Kojto 110:165afa46840b 5676 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 110:165afa46840b 5677 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 5678 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 5679 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 5680 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 5681
Kojto 110:165afa46840b 5682 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 110:165afa46840b 5683 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 5684 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 5685 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 5686 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 5687
Kojto 110:165afa46840b 5688 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 110:165afa46840b 5689 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 110:165afa46840b 5690 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 110:165afa46840b 5691 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 110:165afa46840b 5692
Kojto 110:165afa46840b 5693 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 110:165afa46840b 5694 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 5695 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 5696 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 5697
Kojto 110:165afa46840b 5698 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 110:165afa46840b 5699 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 5700 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 5701 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 5702
Kojto 110:165afa46840b 5703 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
Kojto 110:165afa46840b 5704 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 5705 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 5706 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 5707
Kojto 110:165afa46840b 5708 /****************** Bit definition for FMC_SDCMR register ******************/
Kojto 110:165afa46840b 5709 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
Kojto 110:165afa46840b 5710 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 5711 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 5712 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 5713
Kojto 110:165afa46840b 5714 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
Kojto 110:165afa46840b 5715
Kojto 110:165afa46840b 5716 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
Kojto 110:165afa46840b 5717
Kojto 110:165afa46840b 5718 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
Kojto 110:165afa46840b 5719 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 110:165afa46840b 5720 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 110:165afa46840b 5721 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 110:165afa46840b 5722 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 110:165afa46840b 5723
Kojto 110:165afa46840b 5724 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
Kojto 110:165afa46840b 5725
Kojto 110:165afa46840b 5726 /****************** Bit definition for FMC_SDRTR register ******************/
Kojto 110:165afa46840b 5727 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
Kojto 110:165afa46840b 5728
Kojto 110:165afa46840b 5729 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
Kojto 110:165afa46840b 5730
Kojto 110:165afa46840b 5731 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
Kojto 110:165afa46840b 5732
Kojto 110:165afa46840b 5733 /****************** Bit definition for FMC_SDSR register ******************/
Kojto 110:165afa46840b 5734 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
Kojto 110:165afa46840b 5735
Kojto 110:165afa46840b 5736 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
Kojto 110:165afa46840b 5737 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 110:165afa46840b 5738 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 110:165afa46840b 5739
Kojto 110:165afa46840b 5740 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
Kojto 110:165afa46840b 5741 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 110:165afa46840b 5742 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 110:165afa46840b 5743 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
Kojto 110:165afa46840b 5744
Kojto 110:165afa46840b 5745 /******************************************************************************/
Kojto 110:165afa46840b 5746 /* */
Kojto 110:165afa46840b 5747 /* General Purpose I/O */
Kojto 110:165afa46840b 5748 /* */
Kojto 110:165afa46840b 5749 /******************************************************************************/
Kojto 110:165afa46840b 5750 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 110:165afa46840b 5751 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 110:165afa46840b 5752 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 5753 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 5754
Kojto 110:165afa46840b 5755 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 110:165afa46840b 5756 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 5757 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 5758
Kojto 110:165afa46840b 5759 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 110:165afa46840b 5760 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 5761 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 5762
Kojto 110:165afa46840b 5763 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 110:165afa46840b 5764 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 5765 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 5766
Kojto 110:165afa46840b 5767 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 110:165afa46840b 5768 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 5769 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 5770
Kojto 110:165afa46840b 5771 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 110:165afa46840b 5772 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 5773 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 5774
Kojto 110:165afa46840b 5775 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 110:165afa46840b 5776 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 5777 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 5778
Kojto 110:165afa46840b 5779 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 110:165afa46840b 5780 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 5781 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 5782
Kojto 110:165afa46840b 5783 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 110:165afa46840b 5784 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 5785 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 5786
Kojto 110:165afa46840b 5787 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 110:165afa46840b 5788 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 5789 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 5790
Kojto 110:165afa46840b 5791 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 110:165afa46840b 5792 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 5793 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 5794
Kojto 110:165afa46840b 5795 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 110:165afa46840b 5796 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 5797 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 5798
Kojto 110:165afa46840b 5799 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 110:165afa46840b 5800 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 5801 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 5802
Kojto 110:165afa46840b 5803 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 110:165afa46840b 5804 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 5805 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 5806
Kojto 110:165afa46840b 5807 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 110:165afa46840b 5808 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 5809 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 5810
Kojto 110:165afa46840b 5811 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 110:165afa46840b 5812 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 5813 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 5814
Kojto 110:165afa46840b 5815 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 110:165afa46840b 5816 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 5817 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 5818 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 5819 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 5820 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 5821 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 5822 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 5823 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 5824 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 5825 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 5826 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 5827 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 5828 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 5829 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 5830 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 5831 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 5832
Kojto 110:165afa46840b 5833 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 110:165afa46840b 5834 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 110:165afa46840b 5835 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 5836 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 5837
Kojto 110:165afa46840b 5838 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 110:165afa46840b 5839 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 5840 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 5841
Kojto 110:165afa46840b 5842 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 110:165afa46840b 5843 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 5844 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 5845
Kojto 110:165afa46840b 5846 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 110:165afa46840b 5847 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 5848 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 5849
Kojto 110:165afa46840b 5850 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 110:165afa46840b 5851 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 5852 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 5853
Kojto 110:165afa46840b 5854 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 110:165afa46840b 5855 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 5856 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 5857
Kojto 110:165afa46840b 5858 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 110:165afa46840b 5859 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 5860 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 5861
Kojto 110:165afa46840b 5862 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 110:165afa46840b 5863 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 5864 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 5865
Kojto 110:165afa46840b 5866 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 110:165afa46840b 5867 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 5868 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 5869
Kojto 110:165afa46840b 5870 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 110:165afa46840b 5871 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 5872 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 5873
Kojto 110:165afa46840b 5874 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 110:165afa46840b 5875 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 5876 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 5877
Kojto 110:165afa46840b 5878 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 110:165afa46840b 5879 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 5880 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 5881
Kojto 110:165afa46840b 5882 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 110:165afa46840b 5883 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 5884 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 5885
Kojto 110:165afa46840b 5886 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 110:165afa46840b 5887 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 5888 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 5889
Kojto 110:165afa46840b 5890 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 110:165afa46840b 5891 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 5892 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 5893
Kojto 110:165afa46840b 5894 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 110:165afa46840b 5895 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 5896 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 5897
Kojto 110:165afa46840b 5898 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 110:165afa46840b 5899 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 110:165afa46840b 5900 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 5901 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 5902
Kojto 110:165afa46840b 5903 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 110:165afa46840b 5904 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 5905 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 5906
Kojto 110:165afa46840b 5907 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 110:165afa46840b 5908 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 5909 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 5910
Kojto 110:165afa46840b 5911 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 110:165afa46840b 5912 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 5913 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 5914
Kojto 110:165afa46840b 5915 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 110:165afa46840b 5916 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 5917 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 5918
Kojto 110:165afa46840b 5919 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 110:165afa46840b 5920 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 5921 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 5922
Kojto 110:165afa46840b 5923 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 110:165afa46840b 5924 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 5925 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 5926
Kojto 110:165afa46840b 5927 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 110:165afa46840b 5928 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 5929 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 5930
Kojto 110:165afa46840b 5931 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 110:165afa46840b 5932 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 5933 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 5934
Kojto 110:165afa46840b 5935 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 110:165afa46840b 5936 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 5937 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 5938
Kojto 110:165afa46840b 5939 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 110:165afa46840b 5940 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 5941 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 5942
Kojto 110:165afa46840b 5943 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 110:165afa46840b 5944 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 5945 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 5946
Kojto 110:165afa46840b 5947 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 110:165afa46840b 5948 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 5949 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 5950
Kojto 110:165afa46840b 5951 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 110:165afa46840b 5952 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 5953 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 5954
Kojto 110:165afa46840b 5955 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 110:165afa46840b 5956 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 5957 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 5958
Kojto 110:165afa46840b 5959 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 110:165afa46840b 5960 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 5961 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 5962
Kojto 110:165afa46840b 5963 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 110:165afa46840b 5964 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 5965 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 5966 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 5967 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 5968 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 5969 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 5970 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 5971 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 5972 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 5973 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 5974 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 5975 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 5976 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 5977 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 5978 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 5979 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 5980 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
Kojto 110:165afa46840b 5981 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
Kojto 110:165afa46840b 5982 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
Kojto 110:165afa46840b 5983 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
Kojto 110:165afa46840b 5984 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
Kojto 110:165afa46840b 5985 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
Kojto 110:165afa46840b 5986 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
Kojto 110:165afa46840b 5987 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
Kojto 110:165afa46840b 5988 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
Kojto 110:165afa46840b 5989 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
Kojto 110:165afa46840b 5990 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
Kojto 110:165afa46840b 5991 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
Kojto 110:165afa46840b 5992 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
Kojto 110:165afa46840b 5993 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
Kojto 110:165afa46840b 5994 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
Kojto 110:165afa46840b 5995 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
Kojto 110:165afa46840b 5996 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
Kojto 110:165afa46840b 5997
Kojto 110:165afa46840b 5998 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 110:165afa46840b 5999 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6000 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6001 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6002 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6003 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6004 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6005 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6006 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6007 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6008 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6009 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6010 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6011 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6012 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 6013 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6014 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 6015 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
Kojto 110:165afa46840b 6016 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
Kojto 110:165afa46840b 6017 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
Kojto 110:165afa46840b 6018 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
Kojto 110:165afa46840b 6019 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
Kojto 110:165afa46840b 6020 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
Kojto 110:165afa46840b 6021 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
Kojto 110:165afa46840b 6022 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
Kojto 110:165afa46840b 6023 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
Kojto 110:165afa46840b 6024 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
Kojto 110:165afa46840b 6025 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
Kojto 110:165afa46840b 6026 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
Kojto 110:165afa46840b 6027 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
Kojto 110:165afa46840b 6028 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
Kojto 110:165afa46840b 6029 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
Kojto 110:165afa46840b 6030 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
Kojto 110:165afa46840b 6031 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
Kojto 110:165afa46840b 6032
Kojto 110:165afa46840b 6033 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 110:165afa46840b 6034 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6035 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6036 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6037 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6038 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6039 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6040 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6041 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6042 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6043 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6044 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6045 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6046 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6047 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 6048 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6049 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 6050 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6051 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6052 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6053 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 6054 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6055 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6056 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6057 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 6058 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 6059 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6060 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6061 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 6062 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 6063 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6064 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 6065 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 6066
Kojto 110:165afa46840b 6067 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 110:165afa46840b 6068 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6069 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6070 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6071 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6072 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6073 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6074 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6075 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6076 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6077 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6078 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6079 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6080 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6081 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 6082 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6083 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 6084 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6085
Kojto 110:165afa46840b 6086 /******************************************************************************/
Kojto 110:165afa46840b 6087 /* */
Kojto 110:165afa46840b 6088 /* Inter-integrated Circuit Interface */
Kojto 110:165afa46840b 6089 /* */
Kojto 110:165afa46840b 6090 /******************************************************************************/
Kojto 110:165afa46840b 6091 /******************* Bit definition for I2C_CR1 register ********************/
Kojto 110:165afa46840b 6092 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
Kojto 110:165afa46840b 6093 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
Kojto 110:165afa46840b 6094 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
Kojto 110:165afa46840b 6095 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
Kojto 110:165afa46840b 6096 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
Kojto 110:165afa46840b 6097 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
Kojto 110:165afa46840b 6098 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
Kojto 110:165afa46840b 6099 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
Kojto 110:165afa46840b 6100 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
Kojto 110:165afa46840b 6101 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
Kojto 110:165afa46840b 6102 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
Kojto 110:165afa46840b 6103 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
Kojto 110:165afa46840b 6104 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
Kojto 110:165afa46840b 6105 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
Kojto 110:165afa46840b 6106
Kojto 110:165afa46840b 6107 /******************* Bit definition for I2C_CR2 register ********************/
Kojto 110:165afa46840b 6108 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
Kojto 110:165afa46840b 6109 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 6110 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 6111 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 6112 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 6113 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 6114 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 110:165afa46840b 6115
Kojto 110:165afa46840b 6116 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
Kojto 110:165afa46840b 6117 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
Kojto 110:165afa46840b 6118 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
Kojto 110:165afa46840b 6119 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
Kojto 110:165afa46840b 6120 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
Kojto 110:165afa46840b 6121
Kojto 110:165afa46840b 6122 /******************* Bit definition for I2C_OAR1 register *******************/
Kojto 110:165afa46840b 6123 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
Kojto 110:165afa46840b 6124 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
Kojto 110:165afa46840b 6125
Kojto 110:165afa46840b 6126 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 6127 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 6128 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 6129 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 6130 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 6131 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 110:165afa46840b 6132 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 110:165afa46840b 6133 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 110:165afa46840b 6134 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
Kojto 110:165afa46840b 6135 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
Kojto 110:165afa46840b 6136
Kojto 110:165afa46840b 6137 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
Kojto 110:165afa46840b 6138
Kojto 110:165afa46840b 6139 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 110:165afa46840b 6140 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
Kojto 110:165afa46840b 6141 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
Kojto 110:165afa46840b 6142
Kojto 110:165afa46840b 6143 /******************** Bit definition for I2C_DR register ********************/
Kojto 110:165afa46840b 6144 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
Kojto 110:165afa46840b 6145
Kojto 110:165afa46840b 6146 /******************* Bit definition for I2C_SR1 register ********************/
Kojto 110:165afa46840b 6147 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
Kojto 110:165afa46840b 6148 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
Kojto 110:165afa46840b 6149 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
Kojto 110:165afa46840b 6150 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
Kojto 110:165afa46840b 6151 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
Kojto 110:165afa46840b 6152 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
Kojto 110:165afa46840b 6153 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
Kojto 110:165afa46840b 6154 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
Kojto 110:165afa46840b 6155 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
Kojto 110:165afa46840b 6156 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
Kojto 110:165afa46840b 6157 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
Kojto 110:165afa46840b 6158 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
Kojto 110:165afa46840b 6159 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
Kojto 110:165afa46840b 6160 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
Kojto 110:165afa46840b 6161
Kojto 110:165afa46840b 6162 /******************* Bit definition for I2C_SR2 register ********************/
Kojto 110:165afa46840b 6163 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
Kojto 110:165afa46840b 6164 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
Kojto 110:165afa46840b 6165 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
Kojto 110:165afa46840b 6166 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
Kojto 110:165afa46840b 6167 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
Kojto 110:165afa46840b 6168 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
Kojto 110:165afa46840b 6169 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
Kojto 110:165afa46840b 6170 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
Kojto 110:165afa46840b 6171
Kojto 110:165afa46840b 6172 /******************* Bit definition for I2C_CCR register ********************/
Kojto 110:165afa46840b 6173 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
Kojto 110:165afa46840b 6174 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
Kojto 110:165afa46840b 6175 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
Kojto 110:165afa46840b 6176
Kojto 110:165afa46840b 6177 /****************** Bit definition for I2C_TRISE register *******************/
Kojto 110:165afa46840b 6178 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
Kojto 110:165afa46840b 6179
Kojto 110:165afa46840b 6180 /****************** Bit definition for I2C_FLTR register *******************/
Kojto 110:165afa46840b 6181 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
Kojto 110:165afa46840b 6182 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
Kojto 110:165afa46840b 6183
Kojto 110:165afa46840b 6184 /******************************************************************************/
Kojto 110:165afa46840b 6185 /* */
Kojto 110:165afa46840b 6186 /* Independent WATCHDOG */
Kojto 110:165afa46840b 6187 /* */
Kojto 110:165afa46840b 6188 /******************************************************************************/
Kojto 110:165afa46840b 6189 /******************* Bit definition for IWDG_KR register ********************/
Kojto 110:165afa46840b 6190 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
Kojto 110:165afa46840b 6191
Kojto 110:165afa46840b 6192 /******************* Bit definition for IWDG_PR register ********************/
Kojto 110:165afa46840b 6193 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
Kojto 110:165afa46840b 6194 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 110:165afa46840b 6195 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 110:165afa46840b 6196 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 110:165afa46840b 6197
Kojto 110:165afa46840b 6198 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 110:165afa46840b 6199 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
Kojto 110:165afa46840b 6200
Kojto 110:165afa46840b 6201 /******************* Bit definition for IWDG_SR register ********************/
Kojto 110:165afa46840b 6202 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
Kojto 110:165afa46840b 6203 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
Kojto 110:165afa46840b 6204
Kojto 110:165afa46840b 6205
Kojto 110:165afa46840b 6206 /******************************************************************************/
Kojto 110:165afa46840b 6207 /* */
Kojto 110:165afa46840b 6208 /* LCD-TFT Display Controller (LTDC) */
Kojto 110:165afa46840b 6209 /* */
Kojto 110:165afa46840b 6210 /******************************************************************************/
Kojto 110:165afa46840b 6211
Kojto 110:165afa46840b 6212 /******************** Bit definition for LTDC_SSCR register *****************/
Kojto 110:165afa46840b 6213
Kojto 110:165afa46840b 6214 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
Kojto 110:165afa46840b 6215 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
Kojto 110:165afa46840b 6216
Kojto 110:165afa46840b 6217 /******************** Bit definition for LTDC_BPCR register *****************/
Kojto 110:165afa46840b 6218
Kojto 110:165afa46840b 6219 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
Kojto 110:165afa46840b 6220 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
Kojto 110:165afa46840b 6221
Kojto 110:165afa46840b 6222 /******************** Bit definition for LTDC_AWCR register *****************/
Kojto 110:165afa46840b 6223
Kojto 110:165afa46840b 6224 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
Kojto 110:165afa46840b 6225 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
Kojto 110:165afa46840b 6226
Kojto 110:165afa46840b 6227 /******************** Bit definition for LTDC_TWCR register *****************/
Kojto 110:165afa46840b 6228
Kojto 110:165afa46840b 6229 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
Kojto 110:165afa46840b 6230 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
Kojto 110:165afa46840b 6231
Kojto 110:165afa46840b 6232 /******************** Bit definition for LTDC_GCR register ******************/
Kojto 110:165afa46840b 6233
Kojto 110:165afa46840b 6234 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
Kojto 110:165afa46840b 6235 #define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
Kojto 110:165afa46840b 6236 #define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
Kojto 110:165afa46840b 6237 #define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
Kojto 110:165afa46840b 6238 #define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
Kojto 110:165afa46840b 6239 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
Kojto 110:165afa46840b 6240 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
Kojto 110:165afa46840b 6241 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
Kojto 110:165afa46840b 6242 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
Kojto 110:165afa46840b 6243
Kojto 110:165afa46840b 6244 /******************** Bit definition for LTDC_SRCR register *****************/
Kojto 110:165afa46840b 6245
Kojto 110:165afa46840b 6246 #define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
Kojto 110:165afa46840b 6247 #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
Kojto 110:165afa46840b 6248
Kojto 110:165afa46840b 6249 /******************** Bit definition for LTDC_BCCR register *****************/
Kojto 110:165afa46840b 6250
Kojto 110:165afa46840b 6251 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
Kojto 110:165afa46840b 6252 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
Kojto 110:165afa46840b 6253 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
Kojto 110:165afa46840b 6254
Kojto 110:165afa46840b 6255 /******************** Bit definition for LTDC_IER register ******************/
Kojto 110:165afa46840b 6256
Kojto 110:165afa46840b 6257 #define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
Kojto 110:165afa46840b 6258 #define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
Kojto 110:165afa46840b 6259 #define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
Kojto 110:165afa46840b 6260 #define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
Kojto 110:165afa46840b 6261
Kojto 110:165afa46840b 6262 /******************** Bit definition for LTDC_ISR register ******************/
Kojto 110:165afa46840b 6263
Kojto 110:165afa46840b 6264 #define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
Kojto 110:165afa46840b 6265 #define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
Kojto 110:165afa46840b 6266 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
Kojto 110:165afa46840b 6267 #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
Kojto 110:165afa46840b 6268
Kojto 110:165afa46840b 6269 /******************** Bit definition for LTDC_ICR register ******************/
Kojto 110:165afa46840b 6270
Kojto 110:165afa46840b 6271 #define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
Kojto 110:165afa46840b 6272 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
Kojto 110:165afa46840b 6273 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
Kojto 110:165afa46840b 6274 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
Kojto 110:165afa46840b 6275
Kojto 110:165afa46840b 6276 /******************** Bit definition for LTDC_LIPCR register ****************/
Kojto 110:165afa46840b 6277
Kojto 110:165afa46840b 6278 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
Kojto 110:165afa46840b 6279
Kojto 110:165afa46840b 6280 /******************** Bit definition for LTDC_CPSR register *****************/
Kojto 110:165afa46840b 6281
Kojto 110:165afa46840b 6282 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
Kojto 110:165afa46840b 6283 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
Kojto 110:165afa46840b 6284
Kojto 110:165afa46840b 6285 /******************** Bit definition for LTDC_CDSR register *****************/
Kojto 110:165afa46840b 6286
Kojto 110:165afa46840b 6287 #define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
Kojto 110:165afa46840b 6288 #define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
Kojto 110:165afa46840b 6289 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
Kojto 110:165afa46840b 6290 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
Kojto 110:165afa46840b 6291
Kojto 110:165afa46840b 6292 /******************** Bit definition for LTDC_LxCR register *****************/
Kojto 110:165afa46840b 6293
Kojto 110:165afa46840b 6294 #define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
Kojto 110:165afa46840b 6295 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
Kojto 110:165afa46840b 6296 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
Kojto 110:165afa46840b 6297
Kojto 110:165afa46840b 6298 /******************** Bit definition for LTDC_LxWHPCR register **************/
Kojto 110:165afa46840b 6299
Kojto 110:165afa46840b 6300 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
Kojto 110:165afa46840b 6301 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
Kojto 110:165afa46840b 6302
Kojto 110:165afa46840b 6303 /******************** Bit definition for LTDC_LxWVPCR register **************/
Kojto 110:165afa46840b 6304
Kojto 110:165afa46840b 6305 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
Kojto 110:165afa46840b 6306 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
Kojto 110:165afa46840b 6307
Kojto 110:165afa46840b 6308 /******************** Bit definition for LTDC_LxCKCR register ***************/
Kojto 110:165afa46840b 6309
Kojto 110:165afa46840b 6310 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
Kojto 110:165afa46840b 6311 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
Kojto 110:165afa46840b 6312 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
Kojto 110:165afa46840b 6313
Kojto 110:165afa46840b 6314 /******************** Bit definition for LTDC_LxPFCR register ***************/
Kojto 110:165afa46840b 6315
Kojto 110:165afa46840b 6316 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
Kojto 110:165afa46840b 6317
Kojto 110:165afa46840b 6318 /******************** Bit definition for LTDC_LxCACR register ***************/
Kojto 110:165afa46840b 6319
Kojto 110:165afa46840b 6320 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
Kojto 110:165afa46840b 6321
Kojto 110:165afa46840b 6322 /******************** Bit definition for LTDC_LxDCCR register ***************/
Kojto 110:165afa46840b 6323
Kojto 110:165afa46840b 6324 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
Kojto 110:165afa46840b 6325 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
Kojto 110:165afa46840b 6326 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
Kojto 110:165afa46840b 6327 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
Kojto 110:165afa46840b 6328
Kojto 110:165afa46840b 6329 /******************** Bit definition for LTDC_LxBFCR register ***************/
Kojto 110:165afa46840b 6330
Kojto 110:165afa46840b 6331 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
Kojto 110:165afa46840b 6332 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
Kojto 110:165afa46840b 6333
Kojto 110:165afa46840b 6334 /******************** Bit definition for LTDC_LxCFBAR register **************/
Kojto 110:165afa46840b 6335
Kojto 110:165afa46840b 6336 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
Kojto 110:165afa46840b 6337
Kojto 110:165afa46840b 6338 /******************** Bit definition for LTDC_LxCFBLR register **************/
Kojto 110:165afa46840b 6339
Kojto 110:165afa46840b 6340 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
Kojto 110:165afa46840b 6341 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
Kojto 110:165afa46840b 6342
Kojto 110:165afa46840b 6343 /******************** Bit definition for LTDC_LxCFBLNR register *************/
Kojto 110:165afa46840b 6344
Kojto 110:165afa46840b 6345 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
Kojto 110:165afa46840b 6346
Kojto 110:165afa46840b 6347 /******************** Bit definition for LTDC_LxCLUTWR register *************/
Kojto 110:165afa46840b 6348
Kojto 110:165afa46840b 6349 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
Kojto 110:165afa46840b 6350 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
Kojto 110:165afa46840b 6351 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
Kojto 110:165afa46840b 6352 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
Kojto 110:165afa46840b 6353
Kojto 110:165afa46840b 6354
Kojto 110:165afa46840b 6355 /******************************************************************************/
Kojto 110:165afa46840b 6356 /* */
Kojto 110:165afa46840b 6357 /* Power Control */
Kojto 110:165afa46840b 6358 /* */
Kojto 110:165afa46840b 6359 /******************************************************************************/
Kojto 110:165afa46840b 6360 /******************** Bit definition for PWR_CR register ********************/
Kojto 110:165afa46840b 6361 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
Kojto 110:165afa46840b 6362 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 110:165afa46840b 6363 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 110:165afa46840b 6364 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 110:165afa46840b 6365 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 110:165afa46840b 6366
Kojto 110:165afa46840b 6367 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 110:165afa46840b 6368 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 110:165afa46840b 6369 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 110:165afa46840b 6370 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 110:165afa46840b 6371
Kojto 110:165afa46840b 6372 /*!< PVD level configuration */
Kojto 110:165afa46840b 6373 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Kojto 110:165afa46840b 6374 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Kojto 110:165afa46840b 6375 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Kojto 110:165afa46840b 6376 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Kojto 110:165afa46840b 6377 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Kojto 110:165afa46840b 6378 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Kojto 110:165afa46840b 6379 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Kojto 110:165afa46840b 6380 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Kojto 110:165afa46840b 6381 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 110:165afa46840b 6382 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
Kojto 110:165afa46840b 6383 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
Kojto 110:165afa46840b 6384 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
Kojto 110:165afa46840b 6385 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
Kojto 110:165afa46840b 6386 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
Kojto 110:165afa46840b 6387 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 110:165afa46840b 6388 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 110:165afa46840b 6389 #define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
Kojto 110:165afa46840b 6390 #define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
Kojto 110:165afa46840b 6391 #define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
Kojto 110:165afa46840b 6392 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 110:165afa46840b 6393 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 110:165afa46840b 6394
Kojto 110:165afa46840b 6395 /* Legacy define */
Kojto 110:165afa46840b 6396 #define PWR_CR_PMODE PWR_CR_VOS
Kojto 110:165afa46840b 6397 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
Kojto 110:165afa46840b 6398 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
Kojto 110:165afa46840b 6399
Kojto 110:165afa46840b 6400 /******************* Bit definition for PWR_CSR register ********************/
Kojto 110:165afa46840b 6401 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 110:165afa46840b 6402 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 110:165afa46840b 6403 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 110:165afa46840b 6404 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
Kojto 110:165afa46840b 6405 #define PWR_CSR_WUPP ((uint32_t)0x00000080) /*!< WKUP pin Polarity */
Kojto 110:165afa46840b 6406 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
Kojto 110:165afa46840b 6407 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
Kojto 110:165afa46840b 6408 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
Kojto 110:165afa46840b 6409 #define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
Kojto 110:165afa46840b 6410 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
Kojto 110:165afa46840b 6411 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
Kojto 110:165afa46840b 6412
Kojto 110:165afa46840b 6413 /* Legacy define */
Kojto 110:165afa46840b 6414 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
Kojto 110:165afa46840b 6415
Kojto 110:165afa46840b 6416 /******************************************************************************/
Kojto 110:165afa46840b 6417 /* */
Kojto 110:165afa46840b 6418 /* QUADSPI */
Kojto 110:165afa46840b 6419 /* */
Kojto 110:165afa46840b 6420 /******************************************************************************/
Kojto 110:165afa46840b 6421 /***************** Bit definition for QUADSPI_CR register *******************/
Kojto 110:165afa46840b 6422 #define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
Kojto 110:165afa46840b 6423 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
Kojto 110:165afa46840b 6424 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
Kojto 110:165afa46840b 6425 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
Kojto 110:165afa46840b 6426 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< SSHIFT Sample Shift */
Kojto 110:165afa46840b 6427 #define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
Kojto 110:165afa46840b 6428 #define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
Kojto 110:165afa46840b 6429 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
Kojto 110:165afa46840b 6430 #define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 110:165afa46840b 6431 #define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 110:165afa46840b 6432 #define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 110:165afa46840b 6433 #define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 110:165afa46840b 6434 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
Kojto 110:165afa46840b 6435 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
Kojto 110:165afa46840b 6436 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
Kojto 110:165afa46840b 6437 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
Kojto 110:165afa46840b 6438 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
Kojto 110:165afa46840b 6439 #define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 110:165afa46840b 6440 #define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
Kojto 110:165afa46840b 6441 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
Kojto 110:165afa46840b 6442 #define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 110:165afa46840b 6443 #define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 110:165afa46840b 6444 #define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 110:165afa46840b 6445 #define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Kojto 110:165afa46840b 6446 #define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
Kojto 110:165afa46840b 6447 #define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
Kojto 110:165afa46840b 6448 #define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
Kojto 110:165afa46840b 6449 #define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
Kojto 110:165afa46840b 6450
Kojto 110:165afa46840b 6451 /***************** Bit definition for QUADSPI_DCR register ******************/
Kojto 110:165afa46840b 6452 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
Kojto 110:165afa46840b 6453 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
Kojto 110:165afa46840b 6454 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 110:165afa46840b 6455 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 110:165afa46840b 6456 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 110:165afa46840b 6457 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
Kojto 110:165afa46840b 6458 #define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 110:165afa46840b 6459 #define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 110:165afa46840b 6460 #define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 110:165afa46840b 6461 #define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 110:165afa46840b 6462 #define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 110:165afa46840b 6463
Kojto 110:165afa46840b 6464 /****************** Bit definition for QUADSPI_SR register *******************/
Kojto 110:165afa46840b 6465 #define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
Kojto 110:165afa46840b 6466 #define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
Kojto 110:165afa46840b 6467 #define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
Kojto 110:165afa46840b 6468 #define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
Kojto 110:165afa46840b 6469 #define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
Kojto 110:165afa46840b 6470 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
Kojto 110:165afa46840b 6471 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00003F00) /*!< FIFO Threshlod Flag */
Kojto 110:165afa46840b 6472 #define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 110:165afa46840b 6473 #define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 110:165afa46840b 6474 #define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 110:165afa46840b 6475 #define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 110:165afa46840b 6476 #define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
Kojto 110:165afa46840b 6477 #define QUADSPI_SR_FLEVEL_5 ((uint32_t)0x00002000) /*!< Bit 5 */
Kojto 110:165afa46840b 6478
Kojto 110:165afa46840b 6479 /****************** Bit definition for QUADSPI_FCR register ******************/
Kojto 110:165afa46840b 6480 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
Kojto 110:165afa46840b 6481 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
Kojto 110:165afa46840b 6482 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
Kojto 110:165afa46840b 6483 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
Kojto 110:165afa46840b 6484
Kojto 110:165afa46840b 6485 /****************** Bit definition for QUADSPI_DLR register ******************/
Kojto 110:165afa46840b 6486 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
Kojto 110:165afa46840b 6487
Kojto 110:165afa46840b 6488 /****************** Bit definition for QUADSPI_CCR register ******************/
Kojto 110:165afa46840b 6489 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
Kojto 110:165afa46840b 6490 #define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 110:165afa46840b 6491 #define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 110:165afa46840b 6492 #define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 110:165afa46840b 6493 #define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 110:165afa46840b 6494 #define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 110:165afa46840b 6495 #define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
Kojto 110:165afa46840b 6496 #define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
Kojto 110:165afa46840b 6497 #define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
Kojto 110:165afa46840b 6498 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
Kojto 110:165afa46840b 6499 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 110:165afa46840b 6500 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 110:165afa46840b 6501 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
Kojto 110:165afa46840b 6502 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 110:165afa46840b 6503 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 110:165afa46840b 6504 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
Kojto 110:165afa46840b 6505 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 110:165afa46840b 6506 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 110:165afa46840b 6507 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
Kojto 110:165afa46840b 6508 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 110:165afa46840b 6509 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 110:165afa46840b 6510 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
Kojto 110:165afa46840b 6511 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 110:165afa46840b 6512 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 110:165afa46840b 6513 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
Kojto 110:165afa46840b 6514 #define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 110:165afa46840b 6515 #define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 110:165afa46840b 6516 #define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 110:165afa46840b 6517 #define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Kojto 110:165afa46840b 6518 #define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
Kojto 110:165afa46840b 6519 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
Kojto 110:165afa46840b 6520 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 110:165afa46840b 6521 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 110:165afa46840b 6522 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
Kojto 110:165afa46840b 6523 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 110:165afa46840b 6524 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 110:165afa46840b 6525 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
Kojto 110:165afa46840b 6526 #define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
Kojto 110:165afa46840b 6527 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
Kojto 110:165afa46840b 6528 /****************** Bit definition for QUADSPI_AR register *******************/
Kojto 110:165afa46840b 6529 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
Kojto 110:165afa46840b 6530
Kojto 110:165afa46840b 6531 /****************** Bit definition for QUADSPI_ABR register ******************/
Kojto 110:165afa46840b 6532 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
Kojto 110:165afa46840b 6533
Kojto 110:165afa46840b 6534 /****************** Bit definition for QUADSPI_DR register *******************/
Kojto 110:165afa46840b 6535 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
Kojto 110:165afa46840b 6536
Kojto 110:165afa46840b 6537 /****************** Bit definition for QUADSPI_PSMKR register ****************/
Kojto 110:165afa46840b 6538 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
Kojto 110:165afa46840b 6539
Kojto 110:165afa46840b 6540 /****************** Bit definition for QUADSPI_PSMAR register ****************/
Kojto 110:165afa46840b 6541 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
Kojto 110:165afa46840b 6542
Kojto 110:165afa46840b 6543 /****************** Bit definition for QUADSPI_PIR register *****************/
Kojto 110:165afa46840b 6544 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
Kojto 110:165afa46840b 6545
Kojto 110:165afa46840b 6546 /****************** Bit definition for QUADSPI_LPTR register *****************/
Kojto 110:165afa46840b 6547 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
Kojto 110:165afa46840b 6548
Kojto 110:165afa46840b 6549 /******************************************************************************/
Kojto 110:165afa46840b 6550 /* */
Kojto 110:165afa46840b 6551 /* Reset and Clock Control */
Kojto 110:165afa46840b 6552 /* */
Kojto 110:165afa46840b 6553 /******************************************************************************/
Kojto 110:165afa46840b 6554 /******************** Bit definition for RCC_CR register ********************/
Kojto 110:165afa46840b 6555 #define RCC_CR_HSION ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6556 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6557
Kojto 110:165afa46840b 6558 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
Kojto 110:165afa46840b 6559 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
Kojto 110:165afa46840b 6560 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
Kojto 110:165afa46840b 6561 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
Kojto 110:165afa46840b 6562 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
Kojto 110:165afa46840b 6563 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
Kojto 110:165afa46840b 6564
Kojto 110:165afa46840b 6565 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
Kojto 110:165afa46840b 6566 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
Kojto 110:165afa46840b 6567 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
Kojto 110:165afa46840b 6568 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
Kojto 110:165afa46840b 6569 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
Kojto 110:165afa46840b 6570 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
Kojto 110:165afa46840b 6571 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
Kojto 110:165afa46840b 6572 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
Kojto 110:165afa46840b 6573 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
Kojto 110:165afa46840b 6574
Kojto 110:165afa46840b 6575 #define RCC_CR_HSEON ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6576 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6577 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6578 #define RCC_CR_CSSON ((uint32_t)0x00080000)
Kojto 110:165afa46840b 6579 #define RCC_CR_PLLON ((uint32_t)0x01000000)
Kojto 110:165afa46840b 6580 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6581 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6582 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
Kojto 110:165afa46840b 6583 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
Kojto 110:165afa46840b 6584 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6585
Kojto 110:165afa46840b 6586 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 110:165afa46840b 6587 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
Kojto 110:165afa46840b 6588 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6589 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6590 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6591 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6592 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6593 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6594
Kojto 110:165afa46840b 6595 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
Kojto 110:165afa46840b 6596 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6597 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6598 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6599 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6600 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6601 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6602 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6603 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 6604 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6605
Kojto 110:165afa46840b 6606 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
Kojto 110:165afa46840b 6607 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6608 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6609
Kojto 110:165afa46840b 6610 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6611 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6612 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
Kojto 110:165afa46840b 6613
Kojto 110:165afa46840b 6614 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
Kojto 110:165afa46840b 6615 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 6616 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6617 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6618 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 6619
Kojto 110:165afa46840b 6620 #define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
Kojto 110:165afa46840b 6621 #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 6622 #define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6623 #define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 6624
Kojto 110:165afa46840b 6625
Kojto 110:165afa46840b 6626 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 110:165afa46840b 6627 /*!< SW configuration */
Kojto 110:165afa46840b 6628 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 110:165afa46840b 6629 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 110:165afa46840b 6630 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 110:165afa46840b 6631
Kojto 110:165afa46840b 6632 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 110:165afa46840b 6633 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 110:165afa46840b 6634 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 110:165afa46840b 6635
Kojto 110:165afa46840b 6636 /*!< SWS configuration */
Kojto 110:165afa46840b 6637 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 110:165afa46840b 6638 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 110:165afa46840b 6639 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 110:165afa46840b 6640
Kojto 110:165afa46840b 6641 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 110:165afa46840b 6642 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 110:165afa46840b 6643 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 110:165afa46840b 6644
Kojto 110:165afa46840b 6645 /*!< HPRE configuration */
Kojto 110:165afa46840b 6646 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 110:165afa46840b 6647 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 110:165afa46840b 6648 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 110:165afa46840b 6649 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 110:165afa46840b 6650 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 110:165afa46840b 6651
Kojto 110:165afa46840b 6652 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 110:165afa46840b 6653 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 110:165afa46840b 6654 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 110:165afa46840b 6655 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 110:165afa46840b 6656 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 110:165afa46840b 6657 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 110:165afa46840b 6658 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 110:165afa46840b 6659 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 110:165afa46840b 6660 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 110:165afa46840b 6661
Kojto 110:165afa46840b 6662 /*!< PPRE1 configuration */
Kojto 110:165afa46840b 6663 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 110:165afa46840b 6664 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 110:165afa46840b 6665 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 110:165afa46840b 6666 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 110:165afa46840b 6667
Kojto 110:165afa46840b 6668 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 110:165afa46840b 6669 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
Kojto 110:165afa46840b 6670 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
Kojto 110:165afa46840b 6671 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
Kojto 110:165afa46840b 6672 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
Kojto 110:165afa46840b 6673
Kojto 110:165afa46840b 6674 /*!< PPRE2 configuration */
Kojto 110:165afa46840b 6675 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 110:165afa46840b 6676 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
Kojto 110:165afa46840b 6677 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
Kojto 110:165afa46840b 6678 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
Kojto 110:165afa46840b 6679
Kojto 110:165afa46840b 6680 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 110:165afa46840b 6681 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
Kojto 110:165afa46840b 6682 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
Kojto 110:165afa46840b 6683 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
Kojto 110:165afa46840b 6684 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
Kojto 110:165afa46840b 6685
Kojto 110:165afa46840b 6686 /*!< RTCPRE configuration */
Kojto 110:165afa46840b 6687 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
Kojto 110:165afa46840b 6688 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6689 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6690 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6691 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 6692 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6693
Kojto 110:165afa46840b 6694 /*!< MCO1 configuration */
Kojto 110:165afa46840b 6695 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
Kojto 110:165afa46840b 6696 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6697 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6698
Kojto 110:165afa46840b 6699 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
Kojto 110:165afa46840b 6700
Kojto 110:165afa46840b 6701 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
Kojto 110:165afa46840b 6702 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 6703 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6704 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6705
Kojto 110:165afa46840b 6706 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
Kojto 110:165afa46840b 6707 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 6708 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 6709 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6710
Kojto 110:165afa46840b 6711 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
Kojto 110:165afa46840b 6712 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 6713 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 6714
Kojto 110:165afa46840b 6715 /******************** Bit definition for RCC_CIR register *******************/
Kojto 110:165afa46840b 6716 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6717 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6718 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6719 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6720 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6721 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6722 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6723 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6724 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6725 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6726 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6727 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6728 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6729 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
Kojto 110:165afa46840b 6730 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6731 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6732 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6733 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6734 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
Kojto 110:165afa46840b 6735 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6736 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6737 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6738 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
Kojto 110:165afa46840b 6739
Kojto 110:165afa46840b 6740 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 110:165afa46840b 6741 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6742 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6743 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6744 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6745 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6746 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6747 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6748 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6749 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6750 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6751 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6752 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6753 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6754 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6755 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
Kojto 110:165afa46840b 6756 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6757 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6758
Kojto 110:165afa46840b 6759 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 110:165afa46840b 6760 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6761 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6762 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6763
Kojto 110:165afa46840b 6764 /******************** Bit definition for RCC_AHB3RSTR register **************/
Kojto 110:165afa46840b 6765 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6766 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6767
Kojto 110:165afa46840b 6768 /******************** Bit definition for RCC_APB1RSTR register **************/
Kojto 110:165afa46840b 6769 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6770 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6771 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6772 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6773 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6774 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6775 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6776 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6777 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6778 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6779 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6780 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
Kojto 110:165afa46840b 6781 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6782 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6783 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
Kojto 110:165afa46840b 6784 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6785 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6786 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6787 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
Kojto 110:165afa46840b 6788 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6789 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6790 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
Kojto 110:165afa46840b 6791 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6792 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
Kojto 110:165afa46840b 6793 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
Kojto 110:165afa46840b 6794
Kojto 110:165afa46840b 6795 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 110:165afa46840b 6796 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6797 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6798 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6799 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6800 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6801 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6802 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6803 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
Kojto 110:165afa46840b 6804 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6805 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6806 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6807 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6808 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6809 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6810 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6811 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6812 #define RCC_APB2RSTR_DSIRST ((uint32_t)0x08000000)
Kojto 110:165afa46840b 6813
Kojto 110:165afa46840b 6814 /* Old SPI1RST bit definition, maintained for legacy purpose */
Kojto 110:165afa46840b 6815 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
Kojto 110:165afa46840b 6816
Kojto 110:165afa46840b 6817 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 110:165afa46840b 6818 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6819 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6820 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6821 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6822 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6823 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6824 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6825 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6826 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6827 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6828 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6829
Kojto 110:165afa46840b 6830 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6831 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6832 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6833 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6834 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6835 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
Kojto 110:165afa46840b 6836
Kojto 110:165afa46840b 6837 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6838 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6839 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
Kojto 110:165afa46840b 6840 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
Kojto 110:165afa46840b 6841 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6842 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
Kojto 110:165afa46840b 6843
Kojto 110:165afa46840b 6844 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 110:165afa46840b 6845 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6846 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6847 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6848
Kojto 110:165afa46840b 6849 /******************** Bit definition for RCC_AHB3ENR register ***************/
Kojto 110:165afa46840b 6850 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6851 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6852
Kojto 110:165afa46840b 6853 /******************** Bit definition for RCC_APB1ENR register ***************/
Kojto 110:165afa46840b 6854 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6855 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6856 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6857 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6858 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6859 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6860 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6861 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6862 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6863 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6864 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6865 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
Kojto 110:165afa46840b 6866 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6867 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6868 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
Kojto 110:165afa46840b 6869 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6870 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6871 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6872 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
Kojto 110:165afa46840b 6873 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6874 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6875 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
Kojto 110:165afa46840b 6876 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6877 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
Kojto 110:165afa46840b 6878 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
Kojto 110:165afa46840b 6879
Kojto 110:165afa46840b 6880 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 110:165afa46840b 6881 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6882 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6883 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6884 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6885 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6886 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6887 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6888 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6889 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6890 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
Kojto 110:165afa46840b 6891 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6892 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6893 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6894 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6895 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6896 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6897 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6898 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6899 #define RCC_APB2ENR_DSIEN ((uint32_t)0x08000000)
Kojto 110:165afa46840b 6900
Kojto 110:165afa46840b 6901 /******************** Bit definition for RCC_AHB1LPENR register *************/
Kojto 110:165afa46840b 6902 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6903 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6904 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6905 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6906 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6907 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6908 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6909 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6910 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6911 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6912 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6913
Kojto 110:165afa46840b 6914 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6915 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
Kojto 110:165afa46840b 6916 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6917 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6918 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6919 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
Kojto 110:165afa46840b 6920 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6921 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6922 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
Kojto 110:165afa46840b 6923
Kojto 110:165afa46840b 6924 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6925 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6926 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
Kojto 110:165afa46840b 6927 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
Kojto 110:165afa46840b 6928 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6929 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
Kojto 110:165afa46840b 6930
Kojto 110:165afa46840b 6931 /******************** Bit definition for RCC_AHB2LPENR register *************/
Kojto 110:165afa46840b 6932 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6933 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6934 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6935
Kojto 110:165afa46840b 6936 /******************** Bit definition for RCC_AHB3LPENR register *************/
Kojto 110:165afa46840b 6937 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6938 #define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6939
Kojto 110:165afa46840b 6940 /******************** Bit definition for RCC_APB1LPENR register *************/
Kojto 110:165afa46840b 6941 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6942 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6943 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6944 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6945 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6946 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6947 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
Kojto 110:165afa46840b 6948 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
Kojto 110:165afa46840b 6949 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6950 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6951 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6952 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
Kojto 110:165afa46840b 6953 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6954 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6955 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
Kojto 110:165afa46840b 6956 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6957 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6958 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6959 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
Kojto 110:165afa46840b 6960 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
Kojto 110:165afa46840b 6961 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6962 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
Kojto 110:165afa46840b 6963 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
Kojto 110:165afa46840b 6964 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
Kojto 110:165afa46840b 6965 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
Kojto 110:165afa46840b 6966
Kojto 110:165afa46840b 6967 /******************** Bit definition for RCC_APB2LPENR register *************/
Kojto 110:165afa46840b 6968 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6969 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6970 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
Kojto 110:165afa46840b 6971 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
Kojto 110:165afa46840b 6972 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6973 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6974 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
Kojto 110:165afa46840b 6975 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
Kojto 110:165afa46840b 6976 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
Kojto 110:165afa46840b 6977 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
Kojto 110:165afa46840b 6978 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
Kojto 110:165afa46840b 6979 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
Kojto 110:165afa46840b 6980 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
Kojto 110:165afa46840b 6981 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
Kojto 110:165afa46840b 6982 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
Kojto 110:165afa46840b 6983 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
Kojto 110:165afa46840b 6984 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
Kojto 110:165afa46840b 6985 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
Kojto 110:165afa46840b 6986 #define RCC_APB2LPENR_DSILPEN ((uint32_t)0x08000000)
Kojto 110:165afa46840b 6987
Kojto 110:165afa46840b 6988 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 110:165afa46840b 6989 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
Kojto 110:165afa46840b 6990 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
Kojto 110:165afa46840b 6991 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
Kojto 110:165afa46840b 6992 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
Kojto 110:165afa46840b 6993
Kojto 110:165afa46840b 6994 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
Kojto 110:165afa46840b 6995 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 6996 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 6997
Kojto 110:165afa46840b 6998 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
Kojto 110:165afa46840b 6999 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7000
Kojto 110:165afa46840b 7001 /******************** Bit definition for RCC_CSR register *******************/
Kojto 110:165afa46840b 7002 #define RCC_CSR_LSION ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7003 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7004 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
Kojto 110:165afa46840b 7005 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
Kojto 110:165afa46840b 7006 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
Kojto 110:165afa46840b 7007 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
Kojto 110:165afa46840b 7008 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
Kojto 110:165afa46840b 7009 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
Kojto 110:165afa46840b 7010 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
Kojto 110:165afa46840b 7011 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
Kojto 110:165afa46840b 7012
Kojto 110:165afa46840b 7013 /******************** Bit definition for RCC_SSCGR register *****************/
Kojto 110:165afa46840b 7014 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
Kojto 110:165afa46840b 7015 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
Kojto 110:165afa46840b 7016 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
Kojto 110:165afa46840b 7017 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
Kojto 110:165afa46840b 7018
Kojto 110:165afa46840b 7019 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
Kojto 110:165afa46840b 7020 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
Kojto 110:165afa46840b 7021 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7022 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 7023 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7024 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7025 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7026 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7027 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7028 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7029 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7030
Kojto 110:165afa46840b 7031 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
Kojto 110:165afa46840b 7032 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 7033 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 7034 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 7035 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 7036
Kojto 110:165afa46840b 7037 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
Kojto 110:165afa46840b 7038 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 7039 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 7040 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 7041
Kojto 110:165afa46840b 7042
Kojto 110:165afa46840b 7043 /******************** Bit definition for RCC_PLLSAICFGR register ************/
Kojto 110:165afa46840b 7044 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
Kojto 110:165afa46840b 7045 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7046 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 7047 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7048 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7049 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7050 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7051 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7052 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7053 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7054
Kojto 110:165afa46840b 7055 #define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
Kojto 110:165afa46840b 7056 #define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7057 #define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 7058
Kojto 110:165afa46840b 7059 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
Kojto 110:165afa46840b 7060 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 7061 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 7062 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 7063 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 7064
Kojto 110:165afa46840b 7065 #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
Kojto 110:165afa46840b 7066 #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 7067 #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 7068 #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
Kojto 110:165afa46840b 7069
Kojto 110:165afa46840b 7070 /******************** Bit definition for RCC_DCKCFGR register ***************/
Kojto 110:165afa46840b 7071 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
Kojto 110:165afa46840b 7072 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
Kojto 110:165afa46840b 7073 #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
Kojto 110:165afa46840b 7074 #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
Kojto 110:165afa46840b 7075 #define RCC_DCKCFGR_SAI1ASRC_0 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 7076 #define RCC_DCKCFGR_SAI1ASRC_1 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 7077 #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
Kojto 110:165afa46840b 7078 #define RCC_DCKCFGR_SAI1BSRC_0 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 7079 #define RCC_DCKCFGR_SAI1BSRC_1 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 7080 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
Kojto 110:165afa46840b 7081 #define RCC_DCKCFGR_CK48MSEL ((uint32_t)0x08000000)
Kojto 110:165afa46840b 7082 #define RCC_DCKCFGR_SDIOSEL ((uint32_t)0x10000000)
Kojto 110:165afa46840b 7083 #define RCC_DCKCFGR_DSISEL ((uint32_t)0x20000000)
Kojto 110:165afa46840b 7084
Kojto 110:165afa46840b 7085 /******************************************************************************/
Kojto 110:165afa46840b 7086 /* */
Kojto 110:165afa46840b 7087 /* RNG */
Kojto 110:165afa46840b 7088 /* */
Kojto 110:165afa46840b 7089 /******************************************************************************/
Kojto 110:165afa46840b 7090 /******************** Bits definition for RNG_CR register *******************/
Kojto 110:165afa46840b 7091 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7092 #define RNG_CR_IE ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7093
Kojto 110:165afa46840b 7094 /******************** Bits definition for RNG_SR register *******************/
Kojto 110:165afa46840b 7095 #define RNG_SR_DRDY ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7096 #define RNG_SR_CECS ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7097 #define RNG_SR_SECS ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7098 #define RNG_SR_CEIS ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7099 #define RNG_SR_SEIS ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7100
Kojto 110:165afa46840b 7101 /******************************************************************************/
Kojto 110:165afa46840b 7102 /* */
Kojto 110:165afa46840b 7103 /* Real-Time Clock (RTC) */
Kojto 110:165afa46840b 7104 /* */
Kojto 110:165afa46840b 7105 /******************************************************************************/
Kojto 110:165afa46840b 7106 /******************** Bits definition for RTC_TR register *******************/
Kojto 110:165afa46840b 7107 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 110:165afa46840b 7108 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 110:165afa46840b 7109 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 7110 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 7111 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 110:165afa46840b 7112 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7113 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 7114 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 7115 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 7116 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 110:165afa46840b 7117 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7118 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7119 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7120 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 110:165afa46840b 7121 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7122 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7123 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7124 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7125 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 110:165afa46840b 7126 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7127 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7128 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7129 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 110:165afa46840b 7130 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7131 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7132 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7133 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7134
Kojto 110:165afa46840b 7135 /******************** Bits definition for RTC_DR register *******************/
Kojto 110:165afa46840b 7136 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 110:165afa46840b 7137 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 7138 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 7139 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 7140 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 7141 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 110:165afa46840b 7142 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7143 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 7144 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 7145 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 7146 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 110:165afa46840b 7147 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7148 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7149 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 7150 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7151 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 110:165afa46840b 7152 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7153 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7154 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7155 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7156 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 110:165afa46840b 7157 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7158 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7159 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 110:165afa46840b 7160 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7161 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7162 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7163 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7164
Kojto 110:165afa46840b 7165 /******************** Bits definition for RTC_CR register *******************/
Kojto 110:165afa46840b 7166 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 110:165afa46840b 7167 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 110:165afa46840b 7168 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 7169 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 110:165afa46840b 7170 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 110:165afa46840b 7171 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 110:165afa46840b 7172 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 110:165afa46840b 7173 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 110:165afa46840b 7174 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7175 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 110:165afa46840b 7176 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7177 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7178 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7179 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7180 #define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7181 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7182 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7183 #define RTC_CR_DCE ((uint32_t)0x00000080)
Kojto 110:165afa46840b 7184 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7185 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7186 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7187 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7188 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto 110:165afa46840b 7189 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7190 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7191 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7192
Kojto 110:165afa46840b 7193 /******************** Bits definition for RTC_ISR register ******************/
Kojto 110:165afa46840b 7194 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7195 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7196 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7197 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7198 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7199 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7200 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7201 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7202 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 110:165afa46840b 7203 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7204 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7205 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7206 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7207 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7208 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7209 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7210
Kojto 110:165afa46840b 7211 /******************** Bits definition for RTC_PRER register *****************/
Kojto 110:165afa46840b 7212 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 110:165afa46840b 7213 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto 110:165afa46840b 7214
Kojto 110:165afa46840b 7215 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 110:165afa46840b 7216 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto 110:165afa46840b 7217
Kojto 110:165afa46840b 7218 /******************** Bits definition for RTC_CALIBR register ***************/
Kojto 110:165afa46840b 7219 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
Kojto 110:165afa46840b 7220 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
Kojto 110:165afa46840b 7221
Kojto 110:165afa46840b 7222 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 110:165afa46840b 7223 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 7224 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 110:165afa46840b 7225 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 110:165afa46840b 7226 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 7227 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 7228 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 110:165afa46840b 7229 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 7230 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 7231 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 7232 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 7233 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 7234 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 110:165afa46840b 7235 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 110:165afa46840b 7236 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 7237 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 7238 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 110:165afa46840b 7239 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7240 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 7241 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 7242 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 7243 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 7244 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 110:165afa46840b 7245 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7246 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7247 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7248 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 110:165afa46840b 7249 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7250 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7251 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7252 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7253 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 7254 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 110:165afa46840b 7255 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7256 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7257 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7258 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 110:165afa46840b 7259 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7260 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7261 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7262 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7263
Kojto 110:165afa46840b 7264 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 110:165afa46840b 7265 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
Kojto 110:165afa46840b 7266 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
Kojto 110:165afa46840b 7267 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
Kojto 110:165afa46840b 7268 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
Kojto 110:165afa46840b 7269 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
Kojto 110:165afa46840b 7270 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
Kojto 110:165afa46840b 7271 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 7272 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 7273 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 7274 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 7275 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
Kojto 110:165afa46840b 7276 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
Kojto 110:165afa46840b 7277 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
Kojto 110:165afa46840b 7278 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 7279 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 7280 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
Kojto 110:165afa46840b 7281 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7282 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 7283 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 7284 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 7285 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 7286 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
Kojto 110:165afa46840b 7287 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7288 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7289 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7290 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
Kojto 110:165afa46840b 7291 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7292 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7293 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7294 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7295 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 7296 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
Kojto 110:165afa46840b 7297 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7298 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7299 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7300 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
Kojto 110:165afa46840b 7301 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7302 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7303 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7304 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7305
Kojto 110:165afa46840b 7306 /******************** Bits definition for RTC_WPR register ******************/
Kojto 110:165afa46840b 7307 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 110:165afa46840b 7308
Kojto 110:165afa46840b 7309 /******************** Bits definition for RTC_SSR register ******************/
Kojto 110:165afa46840b 7310 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 110:165afa46840b 7311
Kojto 110:165afa46840b 7312 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 110:165afa46840b 7313 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 110:165afa46840b 7314 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 110:165afa46840b 7315
Kojto 110:165afa46840b 7316 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 110:165afa46840b 7317 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 110:165afa46840b 7318 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 110:165afa46840b 7319 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 110:165afa46840b 7320 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 110:165afa46840b 7321 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 110:165afa46840b 7322 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7323 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 110:165afa46840b 7324 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 110:165afa46840b 7325 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 110:165afa46840b 7326 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 110:165afa46840b 7327 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7328 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7329 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7330 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 110:165afa46840b 7331 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7332 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7333 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7334 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7335 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 110:165afa46840b 7336 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7337 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7338 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7339 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 110:165afa46840b 7340 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7341 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7342 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7343 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7344
Kojto 110:165afa46840b 7345 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 110:165afa46840b 7346 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 110:165afa46840b 7347 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7348 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7349 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 110:165afa46840b 7350 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7351 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 110:165afa46840b 7352 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7353 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7354 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7355 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7356 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 110:165afa46840b 7357 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7358 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7359 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 110:165afa46840b 7360 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7361 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7362 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7363 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7364
Kojto 110:165afa46840b 7365 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 110:165afa46840b 7366 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 110:165afa46840b 7367
Kojto 110:165afa46840b 7368 /******************** Bits definition for RTC_CAL register *****************/
Kojto 110:165afa46840b 7369 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 110:165afa46840b 7370 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7371 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7372 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 110:165afa46840b 7373 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7374 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7375 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7376 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7377 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7378 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 7379 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 7380 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 7381 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7382
Kojto 110:165afa46840b 7383 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 110:165afa46840b 7384 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto 110:165afa46840b 7385 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
Kojto 110:165afa46840b 7386 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
Kojto 110:165afa46840b 7387 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 110:165afa46840b 7388 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 110:165afa46840b 7389 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 7390 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 7391 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 110:165afa46840b 7392 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 7393 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 110:165afa46840b 7394 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 110:165afa46840b 7395 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 7396 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 110:165afa46840b 7397 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 110:165afa46840b 7398 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto 110:165afa46840b 7399 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto 110:165afa46840b 7400 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto 110:165afa46840b 7401 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7402 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7403 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7404
Kojto 110:165afa46840b 7405 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 110:165afa46840b 7406 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 110:165afa46840b 7407 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 7408 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 7409 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 7410 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 7411 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 110:165afa46840b 7412
Kojto 110:165afa46840b 7413 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 110:165afa46840b 7414 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
Kojto 110:165afa46840b 7415 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 110:165afa46840b 7416 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 110:165afa46840b 7417 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 110:165afa46840b 7418 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 110:165afa46840b 7419 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
Kojto 110:165afa46840b 7420
Kojto 110:165afa46840b 7421 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 110:165afa46840b 7422 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7423
Kojto 110:165afa46840b 7424 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 110:165afa46840b 7425 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7426
Kojto 110:165afa46840b 7427 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 110:165afa46840b 7428 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7429
Kojto 110:165afa46840b 7430 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 110:165afa46840b 7431 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7432
Kojto 110:165afa46840b 7433 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 110:165afa46840b 7434 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7435
Kojto 110:165afa46840b 7436 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 110:165afa46840b 7437 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7438
Kojto 110:165afa46840b 7439 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 110:165afa46840b 7440 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7441
Kojto 110:165afa46840b 7442 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 110:165afa46840b 7443 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7444
Kojto 110:165afa46840b 7445 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 110:165afa46840b 7446 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7447
Kojto 110:165afa46840b 7448 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 110:165afa46840b 7449 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7450
Kojto 110:165afa46840b 7451 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 110:165afa46840b 7452 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7453
Kojto 110:165afa46840b 7454 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 110:165afa46840b 7455 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7456
Kojto 110:165afa46840b 7457 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 110:165afa46840b 7458 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7459
Kojto 110:165afa46840b 7460 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 110:165afa46840b 7461 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7462
Kojto 110:165afa46840b 7463 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 110:165afa46840b 7464 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7465
Kojto 110:165afa46840b 7466 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 110:165afa46840b 7467 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7468
Kojto 110:165afa46840b 7469 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 110:165afa46840b 7470 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7471
Kojto 110:165afa46840b 7472 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 110:165afa46840b 7473 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7474
Kojto 110:165afa46840b 7475 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 110:165afa46840b 7476 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7477
Kojto 110:165afa46840b 7478 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 110:165afa46840b 7479 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7480
Kojto 110:165afa46840b 7481 /******************************************************************************/
Kojto 110:165afa46840b 7482 /* */
Kojto 110:165afa46840b 7483 /* Serial Audio Interface */
Kojto 110:165afa46840b 7484 /* */
Kojto 110:165afa46840b 7485 /******************************************************************************/
Kojto 110:165afa46840b 7486 /******************** Bit definition for SAI_GCR register *******************/
Kojto 110:165afa46840b 7487 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
Kojto 110:165afa46840b 7488 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 7489 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 7490
Kojto 110:165afa46840b 7491 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
Kojto 110:165afa46840b 7492 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 7493 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 7494
Kojto 110:165afa46840b 7495 /******************* Bit definition for SAI_xCR1 register *******************/
Kojto 110:165afa46840b 7496 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
Kojto 110:165afa46840b 7497 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 7498 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 7499
Kojto 110:165afa46840b 7500 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
Kojto 110:165afa46840b 7501 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 110:165afa46840b 7502 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 110:165afa46840b 7503
Kojto 110:165afa46840b 7504 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
Kojto 110:165afa46840b 7505 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 110:165afa46840b 7506 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 110:165afa46840b 7507 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 110:165afa46840b 7508
Kojto 110:165afa46840b 7509 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
Kojto 110:165afa46840b 7510 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
Kojto 110:165afa46840b 7511
Kojto 110:165afa46840b 7512 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
Kojto 110:165afa46840b 7513 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 110:165afa46840b 7514 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 110:165afa46840b 7515
Kojto 110:165afa46840b 7516 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
Kojto 110:165afa46840b 7517 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
Kojto 110:165afa46840b 7518 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
Kojto 110:165afa46840b 7519 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
Kojto 110:165afa46840b 7520 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
Kojto 110:165afa46840b 7521
Kojto 110:165afa46840b 7522 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
Kojto 110:165afa46840b 7523 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 7524 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 7525 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 110:165afa46840b 7526 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 110:165afa46840b 7527
Kojto 110:165afa46840b 7528 /******************* Bit definition for SAI_xCR2 register *******************/
Kojto 110:165afa46840b 7529 #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
Kojto 110:165afa46840b 7530 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 7531 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 7532 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 7533
Kojto 110:165afa46840b 7534 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
Kojto 110:165afa46840b 7535 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
Kojto 110:165afa46840b 7536 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
Kojto 110:165afa46840b 7537 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
Kojto 110:165afa46840b 7538
Kojto 110:165afa46840b 7539 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
Kojto 110:165afa46840b 7540 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 110:165afa46840b 7541 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 110:165afa46840b 7542 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
Kojto 110:165afa46840b 7543 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
Kojto 110:165afa46840b 7544 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
Kojto 110:165afa46840b 7545 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
Kojto 110:165afa46840b 7546
Kojto 110:165afa46840b 7547 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
Kojto 110:165afa46840b 7548
Kojto 110:165afa46840b 7549 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
Kojto 110:165afa46840b 7550 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 110:165afa46840b 7551 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 110:165afa46840b 7552
Kojto 110:165afa46840b 7553 /****************** Bit definition for SAI_xFRCR register *******************/
Kojto 110:165afa46840b 7554 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
Kojto 110:165afa46840b 7555 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 7556 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 7557 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 7558 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 7559 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 7560 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 110:165afa46840b 7561 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 110:165afa46840b 7562 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 110:165afa46840b 7563
Kojto 110:165afa46840b 7564 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
Kojto 110:165afa46840b 7565 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 7566 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 7567 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 7568 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 7569 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 110:165afa46840b 7570 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 110:165afa46840b 7571 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 110:165afa46840b 7572
Kojto 110:165afa46840b 7573 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
Kojto 110:165afa46840b 7574 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
Kojto 110:165afa46840b 7575 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
Kojto 110:165afa46840b 7576
Kojto 110:165afa46840b 7577 /****************** Bit definition for SAI_xSLOTR register *******************/
Kojto 110:165afa46840b 7578 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
Kojto 110:165afa46840b 7579 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 7580 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 7581 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 7582 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 7583 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 7584
Kojto 110:165afa46840b 7585 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
Kojto 110:165afa46840b 7586 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 110:165afa46840b 7587 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 110:165afa46840b 7588
Kojto 110:165afa46840b 7589 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
Kojto 110:165afa46840b 7590 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 7591 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 7592 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 110:165afa46840b 7593 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 110:165afa46840b 7594
Kojto 110:165afa46840b 7595 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
Kojto 110:165afa46840b 7596
Kojto 110:165afa46840b 7597 /******************* Bit definition for SAI_xIMR register *******************/
Kojto 110:165afa46840b 7598 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
Kojto 110:165afa46840b 7599 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
Kojto 110:165afa46840b 7600 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
Kojto 110:165afa46840b 7601 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
Kojto 110:165afa46840b 7602 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
Kojto 110:165afa46840b 7603 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
Kojto 110:165afa46840b 7604 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
Kojto 110:165afa46840b 7605
Kojto 110:165afa46840b 7606 /******************** Bit definition for SAI_xSR register *******************/
Kojto 110:165afa46840b 7607 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
Kojto 110:165afa46840b 7608 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
Kojto 110:165afa46840b 7609 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
Kojto 110:165afa46840b 7610 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
Kojto 110:165afa46840b 7611 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
Kojto 110:165afa46840b 7612 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
Kojto 110:165afa46840b 7613 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
Kojto 110:165afa46840b 7614
Kojto 110:165afa46840b 7615 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
Kojto 110:165afa46840b 7616 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 7617 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 7618 #define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 7619
Kojto 110:165afa46840b 7620 /****************** Bit definition for SAI_xCLRFR register ******************/
Kojto 110:165afa46840b 7621 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
Kojto 110:165afa46840b 7622 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
Kojto 110:165afa46840b 7623 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
Kojto 110:165afa46840b 7624 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
Kojto 110:165afa46840b 7625 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
Kojto 110:165afa46840b 7626 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
Kojto 110:165afa46840b 7627 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
Kojto 110:165afa46840b 7628
Kojto 110:165afa46840b 7629 /****************** Bit definition for SAI_xDR register ******************/
Kojto 110:165afa46840b 7630 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
Kojto 110:165afa46840b 7631
Kojto 110:165afa46840b 7632
Kojto 110:165afa46840b 7633 /******************************************************************************/
Kojto 110:165afa46840b 7634 /* */
Kojto 110:165afa46840b 7635 /* SD host Interface */
Kojto 110:165afa46840b 7636 /* */
Kojto 110:165afa46840b 7637 /******************************************************************************/
Kojto 110:165afa46840b 7638 /****************** Bit definition for SDIO_POWER register ******************/
Kojto 110:165afa46840b 7639 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 110:165afa46840b 7640 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 110:165afa46840b 7641 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 110:165afa46840b 7642
Kojto 110:165afa46840b 7643 /****************** Bit definition for SDIO_CLKCR register ******************/
Kojto 110:165afa46840b 7644 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
Kojto 110:165afa46840b 7645 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
Kojto 110:165afa46840b 7646 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
Kojto 110:165afa46840b 7647 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
Kojto 110:165afa46840b 7648
Kojto 110:165afa46840b 7649 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 110:165afa46840b 7650 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
Kojto 110:165afa46840b 7651 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
Kojto 110:165afa46840b 7652
Kojto 110:165afa46840b 7653 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
Kojto 110:165afa46840b 7654 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
Kojto 110:165afa46840b 7655
Kojto 110:165afa46840b 7656 /******************* Bit definition for SDIO_ARG register *******************/
Kojto 110:165afa46840b 7657 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
Kojto 110:165afa46840b 7658
Kojto 110:165afa46840b 7659 /******************* Bit definition for SDIO_CMD register *******************/
Kojto 110:165afa46840b 7660 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
Kojto 110:165afa46840b 7661
Kojto 110:165afa46840b 7662 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
Kojto 110:165afa46840b 7663 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
Kojto 110:165afa46840b 7664 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
Kojto 110:165afa46840b 7665
Kojto 110:165afa46840b 7666 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
Kojto 110:165afa46840b 7667 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 110:165afa46840b 7668 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
Kojto 110:165afa46840b 7669 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
Kojto 110:165afa46840b 7670
Kojto 110:165afa46840b 7671 /***************** Bit definition for SDIO_RESPCMD register *****************/
Kojto 110:165afa46840b 7672 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
Kojto 110:165afa46840b 7673
Kojto 110:165afa46840b 7674 /****************** Bit definition for SDIO_RESP0 register ******************/
Kojto 110:165afa46840b 7675 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 110:165afa46840b 7676
Kojto 110:165afa46840b 7677 /****************** Bit definition for SDIO_RESP1 register ******************/
Kojto 110:165afa46840b 7678 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 110:165afa46840b 7679
Kojto 110:165afa46840b 7680 /****************** Bit definition for SDIO_RESP2 register ******************/
Kojto 110:165afa46840b 7681 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 110:165afa46840b 7682
Kojto 110:165afa46840b 7683 /****************** Bit definition for SDIO_RESP3 register ******************/
Kojto 110:165afa46840b 7684 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 110:165afa46840b 7685
Kojto 110:165afa46840b 7686 /****************** Bit definition for SDIO_RESP4 register ******************/
Kojto 110:165afa46840b 7687 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 110:165afa46840b 7688
Kojto 110:165afa46840b 7689 /****************** Bit definition for SDIO_DTIMER register *****************/
Kojto 110:165afa46840b 7690 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
Kojto 110:165afa46840b 7691
Kojto 110:165afa46840b 7692 /****************** Bit definition for SDIO_DLEN register *******************/
Kojto 110:165afa46840b 7693 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
Kojto 110:165afa46840b 7694
Kojto 110:165afa46840b 7695 /****************** Bit definition for SDIO_DCTRL register ******************/
Kojto 110:165afa46840b 7696 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
Kojto 110:165afa46840b 7697 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
Kojto 110:165afa46840b 7698 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
Kojto 110:165afa46840b 7699 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
Kojto 110:165afa46840b 7700
Kojto 110:165afa46840b 7701 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 110:165afa46840b 7702 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 110:165afa46840b 7703 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 110:165afa46840b 7704 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 110:165afa46840b 7705 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 110:165afa46840b 7706
Kojto 110:165afa46840b 7707 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
Kojto 110:165afa46840b 7708 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
Kojto 110:165afa46840b 7709 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
Kojto 110:165afa46840b 7710 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
Kojto 110:165afa46840b 7711
Kojto 110:165afa46840b 7712 /****************** Bit definition for SDIO_DCOUNT register *****************/
Kojto 110:165afa46840b 7713 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
Kojto 110:165afa46840b 7714
Kojto 110:165afa46840b 7715 /****************** Bit definition for SDIO_STA register ********************/
Kojto 110:165afa46840b 7716 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
Kojto 110:165afa46840b 7717 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
Kojto 110:165afa46840b 7718 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
Kojto 110:165afa46840b 7719 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
Kojto 110:165afa46840b 7720 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
Kojto 110:165afa46840b 7721 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
Kojto 110:165afa46840b 7722 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
Kojto 110:165afa46840b 7723 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
Kojto 110:165afa46840b 7724 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
Kojto 110:165afa46840b 7725 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
Kojto 110:165afa46840b 7726 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
Kojto 110:165afa46840b 7727 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
Kojto 110:165afa46840b 7728 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
Kojto 110:165afa46840b 7729 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 110:165afa46840b 7730 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 110:165afa46840b 7731 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
Kojto 110:165afa46840b 7732 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
Kojto 110:165afa46840b 7733 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
Kojto 110:165afa46840b 7734 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
Kojto 110:165afa46840b 7735 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
Kojto 110:165afa46840b 7736 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
Kojto 110:165afa46840b 7737 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
Kojto 110:165afa46840b 7738
Kojto 110:165afa46840b 7739 /******************* Bit definition for SDIO_ICR register *******************/
Kojto 110:165afa46840b 7740 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
Kojto 110:165afa46840b 7741 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
Kojto 110:165afa46840b 7742 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
Kojto 110:165afa46840b 7743 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
Kojto 110:165afa46840b 7744 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
Kojto 110:165afa46840b 7745 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
Kojto 110:165afa46840b 7746 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
Kojto 110:165afa46840b 7747 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
Kojto 110:165afa46840b 7748 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
Kojto 110:165afa46840b 7749 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
Kojto 110:165afa46840b 7750 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
Kojto 110:165afa46840b 7751
Kojto 110:165afa46840b 7752 /****************** Bit definition for SDIO_MASK register *******************/
Kojto 110:165afa46840b 7753 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
Kojto 110:165afa46840b 7754 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
Kojto 110:165afa46840b 7755 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
Kojto 110:165afa46840b 7756 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
Kojto 110:165afa46840b 7757 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
Kojto 110:165afa46840b 7758 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
Kojto 110:165afa46840b 7759 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
Kojto 110:165afa46840b 7760 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
Kojto 110:165afa46840b 7761 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
Kojto 110:165afa46840b 7762 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
Kojto 110:165afa46840b 7763 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
Kojto 110:165afa46840b 7764 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
Kojto 110:165afa46840b 7765 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
Kojto 110:165afa46840b 7766 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
Kojto 110:165afa46840b 7767 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
Kojto 110:165afa46840b 7768 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
Kojto 110:165afa46840b 7769 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
Kojto 110:165afa46840b 7770 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
Kojto 110:165afa46840b 7771 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
Kojto 110:165afa46840b 7772 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
Kojto 110:165afa46840b 7773 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
Kojto 110:165afa46840b 7774 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
Kojto 110:165afa46840b 7775
Kojto 110:165afa46840b 7776 /***************** Bit definition for SDIO_FIFOCNT register *****************/
Kojto 110:165afa46840b 7777 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
Kojto 110:165afa46840b 7778
Kojto 110:165afa46840b 7779 /****************** Bit definition for SDIO_FIFO register *******************/
Kojto 110:165afa46840b 7780 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
Kojto 110:165afa46840b 7781
Kojto 110:165afa46840b 7782 /******************************************************************************/
Kojto 110:165afa46840b 7783 /* */
Kojto 110:165afa46840b 7784 /* Serial Peripheral Interface */
Kojto 110:165afa46840b 7785 /* */
Kojto 110:165afa46840b 7786 /******************************************************************************/
Kojto 110:165afa46840b 7787 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 110:165afa46840b 7788 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
Kojto 110:165afa46840b 7789 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
Kojto 110:165afa46840b 7790 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
Kojto 110:165afa46840b 7791
Kojto 110:165afa46840b 7792 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
Kojto 110:165afa46840b 7793 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 110:165afa46840b 7794 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 110:165afa46840b 7795 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 110:165afa46840b 7796
Kojto 110:165afa46840b 7797 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
Kojto 110:165afa46840b 7798 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
Kojto 110:165afa46840b 7799 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
Kojto 110:165afa46840b 7800 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
Kojto 110:165afa46840b 7801 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
Kojto 110:165afa46840b 7802 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
Kojto 110:165afa46840b 7803 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
Kojto 110:165afa46840b 7804 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
Kojto 110:165afa46840b 7805 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
Kojto 110:165afa46840b 7806 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
Kojto 110:165afa46840b 7807
Kojto 110:165afa46840b 7808 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 110:165afa46840b 7809 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
Kojto 110:165afa46840b 7810 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
Kojto 110:165afa46840b 7811 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
Kojto 110:165afa46840b 7812 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
Kojto 110:165afa46840b 7813 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
Kojto 110:165afa46840b 7814 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
Kojto 110:165afa46840b 7815 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
Kojto 110:165afa46840b 7816
Kojto 110:165afa46840b 7817 /******************** Bit definition for SPI_SR register ********************/
Kojto 110:165afa46840b 7818 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
Kojto 110:165afa46840b 7819 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
Kojto 110:165afa46840b 7820 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
Kojto 110:165afa46840b 7821 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
Kojto 110:165afa46840b 7822 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
Kojto 110:165afa46840b 7823 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
Kojto 110:165afa46840b 7824 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
Kojto 110:165afa46840b 7825 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
Kojto 110:165afa46840b 7826 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
Kojto 110:165afa46840b 7827
Kojto 110:165afa46840b 7828 /******************** Bit definition for SPI_DR register ********************/
Kojto 110:165afa46840b 7829 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
Kojto 110:165afa46840b 7830
Kojto 110:165afa46840b 7831 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 110:165afa46840b 7832 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
Kojto 110:165afa46840b 7833
Kojto 110:165afa46840b 7834 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 110:165afa46840b 7835 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
Kojto 110:165afa46840b 7836
Kojto 110:165afa46840b 7837 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 110:165afa46840b 7838 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
Kojto 110:165afa46840b 7839
Kojto 110:165afa46840b 7840 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 110:165afa46840b 7841 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
Kojto 110:165afa46840b 7842
Kojto 110:165afa46840b 7843 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 110:165afa46840b 7844 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 110:165afa46840b 7845 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 110:165afa46840b 7846
Kojto 110:165afa46840b 7847 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
Kojto 110:165afa46840b 7848
Kojto 110:165afa46840b 7849 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 110:165afa46840b 7850 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 7851 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 7852
Kojto 110:165afa46840b 7853 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
Kojto 110:165afa46840b 7854
Kojto 110:165afa46840b 7855 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 110:165afa46840b 7856 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 110:165afa46840b 7857 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 110:165afa46840b 7858
Kojto 110:165afa46840b 7859 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
Kojto 110:165afa46840b 7860 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
Kojto 110:165afa46840b 7861 #define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
Kojto 110:165afa46840b 7862
Kojto 110:165afa46840b 7863 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 110:165afa46840b 7864 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
Kojto 110:165afa46840b 7865 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
Kojto 110:165afa46840b 7866 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
Kojto 110:165afa46840b 7867
Kojto 110:165afa46840b 7868 /******************************************************************************/
Kojto 110:165afa46840b 7869 /* */
Kojto 110:165afa46840b 7870 /* SYSCFG */
Kojto 110:165afa46840b 7871 /* */
Kojto 110:165afa46840b 7872 /******************************************************************************/
Kojto 110:165afa46840b 7873 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 110:165afa46840b 7874 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
Kojto 110:165afa46840b 7875 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 7876 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 7877 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 7878
Kojto 110:165afa46840b 7879 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
Kojto 110:165afa46840b 7880 #define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
Kojto 110:165afa46840b 7881
Kojto 110:165afa46840b 7882 /****************** Bit definition for SYSCFG_PMC register ******************/
Kojto 110:165afa46840b 7883 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
Kojto 110:165afa46840b 7884 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
Kojto 110:165afa46840b 7885 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
Kojto 110:165afa46840b 7886 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
Kojto 110:165afa46840b 7887
Kojto 110:165afa46840b 7888 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
Kojto 110:165afa46840b 7889
Kojto 110:165afa46840b 7890 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 110:165afa46840b 7891 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
Kojto 110:165afa46840b 7892 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
Kojto 110:165afa46840b 7893 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
Kojto 110:165afa46840b 7894 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
Kojto 110:165afa46840b 7895 /**
Kojto 110:165afa46840b 7896 * @brief EXTI0 configuration
Kojto 110:165afa46840b 7897 */
Kojto 110:165afa46840b 7898 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
Kojto 110:165afa46840b 7899 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
Kojto 110:165afa46840b 7900 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
Kojto 110:165afa46840b 7901 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
Kojto 110:165afa46840b 7902 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
Kojto 110:165afa46840b 7903 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
Kojto 110:165afa46840b 7904 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
Kojto 110:165afa46840b 7905 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
Kojto 110:165afa46840b 7906 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
Kojto 110:165afa46840b 7907 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
Kojto 110:165afa46840b 7908 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
Kojto 110:165afa46840b 7909
Kojto 110:165afa46840b 7910 /**
Kojto 110:165afa46840b 7911 * @brief EXTI1 configuration
Kojto 110:165afa46840b 7912 */
Kojto 110:165afa46840b 7913 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
Kojto 110:165afa46840b 7914 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
Kojto 110:165afa46840b 7915 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
Kojto 110:165afa46840b 7916 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
Kojto 110:165afa46840b 7917 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
Kojto 110:165afa46840b 7918 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
Kojto 110:165afa46840b 7919 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
Kojto 110:165afa46840b 7920 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
Kojto 110:165afa46840b 7921 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
Kojto 110:165afa46840b 7922 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
Kojto 110:165afa46840b 7923 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
Kojto 110:165afa46840b 7924
Kojto 110:165afa46840b 7925
Kojto 110:165afa46840b 7926 /**
Kojto 110:165afa46840b 7927 * @brief EXTI2 configuration
Kojto 110:165afa46840b 7928 */
Kojto 110:165afa46840b 7929 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
Kojto 110:165afa46840b 7930 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
Kojto 110:165afa46840b 7931 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
Kojto 110:165afa46840b 7932 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
Kojto 110:165afa46840b 7933 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
Kojto 110:165afa46840b 7934 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
Kojto 110:165afa46840b 7935 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
Kojto 110:165afa46840b 7936 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
Kojto 110:165afa46840b 7937 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
Kojto 110:165afa46840b 7938 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
Kojto 110:165afa46840b 7939 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
Kojto 110:165afa46840b 7940
Kojto 110:165afa46840b 7941
Kojto 110:165afa46840b 7942 /**
Kojto 110:165afa46840b 7943 * @brief EXTI3 configuration
Kojto 110:165afa46840b 7944 */
Kojto 110:165afa46840b 7945 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
Kojto 110:165afa46840b 7946 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
Kojto 110:165afa46840b 7947 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
Kojto 110:165afa46840b 7948 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
Kojto 110:165afa46840b 7949 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
Kojto 110:165afa46840b 7950 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
Kojto 110:165afa46840b 7951 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
Kojto 110:165afa46840b 7952 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
Kojto 110:165afa46840b 7953 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
Kojto 110:165afa46840b 7954 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
Kojto 110:165afa46840b 7955 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
Kojto 110:165afa46840b 7956
Kojto 110:165afa46840b 7957
Kojto 110:165afa46840b 7958 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 110:165afa46840b 7959 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
Kojto 110:165afa46840b 7960 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
Kojto 110:165afa46840b 7961 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
Kojto 110:165afa46840b 7962 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
Kojto 110:165afa46840b 7963 /**
Kojto 110:165afa46840b 7964 * @brief EXTI4 configuration
Kojto 110:165afa46840b 7965 */
Kojto 110:165afa46840b 7966 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
Kojto 110:165afa46840b 7967 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
Kojto 110:165afa46840b 7968 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
Kojto 110:165afa46840b 7969 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
Kojto 110:165afa46840b 7970 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
Kojto 110:165afa46840b 7971 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
Kojto 110:165afa46840b 7972 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
Kojto 110:165afa46840b 7973 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
Kojto 110:165afa46840b 7974 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
Kojto 110:165afa46840b 7975 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
Kojto 110:165afa46840b 7976 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
Kojto 110:165afa46840b 7977
Kojto 110:165afa46840b 7978 /**
Kojto 110:165afa46840b 7979 * @brief EXTI5 configuration
Kojto 110:165afa46840b 7980 */
Kojto 110:165afa46840b 7981 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
Kojto 110:165afa46840b 7982 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
Kojto 110:165afa46840b 7983 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
Kojto 110:165afa46840b 7984 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
Kojto 110:165afa46840b 7985 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
Kojto 110:165afa46840b 7986 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
Kojto 110:165afa46840b 7987 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
Kojto 110:165afa46840b 7988 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
Kojto 110:165afa46840b 7989 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
Kojto 110:165afa46840b 7990 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
Kojto 110:165afa46840b 7991 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
Kojto 110:165afa46840b 7992
Kojto 110:165afa46840b 7993 /**
Kojto 110:165afa46840b 7994 * @brief EXTI6 configuration
Kojto 110:165afa46840b 7995 */
Kojto 110:165afa46840b 7996 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
Kojto 110:165afa46840b 7997 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
Kojto 110:165afa46840b 7998 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
Kojto 110:165afa46840b 7999 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
Kojto 110:165afa46840b 8000 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
Kojto 110:165afa46840b 8001 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
Kojto 110:165afa46840b 8002 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
Kojto 110:165afa46840b 8003 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
Kojto 110:165afa46840b 8004 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
Kojto 110:165afa46840b 8005 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
Kojto 110:165afa46840b 8006 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
Kojto 110:165afa46840b 8007
Kojto 110:165afa46840b 8008
Kojto 110:165afa46840b 8009 /**
Kojto 110:165afa46840b 8010 * @brief EXTI7 configuration
Kojto 110:165afa46840b 8011 */
Kojto 110:165afa46840b 8012 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
Kojto 110:165afa46840b 8013 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
Kojto 110:165afa46840b 8014 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
Kojto 110:165afa46840b 8015 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
Kojto 110:165afa46840b 8016 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
Kojto 110:165afa46840b 8017 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
Kojto 110:165afa46840b 8018 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
Kojto 110:165afa46840b 8019 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
Kojto 110:165afa46840b 8020 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
Kojto 110:165afa46840b 8021 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
Kojto 110:165afa46840b 8022 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
Kojto 110:165afa46840b 8023
Kojto 110:165afa46840b 8024 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 110:165afa46840b 8025 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
Kojto 110:165afa46840b 8026 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
Kojto 110:165afa46840b 8027 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
Kojto 110:165afa46840b 8028 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
Kojto 110:165afa46840b 8029
Kojto 110:165afa46840b 8030 /**
Kojto 110:165afa46840b 8031 * @brief EXTI8 configuration
Kojto 110:165afa46840b 8032 */
Kojto 110:165afa46840b 8033 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
Kojto 110:165afa46840b 8034 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
Kojto 110:165afa46840b 8035 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
Kojto 110:165afa46840b 8036 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
Kojto 110:165afa46840b 8037 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
Kojto 110:165afa46840b 8038 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
Kojto 110:165afa46840b 8039 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
Kojto 110:165afa46840b 8040 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
Kojto 110:165afa46840b 8041 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
Kojto 110:165afa46840b 8042 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
Kojto 110:165afa46840b 8043
Kojto 110:165afa46840b 8044 /**
Kojto 110:165afa46840b 8045 * @brief EXTI9 configuration
Kojto 110:165afa46840b 8046 */
Kojto 110:165afa46840b 8047 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
Kojto 110:165afa46840b 8048 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
Kojto 110:165afa46840b 8049 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
Kojto 110:165afa46840b 8050 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
Kojto 110:165afa46840b 8051 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
Kojto 110:165afa46840b 8052 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
Kojto 110:165afa46840b 8053 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
Kojto 110:165afa46840b 8054 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
Kojto 110:165afa46840b 8055 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
Kojto 110:165afa46840b 8056 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
Kojto 110:165afa46840b 8057
Kojto 110:165afa46840b 8058
Kojto 110:165afa46840b 8059 /**
Kojto 110:165afa46840b 8060 * @brief EXTI10 configuration
Kojto 110:165afa46840b 8061 */
Kojto 110:165afa46840b 8062 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
Kojto 110:165afa46840b 8063 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
Kojto 110:165afa46840b 8064 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
Kojto 110:165afa46840b 8065 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
Kojto 110:165afa46840b 8066 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
Kojto 110:165afa46840b 8067 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
Kojto 110:165afa46840b 8068 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
Kojto 110:165afa46840b 8069 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
Kojto 110:165afa46840b 8070 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
Kojto 110:165afa46840b 8071 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
Kojto 110:165afa46840b 8072
Kojto 110:165afa46840b 8073
Kojto 110:165afa46840b 8074 /**
Kojto 110:165afa46840b 8075 * @brief EXTI11 configuration
Kojto 110:165afa46840b 8076 */
Kojto 110:165afa46840b 8077 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
Kojto 110:165afa46840b 8078 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
Kojto 110:165afa46840b 8079 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
Kojto 110:165afa46840b 8080 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
Kojto 110:165afa46840b 8081 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
Kojto 110:165afa46840b 8082 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
Kojto 110:165afa46840b 8083 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
Kojto 110:165afa46840b 8084 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
Kojto 110:165afa46840b 8085 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
Kojto 110:165afa46840b 8086 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
Kojto 110:165afa46840b 8087
Kojto 110:165afa46840b 8088
Kojto 110:165afa46840b 8089 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 110:165afa46840b 8090 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
Kojto 110:165afa46840b 8091 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
Kojto 110:165afa46840b 8092 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
Kojto 110:165afa46840b 8093 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
Kojto 110:165afa46840b 8094 /**
Kojto 110:165afa46840b 8095 * @brief EXTI12 configuration
Kojto 110:165afa46840b 8096 */
Kojto 110:165afa46840b 8097 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
Kojto 110:165afa46840b 8098 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
Kojto 110:165afa46840b 8099 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
Kojto 110:165afa46840b 8100 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
Kojto 110:165afa46840b 8101 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
Kojto 110:165afa46840b 8102 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
Kojto 110:165afa46840b 8103 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
Kojto 110:165afa46840b 8104 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
Kojto 110:165afa46840b 8105 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
Kojto 110:165afa46840b 8106 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
Kojto 110:165afa46840b 8107
Kojto 110:165afa46840b 8108
Kojto 110:165afa46840b 8109 /**
Kojto 110:165afa46840b 8110 * @brief EXTI13 configuration
Kojto 110:165afa46840b 8111 */
Kojto 110:165afa46840b 8112 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
Kojto 110:165afa46840b 8113 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
Kojto 110:165afa46840b 8114 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
Kojto 110:165afa46840b 8115 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
Kojto 110:165afa46840b 8116 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
Kojto 110:165afa46840b 8117 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
Kojto 110:165afa46840b 8118 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
Kojto 110:165afa46840b 8119 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
Kojto 110:165afa46840b 8120 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
Kojto 110:165afa46840b 8121 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
Kojto 110:165afa46840b 8122
Kojto 110:165afa46840b 8123
Kojto 110:165afa46840b 8124 /**
Kojto 110:165afa46840b 8125 * @brief EXTI14 configuration
Kojto 110:165afa46840b 8126 */
Kojto 110:165afa46840b 8127 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
Kojto 110:165afa46840b 8128 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
Kojto 110:165afa46840b 8129 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
Kojto 110:165afa46840b 8130 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
Kojto 110:165afa46840b 8131 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
Kojto 110:165afa46840b 8132 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
Kojto 110:165afa46840b 8133 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
Kojto 110:165afa46840b 8134 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
Kojto 110:165afa46840b 8135 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
Kojto 110:165afa46840b 8136 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
Kojto 110:165afa46840b 8137
Kojto 110:165afa46840b 8138
Kojto 110:165afa46840b 8139 /**
Kojto 110:165afa46840b 8140 * @brief EXTI15 configuration
Kojto 110:165afa46840b 8141 */
Kojto 110:165afa46840b 8142 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
Kojto 110:165afa46840b 8143 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
Kojto 110:165afa46840b 8144 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
Kojto 110:165afa46840b 8145 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
Kojto 110:165afa46840b 8146 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
Kojto 110:165afa46840b 8147 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
Kojto 110:165afa46840b 8148 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
Kojto 110:165afa46840b 8149 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
Kojto 110:165afa46840b 8150 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
Kojto 110:165afa46840b 8151 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
Kojto 110:165afa46840b 8152
Kojto 110:165afa46840b 8153 /****************** Bit definition for SYSCFG_CMPCR register ****************/
Kojto 110:165afa46840b 8154 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
Kojto 110:165afa46840b 8155 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
Kojto 110:165afa46840b 8156
Kojto 110:165afa46840b 8157 /******************************************************************************/
Kojto 110:165afa46840b 8158 /* */
Kojto 110:165afa46840b 8159 /* TIM */
Kojto 110:165afa46840b 8160 /* */
Kojto 110:165afa46840b 8161 /******************************************************************************/
Kojto 110:165afa46840b 8162 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 110:165afa46840b 8163 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
Kojto 110:165afa46840b 8164 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
Kojto 110:165afa46840b 8165 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
Kojto 110:165afa46840b 8166 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
Kojto 110:165afa46840b 8167 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
Kojto 110:165afa46840b 8168
Kojto 110:165afa46840b 8169 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 110:165afa46840b 8170 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
Kojto 110:165afa46840b 8171 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
Kojto 110:165afa46840b 8172
Kojto 110:165afa46840b 8173 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
Kojto 110:165afa46840b 8174
Kojto 110:165afa46840b 8175 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
Kojto 110:165afa46840b 8176 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 110:165afa46840b 8177 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 110:165afa46840b 8178
Kojto 110:165afa46840b 8179 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 110:165afa46840b 8180 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
Kojto 110:165afa46840b 8181 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
Kojto 110:165afa46840b 8182 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
Kojto 110:165afa46840b 8183
Kojto 110:165afa46840b 8184 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 110:165afa46840b 8185 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 110:165afa46840b 8186 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 110:165afa46840b 8187 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 110:165afa46840b 8188
Kojto 110:165afa46840b 8189 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
Kojto 110:165afa46840b 8190 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
Kojto 110:165afa46840b 8191 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
Kojto 110:165afa46840b 8192 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
Kojto 110:165afa46840b 8193 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
Kojto 110:165afa46840b 8194 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
Kojto 110:165afa46840b 8195 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
Kojto 110:165afa46840b 8196 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
Kojto 110:165afa46840b 8197
Kojto 110:165afa46840b 8198 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 110:165afa46840b 8199 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 110:165afa46840b 8200 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 110:165afa46840b 8201 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 110:165afa46840b 8202 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 110:165afa46840b 8203
Kojto 110:165afa46840b 8204 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 110:165afa46840b 8205 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 110:165afa46840b 8206 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 110:165afa46840b 8207 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 110:165afa46840b 8208
Kojto 110:165afa46840b 8209 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
Kojto 110:165afa46840b 8210
Kojto 110:165afa46840b 8211 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 110:165afa46840b 8212 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 110:165afa46840b 8213 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 110:165afa46840b 8214 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 110:165afa46840b 8215 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 110:165afa46840b 8216
Kojto 110:165afa46840b 8217 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 110:165afa46840b 8218 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 110:165afa46840b 8219 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 110:165afa46840b 8220
Kojto 110:165afa46840b 8221 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
Kojto 110:165afa46840b 8222 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
Kojto 110:165afa46840b 8223
Kojto 110:165afa46840b 8224 /******************* Bit definition for TIM_DIER register *******************/
Kojto 110:165afa46840b 8225 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
Kojto 110:165afa46840b 8226 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
Kojto 110:165afa46840b 8227 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
Kojto 110:165afa46840b 8228 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
Kojto 110:165afa46840b 8229 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
Kojto 110:165afa46840b 8230 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
Kojto 110:165afa46840b 8231 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
Kojto 110:165afa46840b 8232 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
Kojto 110:165afa46840b 8233 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
Kojto 110:165afa46840b 8234 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
Kojto 110:165afa46840b 8235 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
Kojto 110:165afa46840b 8236 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
Kojto 110:165afa46840b 8237 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
Kojto 110:165afa46840b 8238 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
Kojto 110:165afa46840b 8239 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
Kojto 110:165afa46840b 8240
Kojto 110:165afa46840b 8241 /******************** Bit definition for TIM_SR register ********************/
Kojto 110:165afa46840b 8242 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
Kojto 110:165afa46840b 8243 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 110:165afa46840b 8244 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 110:165afa46840b 8245 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 110:165afa46840b 8246 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 110:165afa46840b 8247 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
Kojto 110:165afa46840b 8248 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
Kojto 110:165afa46840b 8249 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
Kojto 110:165afa46840b 8250 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 110:165afa46840b 8251 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 110:165afa46840b 8252 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 110:165afa46840b 8253 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 110:165afa46840b 8254
Kojto 110:165afa46840b 8255 /******************* Bit definition for TIM_EGR register ********************/
Kojto 110:165afa46840b 8256 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
Kojto 110:165afa46840b 8257 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
Kojto 110:165afa46840b 8258 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
Kojto 110:165afa46840b 8259 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
Kojto 110:165afa46840b 8260 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
Kojto 110:165afa46840b 8261 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
Kojto 110:165afa46840b 8262 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
Kojto 110:165afa46840b 8263 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
Kojto 110:165afa46840b 8264
Kojto 110:165afa46840b 8265 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 110:165afa46840b 8266 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 110:165afa46840b 8267 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 110:165afa46840b 8268 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 110:165afa46840b 8269
Kojto 110:165afa46840b 8270 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
Kojto 110:165afa46840b 8271 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
Kojto 110:165afa46840b 8272
Kojto 110:165afa46840b 8273 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 110:165afa46840b 8274 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 110:165afa46840b 8275 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 110:165afa46840b 8276 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 110:165afa46840b 8277
Kojto 110:165afa46840b 8278 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
Kojto 110:165afa46840b 8279
Kojto 110:165afa46840b 8280 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 110:165afa46840b 8281 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 110:165afa46840b 8282 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 110:165afa46840b 8283
Kojto 110:165afa46840b 8284 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
Kojto 110:165afa46840b 8285 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
Kojto 110:165afa46840b 8286
Kojto 110:165afa46840b 8287 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 110:165afa46840b 8288 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 110:165afa46840b 8289 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 110:165afa46840b 8290 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 110:165afa46840b 8291
Kojto 110:165afa46840b 8292 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
Kojto 110:165afa46840b 8293
Kojto 110:165afa46840b 8294 /*----------------------------------------------------------------------------*/
Kojto 110:165afa46840b 8295
Kojto 110:165afa46840b 8296 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 110:165afa46840b 8297 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 110:165afa46840b 8298 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 110:165afa46840b 8299
Kojto 110:165afa46840b 8300 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 110:165afa46840b 8301 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 110:165afa46840b 8302 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 110:165afa46840b 8303 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 110:165afa46840b 8304 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 110:165afa46840b 8305
Kojto 110:165afa46840b 8306 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 110:165afa46840b 8307 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 110:165afa46840b 8308 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 110:165afa46840b 8309
Kojto 110:165afa46840b 8310 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 110:165afa46840b 8311 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 110:165afa46840b 8312 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 110:165afa46840b 8313 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 110:165afa46840b 8314 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 110:165afa46840b 8315
Kojto 110:165afa46840b 8316 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 110:165afa46840b 8317 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 110:165afa46840b 8318 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 110:165afa46840b 8319 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 110:165afa46840b 8320
Kojto 110:165afa46840b 8321 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
Kojto 110:165afa46840b 8322 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
Kojto 110:165afa46840b 8323
Kojto 110:165afa46840b 8324 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 110:165afa46840b 8325 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 110:165afa46840b 8326 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 110:165afa46840b 8327 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 110:165afa46840b 8328
Kojto 110:165afa46840b 8329 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
Kojto 110:165afa46840b 8330
Kojto 110:165afa46840b 8331 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 110:165afa46840b 8332 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 110:165afa46840b 8333 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 110:165afa46840b 8334
Kojto 110:165afa46840b 8335 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
Kojto 110:165afa46840b 8336 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
Kojto 110:165afa46840b 8337
Kojto 110:165afa46840b 8338 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 110:165afa46840b 8339 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 110:165afa46840b 8340 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 110:165afa46840b 8341 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 110:165afa46840b 8342
Kojto 110:165afa46840b 8343 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
Kojto 110:165afa46840b 8344
Kojto 110:165afa46840b 8345 /*----------------------------------------------------------------------------*/
Kojto 110:165afa46840b 8346
Kojto 110:165afa46840b 8347 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 110:165afa46840b 8348 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 110:165afa46840b 8349 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 110:165afa46840b 8350
Kojto 110:165afa46840b 8351 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 110:165afa46840b 8352 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 110:165afa46840b 8353 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 110:165afa46840b 8354 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 110:165afa46840b 8355 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 110:165afa46840b 8356
Kojto 110:165afa46840b 8357 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 110:165afa46840b 8358 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 110:165afa46840b 8359 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 110:165afa46840b 8360
Kojto 110:165afa46840b 8361 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 110:165afa46840b 8362 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 110:165afa46840b 8363 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 110:165afa46840b 8364 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 110:165afa46840b 8365 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 110:165afa46840b 8366
Kojto 110:165afa46840b 8367 /******************* Bit definition for TIM_CCER register *******************/
Kojto 110:165afa46840b 8368 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
Kojto 110:165afa46840b 8369 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
Kojto 110:165afa46840b 8370 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 110:165afa46840b 8371 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 110:165afa46840b 8372 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
Kojto 110:165afa46840b 8373 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
Kojto 110:165afa46840b 8374 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 110:165afa46840b 8375 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 110:165afa46840b 8376 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
Kojto 110:165afa46840b 8377 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
Kojto 110:165afa46840b 8378 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 110:165afa46840b 8379 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 110:165afa46840b 8380 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
Kojto 110:165afa46840b 8381 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
Kojto 110:165afa46840b 8382 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 110:165afa46840b 8383
Kojto 110:165afa46840b 8384 /******************* Bit definition for TIM_CNT register ********************/
Kojto 110:165afa46840b 8385 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
Kojto 110:165afa46840b 8386
Kojto 110:165afa46840b 8387 /******************* Bit definition for TIM_PSC register ********************/
Kojto 110:165afa46840b 8388 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
Kojto 110:165afa46840b 8389
Kojto 110:165afa46840b 8390 /******************* Bit definition for TIM_ARR register ********************/
Kojto 110:165afa46840b 8391 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
Kojto 110:165afa46840b 8392
Kojto 110:165afa46840b 8393 /******************* Bit definition for TIM_RCR register ********************/
Kojto 110:165afa46840b 8394 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
Kojto 110:165afa46840b 8395
Kojto 110:165afa46840b 8396 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 110:165afa46840b 8397 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
Kojto 110:165afa46840b 8398
Kojto 110:165afa46840b 8399 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 110:165afa46840b 8400 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
Kojto 110:165afa46840b 8401
Kojto 110:165afa46840b 8402 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 110:165afa46840b 8403 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
Kojto 110:165afa46840b 8404
Kojto 110:165afa46840b 8405 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 110:165afa46840b 8406 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
Kojto 110:165afa46840b 8407
Kojto 110:165afa46840b 8408 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 110:165afa46840b 8409 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 110:165afa46840b 8410 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 110:165afa46840b 8411 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 110:165afa46840b 8412 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 110:165afa46840b 8413 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 110:165afa46840b 8414 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 110:165afa46840b 8415 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 110:165afa46840b 8416 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 110:165afa46840b 8417 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
Kojto 110:165afa46840b 8418
Kojto 110:165afa46840b 8419 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 110:165afa46840b 8420 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 110:165afa46840b 8421 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 110:165afa46840b 8422
Kojto 110:165afa46840b 8423 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
Kojto 110:165afa46840b 8424 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
Kojto 110:165afa46840b 8425 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
Kojto 110:165afa46840b 8426 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
Kojto 110:165afa46840b 8427 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
Kojto 110:165afa46840b 8428 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
Kojto 110:165afa46840b 8429
Kojto 110:165afa46840b 8430 /******************* Bit definition for TIM_DCR register ********************/
Kojto 110:165afa46840b 8431 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 110:165afa46840b 8432 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 110:165afa46840b 8433 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 110:165afa46840b 8434 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 110:165afa46840b 8435 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 110:165afa46840b 8436 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 110:165afa46840b 8437
Kojto 110:165afa46840b 8438 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 110:165afa46840b 8439 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 110:165afa46840b 8440 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 110:165afa46840b 8441 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 110:165afa46840b 8442 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 110:165afa46840b 8443 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
Kojto 110:165afa46840b 8444
Kojto 110:165afa46840b 8445 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 110:165afa46840b 8446 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
Kojto 110:165afa46840b 8447
Kojto 110:165afa46840b 8448 /******************* Bit definition for TIM_OR register *********************/
Kojto 110:165afa46840b 8449 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
Kojto 110:165afa46840b 8450 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
Kojto 110:165afa46840b 8451 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
Kojto 110:165afa46840b 8452 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
Kojto 110:165afa46840b 8453 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 110:165afa46840b 8454 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 110:165afa46840b 8455
Kojto 110:165afa46840b 8456
Kojto 110:165afa46840b 8457 /******************************************************************************/
Kojto 110:165afa46840b 8458 /* */
Kojto 110:165afa46840b 8459 /* Universal Synchronous Asynchronous Receiver Transmitter */
Kojto 110:165afa46840b 8460 /* */
Kojto 110:165afa46840b 8461 /******************************************************************************/
Kojto 110:165afa46840b 8462 /******************* Bit definition for USART_SR register *******************/
Kojto 110:165afa46840b 8463 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
Kojto 110:165afa46840b 8464 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
Kojto 110:165afa46840b 8465 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
Kojto 110:165afa46840b 8466 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
Kojto 110:165afa46840b 8467 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
Kojto 110:165afa46840b 8468 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
Kojto 110:165afa46840b 8469 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
Kojto 110:165afa46840b 8470 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
Kojto 110:165afa46840b 8471 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
Kojto 110:165afa46840b 8472 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
Kojto 110:165afa46840b 8473
Kojto 110:165afa46840b 8474 /******************* Bit definition for USART_DR register *******************/
Kojto 110:165afa46840b 8475 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
Kojto 110:165afa46840b 8476
Kojto 110:165afa46840b 8477 /****************** Bit definition for USART_BRR register *******************/
Kojto 110:165afa46840b 8478 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
Kojto 110:165afa46840b 8479 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
Kojto 110:165afa46840b 8480
Kojto 110:165afa46840b 8481 /****************** Bit definition for USART_CR1 register *******************/
Kojto 110:165afa46840b 8482 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
Kojto 110:165afa46840b 8483 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
Kojto 110:165afa46840b 8484 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
Kojto 110:165afa46840b 8485 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
Kojto 110:165afa46840b 8486 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
Kojto 110:165afa46840b 8487 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
Kojto 110:165afa46840b 8488 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
Kojto 110:165afa46840b 8489 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
Kojto 110:165afa46840b 8490 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
Kojto 110:165afa46840b 8491 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
Kojto 110:165afa46840b 8492 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
Kojto 110:165afa46840b 8493 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
Kojto 110:165afa46840b 8494 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
Kojto 110:165afa46840b 8495 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
Kojto 110:165afa46840b 8496 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
Kojto 110:165afa46840b 8497
Kojto 110:165afa46840b 8498 /****************** Bit definition for USART_CR2 register *******************/
Kojto 110:165afa46840b 8499 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
Kojto 110:165afa46840b 8500 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
Kojto 110:165afa46840b 8501 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
Kojto 110:165afa46840b 8502 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
Kojto 110:165afa46840b 8503 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
Kojto 110:165afa46840b 8504 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
Kojto 110:165afa46840b 8505 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
Kojto 110:165afa46840b 8506
Kojto 110:165afa46840b 8507 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
Kojto 110:165afa46840b 8508 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 110:165afa46840b 8509 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 110:165afa46840b 8510
Kojto 110:165afa46840b 8511 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
Kojto 110:165afa46840b 8512
Kojto 110:165afa46840b 8513 /****************** Bit definition for USART_CR3 register *******************/
Kojto 110:165afa46840b 8514 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
Kojto 110:165afa46840b 8515 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
Kojto 110:165afa46840b 8516 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
Kojto 110:165afa46840b 8517 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
Kojto 110:165afa46840b 8518 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
Kojto 110:165afa46840b 8519 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
Kojto 110:165afa46840b 8520 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
Kojto 110:165afa46840b 8521 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
Kojto 110:165afa46840b 8522 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
Kojto 110:165afa46840b 8523 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
Kojto 110:165afa46840b 8524 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
Kojto 110:165afa46840b 8525 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
Kojto 110:165afa46840b 8526
Kojto 110:165afa46840b 8527 /****************** Bit definition for USART_GTPR register ******************/
Kojto 110:165afa46840b 8528 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
Kojto 110:165afa46840b 8529 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 110:165afa46840b 8530 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 110:165afa46840b 8531 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 110:165afa46840b 8532 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 110:165afa46840b 8533 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 110:165afa46840b 8534 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 110:165afa46840b 8535 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 110:165afa46840b 8536 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
Kojto 110:165afa46840b 8537
Kojto 110:165afa46840b 8538 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
Kojto 110:165afa46840b 8539
Kojto 110:165afa46840b 8540 /******************************************************************************/
Kojto 110:165afa46840b 8541 /* */
Kojto 110:165afa46840b 8542 /* Window WATCHDOG */
Kojto 110:165afa46840b 8543 /* */
Kojto 110:165afa46840b 8544 /******************************************************************************/
Kojto 110:165afa46840b 8545 /******************* Bit definition for WWDG_CR register ********************/
Kojto 110:165afa46840b 8546 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 110:165afa46840b 8547 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 110:165afa46840b 8548 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 110:165afa46840b 8549 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 110:165afa46840b 8550 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
Kojto 110:165afa46840b 8551 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
Kojto 110:165afa46840b 8552 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
Kojto 110:165afa46840b 8553 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
Kojto 110:165afa46840b 8554
Kojto 110:165afa46840b 8555 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Kojto 110:165afa46840b 8556
Kojto 110:165afa46840b 8557 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 110:165afa46840b 8558 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 110:165afa46840b 8559 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 110:165afa46840b 8560 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 110:165afa46840b 8561 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 110:165afa46840b 8562 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 110:165afa46840b 8563 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 110:165afa46840b 8564 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 110:165afa46840b 8565 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 110:165afa46840b 8566
Kojto 110:165afa46840b 8567 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 110:165afa46840b 8568 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
Kojto 110:165afa46840b 8569 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
Kojto 110:165afa46840b 8570
Kojto 110:165afa46840b 8571 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Kojto 110:165afa46840b 8572
Kojto 110:165afa46840b 8573 /******************* Bit definition for WWDG_SR register ********************/
Kojto 110:165afa46840b 8574 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Kojto 110:165afa46840b 8575
Kojto 110:165afa46840b 8576
Kojto 110:165afa46840b 8577 /******************************************************************************/
Kojto 110:165afa46840b 8578 /* */
Kojto 110:165afa46840b 8579 /* DBG */
Kojto 110:165afa46840b 8580 /* */
Kojto 110:165afa46840b 8581 /******************************************************************************/
Kojto 110:165afa46840b 8582 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 110:165afa46840b 8583 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
Kojto 110:165afa46840b 8584 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
Kojto 110:165afa46840b 8585
Kojto 110:165afa46840b 8586 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 110:165afa46840b 8587 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
Kojto 110:165afa46840b 8588 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
Kojto 110:165afa46840b 8589 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
Kojto 110:165afa46840b 8590 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
Kojto 110:165afa46840b 8591
Kojto 110:165afa46840b 8592 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
Kojto 110:165afa46840b 8593 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
Kojto 110:165afa46840b 8594 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
Kojto 110:165afa46840b 8595
Kojto 110:165afa46840b 8596 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 110:165afa46840b 8597 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
Kojto 110:165afa46840b 8598 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
Kojto 110:165afa46840b 8599 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
Kojto 110:165afa46840b 8600 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
Kojto 110:165afa46840b 8601 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
Kojto 110:165afa46840b 8602 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
Kojto 110:165afa46840b 8603 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
Kojto 110:165afa46840b 8604 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
Kojto 110:165afa46840b 8605 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
Kojto 110:165afa46840b 8606 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
Kojto 110:165afa46840b 8607 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
Kojto 110:165afa46840b 8608 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
Kojto 110:165afa46840b 8609 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
Kojto 110:165afa46840b 8610 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
Kojto 110:165afa46840b 8611 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
Kojto 110:165afa46840b 8612 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
Kojto 110:165afa46840b 8613 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
Kojto 110:165afa46840b 8614 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
Kojto 110:165afa46840b 8615 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
Kojto 110:165afa46840b 8616
Kojto 110:165afa46840b 8617 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 110:165afa46840b 8618 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
Kojto 110:165afa46840b 8619 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
Kojto 110:165afa46840b 8620 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
Kojto 110:165afa46840b 8621 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
Kojto 110:165afa46840b 8622 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
Kojto 110:165afa46840b 8623
Kojto 110:165afa46840b 8624 /******************************************************************************/
Kojto 110:165afa46840b 8625 /* */
Kojto 110:165afa46840b 8626 /* Ethernet MAC Registers bits definitions */
Kojto 110:165afa46840b 8627 /* */
Kojto 110:165afa46840b 8628 /******************************************************************************/
Kojto 110:165afa46840b 8629 /* Bit definition for Ethernet MAC Control Register register */
Kojto 110:165afa46840b 8630 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
Kojto 110:165afa46840b 8631 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
Kojto 110:165afa46840b 8632 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
Kojto 110:165afa46840b 8633 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
Kojto 110:165afa46840b 8634 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
Kojto 110:165afa46840b 8635 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
Kojto 110:165afa46840b 8636 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
Kojto 110:165afa46840b 8637 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
Kojto 110:165afa46840b 8638 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
Kojto 110:165afa46840b 8639 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
Kojto 110:165afa46840b 8640 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
Kojto 110:165afa46840b 8641 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
Kojto 110:165afa46840b 8642 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
Kojto 110:165afa46840b 8643 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
Kojto 110:165afa46840b 8644 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
Kojto 110:165afa46840b 8645 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
Kojto 110:165afa46840b 8646 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
Kojto 110:165afa46840b 8647 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
Kojto 110:165afa46840b 8648 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
Kojto 110:165afa46840b 8649 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
Kojto 110:165afa46840b 8650 a transmission attempt during retries after a collision: 0 =< r <2^k */
Kojto 110:165afa46840b 8651 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
Kojto 110:165afa46840b 8652 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
Kojto 110:165afa46840b 8653 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
Kojto 110:165afa46840b 8654 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
Kojto 110:165afa46840b 8655 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
Kojto 110:165afa46840b 8656 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
Kojto 110:165afa46840b 8657 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
Kojto 110:165afa46840b 8658
Kojto 110:165afa46840b 8659 /* Bit definition for Ethernet MAC Frame Filter Register */
Kojto 110:165afa46840b 8660 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
Kojto 110:165afa46840b 8661 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
Kojto 110:165afa46840b 8662 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
Kojto 110:165afa46840b 8663 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
Kojto 110:165afa46840b 8664 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
Kojto 110:165afa46840b 8665 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
Kojto 110:165afa46840b 8666 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
Kojto 110:165afa46840b 8667 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
Kojto 110:165afa46840b 8668 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
Kojto 110:165afa46840b 8669 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
Kojto 110:165afa46840b 8670 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
Kojto 110:165afa46840b 8671 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
Kojto 110:165afa46840b 8672 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
Kojto 110:165afa46840b 8673 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
Kojto 110:165afa46840b 8674
Kojto 110:165afa46840b 8675 /* Bit definition for Ethernet MAC Hash Table High Register */
Kojto 110:165afa46840b 8676 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
Kojto 110:165afa46840b 8677
Kojto 110:165afa46840b 8678 /* Bit definition for Ethernet MAC Hash Table Low Register */
Kojto 110:165afa46840b 8679 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
Kojto 110:165afa46840b 8680
Kojto 110:165afa46840b 8681 /* Bit definition for Ethernet MAC MII Address Register */
Kojto 110:165afa46840b 8682 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
Kojto 110:165afa46840b 8683 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
Kojto 110:165afa46840b 8684 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
Kojto 110:165afa46840b 8685 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
Kojto 110:165afa46840b 8686 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
Kojto 110:165afa46840b 8687 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
Kojto 110:165afa46840b 8688 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
Kojto 110:165afa46840b 8689 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
Kojto 110:165afa46840b 8690 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
Kojto 110:165afa46840b 8691 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
Kojto 110:165afa46840b 8692
Kojto 110:165afa46840b 8693 /* Bit definition for Ethernet MAC MII Data Register */
Kojto 110:165afa46840b 8694 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
Kojto 110:165afa46840b 8695
Kojto 110:165afa46840b 8696 /* Bit definition for Ethernet MAC Flow Control Register */
Kojto 110:165afa46840b 8697 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
Kojto 110:165afa46840b 8698 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
Kojto 110:165afa46840b 8699 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
Kojto 110:165afa46840b 8700 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
Kojto 110:165afa46840b 8701 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
Kojto 110:165afa46840b 8702 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
Kojto 110:165afa46840b 8703 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
Kojto 110:165afa46840b 8704 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
Kojto 110:165afa46840b 8705 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
Kojto 110:165afa46840b 8706 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
Kojto 110:165afa46840b 8707 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
Kojto 110:165afa46840b 8708
Kojto 110:165afa46840b 8709 /* Bit definition for Ethernet MAC VLAN Tag Register */
Kojto 110:165afa46840b 8710 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
Kojto 110:165afa46840b 8711 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
Kojto 110:165afa46840b 8712
Kojto 110:165afa46840b 8713 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
Kojto 110:165afa46840b 8714 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
Kojto 110:165afa46840b 8715 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Kojto 110:165afa46840b 8716 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
Kojto 110:165afa46840b 8717 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Kojto 110:165afa46840b 8718 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Kojto 110:165afa46840b 8719 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Kojto 110:165afa46840b 8720 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Kojto 110:165afa46840b 8721 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
Kojto 110:165afa46840b 8722 RSVD - Filter1 Command - RSVD - Filter0 Command
Kojto 110:165afa46840b 8723 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Kojto 110:165afa46840b 8724 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Kojto 110:165afa46840b 8725 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
Kojto 110:165afa46840b 8726
Kojto 110:165afa46840b 8727 /* Bit definition for Ethernet MAC PMT Control and Status Register */
Kojto 110:165afa46840b 8728 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
Kojto 110:165afa46840b 8729 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
Kojto 110:165afa46840b 8730 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
Kojto 110:165afa46840b 8731 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
Kojto 110:165afa46840b 8732 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
Kojto 110:165afa46840b 8733 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
Kojto 110:165afa46840b 8734 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
Kojto 110:165afa46840b 8735
Kojto 110:165afa46840b 8736 /* Bit definition for Ethernet MAC Status Register */
Kojto 110:165afa46840b 8737 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
Kojto 110:165afa46840b 8738 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
Kojto 110:165afa46840b 8739 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
Kojto 110:165afa46840b 8740 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
Kojto 110:165afa46840b 8741 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
Kojto 110:165afa46840b 8742
Kojto 110:165afa46840b 8743 /* Bit definition for Ethernet MAC Interrupt Mask Register */
Kojto 110:165afa46840b 8744 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
Kojto 110:165afa46840b 8745 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
Kojto 110:165afa46840b 8746
Kojto 110:165afa46840b 8747 /* Bit definition for Ethernet MAC Address0 High Register */
Kojto 110:165afa46840b 8748 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
Kojto 110:165afa46840b 8749
Kojto 110:165afa46840b 8750 /* Bit definition for Ethernet MAC Address0 Low Register */
Kojto 110:165afa46840b 8751 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
Kojto 110:165afa46840b 8752
Kojto 110:165afa46840b 8753 /* Bit definition for Ethernet MAC Address1 High Register */
Kojto 110:165afa46840b 8754 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
Kojto 110:165afa46840b 8755 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
Kojto 110:165afa46840b 8756 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
Kojto 110:165afa46840b 8757 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Kojto 110:165afa46840b 8758 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Kojto 110:165afa46840b 8759 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Kojto 110:165afa46840b 8760 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Kojto 110:165afa46840b 8761 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Kojto 110:165afa46840b 8762 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
Kojto 110:165afa46840b 8763 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
Kojto 110:165afa46840b 8764
Kojto 110:165afa46840b 8765 /* Bit definition for Ethernet MAC Address1 Low Register */
Kojto 110:165afa46840b 8766 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
Kojto 110:165afa46840b 8767
Kojto 110:165afa46840b 8768 /* Bit definition for Ethernet MAC Address2 High Register */
Kojto 110:165afa46840b 8769 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
Kojto 110:165afa46840b 8770 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
Kojto 110:165afa46840b 8771 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
Kojto 110:165afa46840b 8772 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Kojto 110:165afa46840b 8773 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Kojto 110:165afa46840b 8774 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Kojto 110:165afa46840b 8775 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Kojto 110:165afa46840b 8776 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Kojto 110:165afa46840b 8777 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
Kojto 110:165afa46840b 8778 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
Kojto 110:165afa46840b 8779
Kojto 110:165afa46840b 8780 /* Bit definition for Ethernet MAC Address2 Low Register */
Kojto 110:165afa46840b 8781 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
Kojto 110:165afa46840b 8782
Kojto 110:165afa46840b 8783 /* Bit definition for Ethernet MAC Address3 High Register */
Kojto 110:165afa46840b 8784 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
Kojto 110:165afa46840b 8785 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
Kojto 110:165afa46840b 8786 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
Kojto 110:165afa46840b 8787 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Kojto 110:165afa46840b 8788 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Kojto 110:165afa46840b 8789 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Kojto 110:165afa46840b 8790 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Kojto 110:165afa46840b 8791 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Kojto 110:165afa46840b 8792 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
Kojto 110:165afa46840b 8793 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
Kojto 110:165afa46840b 8794
Kojto 110:165afa46840b 8795 /* Bit definition for Ethernet MAC Address3 Low Register */
Kojto 110:165afa46840b 8796 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
Kojto 110:165afa46840b 8797
Kojto 110:165afa46840b 8798 /******************************************************************************/
Kojto 110:165afa46840b 8799 /* Ethernet MMC Registers bits definition */
Kojto 110:165afa46840b 8800 /******************************************************************************/
Kojto 110:165afa46840b 8801
Kojto 110:165afa46840b 8802 /* Bit definition for Ethernet MMC Contol Register */
Kojto 110:165afa46840b 8803 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
Kojto 110:165afa46840b 8804 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
Kojto 110:165afa46840b 8805 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
Kojto 110:165afa46840b 8806 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
Kojto 110:165afa46840b 8807 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
Kojto 110:165afa46840b 8808 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
Kojto 110:165afa46840b 8809
Kojto 110:165afa46840b 8810 /* Bit definition for Ethernet MMC Receive Interrupt Register */
Kojto 110:165afa46840b 8811 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
Kojto 110:165afa46840b 8812 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
Kojto 110:165afa46840b 8813 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
Kojto 110:165afa46840b 8814
Kojto 110:165afa46840b 8815 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
Kojto 110:165afa46840b 8816 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
Kojto 110:165afa46840b 8817 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
Kojto 110:165afa46840b 8818 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
Kojto 110:165afa46840b 8819
Kojto 110:165afa46840b 8820 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
Kojto 110:165afa46840b 8821 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
Kojto 110:165afa46840b 8822 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
Kojto 110:165afa46840b 8823 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
Kojto 110:165afa46840b 8824
Kojto 110:165afa46840b 8825 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
Kojto 110:165afa46840b 8826 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
Kojto 110:165afa46840b 8827 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
Kojto 110:165afa46840b 8828 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
Kojto 110:165afa46840b 8829
Kojto 110:165afa46840b 8830 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
Kojto 110:165afa46840b 8831 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
Kojto 110:165afa46840b 8832
Kojto 110:165afa46840b 8833 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
Kojto 110:165afa46840b 8834 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
Kojto 110:165afa46840b 8835
Kojto 110:165afa46840b 8836 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
Kojto 110:165afa46840b 8837 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
Kojto 110:165afa46840b 8838
Kojto 110:165afa46840b 8839 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
Kojto 110:165afa46840b 8840 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
Kojto 110:165afa46840b 8841
Kojto 110:165afa46840b 8842 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
Kojto 110:165afa46840b 8843 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
Kojto 110:165afa46840b 8844
Kojto 110:165afa46840b 8845 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
Kojto 110:165afa46840b 8846 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
Kojto 110:165afa46840b 8847
Kojto 110:165afa46840b 8848 /******************************************************************************/
Kojto 110:165afa46840b 8849 /* Ethernet PTP Registers bits definition */
Kojto 110:165afa46840b 8850 /******************************************************************************/
Kojto 110:165afa46840b 8851
Kojto 110:165afa46840b 8852 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
Kojto 110:165afa46840b 8853 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
Kojto 110:165afa46840b 8854 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
Kojto 110:165afa46840b 8855 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
Kojto 110:165afa46840b 8856 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
Kojto 110:165afa46840b 8857 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
Kojto 110:165afa46840b 8858 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
Kojto 110:165afa46840b 8859 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
Kojto 110:165afa46840b 8860 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
Kojto 110:165afa46840b 8861 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
Kojto 110:165afa46840b 8862
Kojto 110:165afa46840b 8863 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
Kojto 110:165afa46840b 8864 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
Kojto 110:165afa46840b 8865 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
Kojto 110:165afa46840b 8866 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
Kojto 110:165afa46840b 8867 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
Kojto 110:165afa46840b 8868 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
Kojto 110:165afa46840b 8869
Kojto 110:165afa46840b 8870 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
Kojto 110:165afa46840b 8871 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
Kojto 110:165afa46840b 8872
Kojto 110:165afa46840b 8873 /* Bit definition for Ethernet PTP Time Stamp High Register */
Kojto 110:165afa46840b 8874 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
Kojto 110:165afa46840b 8875
Kojto 110:165afa46840b 8876 /* Bit definition for Ethernet PTP Time Stamp Low Register */
Kojto 110:165afa46840b 8877 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
Kojto 110:165afa46840b 8878 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
Kojto 110:165afa46840b 8879
Kojto 110:165afa46840b 8880 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
Kojto 110:165afa46840b 8881 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
Kojto 110:165afa46840b 8882
Kojto 110:165afa46840b 8883 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
Kojto 110:165afa46840b 8884 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
Kojto 110:165afa46840b 8885 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
Kojto 110:165afa46840b 8886
Kojto 110:165afa46840b 8887 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
Kojto 110:165afa46840b 8888 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
Kojto 110:165afa46840b 8889
Kojto 110:165afa46840b 8890 /* Bit definition for Ethernet PTP Target Time High Register */
Kojto 110:165afa46840b 8891 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
Kojto 110:165afa46840b 8892
Kojto 110:165afa46840b 8893 /* Bit definition for Ethernet PTP Target Time Low Register */
Kojto 110:165afa46840b 8894 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
Kojto 110:165afa46840b 8895
Kojto 110:165afa46840b 8896 /* Bit definition for Ethernet PTP Time Stamp Status Register */
Kojto 110:165afa46840b 8897 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
Kojto 110:165afa46840b 8898 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
Kojto 110:165afa46840b 8899
Kojto 110:165afa46840b 8900 /******************************************************************************/
Kojto 110:165afa46840b 8901 /* Ethernet DMA Registers bits definition */
Kojto 110:165afa46840b 8902 /******************************************************************************/
Kojto 110:165afa46840b 8903
Kojto 110:165afa46840b 8904 /* Bit definition for Ethernet DMA Bus Mode Register */
Kojto 110:165afa46840b 8905 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
Kojto 110:165afa46840b 8906 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
Kojto 110:165afa46840b 8907 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
Kojto 110:165afa46840b 8908 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
Kojto 110:165afa46840b 8909 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
Kojto 110:165afa46840b 8910 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
Kojto 110:165afa46840b 8911 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 110:165afa46840b 8912 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 110:165afa46840b 8913 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 110:165afa46840b 8914 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 110:165afa46840b 8915 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 110:165afa46840b 8916 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 110:165afa46840b 8917 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 110:165afa46840b 8918 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 110:165afa46840b 8919 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
Kojto 110:165afa46840b 8920 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
Kojto 110:165afa46840b 8921 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
Kojto 110:165afa46840b 8922 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
Kojto 110:165afa46840b 8923 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
Kojto 110:165afa46840b 8924 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
Kojto 110:165afa46840b 8925 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
Kojto 110:165afa46840b 8926 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
Kojto 110:165afa46840b 8927 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
Kojto 110:165afa46840b 8928 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
Kojto 110:165afa46840b 8929 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
Kojto 110:165afa46840b 8930 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 110:165afa46840b 8931 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 110:165afa46840b 8932 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 110:165afa46840b 8933 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 110:165afa46840b 8934 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 110:165afa46840b 8935 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 110:165afa46840b 8936 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 110:165afa46840b 8937 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 110:165afa46840b 8938 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
Kojto 110:165afa46840b 8939 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Kojto 110:165afa46840b 8940 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
Kojto 110:165afa46840b 8941 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
Kojto 110:165afa46840b 8942 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
Kojto 110:165afa46840b 8943 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
Kojto 110:165afa46840b 8944
Kojto 110:165afa46840b 8945 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
Kojto 110:165afa46840b 8946 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
Kojto 110:165afa46840b 8947
Kojto 110:165afa46840b 8948 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
Kojto 110:165afa46840b 8949 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
Kojto 110:165afa46840b 8950
Kojto 110:165afa46840b 8951 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
Kojto 110:165afa46840b 8952 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
Kojto 110:165afa46840b 8953
Kojto 110:165afa46840b 8954 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
Kojto 110:165afa46840b 8955 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
Kojto 110:165afa46840b 8956
Kojto 110:165afa46840b 8957 /* Bit definition for Ethernet DMA Status Register */
Kojto 110:165afa46840b 8958 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
Kojto 110:165afa46840b 8959 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
Kojto 110:165afa46840b 8960 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
Kojto 110:165afa46840b 8961 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
Kojto 110:165afa46840b 8962 /* combination with EBS[2:0] for GetFlagStatus function */
Kojto 110:165afa46840b 8963 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
Kojto 110:165afa46840b 8964 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
Kojto 110:165afa46840b 8965 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
Kojto 110:165afa46840b 8966 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
Kojto 110:165afa46840b 8967 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
Kojto 110:165afa46840b 8968 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
Kojto 110:165afa46840b 8969 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
Kojto 110:165afa46840b 8970 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
Kojto 110:165afa46840b 8971 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
Kojto 110:165afa46840b 8972 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
Kojto 110:165afa46840b 8973 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
Kojto 110:165afa46840b 8974 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
Kojto 110:165afa46840b 8975 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
Kojto 110:165afa46840b 8976 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
Kojto 110:165afa46840b 8977 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
Kojto 110:165afa46840b 8978 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
Kojto 110:165afa46840b 8979 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
Kojto 110:165afa46840b 8980 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
Kojto 110:165afa46840b 8981 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
Kojto 110:165afa46840b 8982 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
Kojto 110:165afa46840b 8983 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
Kojto 110:165afa46840b 8984 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
Kojto 110:165afa46840b 8985 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
Kojto 110:165afa46840b 8986 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
Kojto 110:165afa46840b 8987 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
Kojto 110:165afa46840b 8988 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
Kojto 110:165afa46840b 8989 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
Kojto 110:165afa46840b 8990 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
Kojto 110:165afa46840b 8991 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
Kojto 110:165afa46840b 8992 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
Kojto 110:165afa46840b 8993 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
Kojto 110:165afa46840b 8994 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
Kojto 110:165afa46840b 8995
Kojto 110:165afa46840b 8996 /* Bit definition for Ethernet DMA Operation Mode Register */
Kojto 110:165afa46840b 8997 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
Kojto 110:165afa46840b 8998 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
Kojto 110:165afa46840b 8999 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
Kojto 110:165afa46840b 9000 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
Kojto 110:165afa46840b 9001 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
Kojto 110:165afa46840b 9002 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
Kojto 110:165afa46840b 9003 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
Kojto 110:165afa46840b 9004 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
Kojto 110:165afa46840b 9005 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
Kojto 110:165afa46840b 9006 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
Kojto 110:165afa46840b 9007 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
Kojto 110:165afa46840b 9008 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
Kojto 110:165afa46840b 9009 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
Kojto 110:165afa46840b 9010 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
Kojto 110:165afa46840b 9011 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
Kojto 110:165afa46840b 9012 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
Kojto 110:165afa46840b 9013 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
Kojto 110:165afa46840b 9014 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
Kojto 110:165afa46840b 9015 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
Kojto 110:165afa46840b 9016 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
Kojto 110:165afa46840b 9017 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
Kojto 110:165afa46840b 9018 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
Kojto 110:165afa46840b 9019 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
Kojto 110:165afa46840b 9020 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
Kojto 110:165afa46840b 9021
Kojto 110:165afa46840b 9022 /* Bit definition for Ethernet DMA Interrupt Enable Register */
Kojto 110:165afa46840b 9023 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
Kojto 110:165afa46840b 9024 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
Kojto 110:165afa46840b 9025 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
Kojto 110:165afa46840b 9026 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
Kojto 110:165afa46840b 9027 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
Kojto 110:165afa46840b 9028 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
Kojto 110:165afa46840b 9029 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
Kojto 110:165afa46840b 9030 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
Kojto 110:165afa46840b 9031 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
Kojto 110:165afa46840b 9032 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
Kojto 110:165afa46840b 9033 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
Kojto 110:165afa46840b 9034 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
Kojto 110:165afa46840b 9035 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
Kojto 110:165afa46840b 9036 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
Kojto 110:165afa46840b 9037 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
Kojto 110:165afa46840b 9038
Kojto 110:165afa46840b 9039 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
Kojto 110:165afa46840b 9040 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
Kojto 110:165afa46840b 9041 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
Kojto 110:165afa46840b 9042 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
Kojto 110:165afa46840b 9043 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
Kojto 110:165afa46840b 9044
Kojto 110:165afa46840b 9045 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
Kojto 110:165afa46840b 9046 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
Kojto 110:165afa46840b 9047
Kojto 110:165afa46840b 9048 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
Kojto 110:165afa46840b 9049 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
Kojto 110:165afa46840b 9050
Kojto 110:165afa46840b 9051 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
Kojto 110:165afa46840b 9052 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
Kojto 110:165afa46840b 9053
Kojto 110:165afa46840b 9054 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
Kojto 110:165afa46840b 9055 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
Kojto 110:165afa46840b 9056
Kojto 110:165afa46840b 9057 /******************************************************************************/
Kojto 110:165afa46840b 9058 /* */
Kojto 110:165afa46840b 9059 /* USB_OTG */
Kojto 110:165afa46840b 9060 /* */
Kojto 110:165afa46840b 9061 /******************************************************************************/
Kojto 110:165afa46840b 9062 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
Kojto 110:165afa46840b 9063 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
Kojto 110:165afa46840b 9064 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
Kojto 110:165afa46840b 9065 #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
Kojto 110:165afa46840b 9066 #define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
Kojto 110:165afa46840b 9067 #define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
Kojto 110:165afa46840b 9068 #define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
Kojto 110:165afa46840b 9069 #define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
Kojto 110:165afa46840b 9070 #define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
Kojto 110:165afa46840b 9071 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
Kojto 110:165afa46840b 9072 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
Kojto 110:165afa46840b 9073 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
Kojto 110:165afa46840b 9074 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
Kojto 110:165afa46840b 9075 #define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
Kojto 110:165afa46840b 9076 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
Kojto 110:165afa46840b 9077 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
Kojto 110:165afa46840b 9078 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
Kojto 110:165afa46840b 9079 #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
Kojto 110:165afa46840b 9080 #define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
Kojto 110:165afa46840b 9081
Kojto 110:165afa46840b 9082 /******************** Bit definition forUSB_OTG_HCFG register ********************/
Kojto 110:165afa46840b 9083
Kojto 110:165afa46840b 9084 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
Kojto 110:165afa46840b 9085 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 9086 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 9087 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
Kojto 110:165afa46840b 9088
Kojto 110:165afa46840b 9089 /******************** Bit definition forUSB_OTG_DCFG register ********************/
Kojto 110:165afa46840b 9090
Kojto 110:165afa46840b 9091 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
Kojto 110:165afa46840b 9092 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 9093 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 9094 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
Kojto 110:165afa46840b 9095
Kojto 110:165afa46840b 9096 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
Kojto 110:165afa46840b 9097 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 9098 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 9099 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 9100 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 110:165afa46840b 9101 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
Kojto 110:165afa46840b 9102 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
Kojto 110:165afa46840b 9103 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
Kojto 110:165afa46840b 9104
Kojto 110:165afa46840b 9105 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
Kojto 110:165afa46840b 9106 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 110:165afa46840b 9107 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 110:165afa46840b 9108
Kojto 110:165afa46840b 9109 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
Kojto 110:165afa46840b 9110 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 9111 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 9112
Kojto 110:165afa46840b 9113 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
Kojto 110:165afa46840b 9114 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
Kojto 110:165afa46840b 9115 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
Kojto 110:165afa46840b 9116 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
Kojto 110:165afa46840b 9117
Kojto 110:165afa46840b 9118 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
Kojto 110:165afa46840b 9119 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
Kojto 110:165afa46840b 9120 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
Kojto 110:165afa46840b 9121 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
Kojto 110:165afa46840b 9122 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
Kojto 110:165afa46840b 9123 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
Kojto 110:165afa46840b 9124 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
Kojto 110:165afa46840b 9125 #define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
Kojto 110:165afa46840b 9126
Kojto 110:165afa46840b 9127 /******************** Bit definition forUSB_OTG_DCTL register ********************/
Kojto 110:165afa46840b 9128 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
Kojto 110:165afa46840b 9129 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
Kojto 110:165afa46840b 9130 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
Kojto 110:165afa46840b 9131 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
Kojto 110:165afa46840b 9132
Kojto 110:165afa46840b 9133 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
Kojto 110:165afa46840b 9134 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 110:165afa46840b 9135 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 110:165afa46840b 9136 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 110:165afa46840b 9137 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
Kojto 110:165afa46840b 9138 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
Kojto 110:165afa46840b 9139 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
Kojto 110:165afa46840b 9140 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
Kojto 110:165afa46840b 9141 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
Kojto 110:165afa46840b 9142
Kojto 110:165afa46840b 9143 /******************** Bit definition forUSB_OTG_HFIR register ********************/
Kojto 110:165afa46840b 9144 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
Kojto 110:165afa46840b 9145
Kojto 110:165afa46840b 9146 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
Kojto 110:165afa46840b 9147 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
Kojto 110:165afa46840b 9148 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
Kojto 110:165afa46840b 9149
Kojto 110:165afa46840b 9150 /******************** Bit definition forUSB_OTG_DSTS register ********************/
Kojto 110:165afa46840b 9151 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
Kojto 110:165afa46840b 9152
Kojto 110:165afa46840b 9153 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
Kojto 110:165afa46840b 9154 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 110:165afa46840b 9155 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 110:165afa46840b 9156 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
Kojto 110:165afa46840b 9157 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
Kojto 110:165afa46840b 9158
Kojto 110:165afa46840b 9159 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
Kojto 110:165afa46840b 9160 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
Kojto 110:165afa46840b 9161 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
Kojto 110:165afa46840b 9162 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 110:165afa46840b 9163 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 110:165afa46840b 9164 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
Kojto 110:165afa46840b 9165 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
Kojto 110:165afa46840b 9166 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
Kojto 110:165afa46840b 9167 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
Kojto 110:165afa46840b 9168 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
Kojto 110:165afa46840b 9169
Kojto 110:165afa46840b 9170 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
Kojto 110:165afa46840b 9171
Kojto 110:165afa46840b 9172 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
Kojto 110:165afa46840b 9173 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 9174 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 9175 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 9176 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
Kojto 110:165afa46840b 9177 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
Kojto 110:165afa46840b 9178 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
Kojto 110:165afa46840b 9179 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
Kojto 110:165afa46840b 9180 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 110:165afa46840b 9181 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 110:165afa46840b 9182 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 110:165afa46840b 9183 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 110:165afa46840b 9184 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
Kojto 110:165afa46840b 9185 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
Kojto 110:165afa46840b 9186 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
Kojto 110:165afa46840b 9187 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
Kojto 110:165afa46840b 9188 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
Kojto 110:165afa46840b 9189 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
Kojto 110:165afa46840b 9190 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
Kojto 110:165afa46840b 9191 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
Kojto 110:165afa46840b 9192 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
Kojto 110:165afa46840b 9193 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
Kojto 110:165afa46840b 9194 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
Kojto 110:165afa46840b 9195 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
Kojto 110:165afa46840b 9196 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
Kojto 110:165afa46840b 9197
Kojto 110:165afa46840b 9198 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
Kojto 110:165afa46840b 9199 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
Kojto 110:165afa46840b 9200 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
Kojto 110:165afa46840b 9201 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
Kojto 110:165afa46840b 9202 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
Kojto 110:165afa46840b 9203 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
Kojto 110:165afa46840b 9204 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
Kojto 110:165afa46840b 9205 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 110:165afa46840b 9206 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 110:165afa46840b 9207 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 110:165afa46840b 9208 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
Kojto 110:165afa46840b 9209 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
Kojto 110:165afa46840b 9210 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
Kojto 110:165afa46840b 9211 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
Kojto 110:165afa46840b 9212
Kojto 110:165afa46840b 9213 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
Kojto 110:165afa46840b 9214 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 110:165afa46840b 9215 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 110:165afa46840b 9216 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 110:165afa46840b 9217 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 110:165afa46840b 9218 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 110:165afa46840b 9219 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 110:165afa46840b 9220 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 110:165afa46840b 9221 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 110:165afa46840b 9222
Kojto 110:165afa46840b 9223 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
Kojto 110:165afa46840b 9224 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
Kojto 110:165afa46840b 9225 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
Kojto 110:165afa46840b 9226 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 9227 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 9228 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 9229 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 9230 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 110:165afa46840b 9231 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 110:165afa46840b 9232 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 110:165afa46840b 9233 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 110:165afa46840b 9234
Kojto 110:165afa46840b 9235 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
Kojto 110:165afa46840b 9236 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 9237 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 9238 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 9239 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 9240 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 110:165afa46840b 9241 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 110:165afa46840b 9242 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 110:165afa46840b 9243 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 110:165afa46840b 9244
Kojto 110:165afa46840b 9245 /******************** Bit definition forUSB_OTG_HAINT register ********************/
Kojto 110:165afa46840b 9246 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
Kojto 110:165afa46840b 9247
Kojto 110:165afa46840b 9248 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
Kojto 110:165afa46840b 9249 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 110:165afa46840b 9250 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 110:165afa46840b 9251 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
Kojto 110:165afa46840b 9252 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
Kojto 110:165afa46840b 9253 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
Kojto 110:165afa46840b 9254 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 110:165afa46840b 9255 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 110:165afa46840b 9256
Kojto 110:165afa46840b 9257 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
Kojto 110:165afa46840b 9258 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
Kojto 110:165afa46840b 9259 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
Kojto 110:165afa46840b 9260 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
Kojto 110:165afa46840b 9261 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
Kojto 110:165afa46840b 9262 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
Kojto 110:165afa46840b 9263 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
Kojto 110:165afa46840b 9264 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
Kojto 110:165afa46840b 9265 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
Kojto 110:165afa46840b 9266 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
Kojto 110:165afa46840b 9267 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
Kojto 110:165afa46840b 9268 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
Kojto 110:165afa46840b 9269 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
Kojto 110:165afa46840b 9270 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
Kojto 110:165afa46840b 9271 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
Kojto 110:165afa46840b 9272 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
Kojto 110:165afa46840b 9273 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
Kojto 110:165afa46840b 9274 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
Kojto 110:165afa46840b 9275 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
Kojto 110:165afa46840b 9276 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
Kojto 110:165afa46840b 9277 #define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
Kojto 110:165afa46840b 9278 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
Kojto 110:165afa46840b 9279 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
Kojto 110:165afa46840b 9280 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
Kojto 110:165afa46840b 9281 #define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
Kojto 110:165afa46840b 9282 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
Kojto 110:165afa46840b 9283 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
Kojto 110:165afa46840b 9284 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
Kojto 110:165afa46840b 9285 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
Kojto 110:165afa46840b 9286
Kojto 110:165afa46840b 9287 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
Kojto 110:165afa46840b 9288 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
Kojto 110:165afa46840b 9289 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
Kojto 110:165afa46840b 9290 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
Kojto 110:165afa46840b 9291 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
Kojto 110:165afa46840b 9292 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
Kojto 110:165afa46840b 9293 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
Kojto 110:165afa46840b 9294 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
Kojto 110:165afa46840b 9295 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
Kojto 110:165afa46840b 9296 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
Kojto 110:165afa46840b 9297 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
Kojto 110:165afa46840b 9298 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
Kojto 110:165afa46840b 9299 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
Kojto 110:165afa46840b 9300 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
Kojto 110:165afa46840b 9301 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
Kojto 110:165afa46840b 9302 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
Kojto 110:165afa46840b 9303 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
Kojto 110:165afa46840b 9304 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
Kojto 110:165afa46840b 9305 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
Kojto 110:165afa46840b 9306 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
Kojto 110:165afa46840b 9307 #define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
Kojto 110:165afa46840b 9308 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
Kojto 110:165afa46840b 9309 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
Kojto 110:165afa46840b 9310 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
Kojto 110:165afa46840b 9311 #define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
Kojto 110:165afa46840b 9312 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
Kojto 110:165afa46840b 9313 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
Kojto 110:165afa46840b 9314 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
Kojto 110:165afa46840b 9315 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
Kojto 110:165afa46840b 9316
Kojto 110:165afa46840b 9317 /******************** Bit definition forUSB_OTG_DAINT register ********************/
Kojto 110:165afa46840b 9318 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
Kojto 110:165afa46840b 9319 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
Kojto 110:165afa46840b 9320
Kojto 110:165afa46840b 9321 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
Kojto 110:165afa46840b 9322 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
Kojto 110:165afa46840b 9323
Kojto 110:165afa46840b 9324 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
Kojto 110:165afa46840b 9325 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
Kojto 110:165afa46840b 9326 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
Kojto 110:165afa46840b 9327 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
Kojto 110:165afa46840b 9328 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
Kojto 110:165afa46840b 9329
Kojto 110:165afa46840b 9330 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
Kojto 110:165afa46840b 9331 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
Kojto 110:165afa46840b 9332 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
Kojto 110:165afa46840b 9333
Kojto 110:165afa46840b 9334 /******************** Bit definition for OTG register ********************/
Kojto 110:165afa46840b 9335
Kojto 110:165afa46840b 9336 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 110:165afa46840b 9337 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 9338 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 9339 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 9340 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 9341 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 110:165afa46840b 9342
Kojto 110:165afa46840b 9343 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 110:165afa46840b 9344 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 110:165afa46840b 9345 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 110:165afa46840b 9346
Kojto 110:165afa46840b 9347 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 110:165afa46840b 9348 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 110:165afa46840b 9349 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 110:165afa46840b 9350 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 110:165afa46840b 9351 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 110:165afa46840b 9352
Kojto 110:165afa46840b 9353 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 110:165afa46840b 9354 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 9355 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 9356 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 9357 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 9358
Kojto 110:165afa46840b 9359 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 110:165afa46840b 9360 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 110:165afa46840b 9361 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 110:165afa46840b 9362 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 110:165afa46840b 9363 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 110:165afa46840b 9364
Kojto 110:165afa46840b 9365 /******************** Bit definition for OTG register ********************/
Kojto 110:165afa46840b 9366
Kojto 110:165afa46840b 9367 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 110:165afa46840b 9368 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 9369 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 9370 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 9371 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 9372 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 110:165afa46840b 9373
Kojto 110:165afa46840b 9374 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 110:165afa46840b 9375 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 110:165afa46840b 9376 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 110:165afa46840b 9377
Kojto 110:165afa46840b 9378 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 110:165afa46840b 9379 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 110:165afa46840b 9380 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 110:165afa46840b 9381 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 110:165afa46840b 9382 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 110:165afa46840b 9383
Kojto 110:165afa46840b 9384 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 110:165afa46840b 9385 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 9386 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 9387 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 9388 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 9389
Kojto 110:165afa46840b 9390 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 110:165afa46840b 9391 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 110:165afa46840b 9392 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 110:165afa46840b 9393 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 110:165afa46840b 9394 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 110:165afa46840b 9395
Kojto 110:165afa46840b 9396 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
Kojto 110:165afa46840b 9397 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
Kojto 110:165afa46840b 9398
Kojto 110:165afa46840b 9399 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
Kojto 110:165afa46840b 9400 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
Kojto 110:165afa46840b 9401
Kojto 110:165afa46840b 9402 /******************** Bit definition for OTG register ********************/
Kojto 110:165afa46840b 9403 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
Kojto 110:165afa46840b 9404 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
Kojto 110:165afa46840b 9405 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
Kojto 110:165afa46840b 9406 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
Kojto 110:165afa46840b 9407
Kojto 110:165afa46840b 9408 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
Kojto 110:165afa46840b 9409 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
Kojto 110:165afa46840b 9410
Kojto 110:165afa46840b 9411 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
Kojto 110:165afa46840b 9412 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
Kojto 110:165afa46840b 9413
Kojto 110:165afa46840b 9414 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
Kojto 110:165afa46840b 9415 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 110:165afa46840b 9416 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 110:165afa46840b 9417 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 110:165afa46840b 9418 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 110:165afa46840b 9419 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 110:165afa46840b 9420 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 110:165afa46840b 9421 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 110:165afa46840b 9422 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 110:165afa46840b 9423
Kojto 110:165afa46840b 9424 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
Kojto 110:165afa46840b 9425 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 110:165afa46840b 9426 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 110:165afa46840b 9427 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 110:165afa46840b 9428 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 110:165afa46840b 9429 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 110:165afa46840b 9430 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 110:165afa46840b 9431 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 110:165afa46840b 9432
Kojto 110:165afa46840b 9433 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
Kojto 110:165afa46840b 9434 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
Kojto 110:165afa46840b 9435 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
Kojto 110:165afa46840b 9436
Kojto 110:165afa46840b 9437 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
Kojto 110:165afa46840b 9438 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 110:165afa46840b 9439 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 110:165afa46840b 9440 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
Kojto 110:165afa46840b 9441 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
Kojto 110:165afa46840b 9442 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
Kojto 110:165afa46840b 9443 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
Kojto 110:165afa46840b 9444 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
Kojto 110:165afa46840b 9445 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
Kojto 110:165afa46840b 9446 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
Kojto 110:165afa46840b 9447 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
Kojto 110:165afa46840b 9448
Kojto 110:165afa46840b 9449 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
Kojto 110:165afa46840b 9450 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 110:165afa46840b 9451 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 110:165afa46840b 9452 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 110:165afa46840b 9453 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 110:165afa46840b 9454 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
Kojto 110:165afa46840b 9455 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
Kojto 110:165afa46840b 9456 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
Kojto 110:165afa46840b 9457 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
Kojto 110:165afa46840b 9458 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
Kojto 110:165afa46840b 9459 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
Kojto 110:165afa46840b 9460
Kojto 110:165afa46840b 9461 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
Kojto 110:165afa46840b 9462 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
Kojto 110:165afa46840b 9463
Kojto 110:165afa46840b 9464 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
Kojto 110:165afa46840b 9465 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
Kojto 110:165afa46840b 9466 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
Kojto 110:165afa46840b 9467
Kojto 110:165afa46840b 9468 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
Kojto 110:165afa46840b 9469 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
Kojto 110:165afa46840b 9470 #define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
Kojto 110:165afa46840b 9471
Kojto 110:165afa46840b 9472 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
Kojto 110:165afa46840b 9473 #define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
Kojto 110:165afa46840b 9474 #define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
Kojto 110:165afa46840b 9475
Kojto 110:165afa46840b 9476 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
Kojto 110:165afa46840b 9477 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
Kojto 110:165afa46840b 9478 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
Kojto 110:165afa46840b 9479
Kojto 110:165afa46840b 9480 /******************** Bit definition forUSB_OTG_CID register ********************/
Kojto 110:165afa46840b 9481 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
Kojto 110:165afa46840b 9482
Kojto 110:165afa46840b 9483 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
Kojto 110:165afa46840b 9484 #define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
Kojto 110:165afa46840b 9485 #define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
Kojto 110:165afa46840b 9486 #define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
Kojto 110:165afa46840b 9487 #define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
Kojto 110:165afa46840b 9488 #define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
Kojto 110:165afa46840b 9489 #define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
Kojto 110:165afa46840b 9490 #define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
Kojto 110:165afa46840b 9491 #define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
Kojto 110:165afa46840b 9492 #define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
Kojto 110:165afa46840b 9493 #define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
Kojto 110:165afa46840b 9494 #define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
Kojto 110:165afa46840b 9495 #define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
Kojto 110:165afa46840b 9496 #define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
Kojto 110:165afa46840b 9497 #define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
Kojto 110:165afa46840b 9498 #define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
Kojto 110:165afa46840b 9499
Kojto 110:165afa46840b 9500 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
Kojto 110:165afa46840b 9501 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 110:165afa46840b 9502 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 110:165afa46840b 9503 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 110:165afa46840b 9504 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 110:165afa46840b 9505 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 110:165afa46840b 9506 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 110:165afa46840b 9507 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 110:165afa46840b 9508 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 110:165afa46840b 9509 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 110:165afa46840b 9510
Kojto 110:165afa46840b 9511 /******************** Bit definition forUSB_OTG_HPRT register ********************/
Kojto 110:165afa46840b 9512 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
Kojto 110:165afa46840b 9513 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
Kojto 110:165afa46840b 9514 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
Kojto 110:165afa46840b 9515 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
Kojto 110:165afa46840b 9516 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
Kojto 110:165afa46840b 9517 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
Kojto 110:165afa46840b 9518 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
Kojto 110:165afa46840b 9519 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
Kojto 110:165afa46840b 9520 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
Kojto 110:165afa46840b 9521
Kojto 110:165afa46840b 9522 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
Kojto 110:165afa46840b 9523 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 110:165afa46840b 9524 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 110:165afa46840b 9525 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
Kojto 110:165afa46840b 9526
Kojto 110:165afa46840b 9527 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
Kojto 110:165afa46840b 9528 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 110:165afa46840b 9529 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 110:165afa46840b 9530 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 110:165afa46840b 9531 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 110:165afa46840b 9532
Kojto 110:165afa46840b 9533 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
Kojto 110:165afa46840b 9534 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 110:165afa46840b 9535 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 110:165afa46840b 9536
Kojto 110:165afa46840b 9537 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
Kojto 110:165afa46840b 9538 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 110:165afa46840b 9539 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 110:165afa46840b 9540 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
Kojto 110:165afa46840b 9541 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 110:165afa46840b 9542 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 110:165afa46840b 9543 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 110:165afa46840b 9544 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 110:165afa46840b 9545 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 110:165afa46840b 9546 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
Kojto 110:165afa46840b 9547 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 110:165afa46840b 9548 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
Kojto 110:165afa46840b 9549
Kojto 110:165afa46840b 9550 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
Kojto 110:165afa46840b 9551 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
Kojto 110:165afa46840b 9552 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
Kojto 110:165afa46840b 9553
Kojto 110:165afa46840b 9554 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
Kojto 110:165afa46840b 9555 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 110:165afa46840b 9556 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 110:165afa46840b 9557 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
Kojto 110:165afa46840b 9558 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 110:165afa46840b 9559
Kojto 110:165afa46840b 9560 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 110:165afa46840b 9561 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 110:165afa46840b 9562 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 110:165afa46840b 9563 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 110:165afa46840b 9564
Kojto 110:165afa46840b 9565 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
Kojto 110:165afa46840b 9566 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 110:165afa46840b 9567 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 110:165afa46840b 9568 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 110:165afa46840b 9569 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 110:165afa46840b 9570 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 110:165afa46840b 9571 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 110:165afa46840b 9572 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 110:165afa46840b 9573 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 110:165afa46840b 9574 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 110:165afa46840b 9575 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 110:165afa46840b 9576
Kojto 110:165afa46840b 9577 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
Kojto 110:165afa46840b 9578 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 110:165afa46840b 9579
Kojto 110:165afa46840b 9580 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
Kojto 110:165afa46840b 9581 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 110:165afa46840b 9582 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 110:165afa46840b 9583 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
Kojto 110:165afa46840b 9584 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
Kojto 110:165afa46840b 9585 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
Kojto 110:165afa46840b 9586 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
Kojto 110:165afa46840b 9587
Kojto 110:165afa46840b 9588 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 110:165afa46840b 9589 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 110:165afa46840b 9590 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 110:165afa46840b 9591
Kojto 110:165afa46840b 9592 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
Kojto 110:165afa46840b 9593 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 110:165afa46840b 9594 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 110:165afa46840b 9595
Kojto 110:165afa46840b 9596 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
Kojto 110:165afa46840b 9597 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 110:165afa46840b 9598 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 110:165afa46840b 9599 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 110:165afa46840b 9600 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 110:165afa46840b 9601 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
Kojto 110:165afa46840b 9602 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
Kojto 110:165afa46840b 9603 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
Kojto 110:165afa46840b 9604 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
Kojto 110:165afa46840b 9605 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
Kojto 110:165afa46840b 9606 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
Kojto 110:165afa46840b 9607
Kojto 110:165afa46840b 9608 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
Kojto 110:165afa46840b 9609
Kojto 110:165afa46840b 9610 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
Kojto 110:165afa46840b 9611 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 110:165afa46840b 9612 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 110:165afa46840b 9613 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 110:165afa46840b 9614 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 110:165afa46840b 9615 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 110:165afa46840b 9616 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 110:165afa46840b 9617 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 110:165afa46840b 9618
Kojto 110:165afa46840b 9619 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
Kojto 110:165afa46840b 9620 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 110:165afa46840b 9621 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 110:165afa46840b 9622 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
Kojto 110:165afa46840b 9623 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
Kojto 110:165afa46840b 9624 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
Kojto 110:165afa46840b 9625 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
Kojto 110:165afa46840b 9626 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
Kojto 110:165afa46840b 9627
Kojto 110:165afa46840b 9628 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
Kojto 110:165afa46840b 9629 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 110:165afa46840b 9630 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 110:165afa46840b 9631 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
Kojto 110:165afa46840b 9632 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
Kojto 110:165afa46840b 9633
Kojto 110:165afa46840b 9634 /******************** Bit definition forUSB_OTG_HCINT register ********************/
Kojto 110:165afa46840b 9635 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
Kojto 110:165afa46840b 9636 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
Kojto 110:165afa46840b 9637 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 110:165afa46840b 9638 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
Kojto 110:165afa46840b 9639 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
Kojto 110:165afa46840b 9640 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
Kojto 110:165afa46840b 9641 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
Kojto 110:165afa46840b 9642 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
Kojto 110:165afa46840b 9643 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
Kojto 110:165afa46840b 9644 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
Kojto 110:165afa46840b 9645 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
Kojto 110:165afa46840b 9646
Kojto 110:165afa46840b 9647 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
Kojto 110:165afa46840b 9648 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 110:165afa46840b 9649 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 110:165afa46840b 9650 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
Kojto 110:165afa46840b 9651 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
Kojto 110:165afa46840b 9652 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
Kojto 110:165afa46840b 9653 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
Kojto 110:165afa46840b 9654 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
Kojto 110:165afa46840b 9655 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
Kojto 110:165afa46840b 9656 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
Kojto 110:165afa46840b 9657 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
Kojto 110:165afa46840b 9658 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
Kojto 110:165afa46840b 9659
Kojto 110:165afa46840b 9660 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
Kojto 110:165afa46840b 9661 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
Kojto 110:165afa46840b 9662 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
Kojto 110:165afa46840b 9663 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 110:165afa46840b 9664 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
Kojto 110:165afa46840b 9665 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
Kojto 110:165afa46840b 9666 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
Kojto 110:165afa46840b 9667 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
Kojto 110:165afa46840b 9668 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
Kojto 110:165afa46840b 9669 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
Kojto 110:165afa46840b 9670 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
Kojto 110:165afa46840b 9671 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
Kojto 110:165afa46840b 9672
Kojto 110:165afa46840b 9673 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
Kojto 110:165afa46840b 9674
Kojto 110:165afa46840b 9675 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 110:165afa46840b 9676 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 110:165afa46840b 9677 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
Kojto 110:165afa46840b 9678 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
Kojto 110:165afa46840b 9679 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 110:165afa46840b 9680 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 110:165afa46840b 9681 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
Kojto 110:165afa46840b 9682 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
Kojto 110:165afa46840b 9683 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 110:165afa46840b 9684 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 110:165afa46840b 9685
Kojto 110:165afa46840b 9686 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
Kojto 110:165afa46840b 9687 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 110:165afa46840b 9688
Kojto 110:165afa46840b 9689 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
Kojto 110:165afa46840b 9690 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 110:165afa46840b 9691
Kojto 110:165afa46840b 9692 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
Kojto 110:165afa46840b 9693 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
Kojto 110:165afa46840b 9694
Kojto 110:165afa46840b 9695 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
Kojto 110:165afa46840b 9696 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
Kojto 110:165afa46840b 9697 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
Kojto 110:165afa46840b 9698
Kojto 110:165afa46840b 9699 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
Kojto 110:165afa46840b 9700
Kojto 110:165afa46840b 9701 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
Kojto 110:165afa46840b 9702 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 110:165afa46840b 9703 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 110:165afa46840b 9704 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 110:165afa46840b 9705 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 110:165afa46840b 9706 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 110:165afa46840b 9707 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 110:165afa46840b 9708 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 110:165afa46840b 9709 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
Kojto 110:165afa46840b 9710 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 110:165afa46840b 9711 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 110:165afa46840b 9712 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 110:165afa46840b 9713 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 110:165afa46840b 9714 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 110:165afa46840b 9715
Kojto 110:165afa46840b 9716 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
Kojto 110:165afa46840b 9717 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 110:165afa46840b 9718 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 110:165afa46840b 9719 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
Kojto 110:165afa46840b 9720 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
Kojto 110:165afa46840b 9721 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
Kojto 110:165afa46840b 9722 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
Kojto 110:165afa46840b 9723
Kojto 110:165afa46840b 9724 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
Kojto 110:165afa46840b 9725
Kojto 110:165afa46840b 9726 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 110:165afa46840b 9727 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 110:165afa46840b 9728
Kojto 110:165afa46840b 9729 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
Kojto 110:165afa46840b 9730 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 110:165afa46840b 9731 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 110:165afa46840b 9732
Kojto 110:165afa46840b 9733 /******************** Bit definition for PCGCCTL register ********************/
Kojto 110:165afa46840b 9734 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
Kojto 110:165afa46840b 9735 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 110:165afa46840b 9736 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 110:165afa46840b 9737
Kojto 110:165afa46840b 9738
Kojto 110:165afa46840b 9739 /**
Kojto 110:165afa46840b 9740 * @}
Kojto 110:165afa46840b 9741 */
Kojto 110:165afa46840b 9742
Kojto 110:165afa46840b 9743 /**
Kojto 110:165afa46840b 9744 * @}
Kojto 110:165afa46840b 9745 */
Kojto 110:165afa46840b 9746
Kojto 110:165afa46840b 9747 /** @addtogroup Exported_macros
Kojto 110:165afa46840b 9748 * @{
Kojto 110:165afa46840b 9749 */
Kojto 110:165afa46840b 9750
Kojto 110:165afa46840b 9751 /******************************* ADC Instances ********************************/
Kojto 110:165afa46840b 9752 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
Kojto 110:165afa46840b 9753 ((INSTANCE) == ADC2) || \
Kojto 110:165afa46840b 9754 ((INSTANCE) == ADC3))
Kojto 110:165afa46840b 9755
Kojto 110:165afa46840b 9756 /******************************* CAN Instances ********************************/
Kojto 110:165afa46840b 9757 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
Kojto 110:165afa46840b 9758 ((INSTANCE) == CAN2))
Kojto 110:165afa46840b 9759
Kojto 110:165afa46840b 9760 /******************************* CRC Instances ********************************/
Kojto 110:165afa46840b 9761 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 110:165afa46840b 9762
Kojto 110:165afa46840b 9763 /******************************* DAC Instances ********************************/
Kojto 110:165afa46840b 9764 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
Kojto 110:165afa46840b 9765
Kojto 110:165afa46840b 9766 /******************************* DCMI Instances *******************************/
Kojto 110:165afa46840b 9767 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
Kojto 110:165afa46840b 9768
Kojto 110:165afa46840b 9769 /******************************* DMA2D Instances *******************************/
Kojto 110:165afa46840b 9770 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
Kojto 110:165afa46840b 9771
Kojto 110:165afa46840b 9772 /******************************** DMA Instances *******************************/
Kojto 110:165afa46840b 9773 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
Kojto 110:165afa46840b 9774 ((INSTANCE) == DMA1_Stream1) || \
Kojto 110:165afa46840b 9775 ((INSTANCE) == DMA1_Stream2) || \
Kojto 110:165afa46840b 9776 ((INSTANCE) == DMA1_Stream3) || \
Kojto 110:165afa46840b 9777 ((INSTANCE) == DMA1_Stream4) || \
Kojto 110:165afa46840b 9778 ((INSTANCE) == DMA1_Stream5) || \
Kojto 110:165afa46840b 9779 ((INSTANCE) == DMA1_Stream6) || \
Kojto 110:165afa46840b 9780 ((INSTANCE) == DMA1_Stream7) || \
Kojto 110:165afa46840b 9781 ((INSTANCE) == DMA2_Stream0) || \
Kojto 110:165afa46840b 9782 ((INSTANCE) == DMA2_Stream1) || \
Kojto 110:165afa46840b 9783 ((INSTANCE) == DMA2_Stream2) || \
Kojto 110:165afa46840b 9784 ((INSTANCE) == DMA2_Stream3) || \
Kojto 110:165afa46840b 9785 ((INSTANCE) == DMA2_Stream4) || \
Kojto 110:165afa46840b 9786 ((INSTANCE) == DMA2_Stream5) || \
Kojto 110:165afa46840b 9787 ((INSTANCE) == DMA2_Stream6) || \
Kojto 110:165afa46840b 9788 ((INSTANCE) == DMA2_Stream7))
Kojto 110:165afa46840b 9789
Kojto 110:165afa46840b 9790 /******************************* GPIO Instances *******************************/
Kojto 110:165afa46840b 9791 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 110:165afa46840b 9792 ((INSTANCE) == GPIOB) || \
Kojto 110:165afa46840b 9793 ((INSTANCE) == GPIOC) || \
Kojto 110:165afa46840b 9794 ((INSTANCE) == GPIOD) || \
Kojto 110:165afa46840b 9795 ((INSTANCE) == GPIOE) || \
Kojto 110:165afa46840b 9796 ((INSTANCE) == GPIOF) || \
Kojto 110:165afa46840b 9797 ((INSTANCE) == GPIOG) || \
Kojto 110:165afa46840b 9798 ((INSTANCE) == GPIOH) || \
Kojto 110:165afa46840b 9799 ((INSTANCE) == GPIOI) || \
Kojto 110:165afa46840b 9800 ((INSTANCE) == GPIOJ) || \
Kojto 110:165afa46840b 9801 ((INSTANCE) == GPIOK))
Kojto 110:165afa46840b 9802
Kojto 110:165afa46840b 9803 /******************************** I2C Instances *******************************/
Kojto 110:165afa46840b 9804 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 110:165afa46840b 9805 ((INSTANCE) == I2C2) || \
Kojto 110:165afa46840b 9806 ((INSTANCE) == I2C3))
Kojto 110:165afa46840b 9807
Kojto 110:165afa46840b 9808 /******************************** I2S Instances *******************************/
Kojto 110:165afa46840b 9809 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
Kojto 110:165afa46840b 9810 ((INSTANCE) == SPI3))
Kojto 110:165afa46840b 9811
Kojto 110:165afa46840b 9812 /*************************** I2S Extended Instances ***************************/
Kojto 110:165afa46840b 9813 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
Kojto 110:165afa46840b 9814 ((INSTANCE) == SPI3) || \
Kojto 110:165afa46840b 9815 ((INSTANCE) == I2S2ext) || \
Kojto 110:165afa46840b 9816 ((INSTANCE) == I2S3ext))
Kojto 110:165afa46840b 9817
Kojto 110:165afa46840b 9818 /****************************** LTDC Instances ********************************/
Kojto 110:165afa46840b 9819 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
Kojto 110:165afa46840b 9820
Kojto 110:165afa46840b 9821 /******************************* RNG Instances ********************************/
Kojto 110:165afa46840b 9822 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
Kojto 110:165afa46840b 9823
Kojto 110:165afa46840b 9824 /****************************** RTC Instances *********************************/
Kojto 110:165afa46840b 9825 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 110:165afa46840b 9826
Kojto 110:165afa46840b 9827 /******************************* SAI Instances ********************************/
Kojto 110:165afa46840b 9828 #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
Kojto 110:165afa46840b 9829 ((PERIPH) == SAI1_Block_B))
Kojto 110:165afa46840b 9830
Kojto 110:165afa46840b 9831 /******************************** SPI Instances *******************************/
Kojto 110:165afa46840b 9832 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 110:165afa46840b 9833 ((INSTANCE) == SPI2) || \
Kojto 110:165afa46840b 9834 ((INSTANCE) == SPI3) || \
Kojto 110:165afa46840b 9835 ((INSTANCE) == SPI4) || \
Kojto 110:165afa46840b 9836 ((INSTANCE) == SPI5) || \
Kojto 110:165afa46840b 9837 ((INSTANCE) == SPI6))
Kojto 110:165afa46840b 9838
Kojto 110:165afa46840b 9839 /*************************** SPI Extended Instances ***************************/
Kojto 110:165afa46840b 9840 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 110:165afa46840b 9841 ((INSTANCE) == SPI2) || \
Kojto 110:165afa46840b 9842 ((INSTANCE) == SPI3) || \
Kojto 110:165afa46840b 9843 ((INSTANCE) == SPI4) || \
Kojto 110:165afa46840b 9844 ((INSTANCE) == SPI5) || \
Kojto 110:165afa46840b 9845 ((INSTANCE) == SPI6) || \
Kojto 110:165afa46840b 9846 ((INSTANCE) == I2S2ext) || \
Kojto 110:165afa46840b 9847 ((INSTANCE) == I2S3ext))
Kojto 110:165afa46840b 9848
Kojto 110:165afa46840b 9849 /****************** TIM Instances : All supported instances *******************/
Kojto 110:165afa46840b 9850 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9851 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9852 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9853 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9854 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9855 ((INSTANCE) == TIM6) || \
Kojto 110:165afa46840b 9856 ((INSTANCE) == TIM7) || \
Kojto 110:165afa46840b 9857 ((INSTANCE) == TIM8) || \
Kojto 110:165afa46840b 9858 ((INSTANCE) == TIM9) || \
Kojto 110:165afa46840b 9859 ((INSTANCE) == TIM10) || \
Kojto 110:165afa46840b 9860 ((INSTANCE) == TIM11) || \
Kojto 110:165afa46840b 9861 ((INSTANCE) == TIM12) || \
Kojto 110:165afa46840b 9862 ((INSTANCE) == TIM13) || \
Kojto 110:165afa46840b 9863 ((INSTANCE) == TIM14))
Kojto 110:165afa46840b 9864
Kojto 110:165afa46840b 9865 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 110:165afa46840b 9866 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9867 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9868 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9869 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9870 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9871 ((INSTANCE) == TIM8) || \
Kojto 110:165afa46840b 9872 ((INSTANCE) == TIM9) || \
Kojto 110:165afa46840b 9873 ((INSTANCE) == TIM10) || \
Kojto 110:165afa46840b 9874 ((INSTANCE) == TIM11) || \
Kojto 110:165afa46840b 9875 ((INSTANCE) == TIM12) || \
Kojto 110:165afa46840b 9876 ((INSTANCE) == TIM13) || \
Kojto 110:165afa46840b 9877 ((INSTANCE) == TIM14))
Kojto 110:165afa46840b 9878
Kojto 110:165afa46840b 9879 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 110:165afa46840b 9880 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9881 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9882 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9883 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9884 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9885 ((INSTANCE) == TIM8) || \
Kojto 110:165afa46840b 9886 ((INSTANCE) == TIM9) || \
Kojto 110:165afa46840b 9887 ((INSTANCE) == TIM12))
Kojto 110:165afa46840b 9888
Kojto 110:165afa46840b 9889 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 110:165afa46840b 9890 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9891 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9892 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9893 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9894 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9895 ((INSTANCE) == TIM8))
Kojto 110:165afa46840b 9896
Kojto 110:165afa46840b 9897 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 110:165afa46840b 9898 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9899 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9900 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9901 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9902 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9903 ((INSTANCE) == TIM8))
Kojto 110:165afa46840b 9904
Kojto 110:165afa46840b 9905 /******************** TIM Instances : Advanced-control timers *****************/
Kojto 110:165afa46840b 9906 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9907 ((INSTANCE) == TIM8))
Kojto 110:165afa46840b 9908
Kojto 110:165afa46840b 9909 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 110:165afa46840b 9910 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9911 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9912 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9913 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9914 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9915 ((INSTANCE) == TIM8))
Kojto 110:165afa46840b 9916
Kojto 110:165afa46840b 9917 /****************** TIM Instances : DMA requests generation (UDE) *************/
Kojto 110:165afa46840b 9918 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9919 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9920 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9921 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9922 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9923 ((INSTANCE) == TIM6) || \
Kojto 110:165afa46840b 9924 ((INSTANCE) == TIM7) || \
Kojto 110:165afa46840b 9925 ((INSTANCE) == TIM8))
Kojto 110:165afa46840b 9926
Kojto 110:165afa46840b 9927 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
Kojto 110:165afa46840b 9928 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9929 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9930 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9931 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9932 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9933 ((INSTANCE) == TIM8))
Kojto 110:165afa46840b 9934
Kojto 110:165afa46840b 9935 /************ TIM Instances : DMA requests generation (COMDE) *****************/
Kojto 110:165afa46840b 9936 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9937 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9938 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9939 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9940 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9941 ((INSTANCE) == TIM8))
Kojto 110:165afa46840b 9942
Kojto 110:165afa46840b 9943 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 110:165afa46840b 9944 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9945 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9946 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9947 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9948 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9949 ((INSTANCE) == TIM8))
Kojto 110:165afa46840b 9950
Kojto 110:165afa46840b 9951 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
Kojto 110:165afa46840b 9952 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9953 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9954 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9955 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9956 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9957 ((INSTANCE) == TIM6) || \
Kojto 110:165afa46840b 9958 ((INSTANCE) == TIM7) || \
Kojto 110:165afa46840b 9959 ((INSTANCE) == TIM8) || \
Kojto 110:165afa46840b 9960 ((INSTANCE) == TIM9) || \
Kojto 110:165afa46840b 9961 ((INSTANCE) == TIM12))
Kojto 110:165afa46840b 9962
Kojto 110:165afa46840b 9963 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 110:165afa46840b 9964 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9965 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9966 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9967 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9968 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9969 ((INSTANCE) == TIM8) || \
Kojto 110:165afa46840b 9970 ((INSTANCE) == TIM9) || \
Kojto 110:165afa46840b 9971 ((INSTANCE) == TIM12))
Kojto 110:165afa46840b 9972
Kojto 110:165afa46840b 9973 /********************** TIM Instances : 32 bit Counter ************************/
Kojto 110:165afa46840b 9974 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9975 ((INSTANCE) == TIM5))
Kojto 110:165afa46840b 9976
Kojto 110:165afa46840b 9977 /***************** TIM Instances : external trigger input availabe ************/
Kojto 110:165afa46840b 9978 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 110:165afa46840b 9979 ((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9980 ((INSTANCE) == TIM3) || \
Kojto 110:165afa46840b 9981 ((INSTANCE) == TIM4) || \
Kojto 110:165afa46840b 9982 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9983 ((INSTANCE) == TIM8))
Kojto 110:165afa46840b 9984
Kojto 110:165afa46840b 9985 /****************** TIM Instances : remapping capability **********************/
Kojto 110:165afa46840b 9986 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 110:165afa46840b 9987 ((INSTANCE) == TIM5) || \
Kojto 110:165afa46840b 9988 ((INSTANCE) == TIM11))
Kojto 110:165afa46840b 9989
Kojto 110:165afa46840b 9990 /******************* TIM Instances : output(s) available **********************/
Kojto 110:165afa46840b 9991 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 110:165afa46840b 9992 ((((INSTANCE) == TIM1) && \
Kojto 110:165afa46840b 9993 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 9994 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 110:165afa46840b 9995 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 110:165afa46840b 9996 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 110:165afa46840b 9997 || \
Kojto 110:165afa46840b 9998 (((INSTANCE) == TIM2) && \
Kojto 110:165afa46840b 9999 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 10000 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 110:165afa46840b 10001 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 110:165afa46840b 10002 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 110:165afa46840b 10003 || \
Kojto 110:165afa46840b 10004 (((INSTANCE) == TIM3) && \
Kojto 110:165afa46840b 10005 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 10006 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 110:165afa46840b 10007 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 110:165afa46840b 10008 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 110:165afa46840b 10009 || \
Kojto 110:165afa46840b 10010 (((INSTANCE) == TIM4) && \
Kojto 110:165afa46840b 10011 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 10012 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 110:165afa46840b 10013 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 110:165afa46840b 10014 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 110:165afa46840b 10015 || \
Kojto 110:165afa46840b 10016 (((INSTANCE) == TIM5) && \
Kojto 110:165afa46840b 10017 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 10018 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 110:165afa46840b 10019 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 110:165afa46840b 10020 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 110:165afa46840b 10021 || \
Kojto 110:165afa46840b 10022 (((INSTANCE) == TIM8) && \
Kojto 110:165afa46840b 10023 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 10024 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 110:165afa46840b 10025 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 110:165afa46840b 10026 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 110:165afa46840b 10027 || \
Kojto 110:165afa46840b 10028 (((INSTANCE) == TIM9) && \
Kojto 110:165afa46840b 10029 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 10030 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 110:165afa46840b 10031 || \
Kojto 110:165afa46840b 10032 (((INSTANCE) == TIM10) && \
Kojto 110:165afa46840b 10033 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 110:165afa46840b 10034 || \
Kojto 110:165afa46840b 10035 (((INSTANCE) == TIM11) && \
Kojto 110:165afa46840b 10036 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 110:165afa46840b 10037 || \
Kojto 110:165afa46840b 10038 (((INSTANCE) == TIM12) && \
Kojto 110:165afa46840b 10039 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 10040 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 110:165afa46840b 10041 || \
Kojto 110:165afa46840b 10042 (((INSTANCE) == TIM13) && \
Kojto 110:165afa46840b 10043 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 110:165afa46840b 10044 || \
Kojto 110:165afa46840b 10045 (((INSTANCE) == TIM14) && \
Kojto 110:165afa46840b 10046 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 110:165afa46840b 10047
Kojto 110:165afa46840b 10048 /************ TIM Instances : complementary output(s) available ***************/
Kojto 110:165afa46840b 10049 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 110:165afa46840b 10050 ((((INSTANCE) == TIM1) && \
Kojto 110:165afa46840b 10051 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 10052 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 110:165afa46840b 10053 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 110:165afa46840b 10054 || \
Kojto 110:165afa46840b 10055 (((INSTANCE) == TIM8) && \
Kojto 110:165afa46840b 10056 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 110:165afa46840b 10057 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 110:165afa46840b 10058 ((CHANNEL) == TIM_CHANNEL_3))))
Kojto 110:165afa46840b 10059
Kojto 110:165afa46840b 10060 /******************** USART Instances : Synchronous mode **********************/
Kojto 110:165afa46840b 10061 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 110:165afa46840b 10062 ((INSTANCE) == USART2) || \
Kojto 110:165afa46840b 10063 ((INSTANCE) == USART3) || \
Kojto 110:165afa46840b 10064 ((INSTANCE) == USART6))
Kojto 110:165afa46840b 10065
Kojto 110:165afa46840b 10066 /******************** UART Instances : Asynchronous mode **********************/
Kojto 110:165afa46840b 10067 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 110:165afa46840b 10068 ((INSTANCE) == USART2) || \
Kojto 110:165afa46840b 10069 ((INSTANCE) == USART3) || \
Kojto 110:165afa46840b 10070 ((INSTANCE) == UART4) || \
Kojto 110:165afa46840b 10071 ((INSTANCE) == UART5) || \
Kojto 110:165afa46840b 10072 ((INSTANCE) == USART6) || \
Kojto 110:165afa46840b 10073 ((INSTANCE) == UART7) || \
Kojto 110:165afa46840b 10074 ((INSTANCE) == UART8))
Kojto 110:165afa46840b 10075
Kojto 110:165afa46840b 10076 /****************** UART Instances : Hardware Flow control ********************/
Kojto 110:165afa46840b 10077 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 110:165afa46840b 10078 ((INSTANCE) == USART2) || \
Kojto 110:165afa46840b 10079 ((INSTANCE) == USART3) || \
Kojto 110:165afa46840b 10080 ((INSTANCE) == USART6))
Kojto 110:165afa46840b 10081
Kojto 110:165afa46840b 10082 /********************* UART Instances : Smard card mode ***********************/
Kojto 110:165afa46840b 10083 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 110:165afa46840b 10084 ((INSTANCE) == USART2) || \
Kojto 110:165afa46840b 10085 ((INSTANCE) == USART3) || \
Kojto 110:165afa46840b 10086 ((INSTANCE) == USART6))
Kojto 110:165afa46840b 10087
Kojto 110:165afa46840b 10088 /*********************** UART Instances : IRDA mode ***************************/
Kojto 110:165afa46840b 10089 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 110:165afa46840b 10090 ((INSTANCE) == USART2) || \
Kojto 110:165afa46840b 10091 ((INSTANCE) == USART3) || \
Kojto 110:165afa46840b 10092 ((INSTANCE) == UART4) || \
Kojto 110:165afa46840b 10093 ((INSTANCE) == UART5) || \
Kojto 110:165afa46840b 10094 ((INSTANCE) == USART6) || \
Kojto 110:165afa46840b 10095 ((INSTANCE) == UART7) || \
Kojto 110:165afa46840b 10096 ((INSTANCE) == UART8))
Kojto 110:165afa46840b 10097
Kojto 110:165afa46840b 10098 /****************************** SDIO Instances ********************************/
Kojto 110:165afa46840b 10099 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
Kojto 110:165afa46840b 10100
Kojto 110:165afa46840b 10101 /****************************** IWDG Instances ********************************/
Kojto 110:165afa46840b 10102 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 110:165afa46840b 10103
Kojto 110:165afa46840b 10104 /****************************** WWDG Instances ********************************/
Kojto 110:165afa46840b 10105 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 110:165afa46840b 10106
Kojto 110:165afa46840b 10107 /****************************** QSPI Instances ********************************/
Kojto 110:165afa46840b 10108 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
Kojto 110:165afa46840b 10109
Kojto 110:165afa46840b 10110 /****************************** USB Exported Constants ************************/
Kojto 110:165afa46840b 10111 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12
Kojto 110:165afa46840b 10112 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
Kojto 110:165afa46840b 10113 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6 /* Including EP0 */
Kojto 110:165afa46840b 10114 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
Kojto 110:165afa46840b 10115
Kojto 110:165afa46840b 10116 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16
Kojto 110:165afa46840b 10117 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
Kojto 110:165afa46840b 10118 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
Kojto 110:165afa46840b 10119 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
Kojto 110:165afa46840b 10120
Kojto 110:165afa46840b 10121 /**
Kojto 110:165afa46840b 10122 * @}
Kojto 110:165afa46840b 10123 */
Kojto 110:165afa46840b 10124
Kojto 110:165afa46840b 10125 /**
Kojto 110:165afa46840b 10126 * @}
Kojto 110:165afa46840b 10127 */
Kojto 110:165afa46840b 10128
Kojto 110:165afa46840b 10129 /**
Kojto 110:165afa46840b 10130 * @}
Kojto 110:165afa46840b 10131 */
Kojto 110:165afa46840b 10132
Kojto 110:165afa46840b 10133 #ifdef __cplusplus
Kojto 110:165afa46840b 10134 }
Kojto 110:165afa46840b 10135 #endif /* __cplusplus */
Kojto 110:165afa46840b 10136
Kojto 110:165afa46840b 10137 #endif /* __STM32F469xx_H */
Kojto 110:165afa46840b 10138
Kojto 110:165afa46840b 10139
Kojto 110:165afa46840b 10140
Kojto 110:165afa46840b 10141 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/