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TARGET_B96B_F446VE/stm32f446xx.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
112:6f327212ef96 
.

Who changed what in which revision?

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Kojto 112:6f327212ef96 1 /**
Kojto 112:6f327212ef96 2 ******************************************************************************
Kojto 112:6f327212ef96 3 * @file stm32f446xx.h
Kojto 112:6f327212ef96 4 * @author MCD Application Team
Kojto 112:6f327212ef96 5 * @version V2.3.2
Kojto 112:6f327212ef96 6 * @date 26-June-2015
Kojto 112:6f327212ef96 7 * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File.
Kojto 112:6f327212ef96 8 *
Kojto 112:6f327212ef96 9 * This file contains:
Kojto 112:6f327212ef96 10 * - Data structures and the address mapping for all peripherals
Kojto 112:6f327212ef96 11 * - Peripheral's registers declarations and bits definition
Kojto 112:6f327212ef96 12 * - Macros to access peripheral’s registers hardware
Kojto 112:6f327212ef96 13 *
Kojto 112:6f327212ef96 14 ******************************************************************************
Kojto 112:6f327212ef96 15 * @attention
Kojto 112:6f327212ef96 16 *
Kojto 112:6f327212ef96 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 112:6f327212ef96 18 *
Kojto 112:6f327212ef96 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 112:6f327212ef96 20 * are permitted provided that the following conditions are met:
Kojto 112:6f327212ef96 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 112:6f327212ef96 22 * this list of conditions and the following disclaimer.
Kojto 112:6f327212ef96 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 112:6f327212ef96 24 * this list of conditions and the following disclaimer in the documentation
Kojto 112:6f327212ef96 25 * and/or other materials provided with the distribution.
Kojto 112:6f327212ef96 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 112:6f327212ef96 27 * may be used to endorse or promote products derived from this software
Kojto 112:6f327212ef96 28 * without specific prior written permission.
Kojto 112:6f327212ef96 29 *
Kojto 112:6f327212ef96 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 112:6f327212ef96 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 112:6f327212ef96 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 112:6f327212ef96 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 112:6f327212ef96 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 112:6f327212ef96 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 112:6f327212ef96 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 112:6f327212ef96 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 112:6f327212ef96 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 112:6f327212ef96 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 112:6f327212ef96 40 *
Kojto 112:6f327212ef96 41 ******************************************************************************
Kojto 112:6f327212ef96 42 */
Kojto 112:6f327212ef96 43
Kojto 112:6f327212ef96 44 /** @addtogroup CMSIS_Device
Kojto 112:6f327212ef96 45 * @{
Kojto 112:6f327212ef96 46 */
Kojto 112:6f327212ef96 47
Kojto 112:6f327212ef96 48 /** @addtogroup stm32f446xx
Kojto 112:6f327212ef96 49 * @{
Kojto 112:6f327212ef96 50 */
Kojto 112:6f327212ef96 51
Kojto 112:6f327212ef96 52 #ifndef __STM32F446xx_H
Kojto 112:6f327212ef96 53 #define __STM32F446xx_H
Kojto 112:6f327212ef96 54
Kojto 112:6f327212ef96 55 #ifdef __cplusplus
Kojto 112:6f327212ef96 56 extern "C" {
Kojto 112:6f327212ef96 57 #endif /* __cplusplus */
Kojto 112:6f327212ef96 58
Kojto 112:6f327212ef96 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 112:6f327212ef96 60 * @{
Kojto 112:6f327212ef96 61 */
Kojto 112:6f327212ef96 62
Kojto 112:6f327212ef96 63 /**
Kojto 112:6f327212ef96 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
Kojto 112:6f327212ef96 65 */
Kojto 112:6f327212ef96 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
Kojto 112:6f327212ef96 67 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
Kojto 112:6f327212ef96 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
Kojto 112:6f327212ef96 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 112:6f327212ef96 70 #define __FPU_PRESENT 1 /*!< FPU present */
Kojto 112:6f327212ef96 71
Kojto 112:6f327212ef96 72 /**
Kojto 112:6f327212ef96 73 * @}
Kojto 112:6f327212ef96 74 */
Kojto 112:6f327212ef96 75
Kojto 112:6f327212ef96 76 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 112:6f327212ef96 77 * @{
Kojto 112:6f327212ef96 78 */
Kojto 112:6f327212ef96 79
Kojto 112:6f327212ef96 80 /**
Kojto 112:6f327212ef96 81 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
Kojto 112:6f327212ef96 82 * in @ref Library_configuration_section
Kojto 112:6f327212ef96 83 */
Kojto 112:6f327212ef96 84 typedef enum
Kojto 112:6f327212ef96 85 {
Kojto 112:6f327212ef96 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
Kojto 112:6f327212ef96 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 112:6f327212ef96 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
Kojto 112:6f327212ef96 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
Kojto 112:6f327212ef96 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
Kojto 112:6f327212ef96 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
Kojto 112:6f327212ef96 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
Kojto 112:6f327212ef96 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
Kojto 112:6f327212ef96 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
Kojto 112:6f327212ef96 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 112:6f327212ef96 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 112:6f327212ef96 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 112:6f327212ef96 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 112:6f327212ef96 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
Kojto 112:6f327212ef96 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 112:6f327212ef96 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 112:6f327212ef96 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 112:6f327212ef96 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 112:6f327212ef96 104 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 112:6f327212ef96 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 112:6f327212ef96 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 112:6f327212ef96 107 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
Kojto 112:6f327212ef96 108 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
Kojto 112:6f327212ef96 109 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
Kojto 112:6f327212ef96 110 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
Kojto 112:6f327212ef96 111 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
Kojto 112:6f327212ef96 112 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
Kojto 112:6f327212ef96 113 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
Kojto 112:6f327212ef96 114 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
Kojto 112:6f327212ef96 115 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
Kojto 112:6f327212ef96 116 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
Kojto 112:6f327212ef96 117 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
Kojto 112:6f327212ef96 118 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
Kojto 112:6f327212ef96 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 112:6f327212ef96 120 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
Kojto 112:6f327212ef96 121 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
Kojto 112:6f327212ef96 122 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
Kojto 112:6f327212ef96 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 112:6f327212ef96 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 112:6f327212ef96 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 112:6f327212ef96 126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 112:6f327212ef96 127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 112:6f327212ef96 128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 112:6f327212ef96 129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 112:6f327212ef96 130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 112:6f327212ef96 131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 112:6f327212ef96 132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 112:6f327212ef96 133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 112:6f327212ef96 134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 112:6f327212ef96 135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
Kojto 112:6f327212ef96 136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 112:6f327212ef96 137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
Kojto 112:6f327212ef96 138 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
Kojto 112:6f327212ef96 139 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
Kojto 112:6f327212ef96 140 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
Kojto 112:6f327212ef96 141 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
Kojto 112:6f327212ef96 142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
Kojto 112:6f327212ef96 143 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
Kojto 112:6f327212ef96 144 FMC_IRQn = 48, /*!< FMC global Interrupt */
Kojto 112:6f327212ef96 145 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
Kojto 112:6f327212ef96 146 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
Kojto 112:6f327212ef96 147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
Kojto 112:6f327212ef96 148 UART4_IRQn = 52, /*!< UART4 global Interrupt */
Kojto 112:6f327212ef96 149 UART5_IRQn = 53, /*!< UART5 global Interrupt */
Kojto 112:6f327212ef96 150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
Kojto 112:6f327212ef96 151 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
Kojto 112:6f327212ef96 152 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
Kojto 112:6f327212ef96 153 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
Kojto 112:6f327212ef96 154 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
Kojto 112:6f327212ef96 155 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
Kojto 112:6f327212ef96 156 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
Kojto 112:6f327212ef96 157 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
Kojto 112:6f327212ef96 158 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
Kojto 112:6f327212ef96 159 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
Kojto 112:6f327212ef96 160 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
Kojto 112:6f327212ef96 161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
Kojto 112:6f327212ef96 162 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
Kojto 112:6f327212ef96 163 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
Kojto 112:6f327212ef96 164 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
Kojto 112:6f327212ef96 165 USART6_IRQn = 71, /*!< USART6 global interrupt */
Kojto 112:6f327212ef96 166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
Kojto 112:6f327212ef96 167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
Kojto 112:6f327212ef96 168 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
Kojto 112:6f327212ef96 169 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
Kojto 112:6f327212ef96 170 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
Kojto 112:6f327212ef96 171 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
Kojto 112:6f327212ef96 172 DCMI_IRQn = 78, /*!< DCMI global interrupt */
Kojto 112:6f327212ef96 173 FPU_IRQn = 81, /*!< FPU global interrupt */
Kojto 112:6f327212ef96 174 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
Kojto 112:6f327212ef96 175 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
Kojto 112:6f327212ef96 176 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
Kojto 112:6f327212ef96 177 QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
Kojto 112:6f327212ef96 178 CEC_IRQn = 93, /*!< CEC global Interrupt */
Kojto 112:6f327212ef96 179 SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */
Kojto 112:6f327212ef96 180 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
Kojto 112:6f327212ef96 181 FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
Kojto 112:6f327212ef96 182 } IRQn_Type;
Kojto 112:6f327212ef96 183
Kojto 112:6f327212ef96 184 /**
Kojto 112:6f327212ef96 185 * @}
Kojto 112:6f327212ef96 186 */
Kojto 112:6f327212ef96 187
Kojto 112:6f327212ef96 188 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Kojto 112:6f327212ef96 189 #include "system_stm32f4xx.h"
Kojto 112:6f327212ef96 190 #include <stdint.h>
Kojto 112:6f327212ef96 191
Kojto 112:6f327212ef96 192 /** @addtogroup Peripheral_registers_structures
Kojto 112:6f327212ef96 193 * @{
Kojto 112:6f327212ef96 194 */
Kojto 112:6f327212ef96 195
Kojto 112:6f327212ef96 196 /**
Kojto 112:6f327212ef96 197 * @brief Analog to Digital Converter
Kojto 112:6f327212ef96 198 */
Kojto 112:6f327212ef96 199
Kojto 112:6f327212ef96 200 typedef struct
Kojto 112:6f327212ef96 201 {
Kojto 112:6f327212ef96 202 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
Kojto 112:6f327212ef96 203 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
Kojto 112:6f327212ef96 204 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
Kojto 112:6f327212ef96 205 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
Kojto 112:6f327212ef96 206 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
Kojto 112:6f327212ef96 207 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
Kojto 112:6f327212ef96 208 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
Kojto 112:6f327212ef96 209 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
Kojto 112:6f327212ef96 210 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
Kojto 112:6f327212ef96 211 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
Kojto 112:6f327212ef96 212 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
Kojto 112:6f327212ef96 213 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
Kojto 112:6f327212ef96 214 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
Kojto 112:6f327212ef96 215 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
Kojto 112:6f327212ef96 216 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
Kojto 112:6f327212ef96 217 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
Kojto 112:6f327212ef96 218 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
Kojto 112:6f327212ef96 219 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
Kojto 112:6f327212ef96 220 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
Kojto 112:6f327212ef96 221 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
Kojto 112:6f327212ef96 222 } ADC_TypeDef;
Kojto 112:6f327212ef96 223
Kojto 112:6f327212ef96 224 typedef struct
Kojto 112:6f327212ef96 225 {
Kojto 112:6f327212ef96 226 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
Kojto 112:6f327212ef96 227 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
Kojto 112:6f327212ef96 228 __IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto 112:6f327212ef96 229 AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto 112:6f327212ef96 230 } ADC_Common_TypeDef;
Kojto 112:6f327212ef96 231
Kojto 112:6f327212ef96 232
Kojto 112:6f327212ef96 233 /**
Kojto 112:6f327212ef96 234 * @brief Controller Area Network TxMailBox
Kojto 112:6f327212ef96 235 */
Kojto 112:6f327212ef96 236
Kojto 112:6f327212ef96 237 typedef struct
Kojto 112:6f327212ef96 238 {
Kojto 112:6f327212ef96 239 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 112:6f327212ef96 240 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 112:6f327212ef96 241 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 112:6f327212ef96 242 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 112:6f327212ef96 243 } CAN_TxMailBox_TypeDef;
Kojto 112:6f327212ef96 244
Kojto 112:6f327212ef96 245 /**
Kojto 112:6f327212ef96 246 * @brief Controller Area Network FIFOMailBox
Kojto 112:6f327212ef96 247 */
Kojto 112:6f327212ef96 248
Kojto 112:6f327212ef96 249 typedef struct
Kojto 112:6f327212ef96 250 {
Kojto 112:6f327212ef96 251 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 112:6f327212ef96 252 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 112:6f327212ef96 253 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 112:6f327212ef96 254 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 112:6f327212ef96 255 } CAN_FIFOMailBox_TypeDef;
Kojto 112:6f327212ef96 256
Kojto 112:6f327212ef96 257 /**
Kojto 112:6f327212ef96 258 * @brief Controller Area Network FilterRegister
Kojto 112:6f327212ef96 259 */
Kojto 112:6f327212ef96 260
Kojto 112:6f327212ef96 261 typedef struct
Kojto 112:6f327212ef96 262 {
Kojto 112:6f327212ef96 263 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 112:6f327212ef96 264 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 112:6f327212ef96 265 } CAN_FilterRegister_TypeDef;
Kojto 112:6f327212ef96 266
Kojto 112:6f327212ef96 267 /**
Kojto 112:6f327212ef96 268 * @brief Controller Area Network
Kojto 112:6f327212ef96 269 */
Kojto 112:6f327212ef96 270
Kojto 112:6f327212ef96 271 typedef struct
Kojto 112:6f327212ef96 272 {
Kojto 112:6f327212ef96 273 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 274 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 112:6f327212ef96 275 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 276 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 112:6f327212ef96 277 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 112:6f327212ef96 278 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 112:6f327212ef96 279 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 112:6f327212ef96 280 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 112:6f327212ef96 281 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 112:6f327212ef96 282 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 112:6f327212ef96 283 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 112:6f327212ef96 284 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 112:6f327212ef96 285 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 112:6f327212ef96 286 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 112:6f327212ef96 287 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 112:6f327212ef96 288 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 112:6f327212ef96 289 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 112:6f327212ef96 290 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 112:6f327212ef96 291 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 112:6f327212ef96 292 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 112:6f327212ef96 293 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 112:6f327212ef96 294 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 112:6f327212ef96 295 } CAN_TypeDef;
Kojto 112:6f327212ef96 296
Kojto 112:6f327212ef96 297 /**
Kojto 112:6f327212ef96 298 * @brief Consumer Electronics Control
Kojto 112:6f327212ef96 299 */
Kojto 112:6f327212ef96 300
Kojto 112:6f327212ef96 301 typedef struct
Kojto 112:6f327212ef96 302 {
Kojto 112:6f327212ef96 303 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
Kojto 112:6f327212ef96 304 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
Kojto 112:6f327212ef96 305 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
Kojto 112:6f327212ef96 306 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
Kojto 112:6f327212ef96 307 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
Kojto 112:6f327212ef96 308 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
Kojto 112:6f327212ef96 309 }CEC_TypeDef;
Kojto 112:6f327212ef96 310
Kojto 112:6f327212ef96 311 /**
Kojto 112:6f327212ef96 312 * @brief CRC calculation unit
Kojto 112:6f327212ef96 313 */
Kojto 112:6f327212ef96 314
Kojto 112:6f327212ef96 315 typedef struct
Kojto 112:6f327212ef96 316 {
Kojto 112:6f327212ef96 317 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 112:6f327212ef96 318 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 112:6f327212ef96 319 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 112:6f327212ef96 320 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 112:6f327212ef96 321 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 112:6f327212ef96 322 } CRC_TypeDef;
Kojto 112:6f327212ef96 323
Kojto 112:6f327212ef96 324 /**
Kojto 112:6f327212ef96 325 * @brief Digital to Analog Converter
Kojto 112:6f327212ef96 326 */
Kojto 112:6f327212ef96 327
Kojto 112:6f327212ef96 328 typedef struct
Kojto 112:6f327212ef96 329 {
Kojto 112:6f327212ef96 330 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 331 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 112:6f327212ef96 332 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 112:6f327212ef96 333 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 112:6f327212ef96 334 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 112:6f327212ef96 335 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 112:6f327212ef96 336 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 112:6f327212ef96 337 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 112:6f327212ef96 338 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 112:6f327212ef96 339 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 112:6f327212ef96 340 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 112:6f327212ef96 341 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 112:6f327212ef96 342 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 112:6f327212ef96 343 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 112:6f327212ef96 344 } DAC_TypeDef;
Kojto 112:6f327212ef96 345
Kojto 112:6f327212ef96 346 /**
Kojto 112:6f327212ef96 347 * @brief Debug MCU
Kojto 112:6f327212ef96 348 */
Kojto 112:6f327212ef96 349
Kojto 112:6f327212ef96 350 typedef struct
Kojto 112:6f327212ef96 351 {
Kojto 112:6f327212ef96 352 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 112:6f327212ef96 353 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 354 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 112:6f327212ef96 355 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 112:6f327212ef96 356 }DBGMCU_TypeDef;
Kojto 112:6f327212ef96 357
Kojto 112:6f327212ef96 358 /**
Kojto 112:6f327212ef96 359 * @brief DCMI
Kojto 112:6f327212ef96 360 */
Kojto 112:6f327212ef96 361
Kojto 112:6f327212ef96 362 typedef struct
Kojto 112:6f327212ef96 363 {
Kojto 112:6f327212ef96 364 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
Kojto 112:6f327212ef96 365 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
Kojto 112:6f327212ef96 366 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 367 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
Kojto 112:6f327212ef96 368 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
Kojto 112:6f327212ef96 369 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
Kojto 112:6f327212ef96 370 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
Kojto 112:6f327212ef96 371 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
Kojto 112:6f327212ef96 372 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
Kojto 112:6f327212ef96 373 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
Kojto 112:6f327212ef96 374 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
Kojto 112:6f327212ef96 375 } DCMI_TypeDef;
Kojto 112:6f327212ef96 376
Kojto 112:6f327212ef96 377 /**
Kojto 112:6f327212ef96 378 * @brief DMA Controller
Kojto 112:6f327212ef96 379 */
Kojto 112:6f327212ef96 380
Kojto 112:6f327212ef96 381 typedef struct
Kojto 112:6f327212ef96 382 {
Kojto 112:6f327212ef96 383 __IO uint32_t CR; /*!< DMA stream x configuration register */
Kojto 112:6f327212ef96 384 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
Kojto 112:6f327212ef96 385 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
Kojto 112:6f327212ef96 386 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
Kojto 112:6f327212ef96 387 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
Kojto 112:6f327212ef96 388 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
Kojto 112:6f327212ef96 389 } DMA_Stream_TypeDef;
Kojto 112:6f327212ef96 390
Kojto 112:6f327212ef96 391 typedef struct
Kojto 112:6f327212ef96 392 {
Kojto 112:6f327212ef96 393 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
Kojto 112:6f327212ef96 394 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
Kojto 112:6f327212ef96 395 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
Kojto 112:6f327212ef96 396 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
Kojto 112:6f327212ef96 397 } DMA_TypeDef;
Kojto 112:6f327212ef96 398
Kojto 112:6f327212ef96 399
Kojto 112:6f327212ef96 400 /**
Kojto 112:6f327212ef96 401 * @brief External Interrupt/Event Controller
Kojto 112:6f327212ef96 402 */
Kojto 112:6f327212ef96 403
Kojto 112:6f327212ef96 404 typedef struct
Kojto 112:6f327212ef96 405 {
Kojto 112:6f327212ef96 406 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 112:6f327212ef96 407 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
Kojto 112:6f327212ef96 408 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
Kojto 112:6f327212ef96 409 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 112:6f327212ef96 410 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 112:6f327212ef96 411 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
Kojto 112:6f327212ef96 412 } EXTI_TypeDef;
Kojto 112:6f327212ef96 413
Kojto 112:6f327212ef96 414 /**
Kojto 112:6f327212ef96 415 * @brief FLASH Registers
Kojto 112:6f327212ef96 416 */
Kojto 112:6f327212ef96 417
Kojto 112:6f327212ef96 418 typedef struct
Kojto 112:6f327212ef96 419 {
Kojto 112:6f327212ef96 420 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 421 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
Kojto 112:6f327212ef96 422 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
Kojto 112:6f327212ef96 423 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
Kojto 112:6f327212ef96 424 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
Kojto 112:6f327212ef96 425 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
Kojto 112:6f327212ef96 426 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
Kojto 112:6f327212ef96 427 } FLASH_TypeDef;
Kojto 112:6f327212ef96 428
Kojto 112:6f327212ef96 429 /**
Kojto 112:6f327212ef96 430 * @brief Flexible Memory Controller
Kojto 112:6f327212ef96 431 */
Kojto 112:6f327212ef96 432
Kojto 112:6f327212ef96 433 typedef struct
Kojto 112:6f327212ef96 434 {
Kojto 112:6f327212ef96 435 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
Kojto 112:6f327212ef96 436 } FMC_Bank1_TypeDef;
Kojto 112:6f327212ef96 437
Kojto 112:6f327212ef96 438 /**
Kojto 112:6f327212ef96 439 * @brief Flexible Memory Controller Bank1E
Kojto 112:6f327212ef96 440 */
Kojto 112:6f327212ef96 441
Kojto 112:6f327212ef96 442 typedef struct
Kojto 112:6f327212ef96 443 {
Kojto 112:6f327212ef96 444 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
Kojto 112:6f327212ef96 445 } FMC_Bank1E_TypeDef;
Kojto 112:6f327212ef96 446
Kojto 112:6f327212ef96 447 /**
Kojto 112:6f327212ef96 448 * @brief Flexible Memory Controller Bank3
Kojto 112:6f327212ef96 449 */
Kojto 112:6f327212ef96 450
Kojto 112:6f327212ef96 451 typedef struct
Kojto 112:6f327212ef96 452 {
Kojto 112:6f327212ef96 453 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
Kojto 112:6f327212ef96 454 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
Kojto 112:6f327212ef96 455 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
Kojto 112:6f327212ef96 456 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
Kojto 112:6f327212ef96 457 uint32_t RESERVED; /*!< Reserved, 0x90 */
Kojto 112:6f327212ef96 458 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
Kojto 112:6f327212ef96 459 } FMC_Bank3_TypeDef;
Kojto 112:6f327212ef96 460
Kojto 112:6f327212ef96 461 /**
Kojto 112:6f327212ef96 462 * @brief Flexible Memory Controller Bank5_6
Kojto 112:6f327212ef96 463 */
Kojto 112:6f327212ef96 464
Kojto 112:6f327212ef96 465 typedef struct
Kojto 112:6f327212ef96 466 {
Kojto 112:6f327212ef96 467 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
Kojto 112:6f327212ef96 468 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
Kojto 112:6f327212ef96 469 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
Kojto 112:6f327212ef96 470 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
Kojto 112:6f327212ef96 471 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
Kojto 112:6f327212ef96 472 } FMC_Bank5_6_TypeDef;
Kojto 112:6f327212ef96 473
Kojto 112:6f327212ef96 474 /**
Kojto 112:6f327212ef96 475 * @brief General Purpose I/O
Kojto 112:6f327212ef96 476 */
Kojto 112:6f327212ef96 477
Kojto 112:6f327212ef96 478 typedef struct
Kojto 112:6f327212ef96 479 {
Kojto 112:6f327212ef96 480 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 112:6f327212ef96 481 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 112:6f327212ef96 482 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 112:6f327212ef96 483 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 112:6f327212ef96 484 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 112:6f327212ef96 485 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 112:6f327212ef96 486 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
Kojto 112:6f327212ef96 487 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 112:6f327212ef96 488 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 112:6f327212ef96 489 } GPIO_TypeDef;
Kojto 112:6f327212ef96 490
Kojto 112:6f327212ef96 491 /**
Kojto 112:6f327212ef96 492 * @brief System configuration controller
Kojto 112:6f327212ef96 493 */
Kojto 112:6f327212ef96 494
Kojto 112:6f327212ef96 495 typedef struct
Kojto 112:6f327212ef96 496 {
Kojto 112:6f327212ef96 497 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 112:6f327212ef96 498 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 499 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 112:6f327212ef96 500 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
Kojto 112:6f327212ef96 501 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
Kojto 112:6f327212ef96 502 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
Kojto 112:6f327212ef96 503 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
Kojto 112:6f327212ef96 504 } SYSCFG_TypeDef;
Kojto 112:6f327212ef96 505
Kojto 112:6f327212ef96 506 /**
Kojto 112:6f327212ef96 507 * @brief Inter-integrated Circuit Interface
Kojto 112:6f327212ef96 508 */
Kojto 112:6f327212ef96 509
Kojto 112:6f327212ef96 510 typedef struct
Kojto 112:6f327212ef96 511 {
Kojto 112:6f327212ef96 512 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 112:6f327212ef96 513 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 112:6f327212ef96 514 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
Kojto 112:6f327212ef96 515 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
Kojto 112:6f327212ef96 516 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
Kojto 112:6f327212ef96 517 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
Kojto 112:6f327212ef96 518 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
Kojto 112:6f327212ef96 519 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
Kojto 112:6f327212ef96 520 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
Kojto 112:6f327212ef96 521 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
Kojto 112:6f327212ef96 522 } I2C_TypeDef;
Kojto 112:6f327212ef96 523
Kojto 112:6f327212ef96 524 /**
Kojto 112:6f327212ef96 525 * @brief Inter-integrated Circuit Interface
Kojto 112:6f327212ef96 526 */
Kojto 112:6f327212ef96 527
Kojto 112:6f327212ef96 528 typedef struct
Kojto 112:6f327212ef96 529 {
Kojto 112:6f327212ef96 530 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
Kojto 112:6f327212ef96 531 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
Kojto 112:6f327212ef96 532 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
Kojto 112:6f327212ef96 533 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
Kojto 112:6f327212ef96 534 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
Kojto 112:6f327212ef96 535 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
Kojto 112:6f327212ef96 536 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
Kojto 112:6f327212ef96 537 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
Kojto 112:6f327212ef96 538 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
Kojto 112:6f327212ef96 539 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
Kojto 112:6f327212ef96 540 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
Kojto 112:6f327212ef96 541 } FMPI2C_TypeDef;
Kojto 112:6f327212ef96 542
Kojto 112:6f327212ef96 543 /**
Kojto 112:6f327212ef96 544 * @brief Independent WATCHDOG
Kojto 112:6f327212ef96 545 */
Kojto 112:6f327212ef96 546
Kojto 112:6f327212ef96 547 typedef struct
Kojto 112:6f327212ef96 548 {
Kojto 112:6f327212ef96 549 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 112:6f327212ef96 550 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 112:6f327212ef96 551 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 112:6f327212ef96 552 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 112:6f327212ef96 553 } IWDG_TypeDef;
Kojto 112:6f327212ef96 554
Kojto 112:6f327212ef96 555 /**
Kojto 112:6f327212ef96 556 * @brief Power Control
Kojto 112:6f327212ef96 557 */
Kojto 112:6f327212ef96 558
Kojto 112:6f327212ef96 559 typedef struct
Kojto 112:6f327212ef96 560 {
Kojto 112:6f327212ef96 561 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 562 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 112:6f327212ef96 563 } PWR_TypeDef;
Kojto 112:6f327212ef96 564
Kojto 112:6f327212ef96 565 /**
Kojto 112:6f327212ef96 566 * @brief Reset and Clock Control
Kojto 112:6f327212ef96 567 */
Kojto 112:6f327212ef96 568
Kojto 112:6f327212ef96 569 typedef struct
Kojto 112:6f327212ef96 570 {
Kojto 112:6f327212ef96 571 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 572 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 573 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
Kojto 112:6f327212ef96 574 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
Kojto 112:6f327212ef96 575 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
Kojto 112:6f327212ef96 576 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
Kojto 112:6f327212ef96 577 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
Kojto 112:6f327212ef96 578 uint32_t RESERVED0; /*!< Reserved, 0x1C */
Kojto 112:6f327212ef96 579 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
Kojto 112:6f327212ef96 580 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
Kojto 112:6f327212ef96 581 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
Kojto 112:6f327212ef96 582 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
Kojto 112:6f327212ef96 583 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
Kojto 112:6f327212ef96 584 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
Kojto 112:6f327212ef96 585 uint32_t RESERVED2; /*!< Reserved, 0x3C */
Kojto 112:6f327212ef96 586 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
Kojto 112:6f327212ef96 587 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
Kojto 112:6f327212ef96 588 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
Kojto 112:6f327212ef96 589 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
Kojto 112:6f327212ef96 590 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
Kojto 112:6f327212ef96 591 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
Kojto 112:6f327212ef96 592 uint32_t RESERVED4; /*!< Reserved, 0x5C */
Kojto 112:6f327212ef96 593 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
Kojto 112:6f327212ef96 594 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
Kojto 112:6f327212ef96 595 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
Kojto 112:6f327212ef96 596 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
Kojto 112:6f327212ef96 597 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
Kojto 112:6f327212ef96 598 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
Kojto 112:6f327212ef96 599 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
Kojto 112:6f327212ef96 600 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
Kojto 112:6f327212ef96 601 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
Kojto 112:6f327212ef96 602 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
Kojto 112:6f327212ef96 603 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
Kojto 112:6f327212ef96 604 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
Kojto 112:6f327212ef96 605 } RCC_TypeDef;
Kojto 112:6f327212ef96 606
Kojto 112:6f327212ef96 607 /**
Kojto 112:6f327212ef96 608 * @brief Real-Time Clock
Kojto 112:6f327212ef96 609 */
Kojto 112:6f327212ef96 610
Kojto 112:6f327212ef96 611 typedef struct
Kojto 112:6f327212ef96 612 {
Kojto 112:6f327212ef96 613 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 112:6f327212ef96 614 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 112:6f327212ef96 615 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 112:6f327212ef96 616 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 112:6f327212ef96 617 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 112:6f327212ef96 618 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 112:6f327212ef96 619 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
Kojto 112:6f327212ef96 620 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 112:6f327212ef96 621 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 112:6f327212ef96 622 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 112:6f327212ef96 623 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 112:6f327212ef96 624 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 112:6f327212ef96 625 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 112:6f327212ef96 626 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 112:6f327212ef96 627 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 112:6f327212ef96 628 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 112:6f327212ef96 629 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 112:6f327212ef96 630 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 112:6f327212ef96 631 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 112:6f327212ef96 632 uint32_t RESERVED7; /*!< Reserved, 0x4C */
Kojto 112:6f327212ef96 633 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
Kojto 112:6f327212ef96 634 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 112:6f327212ef96 635 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 112:6f327212ef96 636 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 112:6f327212ef96 637 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 112:6f327212ef96 638 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 112:6f327212ef96 639 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 112:6f327212ef96 640 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 112:6f327212ef96 641 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 112:6f327212ef96 642 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 112:6f327212ef96 643 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 112:6f327212ef96 644 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 112:6f327212ef96 645 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 112:6f327212ef96 646 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 112:6f327212ef96 647 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 112:6f327212ef96 648 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 112:6f327212ef96 649 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 112:6f327212ef96 650 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 112:6f327212ef96 651 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 112:6f327212ef96 652 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 112:6f327212ef96 653 } RTC_TypeDef;
Kojto 112:6f327212ef96 654
Kojto 112:6f327212ef96 655 /**
Kojto 112:6f327212ef96 656 * @brief Serial Audio Interface
Kojto 112:6f327212ef96 657 */
Kojto 112:6f327212ef96 658
Kojto 112:6f327212ef96 659 typedef struct
Kojto 112:6f327212ef96 660 {
Kojto 112:6f327212ef96 661 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
Kojto 112:6f327212ef96 662 } SAI_TypeDef;
Kojto 112:6f327212ef96 663
Kojto 112:6f327212ef96 664 typedef struct
Kojto 112:6f327212ef96 665 {
Kojto 112:6f327212ef96 666 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
Kojto 112:6f327212ef96 667 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
Kojto 112:6f327212ef96 668 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
Kojto 112:6f327212ef96 669 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
Kojto 112:6f327212ef96 670 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
Kojto 112:6f327212ef96 671 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
Kojto 112:6f327212ef96 672 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
Kojto 112:6f327212ef96 673 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
Kojto 112:6f327212ef96 674 } SAI_Block_TypeDef;
Kojto 112:6f327212ef96 675
Kojto 112:6f327212ef96 676 /**
Kojto 112:6f327212ef96 677 * @brief SD host Interface
Kojto 112:6f327212ef96 678 */
Kojto 112:6f327212ef96 679
Kojto 112:6f327212ef96 680 typedef struct
Kojto 112:6f327212ef96 681 {
Kojto 112:6f327212ef96 682 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 683 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
Kojto 112:6f327212ef96 684 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
Kojto 112:6f327212ef96 685 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
Kojto 112:6f327212ef96 686 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
Kojto 112:6f327212ef96 687 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
Kojto 112:6f327212ef96 688 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
Kojto 112:6f327212ef96 689 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
Kojto 112:6f327212ef96 690 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
Kojto 112:6f327212ef96 691 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
Kojto 112:6f327212ef96 692 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
Kojto 112:6f327212ef96 693 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
Kojto 112:6f327212ef96 694 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
Kojto 112:6f327212ef96 695 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
Kojto 112:6f327212ef96 696 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
Kojto 112:6f327212ef96 697 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
Kojto 112:6f327212ef96 698 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
Kojto 112:6f327212ef96 699 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
Kojto 112:6f327212ef96 700 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
Kojto 112:6f327212ef96 701 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
Kojto 112:6f327212ef96 702 } SDIO_TypeDef;
Kojto 112:6f327212ef96 703
Kojto 112:6f327212ef96 704 /**
Kojto 112:6f327212ef96 705 * @brief Serial Peripheral Interface
Kojto 112:6f327212ef96 706 */
Kojto 112:6f327212ef96 707
Kojto 112:6f327212ef96 708 typedef struct
Kojto 112:6f327212ef96 709 {
Kojto 112:6f327212ef96 710 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 112:6f327212ef96 711 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
Kojto 112:6f327212ef96 712 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 713 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 112:6f327212ef96 714 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 112:6f327212ef96 715 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 112:6f327212ef96 716 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 112:6f327212ef96 717 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 112:6f327212ef96 718 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 112:6f327212ef96 719 } SPI_TypeDef;
Kojto 112:6f327212ef96 720
Kojto 112:6f327212ef96 721 /**
Kojto 112:6f327212ef96 722 * @brief QUAD Serial Peripheral Interface
Kojto 112:6f327212ef96 723 */
Kojto 112:6f327212ef96 724
Kojto 112:6f327212ef96 725 typedef struct
Kojto 112:6f327212ef96 726 {
Kojto 112:6f327212ef96 727 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 728 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 729 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 730 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
Kojto 112:6f327212ef96 731 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
Kojto 112:6f327212ef96 732 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
Kojto 112:6f327212ef96 733 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
Kojto 112:6f327212ef96 734 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
Kojto 112:6f327212ef96 735 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
Kojto 112:6f327212ef96 736 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
Kojto 112:6f327212ef96 737 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
Kojto 112:6f327212ef96 738 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
Kojto 112:6f327212ef96 739 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
Kojto 112:6f327212ef96 740 } QUADSPI_TypeDef;
Kojto 112:6f327212ef96 741
Kojto 112:6f327212ef96 742 /**
Kojto 112:6f327212ef96 743 * @brief SPDIFRX Interface
Kojto 112:6f327212ef96 744 */
Kojto 112:6f327212ef96 745
Kojto 112:6f327212ef96 746 typedef struct
Kojto 112:6f327212ef96 747 {
Kojto 112:6f327212ef96 748 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 749 __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
Kojto 112:6f327212ef96 750 uint16_t RESERVED0; /*!< Reserved, 0x06 */
Kojto 112:6f327212ef96 751 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 752 __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
Kojto 112:6f327212ef96 753 uint16_t RESERVED1; /*!< Reserved, 0x0E */
Kojto 112:6f327212ef96 754 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
Kojto 112:6f327212ef96 755 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
Kojto 112:6f327212ef96 756 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
Kojto 112:6f327212ef96 757 uint16_t RESERVED2; /*!< Reserved, 0x1A */
Kojto 112:6f327212ef96 758 } SPDIFRX_TypeDef;
Kojto 112:6f327212ef96 759
Kojto 112:6f327212ef96 760 /**
Kojto 112:6f327212ef96 761 * @brief TIM
Kojto 112:6f327212ef96 762 */
Kojto 112:6f327212ef96 763
Kojto 112:6f327212ef96 764 typedef struct
Kojto 112:6f327212ef96 765 {
Kojto 112:6f327212ef96 766 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 112:6f327212ef96 767 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 112:6f327212ef96 768 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 112:6f327212ef96 769 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 112:6f327212ef96 770 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 112:6f327212ef96 771 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 112:6f327212ef96 772 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 112:6f327212ef96 773 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 112:6f327212ef96 774 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 112:6f327212ef96 775 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 112:6f327212ef96 776 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 112:6f327212ef96 777 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 112:6f327212ef96 778 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 112:6f327212ef96 779 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 112:6f327212ef96 780 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 112:6f327212ef96 781 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 112:6f327212ef96 782 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 112:6f327212ef96 783 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 112:6f327212ef96 784 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 112:6f327212ef96 785 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 112:6f327212ef96 786 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 112:6f327212ef96 787 } TIM_TypeDef;
Kojto 112:6f327212ef96 788
Kojto 112:6f327212ef96 789 /**
Kojto 112:6f327212ef96 790 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 112:6f327212ef96 791 */
Kojto 112:6f327212ef96 792
Kojto 112:6f327212ef96 793 typedef struct
Kojto 112:6f327212ef96 794 {
Kojto 112:6f327212ef96 795 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
Kojto 112:6f327212ef96 796 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
Kojto 112:6f327212ef96 797 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
Kojto 112:6f327212ef96 798 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
Kojto 112:6f327212ef96 799 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
Kojto 112:6f327212ef96 800 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
Kojto 112:6f327212ef96 801 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
Kojto 112:6f327212ef96 802 } USART_TypeDef;
Kojto 112:6f327212ef96 803
Kojto 112:6f327212ef96 804 /**
Kojto 112:6f327212ef96 805 * @brief Window WATCHDOG
Kojto 112:6f327212ef96 806 */
Kojto 112:6f327212ef96 807
Kojto 112:6f327212ef96 808 typedef struct
Kojto 112:6f327212ef96 809 {
Kojto 112:6f327212ef96 810 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 112:6f327212ef96 811 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 112:6f327212ef96 812 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 112:6f327212ef96 813 } WWDG_TypeDef;
Kojto 112:6f327212ef96 814
Kojto 112:6f327212ef96 815 /**
Kojto 112:6f327212ef96 816 * @brief USB_OTG_Core_Registers
Kojto 112:6f327212ef96 817 */
Kojto 112:6f327212ef96 818 typedef struct
Kojto 112:6f327212ef96 819 {
Kojto 112:6f327212ef96 820 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
Kojto 112:6f327212ef96 821 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
Kojto 112:6f327212ef96 822 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
Kojto 112:6f327212ef96 823 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
Kojto 112:6f327212ef96 824 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
Kojto 112:6f327212ef96 825 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
Kojto 112:6f327212ef96 826 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
Kojto 112:6f327212ef96 827 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
Kojto 112:6f327212ef96 828 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
Kojto 112:6f327212ef96 829 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
Kojto 112:6f327212ef96 830 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
Kojto 112:6f327212ef96 831 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
Kojto 112:6f327212ef96 832 uint32_t Reserved30[2]; /*!< Reserved 030h */
Kojto 112:6f327212ef96 833 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
Kojto 112:6f327212ef96 834 __IO uint32_t CID; /*!< User ID Register 03Ch */
Kojto 112:6f327212ef96 835 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
Kojto 112:6f327212ef96 836 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
Kojto 112:6f327212ef96 837 uint32_t Reserved6; /*!< Reserved 050h */
Kojto 112:6f327212ef96 838 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
Kojto 112:6f327212ef96 839 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
Kojto 112:6f327212ef96 840 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
Kojto 112:6f327212ef96 841 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
Kojto 112:6f327212ef96 842 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
Kojto 112:6f327212ef96 843 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
Kojto 112:6f327212ef96 844 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
Kojto 112:6f327212ef96 845 } USB_OTG_GlobalTypeDef;
Kojto 112:6f327212ef96 846
Kojto 112:6f327212ef96 847 /**
Kojto 112:6f327212ef96 848 * @brief USB_OTG_device_Registers
Kojto 112:6f327212ef96 849 */
Kojto 112:6f327212ef96 850 typedef struct
Kojto 112:6f327212ef96 851 {
Kojto 112:6f327212ef96 852 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
Kojto 112:6f327212ef96 853 __IO uint32_t DCTL; /*!< dev Control Register 804h */
Kojto 112:6f327212ef96 854 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
Kojto 112:6f327212ef96 855 uint32_t Reserved0C; /*!< Reserved 80Ch */
Kojto 112:6f327212ef96 856 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
Kojto 112:6f327212ef96 857 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
Kojto 112:6f327212ef96 858 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
Kojto 112:6f327212ef96 859 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
Kojto 112:6f327212ef96 860 uint32_t Reserved20; /*!< Reserved 820h */
Kojto 112:6f327212ef96 861 uint32_t Reserved9; /*!< Reserved 824h */
Kojto 112:6f327212ef96 862 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
Kojto 112:6f327212ef96 863 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
Kojto 112:6f327212ef96 864 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
Kojto 112:6f327212ef96 865 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
Kojto 112:6f327212ef96 866 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
Kojto 112:6f327212ef96 867 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
Kojto 112:6f327212ef96 868 uint32_t Reserved40; /*!< dedicated EP mask 840h */
Kojto 112:6f327212ef96 869 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
Kojto 112:6f327212ef96 870 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
Kojto 112:6f327212ef96 871 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
Kojto 112:6f327212ef96 872 } USB_OTG_DeviceTypeDef;
Kojto 112:6f327212ef96 873
Kojto 112:6f327212ef96 874 /**
Kojto 112:6f327212ef96 875 * @brief USB_OTG_IN_Endpoint-Specific_Register
Kojto 112:6f327212ef96 876 */
Kojto 112:6f327212ef96 877 typedef struct
Kojto 112:6f327212ef96 878 {
Kojto 112:6f327212ef96 879 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
Kojto 112:6f327212ef96 880 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
Kojto 112:6f327212ef96 881 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
Kojto 112:6f327212ef96 882 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
Kojto 112:6f327212ef96 883 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
Kojto 112:6f327212ef96 884 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
Kojto 112:6f327212ef96 885 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
Kojto 112:6f327212ef96 886 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto 112:6f327212ef96 887 } USB_OTG_INEndpointTypeDef;
Kojto 112:6f327212ef96 888
Kojto 112:6f327212ef96 889 /**
Kojto 112:6f327212ef96 890 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
Kojto 112:6f327212ef96 891 */
Kojto 112:6f327212ef96 892 typedef struct
Kojto 112:6f327212ef96 893 {
Kojto 112:6f327212ef96 894 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
Kojto 112:6f327212ef96 895 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
Kojto 112:6f327212ef96 896 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
Kojto 112:6f327212ef96 897 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
Kojto 112:6f327212ef96 898 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
Kojto 112:6f327212ef96 899 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
Kojto 112:6f327212ef96 900 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
Kojto 112:6f327212ef96 901 } USB_OTG_OUTEndpointTypeDef;
Kojto 112:6f327212ef96 902
Kojto 112:6f327212ef96 903 /**
Kojto 112:6f327212ef96 904 * @brief USB_OTG_Host_Mode_Register_Structures
Kojto 112:6f327212ef96 905 */
Kojto 112:6f327212ef96 906 typedef struct
Kojto 112:6f327212ef96 907 {
Kojto 112:6f327212ef96 908 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
Kojto 112:6f327212ef96 909 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
Kojto 112:6f327212ef96 910 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
Kojto 112:6f327212ef96 911 uint32_t Reserved40C; /*!< Reserved 40Ch */
Kojto 112:6f327212ef96 912 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
Kojto 112:6f327212ef96 913 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
Kojto 112:6f327212ef96 914 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
Kojto 112:6f327212ef96 915 } USB_OTG_HostTypeDef;
Kojto 112:6f327212ef96 916
Kojto 112:6f327212ef96 917 /**
Kojto 112:6f327212ef96 918 * @brief USB_OTG_Host_Channel_Specific_Registers
Kojto 112:6f327212ef96 919 */
Kojto 112:6f327212ef96 920 typedef struct
Kojto 112:6f327212ef96 921 {
Kojto 112:6f327212ef96 922 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
Kojto 112:6f327212ef96 923 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
Kojto 112:6f327212ef96 924 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
Kojto 112:6f327212ef96 925 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
Kojto 112:6f327212ef96 926 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
Kojto 112:6f327212ef96 927 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
Kojto 112:6f327212ef96 928 uint32_t Reserved[2]; /*!< Reserved */
Kojto 112:6f327212ef96 929 } USB_OTG_HostChannelTypeDef;
Kojto 112:6f327212ef96 930
Kojto 112:6f327212ef96 931 /**
Kojto 112:6f327212ef96 932 * @}
Kojto 112:6f327212ef96 933 */
Kojto 112:6f327212ef96 934
Kojto 112:6f327212ef96 935 /** @addtogroup Peripheral_memory_map
Kojto 112:6f327212ef96 936 * @{
Kojto 112:6f327212ef96 937 */
Kojto 112:6f327212ef96 938 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
Kojto 112:6f327212ef96 939 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
Kojto 112:6f327212ef96 940 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
Kojto 112:6f327212ef96 941 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 112:6f327212ef96 942 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
Kojto 112:6f327212ef96 943 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
Kojto 112:6f327212ef96 944 #define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
Kojto 112:6f327212ef96 945
Kojto 112:6f327212ef96 946 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
Kojto 112:6f327212ef96 947 #define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
Kojto 112:6f327212ef96 948 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
Kojto 112:6f327212ef96 949 #define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
Kojto 112:6f327212ef96 950 #define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
Kojto 112:6f327212ef96 951
Kojto 112:6f327212ef96 952
Kojto 112:6f327212ef96 953 /* Legacy defines */
Kojto 112:6f327212ef96 954 #define SRAM_BASE SRAM1_BASE
Kojto 112:6f327212ef96 955 #define SRAM_BB_BASE SRAM1_BB_BASE
Kojto 112:6f327212ef96 956
Kojto 112:6f327212ef96 957
Kojto 112:6f327212ef96 958 /*!< Peripheral memory map */
Kojto 112:6f327212ef96 959 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 112:6f327212ef96 960 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
Kojto 112:6f327212ef96 961 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 112:6f327212ef96 962 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
Kojto 112:6f327212ef96 963
Kojto 112:6f327212ef96 964 /*!< APB1 peripherals */
Kojto 112:6f327212ef96 965 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
Kojto 112:6f327212ef96 966 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
Kojto 112:6f327212ef96 967 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
Kojto 112:6f327212ef96 968 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
Kojto 112:6f327212ef96 969 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
Kojto 112:6f327212ef96 970 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
Kojto 112:6f327212ef96 971 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
Kojto 112:6f327212ef96 972 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
Kojto 112:6f327212ef96 973 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
Kojto 112:6f327212ef96 974 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
Kojto 112:6f327212ef96 975 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
Kojto 112:6f327212ef96 976 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
Kojto 112:6f327212ef96 977 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
Kojto 112:6f327212ef96 978 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
Kojto 112:6f327212ef96 979 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
Kojto 112:6f327212ef96 980 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
Kojto 112:6f327212ef96 981 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
Kojto 112:6f327212ef96 982 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
Kojto 112:6f327212ef96 983 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
Kojto 112:6f327212ef96 984 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
Kojto 112:6f327212ef96 985 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
Kojto 112:6f327212ef96 986 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
Kojto 112:6f327212ef96 987 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
Kojto 112:6f327212ef96 988 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
Kojto 112:6f327212ef96 989 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
Kojto 112:6f327212ef96 990 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
Kojto 112:6f327212ef96 991 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
Kojto 112:6f327212ef96 992 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
Kojto 112:6f327212ef96 993
Kojto 112:6f327212ef96 994 /*!< APB2 peripherals */
Kojto 112:6f327212ef96 995 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
Kojto 112:6f327212ef96 996 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
Kojto 112:6f327212ef96 997 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
Kojto 112:6f327212ef96 998 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
Kojto 112:6f327212ef96 999 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
Kojto 112:6f327212ef96 1000 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
Kojto 112:6f327212ef96 1001 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
Kojto 112:6f327212ef96 1002 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
Kojto 112:6f327212ef96 1003 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
Kojto 112:6f327212ef96 1004 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
Kojto 112:6f327212ef96 1005 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
Kojto 112:6f327212ef96 1006 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
Kojto 112:6f327212ef96 1007 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
Kojto 112:6f327212ef96 1008 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
Kojto 112:6f327212ef96 1009 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
Kojto 112:6f327212ef96 1010 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
Kojto 112:6f327212ef96 1011 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
Kojto 112:6f327212ef96 1012 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
Kojto 112:6f327212ef96 1013 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
Kojto 112:6f327212ef96 1014 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
Kojto 112:6f327212ef96 1015 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
Kojto 112:6f327212ef96 1016 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
Kojto 112:6f327212ef96 1017
Kojto 112:6f327212ef96 1018 /*!< AHB1 peripherals */
Kojto 112:6f327212ef96 1019 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
Kojto 112:6f327212ef96 1020 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
Kojto 112:6f327212ef96 1021 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
Kojto 112:6f327212ef96 1022 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
Kojto 112:6f327212ef96 1023 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
Kojto 112:6f327212ef96 1024 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
Kojto 112:6f327212ef96 1025 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
Kojto 112:6f327212ef96 1026 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
Kojto 112:6f327212ef96 1027 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
Kojto 112:6f327212ef96 1028 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
Kojto 112:6f327212ef96 1029 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
Kojto 112:6f327212ef96 1030 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
Kojto 112:6f327212ef96 1031 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
Kojto 112:6f327212ef96 1032 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
Kojto 112:6f327212ef96 1033 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
Kojto 112:6f327212ef96 1034 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
Kojto 112:6f327212ef96 1035 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
Kojto 112:6f327212ef96 1036 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
Kojto 112:6f327212ef96 1037 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
Kojto 112:6f327212ef96 1038 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
Kojto 112:6f327212ef96 1039 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
Kojto 112:6f327212ef96 1040 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
Kojto 112:6f327212ef96 1041 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
Kojto 112:6f327212ef96 1042 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
Kojto 112:6f327212ef96 1043 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
Kojto 112:6f327212ef96 1044 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
Kojto 112:6f327212ef96 1045 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
Kojto 112:6f327212ef96 1046 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
Kojto 112:6f327212ef96 1047 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
Kojto 112:6f327212ef96 1048
Kojto 112:6f327212ef96 1049 /*!< AHB2 peripherals */
Kojto 112:6f327212ef96 1050 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
Kojto 112:6f327212ef96 1051
Kojto 112:6f327212ef96 1052 /*!< FMC Bankx registers base address */
Kojto 112:6f327212ef96 1053 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
Kojto 112:6f327212ef96 1054 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
Kojto 112:6f327212ef96 1055 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
Kojto 112:6f327212ef96 1056 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
Kojto 112:6f327212ef96 1057
Kojto 112:6f327212ef96 1058 /*!< Debug MCU registers base address */
Kojto 112:6f327212ef96 1059 #define DBGMCU_BASE ((uint32_t )0xE0042000)
Kojto 112:6f327212ef96 1060
Kojto 112:6f327212ef96 1061 /*!< USB registers base address */
Kojto 112:6f327212ef96 1062 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
Kojto 112:6f327212ef96 1063 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
Kojto 112:6f327212ef96 1064
Kojto 112:6f327212ef96 1065 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
Kojto 112:6f327212ef96 1066 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
Kojto 112:6f327212ef96 1067 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
Kojto 112:6f327212ef96 1068 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
Kojto 112:6f327212ef96 1069 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
Kojto 112:6f327212ef96 1070 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
Kojto 112:6f327212ef96 1071 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
Kojto 112:6f327212ef96 1072 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
Kojto 112:6f327212ef96 1073 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
Kojto 112:6f327212ef96 1074 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
Kojto 112:6f327212ef96 1075 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
Kojto 112:6f327212ef96 1076 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
Kojto 112:6f327212ef96 1077
Kojto 112:6f327212ef96 1078 /**
Kojto 112:6f327212ef96 1079 * @}
Kojto 112:6f327212ef96 1080 */
Kojto 112:6f327212ef96 1081
Kojto 112:6f327212ef96 1082 /** @addtogroup Peripheral_declaration
Kojto 112:6f327212ef96 1083 * @{
Kojto 112:6f327212ef96 1084 */
Kojto 112:6f327212ef96 1085 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 112:6f327212ef96 1086 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 112:6f327212ef96 1087 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 112:6f327212ef96 1088 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto 112:6f327212ef96 1089 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 112:6f327212ef96 1090 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 112:6f327212ef96 1091 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
Kojto 112:6f327212ef96 1092 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
Kojto 112:6f327212ef96 1093 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 112:6f327212ef96 1094 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 112:6f327212ef96 1095 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 112:6f327212ef96 1096 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 112:6f327212ef96 1097 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 112:6f327212ef96 1098 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 112:6f327212ef96 1099 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
Kojto 112:6f327212ef96 1100 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 112:6f327212ef96 1101 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 112:6f327212ef96 1102 #define UART4 ((USART_TypeDef *) UART4_BASE)
Kojto 112:6f327212ef96 1103 #define UART5 ((USART_TypeDef *) UART5_BASE)
Kojto 112:6f327212ef96 1104 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 112:6f327212ef96 1105 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 112:6f327212ef96 1106 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto 112:6f327212ef96 1107 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
Kojto 112:6f327212ef96 1108 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto 112:6f327212ef96 1109 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
Kojto 112:6f327212ef96 1110 #define CEC ((CEC_TypeDef *) CEC_BASE)
Kojto 112:6f327212ef96 1111 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 112:6f327212ef96 1112 #define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto 112:6f327212ef96 1113 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 112:6f327212ef96 1114 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
Kojto 112:6f327212ef96 1115 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 112:6f327212ef96 1116 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 112:6f327212ef96 1117 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 112:6f327212ef96 1118 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 112:6f327212ef96 1119 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto 112:6f327212ef96 1120 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
Kojto 112:6f327212ef96 1121 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
Kojto 112:6f327212ef96 1122 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 112:6f327212ef96 1123 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto 112:6f327212ef96 1124 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 112:6f327212ef96 1125 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 112:6f327212ef96 1126 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto 112:6f327212ef96 1127 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto 112:6f327212ef96 1128 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto 112:6f327212ef96 1129 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
Kojto 112:6f327212ef96 1130 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
Kojto 112:6f327212ef96 1131 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
Kojto 112:6f327212ef96 1132 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
Kojto 112:6f327212ef96 1133 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
Kojto 112:6f327212ef96 1134 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
Kojto 112:6f327212ef96 1135
Kojto 112:6f327212ef96 1136 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 112:6f327212ef96 1137 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 112:6f327212ef96 1138 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 112:6f327212ef96 1139 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 112:6f327212ef96 1140 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 112:6f327212ef96 1141 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 112:6f327212ef96 1142 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Kojto 112:6f327212ef96 1143 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 112:6f327212ef96 1144 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 112:6f327212ef96 1145 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 112:6f327212ef96 1146 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 112:6f327212ef96 1147 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 112:6f327212ef96 1148 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto 112:6f327212ef96 1149 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto 112:6f327212ef96 1150 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto 112:6f327212ef96 1151 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto 112:6f327212ef96 1152 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto 112:6f327212ef96 1153 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto 112:6f327212ef96 1154 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto 112:6f327212ef96 1155 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto 112:6f327212ef96 1156 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 112:6f327212ef96 1157 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto 112:6f327212ef96 1158 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto 112:6f327212ef96 1159 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto 112:6f327212ef96 1160 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto 112:6f327212ef96 1161 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto 112:6f327212ef96 1162 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto 112:6f327212ef96 1163 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto 112:6f327212ef96 1164 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto 112:6f327212ef96 1165 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
Kojto 112:6f327212ef96 1166 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
Kojto 112:6f327212ef96 1167 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
Kojto 112:6f327212ef96 1168 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
Kojto 112:6f327212ef96 1169 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
Kojto 112:6f327212ef96 1170 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
Kojto 112:6f327212ef96 1171
Kojto 112:6f327212ef96 1172 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 112:6f327212ef96 1173
Kojto 112:6f327212ef96 1174 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto 112:6f327212ef96 1175 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
Kojto 112:6f327212ef96 1176
Kojto 112:6f327212ef96 1177 /**
Kojto 112:6f327212ef96 1178 * @}
Kojto 112:6f327212ef96 1179 */
Kojto 112:6f327212ef96 1180
Kojto 112:6f327212ef96 1181 /** @addtogroup Exported_constants
Kojto 112:6f327212ef96 1182 * @{
Kojto 112:6f327212ef96 1183 */
Kojto 112:6f327212ef96 1184
Kojto 112:6f327212ef96 1185 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 112:6f327212ef96 1186 * @{
Kojto 112:6f327212ef96 1187 */
Kojto 112:6f327212ef96 1188
Kojto 112:6f327212ef96 1189 /******************************************************************************/
Kojto 112:6f327212ef96 1190 /* Peripheral Registers_Bits_Definition */
Kojto 112:6f327212ef96 1191 /******************************************************************************/
Kojto 112:6f327212ef96 1192
Kojto 112:6f327212ef96 1193 /******************************************************************************/
Kojto 112:6f327212ef96 1194 /* */
Kojto 112:6f327212ef96 1195 /* Analog to Digital Converter */
Kojto 112:6f327212ef96 1196 /* */
Kojto 112:6f327212ef96 1197 /******************************************************************************/
Kojto 112:6f327212ef96 1198 /******************** Bit definition for ADC_SR register ********************/
Kojto 112:6f327212ef96 1199 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
Kojto 112:6f327212ef96 1200 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
Kojto 112:6f327212ef96 1201 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
Kojto 112:6f327212ef96 1202 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
Kojto 112:6f327212ef96 1203 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
Kojto 112:6f327212ef96 1204 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
Kojto 112:6f327212ef96 1205
Kojto 112:6f327212ef96 1206 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 112:6f327212ef96 1207 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 112:6f327212ef96 1208 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 1209 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 1210 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 1211 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 1212 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 1213 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
Kojto 112:6f327212ef96 1214 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
Kojto 112:6f327212ef96 1215 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
Kojto 112:6f327212ef96 1216 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
Kojto 112:6f327212ef96 1217 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
Kojto 112:6f327212ef96 1218 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
Kojto 112:6f327212ef96 1219 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
Kojto 112:6f327212ef96 1220 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
Kojto 112:6f327212ef96 1221 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 112:6f327212ef96 1222 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1223 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1224 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1225 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
Kojto 112:6f327212ef96 1226 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
Kojto 112:6f327212ef96 1227 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
Kojto 112:6f327212ef96 1228 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1229 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1230 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
Kojto 112:6f327212ef96 1231
Kojto 112:6f327212ef96 1232 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 112:6f327212ef96 1233 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
Kojto 112:6f327212ef96 1234 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
Kojto 112:6f327212ef96 1235 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
Kojto 112:6f327212ef96 1236 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
Kojto 112:6f327212ef96 1237 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
Kojto 112:6f327212ef96 1238 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
Kojto 112:6f327212ef96 1239 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
Kojto 112:6f327212ef96 1240 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1241 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1242 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1243 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1244 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
Kojto 112:6f327212ef96 1245 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1246 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1247 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
Kojto 112:6f327212ef96 1248 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
Kojto 112:6f327212ef96 1249 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1250 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1251 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1252 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1253 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
Kojto 112:6f327212ef96 1254 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1255 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1256 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
Kojto 112:6f327212ef96 1257
Kojto 112:6f327212ef96 1258 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 112:6f327212ef96 1259 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 112:6f327212ef96 1260 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 1261 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 1262 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 1263 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 112:6f327212ef96 1264 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 112:6f327212ef96 1265 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 112:6f327212ef96 1266 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 112:6f327212ef96 1267 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 112:6f327212ef96 1268 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 112:6f327212ef96 1269 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 112:6f327212ef96 1270 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 112:6f327212ef96 1271 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 112:6f327212ef96 1272 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 112:6f327212ef96 1273 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 112:6f327212ef96 1274 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 112:6f327212ef96 1275 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 112:6f327212ef96 1276 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1277 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1278 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1279 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 112:6f327212ef96 1280 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1281 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1282 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1283 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 112:6f327212ef96 1284 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1285 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1286 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1287 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 112:6f327212ef96 1288 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1289 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1290 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1291 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
Kojto 112:6f327212ef96 1292 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1293 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1294 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1295
Kojto 112:6f327212ef96 1296 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 112:6f327212ef96 1297 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 112:6f327212ef96 1298 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 1299 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 1300 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 1301 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 112:6f327212ef96 1302 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 112:6f327212ef96 1303 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 112:6f327212ef96 1304 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 112:6f327212ef96 1305 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 112:6f327212ef96 1306 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 112:6f327212ef96 1307 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 112:6f327212ef96 1308 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 112:6f327212ef96 1309 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 112:6f327212ef96 1310 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 112:6f327212ef96 1311 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 112:6f327212ef96 1312 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 112:6f327212ef96 1313 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 112:6f327212ef96 1314 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1315 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1316 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1317 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 112:6f327212ef96 1318 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1319 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1320 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1321 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 112:6f327212ef96 1322 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1323 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1324 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1325 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 112:6f327212ef96 1326 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1327 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1328 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1329 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 112:6f327212ef96 1330 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1331 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1332 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1333 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 112:6f327212ef96 1334 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1335 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1336 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1337
Kojto 112:6f327212ef96 1338 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 112:6f327212ef96 1339 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
Kojto 112:6f327212ef96 1340
Kojto 112:6f327212ef96 1341 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 112:6f327212ef96 1342 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
Kojto 112:6f327212ef96 1343
Kojto 112:6f327212ef96 1344 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 112:6f327212ef96 1345 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
Kojto 112:6f327212ef96 1346
Kojto 112:6f327212ef96 1347 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 112:6f327212ef96 1348 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
Kojto 112:6f327212ef96 1349
Kojto 112:6f327212ef96 1350 /******************* Bit definition for ADC_HTR register ********************/
Kojto 112:6f327212ef96 1351 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
Kojto 112:6f327212ef96 1352
Kojto 112:6f327212ef96 1353 /******************* Bit definition for ADC_LTR register ********************/
Kojto 112:6f327212ef96 1354 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
Kojto 112:6f327212ef96 1355
Kojto 112:6f327212ef96 1356 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 112:6f327212ef96 1357 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 112:6f327212ef96 1358 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 1359 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 1360 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 1361 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 1362 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 1363 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 112:6f327212ef96 1364 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 112:6f327212ef96 1365 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 112:6f327212ef96 1366 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 112:6f327212ef96 1367 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 112:6f327212ef96 1368 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 112:6f327212ef96 1369 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 112:6f327212ef96 1370 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 112:6f327212ef96 1371 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 112:6f327212ef96 1372 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1373 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1374 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1375 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 112:6f327212ef96 1376 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1377 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1378 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1379 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1380 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1381 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
Kojto 112:6f327212ef96 1382 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1383 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1384 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1385 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1386
Kojto 112:6f327212ef96 1387 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 112:6f327212ef96 1388 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 112:6f327212ef96 1389 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 1390 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 1391 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 1392 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 1393 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 1394 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 112:6f327212ef96 1395 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 112:6f327212ef96 1396 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 112:6f327212ef96 1397 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 112:6f327212ef96 1398 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 112:6f327212ef96 1399 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 112:6f327212ef96 1400 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 112:6f327212ef96 1401 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 112:6f327212ef96 1402 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 112:6f327212ef96 1403 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1404 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1405 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1406 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 112:6f327212ef96 1407 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1408 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1409 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1410 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1411 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1412 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 112:6f327212ef96 1413 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1414 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1415 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1416 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1417 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1418 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 112:6f327212ef96 1419 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1420 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1421 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1422 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1423 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1424
Kojto 112:6f327212ef96 1425 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 112:6f327212ef96 1426 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 112:6f327212ef96 1427 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 1428 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 1429 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 1430 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 1431 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 1432 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 112:6f327212ef96 1433 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 112:6f327212ef96 1434 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 112:6f327212ef96 1435 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 112:6f327212ef96 1436 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 112:6f327212ef96 1437 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 112:6f327212ef96 1438 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 112:6f327212ef96 1439 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 112:6f327212ef96 1440 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 112:6f327212ef96 1441 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1442 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1443 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1444 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 112:6f327212ef96 1445 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1446 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1447 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1448 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1449 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1450 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 112:6f327212ef96 1451 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1452 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1453 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1454 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1455 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1456 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 112:6f327212ef96 1457 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1458 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1459 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1460 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1461 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1462
Kojto 112:6f327212ef96 1463 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 112:6f327212ef96 1464 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 112:6f327212ef96 1465 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 1466 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 1467 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 1468 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 1469 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 1470 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 112:6f327212ef96 1471 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 112:6f327212ef96 1472 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 112:6f327212ef96 1473 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 112:6f327212ef96 1474 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 112:6f327212ef96 1475 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 112:6f327212ef96 1476 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 112:6f327212ef96 1477 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 112:6f327212ef96 1478 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 112:6f327212ef96 1479 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1480 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1481 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1482 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 112:6f327212ef96 1483 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1484 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1485 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1486 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1487 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 112:6f327212ef96 1488 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
Kojto 112:6f327212ef96 1489 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1490 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1491
Kojto 112:6f327212ef96 1492 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 112:6f327212ef96 1493 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 112:6f327212ef96 1494
Kojto 112:6f327212ef96 1495 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 112:6f327212ef96 1496 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 112:6f327212ef96 1497
Kojto 112:6f327212ef96 1498 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 112:6f327212ef96 1499 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 112:6f327212ef96 1500
Kojto 112:6f327212ef96 1501 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 112:6f327212ef96 1502 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
Kojto 112:6f327212ef96 1503
Kojto 112:6f327212ef96 1504 /******************** Bit definition for ADC_DR register ********************/
Kojto 112:6f327212ef96 1505 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
Kojto 112:6f327212ef96 1506 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
Kojto 112:6f327212ef96 1507
Kojto 112:6f327212ef96 1508 /******************* Bit definition for ADC_CSR register ********************/
Kojto 112:6f327212ef96 1509 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
Kojto 112:6f327212ef96 1510 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
Kojto 112:6f327212ef96 1511 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
Kojto 112:6f327212ef96 1512 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
Kojto 112:6f327212ef96 1513 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
Kojto 112:6f327212ef96 1514 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
Kojto 112:6f327212ef96 1515 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
Kojto 112:6f327212ef96 1516 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
Kojto 112:6f327212ef96 1517 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
Kojto 112:6f327212ef96 1518 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
Kojto 112:6f327212ef96 1519 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
Kojto 112:6f327212ef96 1520 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
Kojto 112:6f327212ef96 1521 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
Kojto 112:6f327212ef96 1522 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
Kojto 112:6f327212ef96 1523 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
Kojto 112:6f327212ef96 1524 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
Kojto 112:6f327212ef96 1525 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
Kojto 112:6f327212ef96 1526 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
Kojto 112:6f327212ef96 1527
Kojto 112:6f327212ef96 1528 /******************* Bit definition for ADC_CCR register ********************/
Kojto 112:6f327212ef96 1529 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
Kojto 112:6f327212ef96 1530 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 1531 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 1532 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 1533 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 1534 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 1535 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
Kojto 112:6f327212ef96 1536 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 1537 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 1538 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 1539 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 1540 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
Kojto 112:6f327212ef96 1541 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
Kojto 112:6f327212ef96 1542 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1543 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1544 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
Kojto 112:6f327212ef96 1545 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1546 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1547 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
Kojto 112:6f327212ef96 1548 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
Kojto 112:6f327212ef96 1549
Kojto 112:6f327212ef96 1550 /******************* Bit definition for ADC_CDR register ********************/
Kojto 112:6f327212ef96 1551 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
Kojto 112:6f327212ef96 1552 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
Kojto 112:6f327212ef96 1553
Kojto 112:6f327212ef96 1554 /******************************************************************************/
Kojto 112:6f327212ef96 1555 /* */
Kojto 112:6f327212ef96 1556 /* Controller Area Network */
Kojto 112:6f327212ef96 1557 /* */
Kojto 112:6f327212ef96 1558 /******************************************************************************/
Kojto 112:6f327212ef96 1559 /*!<CAN control and status registers */
Kojto 112:6f327212ef96 1560 /******************* Bit definition for CAN_MCR register ********************/
Kojto 112:6f327212ef96 1561 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
Kojto 112:6f327212ef96 1562 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
Kojto 112:6f327212ef96 1563 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
Kojto 112:6f327212ef96 1564 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
Kojto 112:6f327212ef96 1565 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
Kojto 112:6f327212ef96 1566 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
Kojto 112:6f327212ef96 1567 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
Kojto 112:6f327212ef96 1568 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
Kojto 112:6f327212ef96 1569 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
Kojto 112:6f327212ef96 1570 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
Kojto 112:6f327212ef96 1571 /******************* Bit definition for CAN_MSR register ********************/
Kojto 112:6f327212ef96 1572 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
Kojto 112:6f327212ef96 1573 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
Kojto 112:6f327212ef96 1574 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
Kojto 112:6f327212ef96 1575 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
Kojto 112:6f327212ef96 1576 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
Kojto 112:6f327212ef96 1577 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
Kojto 112:6f327212ef96 1578 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
Kojto 112:6f327212ef96 1579 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
Kojto 112:6f327212ef96 1580 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
Kojto 112:6f327212ef96 1581
Kojto 112:6f327212ef96 1582 /******************* Bit definition for CAN_TSR register ********************/
Kojto 112:6f327212ef96 1583 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
Kojto 112:6f327212ef96 1584 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
Kojto 112:6f327212ef96 1585 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
Kojto 112:6f327212ef96 1586 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
Kojto 112:6f327212ef96 1587 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
Kojto 112:6f327212ef96 1588 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
Kojto 112:6f327212ef96 1589 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
Kojto 112:6f327212ef96 1590 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
Kojto 112:6f327212ef96 1591 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
Kojto 112:6f327212ef96 1592 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
Kojto 112:6f327212ef96 1593 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
Kojto 112:6f327212ef96 1594 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
Kojto 112:6f327212ef96 1595 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
Kojto 112:6f327212ef96 1596 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
Kojto 112:6f327212ef96 1597 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
Kojto 112:6f327212ef96 1598 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
Kojto 112:6f327212ef96 1599
Kojto 112:6f327212ef96 1600 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
Kojto 112:6f327212ef96 1601 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
Kojto 112:6f327212ef96 1602 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
Kojto 112:6f327212ef96 1603 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
Kojto 112:6f327212ef96 1604
Kojto 112:6f327212ef96 1605 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
Kojto 112:6f327212ef96 1606 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 112:6f327212ef96 1607 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 112:6f327212ef96 1608 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 112:6f327212ef96 1609
Kojto 112:6f327212ef96 1610 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 112:6f327212ef96 1611 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
Kojto 112:6f327212ef96 1612 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
Kojto 112:6f327212ef96 1613 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
Kojto 112:6f327212ef96 1614 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
Kojto 112:6f327212ef96 1615
Kojto 112:6f327212ef96 1616 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 112:6f327212ef96 1617 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
Kojto 112:6f327212ef96 1618 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
Kojto 112:6f327212ef96 1619 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
Kojto 112:6f327212ef96 1620 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
Kojto 112:6f327212ef96 1621
Kojto 112:6f327212ef96 1622 /******************** Bit definition for CAN_IER register *******************/
Kojto 112:6f327212ef96 1623 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 112:6f327212ef96 1624 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
Kojto 112:6f327212ef96 1625 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
Kojto 112:6f327212ef96 1626 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
Kojto 112:6f327212ef96 1627 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
Kojto 112:6f327212ef96 1628 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
Kojto 112:6f327212ef96 1629 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
Kojto 112:6f327212ef96 1630 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
Kojto 112:6f327212ef96 1631 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
Kojto 112:6f327212ef96 1632 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
Kojto 112:6f327212ef96 1633 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
Kojto 112:6f327212ef96 1634 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
Kojto 112:6f327212ef96 1635 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
Kojto 112:6f327212ef96 1636 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
Kojto 112:6f327212ef96 1637 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
Kojto 112:6f327212ef96 1638 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
Kojto 112:6f327212ef96 1639 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
Kojto 112:6f327212ef96 1640 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
Kojto 112:6f327212ef96 1641 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
Kojto 112:6f327212ef96 1642
Kojto 112:6f327212ef96 1643
Kojto 112:6f327212ef96 1644 /******************** Bit definition for CAN_ESR register *******************/
Kojto 112:6f327212ef96 1645 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
Kojto 112:6f327212ef96 1646 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
Kojto 112:6f327212ef96 1647 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
Kojto 112:6f327212ef96 1648
Kojto 112:6f327212ef96 1649 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
Kojto 112:6f327212ef96 1650 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 1651 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 1652 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 1653
Kojto 112:6f327212ef96 1654 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 112:6f327212ef96 1655 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
Kojto 112:6f327212ef96 1656
Kojto 112:6f327212ef96 1657 /******************* Bit definition for CAN_BTR register ********************/
Kojto 112:6f327212ef96 1658 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
Kojto 112:6f327212ef96 1659 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
Kojto 112:6f327212ef96 1660 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1661 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1662 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1663 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 1664 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
Kojto 112:6f327212ef96 1665 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1666 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1667 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 1668 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
Kojto 112:6f327212ef96 1669 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 1670 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 1671 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
Kojto 112:6f327212ef96 1672 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
Kojto 112:6f327212ef96 1673
Kojto 112:6f327212ef96 1674
Kojto 112:6f327212ef96 1675 /*!<Mailbox registers */
Kojto 112:6f327212ef96 1676 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 112:6f327212ef96 1677 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 112:6f327212ef96 1678 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 112:6f327212ef96 1679 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 112:6f327212ef96 1680 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 112:6f327212ef96 1681 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1682
Kojto 112:6f327212ef96 1683 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 112:6f327212ef96 1684 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 112:6f327212ef96 1685 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 112:6f327212ef96 1686 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1687
Kojto 112:6f327212ef96 1688 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 112:6f327212ef96 1689 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 112:6f327212ef96 1690 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 112:6f327212ef96 1691 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 112:6f327212ef96 1692 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 112:6f327212ef96 1693
Kojto 112:6f327212ef96 1694 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 112:6f327212ef96 1695 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 112:6f327212ef96 1696 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 112:6f327212ef96 1697 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 112:6f327212ef96 1698 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 112:6f327212ef96 1699
Kojto 112:6f327212ef96 1700 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 112:6f327212ef96 1701 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 112:6f327212ef96 1702 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 112:6f327212ef96 1703 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 112:6f327212ef96 1704 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 112:6f327212ef96 1705 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1706
Kojto 112:6f327212ef96 1707 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 112:6f327212ef96 1708 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 112:6f327212ef96 1709 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 112:6f327212ef96 1710 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1711
Kojto 112:6f327212ef96 1712 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 112:6f327212ef96 1713 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 112:6f327212ef96 1714 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 112:6f327212ef96 1715 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 112:6f327212ef96 1716 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 112:6f327212ef96 1717
Kojto 112:6f327212ef96 1718 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 112:6f327212ef96 1719 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 112:6f327212ef96 1720 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 112:6f327212ef96 1721 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 112:6f327212ef96 1722 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 112:6f327212ef96 1723
Kojto 112:6f327212ef96 1724 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 112:6f327212ef96 1725 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 112:6f327212ef96 1726 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 112:6f327212ef96 1727 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 112:6f327212ef96 1728 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 112:6f327212ef96 1729 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1730
Kojto 112:6f327212ef96 1731 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 112:6f327212ef96 1732 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 112:6f327212ef96 1733 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 112:6f327212ef96 1734 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1735
Kojto 112:6f327212ef96 1736 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 112:6f327212ef96 1737 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 112:6f327212ef96 1738 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 112:6f327212ef96 1739 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 112:6f327212ef96 1740 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 112:6f327212ef96 1741
Kojto 112:6f327212ef96 1742 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 112:6f327212ef96 1743 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 112:6f327212ef96 1744 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 112:6f327212ef96 1745 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 112:6f327212ef96 1746 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 112:6f327212ef96 1747
Kojto 112:6f327212ef96 1748 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 112:6f327212ef96 1749 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 112:6f327212ef96 1750 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 112:6f327212ef96 1751 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 112:6f327212ef96 1752 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1753
Kojto 112:6f327212ef96 1754 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 112:6f327212ef96 1755 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 112:6f327212ef96 1756 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 112:6f327212ef96 1757 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1758
Kojto 112:6f327212ef96 1759 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 112:6f327212ef96 1760 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 112:6f327212ef96 1761 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 112:6f327212ef96 1762 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 112:6f327212ef96 1763 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 112:6f327212ef96 1764
Kojto 112:6f327212ef96 1765 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 112:6f327212ef96 1766 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 112:6f327212ef96 1767 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 112:6f327212ef96 1768 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 112:6f327212ef96 1769 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 112:6f327212ef96 1770
Kojto 112:6f327212ef96 1771 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 112:6f327212ef96 1772 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 112:6f327212ef96 1773 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 112:6f327212ef96 1774 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 112:6f327212ef96 1775 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 112:6f327212ef96 1776
Kojto 112:6f327212ef96 1777 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 112:6f327212ef96 1778 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 112:6f327212ef96 1779 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 112:6f327212ef96 1780 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 112:6f327212ef96 1781
Kojto 112:6f327212ef96 1782 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 112:6f327212ef96 1783 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 112:6f327212ef96 1784 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 112:6f327212ef96 1785 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 112:6f327212ef96 1786 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 112:6f327212ef96 1787
Kojto 112:6f327212ef96 1788 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 112:6f327212ef96 1789 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 112:6f327212ef96 1790 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 112:6f327212ef96 1791 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 112:6f327212ef96 1792 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 112:6f327212ef96 1793
Kojto 112:6f327212ef96 1794 /*!<CAN filter registers */
Kojto 112:6f327212ef96 1795 /******************* Bit definition for CAN_FMR register ********************/
Kojto 112:6f327212ef96 1796 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
Kojto 112:6f327212ef96 1797 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
Kojto 112:6f327212ef96 1798
Kojto 112:6f327212ef96 1799 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 112:6f327212ef96 1800 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
Kojto 112:6f327212ef96 1801 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
Kojto 112:6f327212ef96 1802 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
Kojto 112:6f327212ef96 1803 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
Kojto 112:6f327212ef96 1804 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
Kojto 112:6f327212ef96 1805 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
Kojto 112:6f327212ef96 1806 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
Kojto 112:6f327212ef96 1807 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
Kojto 112:6f327212ef96 1808 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
Kojto 112:6f327212ef96 1809 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
Kojto 112:6f327212ef96 1810 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
Kojto 112:6f327212ef96 1811 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
Kojto 112:6f327212ef96 1812 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
Kojto 112:6f327212ef96 1813 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
Kojto 112:6f327212ef96 1814 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
Kojto 112:6f327212ef96 1815 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
Kojto 112:6f327212ef96 1816 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
Kojto 112:6f327212ef96 1817 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
Kojto 112:6f327212ef96 1818 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
Kojto 112:6f327212ef96 1819 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
Kojto 112:6f327212ef96 1820 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
Kojto 112:6f327212ef96 1821 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
Kojto 112:6f327212ef96 1822 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
Kojto 112:6f327212ef96 1823 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
Kojto 112:6f327212ef96 1824 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
Kojto 112:6f327212ef96 1825 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
Kojto 112:6f327212ef96 1826 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
Kojto 112:6f327212ef96 1827 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
Kojto 112:6f327212ef96 1828 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
Kojto 112:6f327212ef96 1829
Kojto 112:6f327212ef96 1830 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 112:6f327212ef96 1831 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
Kojto 112:6f327212ef96 1832 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
Kojto 112:6f327212ef96 1833 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
Kojto 112:6f327212ef96 1834 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
Kojto 112:6f327212ef96 1835 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
Kojto 112:6f327212ef96 1836 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
Kojto 112:6f327212ef96 1837 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
Kojto 112:6f327212ef96 1838 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
Kojto 112:6f327212ef96 1839 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
Kojto 112:6f327212ef96 1840 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
Kojto 112:6f327212ef96 1841 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
Kojto 112:6f327212ef96 1842 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
Kojto 112:6f327212ef96 1843 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
Kojto 112:6f327212ef96 1844 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
Kojto 112:6f327212ef96 1845 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
Kojto 112:6f327212ef96 1846 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
Kojto 112:6f327212ef96 1847 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
Kojto 112:6f327212ef96 1848 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
Kojto 112:6f327212ef96 1849 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
Kojto 112:6f327212ef96 1850 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
Kojto 112:6f327212ef96 1851 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
Kojto 112:6f327212ef96 1852 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
Kojto 112:6f327212ef96 1853 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
Kojto 112:6f327212ef96 1854 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
Kojto 112:6f327212ef96 1855 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
Kojto 112:6f327212ef96 1856 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
Kojto 112:6f327212ef96 1857 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
Kojto 112:6f327212ef96 1858 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
Kojto 112:6f327212ef96 1859 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
Kojto 112:6f327212ef96 1860
Kojto 112:6f327212ef96 1861 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 112:6f327212ef96 1862 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
Kojto 112:6f327212ef96 1863 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
Kojto 112:6f327212ef96 1864 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
Kojto 112:6f327212ef96 1865 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
Kojto 112:6f327212ef96 1866 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
Kojto 112:6f327212ef96 1867 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
Kojto 112:6f327212ef96 1868 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
Kojto 112:6f327212ef96 1869 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
Kojto 112:6f327212ef96 1870 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
Kojto 112:6f327212ef96 1871 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
Kojto 112:6f327212ef96 1872 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
Kojto 112:6f327212ef96 1873 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
Kojto 112:6f327212ef96 1874 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
Kojto 112:6f327212ef96 1875 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
Kojto 112:6f327212ef96 1876 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
Kojto 112:6f327212ef96 1877 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
Kojto 112:6f327212ef96 1878 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
Kojto 112:6f327212ef96 1879 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
Kojto 112:6f327212ef96 1880 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
Kojto 112:6f327212ef96 1881 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
Kojto 112:6f327212ef96 1882 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
Kojto 112:6f327212ef96 1883 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
Kojto 112:6f327212ef96 1884 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
Kojto 112:6f327212ef96 1885 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
Kojto 112:6f327212ef96 1886 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
Kojto 112:6f327212ef96 1887 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
Kojto 112:6f327212ef96 1888 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
Kojto 112:6f327212ef96 1889 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
Kojto 112:6f327212ef96 1890 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
Kojto 112:6f327212ef96 1891
Kojto 112:6f327212ef96 1892 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 112:6f327212ef96 1893 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
Kojto 112:6f327212ef96 1894 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
Kojto 112:6f327212ef96 1895 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
Kojto 112:6f327212ef96 1896 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
Kojto 112:6f327212ef96 1897 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
Kojto 112:6f327212ef96 1898 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
Kojto 112:6f327212ef96 1899 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
Kojto 112:6f327212ef96 1900 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
Kojto 112:6f327212ef96 1901 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
Kojto 112:6f327212ef96 1902 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
Kojto 112:6f327212ef96 1903 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
Kojto 112:6f327212ef96 1904 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
Kojto 112:6f327212ef96 1905 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
Kojto 112:6f327212ef96 1906 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
Kojto 112:6f327212ef96 1907 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
Kojto 112:6f327212ef96 1908 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
Kojto 112:6f327212ef96 1909 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
Kojto 112:6f327212ef96 1910 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
Kojto 112:6f327212ef96 1911 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
Kojto 112:6f327212ef96 1912 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
Kojto 112:6f327212ef96 1913 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
Kojto 112:6f327212ef96 1914 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
Kojto 112:6f327212ef96 1915 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
Kojto 112:6f327212ef96 1916 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
Kojto 112:6f327212ef96 1917 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
Kojto 112:6f327212ef96 1918 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
Kojto 112:6f327212ef96 1919 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
Kojto 112:6f327212ef96 1920 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
Kojto 112:6f327212ef96 1921 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
Kojto 112:6f327212ef96 1922
Kojto 112:6f327212ef96 1923
Kojto 112:6f327212ef96 1924 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 112:6f327212ef96 1925 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 1926 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 1927 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 1928 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 1929 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 1930 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 1931 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 1932 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 1933 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 1934 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 1935 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 1936 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 1937 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 1938 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 1939 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 1940 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 1941 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 1942 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 1943 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 1944 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 1945 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 1946 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 1947 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 1948 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 1949 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 1950 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 1951 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 1952 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 1953 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 1954 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 1955 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 1956 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 1957
Kojto 112:6f327212ef96 1958 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 112:6f327212ef96 1959 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 1960 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 1961 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 1962 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 1963 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 1964 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 1965 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 1966 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 1967 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 1968 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 1969 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 1970 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 1971 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 1972 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 1973 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 1974 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 1975 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 1976 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 1977 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 1978 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 1979 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 1980 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 1981 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 1982 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 1983 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 1984 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 1985 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 1986 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 1987 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 1988 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 1989 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 1990 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 1991
Kojto 112:6f327212ef96 1992 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 112:6f327212ef96 1993 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 1994 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 1995 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 1996 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 1997 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 1998 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 1999 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2000 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2001 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2002 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2003 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2004 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2005 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2006 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2007 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2008 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2009 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2010 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2011 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2012 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2013 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2014 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2015 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2016 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2017 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2018 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2019 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2020 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2021 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2022 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2023 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2024 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2025
Kojto 112:6f327212ef96 2026 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 112:6f327212ef96 2027 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2028 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2029 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2030 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2031 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2032 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2033 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2034 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2035 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2036 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2037 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2038 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2039 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2040 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2041 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2042 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2043 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2044 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2045 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2046 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2047 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2048 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2049 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2050 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2051 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2052 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2053 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2054 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2055 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2056 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2057 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2058 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2059
Kojto 112:6f327212ef96 2060 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 112:6f327212ef96 2061 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2062 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2063 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2064 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2065 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2066 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2067 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2068 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2069 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2070 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2071 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2072 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2073 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2074 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2075 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2076 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2077 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2078 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2079 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2080 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2081 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2082 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2083 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2084 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2085 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2086 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2087 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2088 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2089 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2090 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2091 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2092 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2093
Kojto 112:6f327212ef96 2094 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 112:6f327212ef96 2095 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2096 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2097 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2098 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2099 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2100 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2101 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2102 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2103 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2104 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2105 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2106 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2107 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2108 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2109 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2110 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2111 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2112 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2113 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2114 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2115 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2116 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2117 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2118 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2119 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2120 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2121 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2122 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2123 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2124 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2125 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2126 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2127
Kojto 112:6f327212ef96 2128 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 112:6f327212ef96 2129 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2130 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2131 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2132 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2133 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2134 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2135 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2136 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2137 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2138 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2139 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2140 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2141 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2142 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2143 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2144 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2145 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2146 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2147 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2148 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2149 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2150 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2151 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2152 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2153 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2154 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2155 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2156 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2157 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2158 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2159 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2160 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2161
Kojto 112:6f327212ef96 2162 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 112:6f327212ef96 2163 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2164 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2165 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2166 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2167 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2168 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2169 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2170 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2171 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2172 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2173 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2174 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2175 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2176 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2177 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2178 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2179 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2180 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2181 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2182 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2183 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2184 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2185 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2186 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2187 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2188 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2189 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2190 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2191 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2192 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2193 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2194 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2195
Kojto 112:6f327212ef96 2196 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 112:6f327212ef96 2197 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2198 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2199 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2200 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2201 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2202 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2203 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2204 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2205 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2206 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2207 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2208 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2209 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2210 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2211 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2212 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2213 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2214 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2215 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2216 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2217 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2218 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2219 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2220 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2221 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2222 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2223 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2224 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2225 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2226 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2227 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2228 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2229
Kojto 112:6f327212ef96 2230 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 112:6f327212ef96 2231 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2232 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2233 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2234 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2235 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2236 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2237 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2238 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2239 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2240 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2241 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2242 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2243 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2244 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2245 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2246 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2247 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2248 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2249 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2250 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2251 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2252 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2253 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2254 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2255 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2256 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2257 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2258 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2259 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2260 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2261 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2262 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2263
Kojto 112:6f327212ef96 2264 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 112:6f327212ef96 2265 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2266 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2267 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2268 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2269 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2270 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2271 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2272 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2273 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2274 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2275 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2276 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2277 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2278 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2279 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2280 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2281 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2282 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2283 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2284 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2285 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2286 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2287 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2288 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2289 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2290 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2291 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2292 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2293 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2294 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2295 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2296 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2297
Kojto 112:6f327212ef96 2298 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 112:6f327212ef96 2299 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2300 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2301 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2302 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2303 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2304 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2305 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2306 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2307 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2308 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2309 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2310 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2311 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2312 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2313 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2314 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2315 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2316 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2317 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2318 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2319 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2320 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2321 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2322 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2323 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2324 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2325 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2326 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2327 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2328 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2329 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2330 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2331
Kojto 112:6f327212ef96 2332 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 112:6f327212ef96 2333 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2334 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2335 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2336 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2337 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2338 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2339 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2340 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2341 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2342 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2343 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2344 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2345 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2346 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2347 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2348 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2349 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2350 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2351 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2352 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2353 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2354 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2355 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2356 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2357 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2358 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2359 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2360 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2361 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2362 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2363 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2364 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2365
Kojto 112:6f327212ef96 2366 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 112:6f327212ef96 2367 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2368 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2369 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2370 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2371 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2372 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2373 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2374 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2375 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2376 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2377 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2378 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2379 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2380 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2381 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2382 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2383 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2384 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2385 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2386 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2387 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2388 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2389 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2390 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2391 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2392 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2393 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2394 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2395 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2396 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2397 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2398 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2399
Kojto 112:6f327212ef96 2400 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 112:6f327212ef96 2401 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2402 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2403 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2404 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2405 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2406 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2407 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2408 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2409 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2410 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2411 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2412 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2413 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2414 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2415 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2416 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2417 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2418 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2419 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2420 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2421 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2422 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2423 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2424 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2425 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2426 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2427 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2428 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2429 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2430 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2431 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2432 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2433
Kojto 112:6f327212ef96 2434 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 112:6f327212ef96 2435 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2436 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2437 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2438 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2439 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2440 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2441 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2442 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2443 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2444 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2445 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2446 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2447 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2448 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2449 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2450 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2451 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2452 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2453 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2454 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2455 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2456 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2457 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2458 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2459 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2460 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2461 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2462 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2463 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2464 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2465 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2466 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2467
Kojto 112:6f327212ef96 2468 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 112:6f327212ef96 2469 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2470 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2471 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2472 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2473 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2474 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2475 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2476 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2477 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2478 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2479 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2480 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2481 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2482 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2483 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2484 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2485 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2486 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2487 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2488 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2489 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2490 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2491 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2492 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2493 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2494 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2495 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2496 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2497 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2498 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2499 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2500 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2501
Kojto 112:6f327212ef96 2502 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 112:6f327212ef96 2503 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2504 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2505 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2506 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2507 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2508 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2509 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2510 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2511 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2512 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2513 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2514 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2515 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2516 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2517 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2518 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2519 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2520 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2521 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2522 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2523 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2524 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2525 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2526 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2527 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2528 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2529 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2530 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2531 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2532 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2533 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2534 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2535
Kojto 112:6f327212ef96 2536 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 112:6f327212ef96 2537 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2538 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2539 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2540 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2541 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2542 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2543 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2544 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2545 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2546 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2547 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2548 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2549 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2550 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2551 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2552 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2553 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2554 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2555 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2556 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2557 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2558 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2559 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2560 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2561 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2562 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2563 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2564 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2565 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2566 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2567 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2568 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2569
Kojto 112:6f327212ef96 2570 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 112:6f327212ef96 2571 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2572 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2573 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2574 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2575 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2576 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2577 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2578 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2579 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2580 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2581 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2582 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2583 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2584 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2585 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2586 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2587 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2588 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2589 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2590 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2591 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2592 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2593 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2594 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2595 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2596 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2597 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2598 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2599 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2600 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2601 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2602 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2603
Kojto 112:6f327212ef96 2604 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 112:6f327212ef96 2605 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2606 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2607 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2608 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2609 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2610 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2611 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2612 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2613 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2614 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2615 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2616 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2617 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2618 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2619 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2620 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2621 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2622 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2623 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2624 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2625 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2626 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2627 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2628 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2629 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2630 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2631 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2632 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2633 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2634 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2635 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2636 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2637
Kojto 112:6f327212ef96 2638 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 112:6f327212ef96 2639 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2640 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2641 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2642 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2643 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2644 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2645 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2646 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2647 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2648 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2649 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2650 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2651 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2652 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2653 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2654 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2655 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2656 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2657 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2658 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2659 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2660 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2661 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2662 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2663 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2664 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2665 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2666 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2667 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2668 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2669 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2670 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2671
Kojto 112:6f327212ef96 2672 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 112:6f327212ef96 2673 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2674 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2675 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2676 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2677 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2678 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2679 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2680 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2681 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2682 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2683 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2684 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2685 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2686 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2687 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2688 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2689 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2690 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2691 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2692 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2693 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2694 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2695 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2696 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2697 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2698 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2699 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2700 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2701 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2702 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2703 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2704 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2705
Kojto 112:6f327212ef96 2706 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 112:6f327212ef96 2707 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2708 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2709 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2710 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2711 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2712 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2713 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2714 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2715 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2716 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2717 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2718 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2719 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2720 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2721 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2722 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2723 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2724 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2725 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2726 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2727 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2728 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2729 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2730 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2731 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2732 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2733 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2734 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2735 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2736 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2737 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2738 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2739
Kojto 112:6f327212ef96 2740 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 112:6f327212ef96 2741 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2742 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2743 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2744 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2745 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2746 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2747 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2748 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2749 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2750 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2751 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2752 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2753 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2754 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2755 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2756 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2757 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2758 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2759 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2760 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2761 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2762 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2763 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2764 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2765 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2766 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2767 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2768 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2769 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2770 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2771 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2772 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2773
Kojto 112:6f327212ef96 2774 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 112:6f327212ef96 2775 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2776 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2777 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2778 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2779 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2780 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2781 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2782 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2783 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2784 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2785 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2786 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2787 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2788 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2789 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2790 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2791 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2792 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2793 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2794 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2795 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2796 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2797 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2798 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2799 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2800 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2801 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2802 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2803 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2804 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2805 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2806 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2807
Kojto 112:6f327212ef96 2808 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 112:6f327212ef96 2809 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2810 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2811 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2812 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2813 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2814 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2815 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2816 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2817 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2818 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2819 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2820 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2821 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2822 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2823 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2824 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2825 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2826 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2827 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2828 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2829 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2830 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2831 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2832 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2833 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2834 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2835 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2836 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2837 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2838 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2839 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2840 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2841
Kojto 112:6f327212ef96 2842 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 112:6f327212ef96 2843 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 112:6f327212ef96 2844 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 112:6f327212ef96 2845 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 112:6f327212ef96 2846 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 112:6f327212ef96 2847 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 112:6f327212ef96 2848 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 112:6f327212ef96 2849 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 112:6f327212ef96 2850 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 112:6f327212ef96 2851 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 112:6f327212ef96 2852 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 112:6f327212ef96 2853 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 112:6f327212ef96 2854 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 112:6f327212ef96 2855 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 112:6f327212ef96 2856 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 112:6f327212ef96 2857 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 112:6f327212ef96 2858 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 112:6f327212ef96 2859 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 112:6f327212ef96 2860 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 112:6f327212ef96 2861 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 112:6f327212ef96 2862 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 112:6f327212ef96 2863 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 112:6f327212ef96 2864 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 112:6f327212ef96 2865 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 112:6f327212ef96 2866 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 112:6f327212ef96 2867 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 112:6f327212ef96 2868 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 112:6f327212ef96 2869 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 112:6f327212ef96 2870 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 112:6f327212ef96 2871 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 112:6f327212ef96 2872 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 112:6f327212ef96 2873 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 112:6f327212ef96 2874 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 112:6f327212ef96 2875
Kojto 112:6f327212ef96 2876 /******************************************************************************/
Kojto 112:6f327212ef96 2877 /* */
Kojto 112:6f327212ef96 2878 /* HDMI-CEC (CEC) */
Kojto 112:6f327212ef96 2879 /* */
Kojto 112:6f327212ef96 2880 /******************************************************************************/
Kojto 112:6f327212ef96 2881
Kojto 112:6f327212ef96 2882 /******************* Bit definition for CEC_CR register *********************/
Kojto 112:6f327212ef96 2883 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
Kojto 112:6f327212ef96 2884 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
Kojto 112:6f327212ef96 2885 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
Kojto 112:6f327212ef96 2886
Kojto 112:6f327212ef96 2887 /******************* Bit definition for CEC_CFGR register *******************/
Kojto 112:6f327212ef96 2888 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
Kojto 112:6f327212ef96 2889 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
Kojto 112:6f327212ef96 2890 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
Kojto 112:6f327212ef96 2891 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
Kojto 112:6f327212ef96 2892 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error generation */
Kojto 112:6f327212ef96 2893 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
Kojto 112:6f327212ef96 2894 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No error generation */
Kojto 112:6f327212ef96 2895 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
Kojto 112:6f327212ef96 2896 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
Kojto 112:6f327212ef96 2897
Kojto 112:6f327212ef96 2898 /******************* Bit definition for CEC_TXDR register *******************/
Kojto 112:6f327212ef96 2899 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
Kojto 112:6f327212ef96 2900
Kojto 112:6f327212ef96 2901 /******************* Bit definition for CEC_RXDR register *******************/
Kojto 112:6f327212ef96 2902 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
Kojto 112:6f327212ef96 2903
Kojto 112:6f327212ef96 2904 /******************* Bit definition for CEC_ISR register ********************/
Kojto 112:6f327212ef96 2905 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
Kojto 112:6f327212ef96 2906 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
Kojto 112:6f327212ef96 2907 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
Kojto 112:6f327212ef96 2908 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
Kojto 112:6f327212ef96 2909 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
Kojto 112:6f327212ef96 2910 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
Kojto 112:6f327212ef96 2911 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
Kojto 112:6f327212ef96 2912 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
Kojto 112:6f327212ef96 2913 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
Kojto 112:6f327212ef96 2914 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
Kojto 112:6f327212ef96 2915 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
Kojto 112:6f327212ef96 2916 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
Kojto 112:6f327212ef96 2917 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
Kojto 112:6f327212ef96 2918
Kojto 112:6f327212ef96 2919 /******************* Bit definition for CEC_IER register ********************/
Kojto 112:6f327212ef96 2920 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
Kojto 112:6f327212ef96 2921 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
Kojto 112:6f327212ef96 2922 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
Kojto 112:6f327212ef96 2923 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
Kojto 112:6f327212ef96 2924 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable */
Kojto 112:6f327212ef96 2925 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
Kojto 112:6f327212ef96 2926 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
Kojto 112:6f327212ef96 2927 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
Kojto 112:6f327212ef96 2928 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
Kojto 112:6f327212ef96 2929 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
Kojto 112:6f327212ef96 2930 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
Kojto 112:6f327212ef96 2931 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
Kojto 112:6f327212ef96 2932 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
Kojto 112:6f327212ef96 2933
Kojto 112:6f327212ef96 2934 /******************************************************************************/
Kojto 112:6f327212ef96 2935 /* */
Kojto 112:6f327212ef96 2936 /* CRC calculation unit */
Kojto 112:6f327212ef96 2937 /* */
Kojto 112:6f327212ef96 2938 /******************************************************************************/
Kojto 112:6f327212ef96 2939 /******************* Bit definition for CRC_DR register *********************/
Kojto 112:6f327212ef96 2940 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 112:6f327212ef96 2941
Kojto 112:6f327212ef96 2942
Kojto 112:6f327212ef96 2943 /******************* Bit definition for CRC_IDR register ********************/
Kojto 112:6f327212ef96 2944 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 112:6f327212ef96 2945
Kojto 112:6f327212ef96 2946
Kojto 112:6f327212ef96 2947 /******************** Bit definition for CRC_CR register ********************/
Kojto 112:6f327212ef96 2948 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
Kojto 112:6f327212ef96 2949
Kojto 112:6f327212ef96 2950 /******************************************************************************/
Kojto 112:6f327212ef96 2951 /* */
Kojto 112:6f327212ef96 2952 /* Digital to Analog Converter */
Kojto 112:6f327212ef96 2953 /* */
Kojto 112:6f327212ef96 2954 /******************************************************************************/
Kojto 112:6f327212ef96 2955 /******************** Bit definition for DAC_CR register ********************/
Kojto 112:6f327212ef96 2956 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
Kojto 112:6f327212ef96 2957 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
Kojto 112:6f327212ef96 2958 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
Kojto 112:6f327212ef96 2959
Kojto 112:6f327212ef96 2960 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 112:6f327212ef96 2961 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 112:6f327212ef96 2962 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 112:6f327212ef96 2963 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 112:6f327212ef96 2964
Kojto 112:6f327212ef96 2965 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 112:6f327212ef96 2966 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 112:6f327212ef96 2967 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 112:6f327212ef96 2968
Kojto 112:6f327212ef96 2969 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 112:6f327212ef96 2970 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 2971 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 2972 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 2973 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 2974
Kojto 112:6f327212ef96 2975 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
Kojto 112:6f327212ef96 2976 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
Kojto 112:6f327212ef96 2977 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
Kojto 112:6f327212ef96 2978 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
Kojto 112:6f327212ef96 2979
Kojto 112:6f327212ef96 2980 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 112:6f327212ef96 2981 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
Kojto 112:6f327212ef96 2982 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
Kojto 112:6f327212ef96 2983 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
Kojto 112:6f327212ef96 2984
Kojto 112:6f327212ef96 2985 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 112:6f327212ef96 2986 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 112:6f327212ef96 2987 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 112:6f327212ef96 2988
Kojto 112:6f327212ef96 2989 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 112:6f327212ef96 2990 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 2991 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 2992 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 2993 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 2994
Kojto 112:6f327212ef96 2995 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
Kojto 112:6f327212ef96 2996
Kojto 112:6f327212ef96 2997 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 112:6f327212ef96 2998 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
Kojto 112:6f327212ef96 2999 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
Kojto 112:6f327212ef96 3000
Kojto 112:6f327212ef96 3001 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 112:6f327212ef96 3002 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
Kojto 112:6f327212ef96 3003
Kojto 112:6f327212ef96 3004 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 112:6f327212ef96 3005 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
Kojto 112:6f327212ef96 3006
Kojto 112:6f327212ef96 3007 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 112:6f327212ef96 3008 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
Kojto 112:6f327212ef96 3009
Kojto 112:6f327212ef96 3010 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 112:6f327212ef96 3011 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
Kojto 112:6f327212ef96 3012
Kojto 112:6f327212ef96 3013 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 112:6f327212ef96 3014 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
Kojto 112:6f327212ef96 3015
Kojto 112:6f327212ef96 3016 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 112:6f327212ef96 3017 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
Kojto 112:6f327212ef96 3018
Kojto 112:6f327212ef96 3019 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 112:6f327212ef96 3020 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
Kojto 112:6f327212ef96 3021 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
Kojto 112:6f327212ef96 3022
Kojto 112:6f327212ef96 3023 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 112:6f327212ef96 3024 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
Kojto 112:6f327212ef96 3025 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
Kojto 112:6f327212ef96 3026
Kojto 112:6f327212ef96 3027 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 112:6f327212ef96 3028 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
Kojto 112:6f327212ef96 3029 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
Kojto 112:6f327212ef96 3030
Kojto 112:6f327212ef96 3031 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 112:6f327212ef96 3032 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
Kojto 112:6f327212ef96 3033
Kojto 112:6f327212ef96 3034 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 112:6f327212ef96 3035 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
Kojto 112:6f327212ef96 3036
Kojto 112:6f327212ef96 3037 /******************** Bit definition for DAC_SR register ********************/
Kojto 112:6f327212ef96 3038 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
Kojto 112:6f327212ef96 3039 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
Kojto 112:6f327212ef96 3040
Kojto 112:6f327212ef96 3041 /******************************************************************************/
Kojto 112:6f327212ef96 3042 /* */
Kojto 112:6f327212ef96 3043 /* Debug MCU */
Kojto 112:6f327212ef96 3044 /* */
Kojto 112:6f327212ef96 3045 /******************************************************************************/
Kojto 112:6f327212ef96 3046
Kojto 112:6f327212ef96 3047 /******************************************************************************/
Kojto 112:6f327212ef96 3048 /* */
Kojto 112:6f327212ef96 3049 /* DCMI */
Kojto 112:6f327212ef96 3050 /* */
Kojto 112:6f327212ef96 3051 /******************************************************************************/
Kojto 112:6f327212ef96 3052 /******************** Bits definition for DCMI_CR register ******************/
Kojto 112:6f327212ef96 3053 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3054 #define DCMI_CR_CM ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3055 #define DCMI_CR_CROP ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3056 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3057 #define DCMI_CR_ESS ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3058 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3059 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3060 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 3061 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3062 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3063 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 3064 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 3065 #define DCMI_CR_OUTEN ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 3066 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 3067 #define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3068 #define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 3069 #define DCMI_CR_OEBS ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 3070 #define DCMI_CR_LSM ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 3071 #define DCMI_CR_OELS ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 3072
Kojto 112:6f327212ef96 3073 /******************** Bits definition for DCMI_SR register ******************/
Kojto 112:6f327212ef96 3074 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3075 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3076 #define DCMI_SR_FNE ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3077
Kojto 112:6f327212ef96 3078 /******************** Bits definition for DCMI_RISR register ****************/
Kojto 112:6f327212ef96 3079 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3080 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3081 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3082 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3083 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3084
Kojto 112:6f327212ef96 3085 /******************** Bits definition for DCMI_IER register *****************/
Kojto 112:6f327212ef96 3086 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3087 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3088 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3089 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3090 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3091
Kojto 112:6f327212ef96 3092 /******************** Bits definition for DCMI_MISR register ****************/
Kojto 112:6f327212ef96 3093 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3094 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3095 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3096 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3097 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3098
Kojto 112:6f327212ef96 3099 /******************** Bits definition for DCMI_ICR register *****************/
Kojto 112:6f327212ef96 3100 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3101 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3102 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3103 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3104 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3105
Kojto 112:6f327212ef96 3106 /******************************************************************************/
Kojto 112:6f327212ef96 3107 /* */
Kojto 112:6f327212ef96 3108 /* DMA Controller */
Kojto 112:6f327212ef96 3109 /* */
Kojto 112:6f327212ef96 3110 /******************************************************************************/
Kojto 112:6f327212ef96 3111 /******************** Bits definition for DMA_SxCR register *****************/
Kojto 112:6f327212ef96 3112 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
Kojto 112:6f327212ef96 3113 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 3114 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 3115 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 3116 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
Kojto 112:6f327212ef96 3117 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 3118 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 3119 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
Kojto 112:6f327212ef96 3120 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 3121 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 3122 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 3123 #define DMA_SxCR_CT ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 3124 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 3125 #define DMA_SxCR_PL ((uint32_t)0x00030000)
Kojto 112:6f327212ef96 3126 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3127 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 3128 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 3129 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
Kojto 112:6f327212ef96 3130 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 3131 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 3132 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
Kojto 112:6f327212ef96 3133 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 3134 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 3135 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 3136 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3137 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3138 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
Kojto 112:6f327212ef96 3139 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3140 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 3141 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3142 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3143 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3144 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3145 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3146 #define DMA_SxCR_EN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3147
Kojto 112:6f327212ef96 3148 /******************** Bits definition for DMA_SxCNDTR register **************/
Kojto 112:6f327212ef96 3149 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
Kojto 112:6f327212ef96 3150 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3151 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3152 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3153 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3154 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3155 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3156 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3157 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 3158 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3159 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3160 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 3161 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 3162 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 3163 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 3164 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 3165 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 3166
Kojto 112:6f327212ef96 3167 /******************** Bits definition for DMA_SxFCR register ****************/
Kojto 112:6f327212ef96 3168 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 3169 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
Kojto 112:6f327212ef96 3170 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3171 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3172 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3173 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3174 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
Kojto 112:6f327212ef96 3175 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3176 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3177
Kojto 112:6f327212ef96 3178 /******************** Bits definition for DMA_LISR register *****************/
Kojto 112:6f327212ef96 3179 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 3180 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 3181 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 3182 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 3183 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 3184 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 3185 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 3186 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 3187 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 3188 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3189 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 3190 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 3191 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3192 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3193 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3194 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3195 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3196 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3197 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3198 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3199
Kojto 112:6f327212ef96 3200 /******************** Bits definition for DMA_HISR register *****************/
Kojto 112:6f327212ef96 3201 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 3202 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 3203 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 3204 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 3205 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 3206 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 3207 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 3208 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 3209 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 3210 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3211 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 3212 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 3213 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3214 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3215 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3216 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3217 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3218 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3219 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3220 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3221
Kojto 112:6f327212ef96 3222 /******************** Bits definition for DMA_LIFCR register ****************/
Kojto 112:6f327212ef96 3223 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 3224 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 3225 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 3226 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 3227 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 3228 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 3229 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 3230 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 3231 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 3232 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3233 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 3234 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 3235 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3236 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3237 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3238 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3239 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3240 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3241 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3242 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3243
Kojto 112:6f327212ef96 3244 /******************** Bits definition for DMA_HIFCR register ****************/
Kojto 112:6f327212ef96 3245 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 3246 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 3247 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 3248 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 3249 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 3250 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 3251 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 3252 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 3253 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 3254 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3255 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 3256 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 3257 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3258 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3259 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3260 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3261 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3262 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3263 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3264 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3265
Kojto 112:6f327212ef96 3266
Kojto 112:6f327212ef96 3267 /******************************************************************************/
Kojto 112:6f327212ef96 3268 /* */
Kojto 112:6f327212ef96 3269 /* External Interrupt/Event Controller */
Kojto 112:6f327212ef96 3270 /* */
Kojto 112:6f327212ef96 3271 /******************************************************************************/
Kojto 112:6f327212ef96 3272 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 112:6f327212ef96 3273 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 112:6f327212ef96 3274 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 112:6f327212ef96 3275 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 112:6f327212ef96 3276 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 112:6f327212ef96 3277 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 112:6f327212ef96 3278 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 112:6f327212ef96 3279 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 112:6f327212ef96 3280 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 112:6f327212ef96 3281 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 112:6f327212ef96 3282 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 112:6f327212ef96 3283 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 112:6f327212ef96 3284 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 112:6f327212ef96 3285 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 112:6f327212ef96 3286 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 112:6f327212ef96 3287 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 112:6f327212ef96 3288 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 112:6f327212ef96 3289 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 112:6f327212ef96 3290 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 112:6f327212ef96 3291 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
Kojto 112:6f327212ef96 3292 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 112:6f327212ef96 3293 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
Kojto 112:6f327212ef96 3294 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Kojto 112:6f327212ef96 3295 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Kojto 112:6f327212ef96 3296
Kojto 112:6f327212ef96 3297 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 112:6f327212ef96 3298 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 112:6f327212ef96 3299 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 112:6f327212ef96 3300 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 112:6f327212ef96 3301 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 112:6f327212ef96 3302 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 112:6f327212ef96 3303 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 112:6f327212ef96 3304 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 112:6f327212ef96 3305 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 112:6f327212ef96 3306 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 112:6f327212ef96 3307 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 112:6f327212ef96 3308 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 112:6f327212ef96 3309 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 112:6f327212ef96 3310 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 112:6f327212ef96 3311 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 112:6f327212ef96 3312 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 112:6f327212ef96 3313 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 112:6f327212ef96 3314 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 112:6f327212ef96 3315 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 112:6f327212ef96 3316 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
Kojto 112:6f327212ef96 3317 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 112:6f327212ef96 3318 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
Kojto 112:6f327212ef96 3319 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Kojto 112:6f327212ef96 3320 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Kojto 112:6f327212ef96 3321
Kojto 112:6f327212ef96 3322 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 112:6f327212ef96 3323 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 112:6f327212ef96 3324 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 112:6f327212ef96 3325 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 112:6f327212ef96 3326 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 112:6f327212ef96 3327 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 112:6f327212ef96 3328 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 112:6f327212ef96 3329 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 112:6f327212ef96 3330 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 112:6f327212ef96 3331 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 112:6f327212ef96 3332 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 112:6f327212ef96 3333 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 112:6f327212ef96 3334 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 112:6f327212ef96 3335 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 112:6f327212ef96 3336 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 112:6f327212ef96 3337 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 112:6f327212ef96 3338 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 112:6f327212ef96 3339 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 112:6f327212ef96 3340 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 112:6f327212ef96 3341 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
Kojto 112:6f327212ef96 3342 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 112:6f327212ef96 3343 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
Kojto 112:6f327212ef96 3344 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
Kojto 112:6f327212ef96 3345 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
Kojto 112:6f327212ef96 3346
Kojto 112:6f327212ef96 3347 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 112:6f327212ef96 3348 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 112:6f327212ef96 3349 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 112:6f327212ef96 3350 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 112:6f327212ef96 3351 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 112:6f327212ef96 3352 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 112:6f327212ef96 3353 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 112:6f327212ef96 3354 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 112:6f327212ef96 3355 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 112:6f327212ef96 3356 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 112:6f327212ef96 3357 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 112:6f327212ef96 3358 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 112:6f327212ef96 3359 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 112:6f327212ef96 3360 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 112:6f327212ef96 3361 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 112:6f327212ef96 3362 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 112:6f327212ef96 3363 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 112:6f327212ef96 3364 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 112:6f327212ef96 3365 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 112:6f327212ef96 3366 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
Kojto 112:6f327212ef96 3367 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 112:6f327212ef96 3368 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
Kojto 112:6f327212ef96 3369 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
Kojto 112:6f327212ef96 3370 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
Kojto 112:6f327212ef96 3371
Kojto 112:6f327212ef96 3372 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 112:6f327212ef96 3373 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 112:6f327212ef96 3374 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 112:6f327212ef96 3375 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 112:6f327212ef96 3376 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 112:6f327212ef96 3377 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 112:6f327212ef96 3378 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 112:6f327212ef96 3379 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 112:6f327212ef96 3380 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 112:6f327212ef96 3381 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 112:6f327212ef96 3382 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 112:6f327212ef96 3383 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 112:6f327212ef96 3384 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 112:6f327212ef96 3385 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 112:6f327212ef96 3386 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 112:6f327212ef96 3387 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 112:6f327212ef96 3388 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 112:6f327212ef96 3389 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 112:6f327212ef96 3390 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 112:6f327212ef96 3391 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
Kojto 112:6f327212ef96 3392 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 112:6f327212ef96 3393 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
Kojto 112:6f327212ef96 3394 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
Kojto 112:6f327212ef96 3395 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
Kojto 112:6f327212ef96 3396
Kojto 112:6f327212ef96 3397 /******************* Bit definition for EXTI_PR register ********************/
Kojto 112:6f327212ef96 3398 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
Kojto 112:6f327212ef96 3399 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
Kojto 112:6f327212ef96 3400 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
Kojto 112:6f327212ef96 3401 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
Kojto 112:6f327212ef96 3402 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
Kojto 112:6f327212ef96 3403 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
Kojto 112:6f327212ef96 3404 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
Kojto 112:6f327212ef96 3405 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
Kojto 112:6f327212ef96 3406 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
Kojto 112:6f327212ef96 3407 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
Kojto 112:6f327212ef96 3408 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
Kojto 112:6f327212ef96 3409 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
Kojto 112:6f327212ef96 3410 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
Kojto 112:6f327212ef96 3411 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
Kojto 112:6f327212ef96 3412 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
Kojto 112:6f327212ef96 3413 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
Kojto 112:6f327212ef96 3414 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
Kojto 112:6f327212ef96 3415 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
Kojto 112:6f327212ef96 3416 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
Kojto 112:6f327212ef96 3417 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
Kojto 112:6f327212ef96 3418 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
Kojto 112:6f327212ef96 3419 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
Kojto 112:6f327212ef96 3420 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
Kojto 112:6f327212ef96 3421
Kojto 112:6f327212ef96 3422 /******************************************************************************/
Kojto 112:6f327212ef96 3423 /* */
Kojto 112:6f327212ef96 3424 /* FLASH */
Kojto 112:6f327212ef96 3425 /* */
Kojto 112:6f327212ef96 3426 /******************************************************************************/
Kojto 112:6f327212ef96 3427 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 112:6f327212ef96 3428 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
Kojto 112:6f327212ef96 3429 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
Kojto 112:6f327212ef96 3430 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3431 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3432 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
Kojto 112:6f327212ef96 3433 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3434 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
Kojto 112:6f327212ef96 3435 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
Kojto 112:6f327212ef96 3436 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
Kojto 112:6f327212ef96 3437 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3438 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
Kojto 112:6f327212ef96 3439 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
Kojto 112:6f327212ef96 3440 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
Kojto 112:6f327212ef96 3441 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
Kojto 112:6f327212ef96 3442 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
Kojto 112:6f327212ef96 3443 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
Kojto 112:6f327212ef96 3444 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
Kojto 112:6f327212ef96 3445 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3446 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3447 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 3448 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 3449 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 3450 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
Kojto 112:6f327212ef96 3451 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
Kojto 112:6f327212ef96 3452
Kojto 112:6f327212ef96 3453 /******************* Bits definition for FLASH_SR register ******************/
Kojto 112:6f327212ef96 3454 #define FLASH_SR_EOP ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3455 #define FLASH_SR_SOP ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3456 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3457 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3458 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3459 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 3460 #define FLASH_SR_BSY ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3461
Kojto 112:6f327212ef96 3462 /******************* Bits definition for FLASH_CR register ******************/
Kojto 112:6f327212ef96 3463 #define FLASH_CR_PG ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3464 #define FLASH_CR_SER ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3465 #define FLASH_CR_MER ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3466 #define FLASH_CR_MER1 FLASH_CR_MER
Kojto 112:6f327212ef96 3467 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
Kojto 112:6f327212ef96 3468 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3469 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3470 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3471 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3472 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 3473 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
Kojto 112:6f327212ef96 3474 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3475 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3476 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 3477 #define FLASH_CR_STRT ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3478 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 3479 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 3480
Kojto 112:6f327212ef96 3481 /******************* Bits definition for FLASH_OPTCR register ***************/
Kojto 112:6f327212ef96 3482 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 3483 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 3484 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 3485 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 3486 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
Kojto 112:6f327212ef96 3487 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 3488 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 3489 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 3490 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 3491 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
Kojto 112:6f327212ef96 3492 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 3493 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 3494 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 3495 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 3496 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 3497 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 3498 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 3499 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 3500 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
Kojto 112:6f327212ef96 3501 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3502 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 3503 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 3504 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 3505 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 3506 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 3507 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 3508 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 3509 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 3510 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 3511 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 3512 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 3513 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 3514 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 3515
Kojto 112:6f327212ef96 3516 /****************** Bits definition for FLASH_OPTCR1 register ***************/
Kojto 112:6f327212ef96 3517 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
Kojto 112:6f327212ef96 3518 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 3519 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 3520 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 3521 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 3522 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 3523 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 3524 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 3525 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 3526 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 3527 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 3528 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 3529 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 3530
Kojto 112:6f327212ef96 3531 /******************************************************************************/
Kojto 112:6f327212ef96 3532 /* */
Kojto 112:6f327212ef96 3533 /* Flexible Memory Controller */
Kojto 112:6f327212ef96 3534 /* */
Kojto 112:6f327212ef96 3535 /******************************************************************************/
Kojto 112:6f327212ef96 3536 /****************** Bit definition for FMC_BCR1 register *******************/
Kojto 112:6f327212ef96 3537 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 112:6f327212ef96 3538 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 112:6f327212ef96 3539
Kojto 112:6f327212ef96 3540 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 112:6f327212ef96 3541 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 112:6f327212ef96 3542 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 112:6f327212ef96 3543
Kojto 112:6f327212ef96 3544 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 112:6f327212ef96 3545 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3546 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3547
Kojto 112:6f327212ef96 3548 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 112:6f327212ef96 3549 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 112:6f327212ef96 3550 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 112:6f327212ef96 3551 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 112:6f327212ef96 3552 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 112:6f327212ef96 3553 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 112:6f327212ef96 3554 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 112:6f327212ef96 3555 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 112:6f327212ef96 3556 #define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
Kojto 112:6f327212ef96 3557 #define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3558 #define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3559 #define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3560 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 112:6f327212ef96 3561 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
Kojto 112:6f327212ef96 3562 #define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
Kojto 112:6f327212ef96 3563
Kojto 112:6f327212ef96 3564 /****************** Bit definition for FMC_BCR2 register *******************/
Kojto 112:6f327212ef96 3565 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 112:6f327212ef96 3566 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 112:6f327212ef96 3567
Kojto 112:6f327212ef96 3568 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 112:6f327212ef96 3569 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 112:6f327212ef96 3570 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 112:6f327212ef96 3571
Kojto 112:6f327212ef96 3572 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 112:6f327212ef96 3573 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3574 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3575
Kojto 112:6f327212ef96 3576 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 112:6f327212ef96 3577 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 112:6f327212ef96 3578 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 112:6f327212ef96 3579 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 112:6f327212ef96 3580 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 112:6f327212ef96 3581 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 112:6f327212ef96 3582 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 112:6f327212ef96 3583 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 112:6f327212ef96 3584 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 112:6f327212ef96 3585
Kojto 112:6f327212ef96 3586 /****************** Bit definition for FMC_BCR3 register *******************/
Kojto 112:6f327212ef96 3587 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 112:6f327212ef96 3588 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 112:6f327212ef96 3589
Kojto 112:6f327212ef96 3590 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 112:6f327212ef96 3591 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 112:6f327212ef96 3592 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 112:6f327212ef96 3593
Kojto 112:6f327212ef96 3594 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 112:6f327212ef96 3595 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3596 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3597
Kojto 112:6f327212ef96 3598 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 112:6f327212ef96 3599 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 112:6f327212ef96 3600 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 112:6f327212ef96 3601 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 112:6f327212ef96 3602 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 112:6f327212ef96 3603 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 112:6f327212ef96 3604 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 112:6f327212ef96 3605 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 112:6f327212ef96 3606 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 112:6f327212ef96 3607
Kojto 112:6f327212ef96 3608 /****************** Bit definition for FMC_BCR4 register *******************/
Kojto 112:6f327212ef96 3609 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 112:6f327212ef96 3610 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 112:6f327212ef96 3611
Kojto 112:6f327212ef96 3612 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 112:6f327212ef96 3613 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 112:6f327212ef96 3614 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 112:6f327212ef96 3615
Kojto 112:6f327212ef96 3616 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 112:6f327212ef96 3617 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3618 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3619
Kojto 112:6f327212ef96 3620 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 112:6f327212ef96 3621 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 112:6f327212ef96 3622 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 112:6f327212ef96 3623 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 112:6f327212ef96 3624 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 112:6f327212ef96 3625 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 112:6f327212ef96 3626 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 112:6f327212ef96 3627 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 112:6f327212ef96 3628 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 112:6f327212ef96 3629
Kojto 112:6f327212ef96 3630 /****************** Bit definition for FMC_BTR1 register ******************/
Kojto 112:6f327212ef96 3631 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 112:6f327212ef96 3632 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 3633 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 3634 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 3635 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 3636
Kojto 112:6f327212ef96 3637 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 112:6f327212ef96 3638 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3639 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3640 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 3641 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 3642
Kojto 112:6f327212ef96 3643 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 112:6f327212ef96 3644 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 3645 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 3646 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 3647 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 3648 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 3649 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 3650 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 3651 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 3652
Kojto 112:6f327212ef96 3653 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 112:6f327212ef96 3654 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3655 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3656 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3657 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3658
Kojto 112:6f327212ef96 3659 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 112:6f327212ef96 3660 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3661 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3662 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3663 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3664
Kojto 112:6f327212ef96 3665 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 112:6f327212ef96 3666 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3667 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3668 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3669 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3670
Kojto 112:6f327212ef96 3671 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 112:6f327212ef96 3672 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3673 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3674
Kojto 112:6f327212ef96 3675 /****************** Bit definition for FMC_BTR2 register *******************/
Kojto 112:6f327212ef96 3676 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 112:6f327212ef96 3677 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 3678 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 3679 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 3680 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 3681
Kojto 112:6f327212ef96 3682 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 112:6f327212ef96 3683 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3684 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3685 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 3686 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 3687
Kojto 112:6f327212ef96 3688 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 112:6f327212ef96 3689 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 3690 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 3691 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 3692 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 3693 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 3694 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 3695 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 3696 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 3697
Kojto 112:6f327212ef96 3698 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 112:6f327212ef96 3699 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3700 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3701 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3702 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3703
Kojto 112:6f327212ef96 3704 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 112:6f327212ef96 3705 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3706 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3707 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3708 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3709
Kojto 112:6f327212ef96 3710 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 112:6f327212ef96 3711 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3712 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3713 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3714 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3715
Kojto 112:6f327212ef96 3716 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 112:6f327212ef96 3717 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3718 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3719
Kojto 112:6f327212ef96 3720 /******************* Bit definition for FMC_BTR3 register *******************/
Kojto 112:6f327212ef96 3721 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 112:6f327212ef96 3722 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 3723 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 3724 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 3725 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 3726
Kojto 112:6f327212ef96 3727 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 112:6f327212ef96 3728 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3729 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3730 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 3731 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 3732
Kojto 112:6f327212ef96 3733 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 112:6f327212ef96 3734 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 3735 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 3736 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 3737 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 3738 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 3739 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 3740 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 3741 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 3742
Kojto 112:6f327212ef96 3743 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 112:6f327212ef96 3744 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3745 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3746 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3747 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3748
Kojto 112:6f327212ef96 3749 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 112:6f327212ef96 3750 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3751 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3752 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3753 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3754
Kojto 112:6f327212ef96 3755 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 112:6f327212ef96 3756 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3757 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3758 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3759 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3760
Kojto 112:6f327212ef96 3761 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 112:6f327212ef96 3762 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3763 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3764
Kojto 112:6f327212ef96 3765 /****************** Bit definition for FMC_BTR4 register *******************/
Kojto 112:6f327212ef96 3766 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 112:6f327212ef96 3767 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 3768 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 3769 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 3770 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 3771
Kojto 112:6f327212ef96 3772 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 112:6f327212ef96 3773 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3774 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3775 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 3776 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 3777
Kojto 112:6f327212ef96 3778 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 112:6f327212ef96 3779 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 3780 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 3781 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 3782 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 3783 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 3784 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 3785 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 3786 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 3787
Kojto 112:6f327212ef96 3788 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 112:6f327212ef96 3789 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3790 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3791 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3792 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3793
Kojto 112:6f327212ef96 3794 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 112:6f327212ef96 3795 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3796 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3797 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3798 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3799
Kojto 112:6f327212ef96 3800 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 112:6f327212ef96 3801 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3802 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3803 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3804 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3805
Kojto 112:6f327212ef96 3806 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 112:6f327212ef96 3807 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3808 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3809
Kojto 112:6f327212ef96 3810 /****************** Bit definition for FMC_BWTR1 register ******************/
Kojto 112:6f327212ef96 3811 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 112:6f327212ef96 3812 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 3813 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 3814 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 3815 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 3816
Kojto 112:6f327212ef96 3817 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 112:6f327212ef96 3818 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3819 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3820 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 3821 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 3822
Kojto 112:6f327212ef96 3823 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 112:6f327212ef96 3824 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 3825 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 3826 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 3827 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 3828 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 3829 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 3830 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 3831 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 3832
Kojto 112:6f327212ef96 3833 #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 112:6f327212ef96 3834 #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3835 #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3836 #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3837 #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3838
Kojto 112:6f327212ef96 3839 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 112:6f327212ef96 3840 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3841 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3842
Kojto 112:6f327212ef96 3843 /****************** Bit definition for FMC_BWTR2 register ******************/
Kojto 112:6f327212ef96 3844 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 112:6f327212ef96 3845 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 3846 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 3847 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 3848 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 3849
Kojto 112:6f327212ef96 3850 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 112:6f327212ef96 3851 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3852 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3853 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 3854 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 3855
Kojto 112:6f327212ef96 3856 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 112:6f327212ef96 3857 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 3858 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 3859 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 3860 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 3861 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 3862 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 3863 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 3864 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 3865
Kojto 112:6f327212ef96 3866 #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 112:6f327212ef96 3867 #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3868 #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3869 #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3870 #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3871
Kojto 112:6f327212ef96 3872 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 112:6f327212ef96 3873 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3874 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3875
Kojto 112:6f327212ef96 3876 /****************** Bit definition for FMC_BWTR3 register ******************/
Kojto 112:6f327212ef96 3877 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 112:6f327212ef96 3878 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 3879 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 3880 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 3881 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 3882
Kojto 112:6f327212ef96 3883 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 112:6f327212ef96 3884 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3885 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3886 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 3887 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 3888
Kojto 112:6f327212ef96 3889 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 112:6f327212ef96 3890 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 3891 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 3892 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 3893 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 3894 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 3895 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 3896 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 3897 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 3898
Kojto 112:6f327212ef96 3899 #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 112:6f327212ef96 3900 #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3901 #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3902 #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3903 #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3904
Kojto 112:6f327212ef96 3905 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 112:6f327212ef96 3906 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3907 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3908
Kojto 112:6f327212ef96 3909 /****************** Bit definition for FMC_BWTR4 register ******************/
Kojto 112:6f327212ef96 3910 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 112:6f327212ef96 3911 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 3912 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 3913 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 3914 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 3915
Kojto 112:6f327212ef96 3916 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 112:6f327212ef96 3917 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3918 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3919 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 3920 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 3921
Kojto 112:6f327212ef96 3922 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 112:6f327212ef96 3923 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 3924 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 3925 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 3926 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 3927 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 3928 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 3929 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 3930 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 3931
Kojto 112:6f327212ef96 3932 #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
Kojto 112:6f327212ef96 3933 #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3934 #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3935 #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3936 #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3937
Kojto 112:6f327212ef96 3938 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 112:6f327212ef96 3939 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3940 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3941
Kojto 112:6f327212ef96 3942 /****************** Bit definition for FMC_PCR register *******************/
Kojto 112:6f327212ef96 3943 #define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
Kojto 112:6f327212ef96 3944 #define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
Kojto 112:6f327212ef96 3945 #define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
Kojto 112:6f327212ef96 3946
Kojto 112:6f327212ef96 3947 #define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
Kojto 112:6f327212ef96 3948 #define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 3949 #define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 3950
Kojto 112:6f327212ef96 3951 #define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
Kojto 112:6f327212ef96 3952
Kojto 112:6f327212ef96 3953 #define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
Kojto 112:6f327212ef96 3954 #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 112:6f327212ef96 3955 #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 112:6f327212ef96 3956 #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 112:6f327212ef96 3957 #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3958
Kojto 112:6f327212ef96 3959 #define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
Kojto 112:6f327212ef96 3960 #define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3961 #define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3962 #define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3963 #define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 112:6f327212ef96 3964
Kojto 112:6f327212ef96 3965 #define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
Kojto 112:6f327212ef96 3966 #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 112:6f327212ef96 3967 #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 112:6f327212ef96 3968 #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 112:6f327212ef96 3969
Kojto 112:6f327212ef96 3970 /******************* Bit definition for FMC_SR register *******************/
Kojto 112:6f327212ef96 3971 #define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
Kojto 112:6f327212ef96 3972 #define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
Kojto 112:6f327212ef96 3973 #define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
Kojto 112:6f327212ef96 3974 #define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
Kojto 112:6f327212ef96 3975 #define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
Kojto 112:6f327212ef96 3976 #define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
Kojto 112:6f327212ef96 3977 #define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
Kojto 112:6f327212ef96 3978
Kojto 112:6f327212ef96 3979 /****************** Bit definition for FMC_PMEM register ******************/
Kojto 112:6f327212ef96 3980 #define FMC_PMEM_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
Kojto 112:6f327212ef96 3981 #define FMC_PMEM_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 3982 #define FMC_PMEM_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 3983 #define FMC_PMEM_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 3984 #define FMC_PMEM_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 3985 #define FMC_PMEM_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 3986 #define FMC_PMEM_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 112:6f327212ef96 3987 #define FMC_PMEM_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 112:6f327212ef96 3988 #define FMC_PMEM_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 112:6f327212ef96 3989
Kojto 112:6f327212ef96 3990 #define FMC_PMEM_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
Kojto 112:6f327212ef96 3991 #define FMC_PMEM_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 3992 #define FMC_PMEM_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 3993 #define FMC_PMEM_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 3994 #define FMC_PMEM_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 3995 #define FMC_PMEM_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 3996 #define FMC_PMEM_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 3997 #define FMC_PMEM_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 3998 #define FMC_PMEM_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 3999
Kojto 112:6f327212ef96 4000 #define FMC_PMEM_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
Kojto 112:6f327212ef96 4001 #define FMC_PMEM_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4002 #define FMC_PMEM_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4003 #define FMC_PMEM_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4004 #define FMC_PMEM_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 4005 #define FMC_PMEM_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 112:6f327212ef96 4006 #define FMC_PMEM_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 112:6f327212ef96 4007 #define FMC_PMEM_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 112:6f327212ef96 4008 #define FMC_PMEM_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 112:6f327212ef96 4009
Kojto 112:6f327212ef96 4010 #define FMC_PMEM_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
Kojto 112:6f327212ef96 4011 #define FMC_PMEM_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4012 #define FMC_PMEM_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4013 #define FMC_PMEM_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4014 #define FMC_PMEM_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 4015 #define FMC_PMEM_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 112:6f327212ef96 4016 #define FMC_PMEM_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 112:6f327212ef96 4017 #define FMC_PMEM_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 112:6f327212ef96 4018 #define FMC_PMEM_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 112:6f327212ef96 4019
Kojto 112:6f327212ef96 4020 /****************** Bit definition for FMC_PATT register ******************/
Kojto 112:6f327212ef96 4021 #define FMC_PATT_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
Kojto 112:6f327212ef96 4022 #define FMC_PATT_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 4023 #define FMC_PATT_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 4024 #define FMC_PATT_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 4025 #define FMC_PATT_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 4026 #define FMC_PATT_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 4027 #define FMC_PATT_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 112:6f327212ef96 4028 #define FMC_PATT_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 112:6f327212ef96 4029 #define FMC_PATT_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 112:6f327212ef96 4030
Kojto 112:6f327212ef96 4031 #define FMC_PATT_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
Kojto 112:6f327212ef96 4032 #define FMC_PATT_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 4033 #define FMC_PATT_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 4034 #define FMC_PATT_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 4035 #define FMC_PATT_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 4036 #define FMC_PATT_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 4037 #define FMC_PATT_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 4038 #define FMC_PATT_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 4039 #define FMC_PATT_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 112:6f327212ef96 4040
Kojto 112:6f327212ef96 4041 #define FMC_PATT_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
Kojto 112:6f327212ef96 4042 #define FMC_PATT_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4043 #define FMC_PATT_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4044 #define FMC_PATT_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4045 #define FMC_PATT_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 4046 #define FMC_PATT_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 112:6f327212ef96 4047 #define FMC_PATT_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 112:6f327212ef96 4048 #define FMC_PATT_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 112:6f327212ef96 4049 #define FMC_PATT_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 112:6f327212ef96 4050
Kojto 112:6f327212ef96 4051 #define FMC_PATT_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
Kojto 112:6f327212ef96 4052 #define FMC_PATT_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4053 #define FMC_PATT_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4054 #define FMC_PATT_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4055 #define FMC_PATT_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 4056 #define FMC_PATT_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 112:6f327212ef96 4057 #define FMC_PATT_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 112:6f327212ef96 4058 #define FMC_PATT_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 112:6f327212ef96 4059 #define FMC_PATT_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 112:6f327212ef96 4060
Kojto 112:6f327212ef96 4061 /****************** Bit definition for FMC_ECCR register ******************/
Kojto 112:6f327212ef96 4062 #define FMC_ECCR_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
Kojto 112:6f327212ef96 4063
Kojto 112:6f327212ef96 4064 /****************** Bit definition for FMC_SDCR1 register ******************/
Kojto 112:6f327212ef96 4065 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
Kojto 112:6f327212ef96 4066 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 4067 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 4068
Kojto 112:6f327212ef96 4069 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
Kojto 112:6f327212ef96 4070 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 112:6f327212ef96 4071 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 112:6f327212ef96 4072
Kojto 112:6f327212ef96 4073 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
Kojto 112:6f327212ef96 4074 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 4075 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 4076
Kojto 112:6f327212ef96 4077 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
Kojto 112:6f327212ef96 4078
Kojto 112:6f327212ef96 4079 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
Kojto 112:6f327212ef96 4080 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 112:6f327212ef96 4081 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 112:6f327212ef96 4082
Kojto 112:6f327212ef96 4083 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
Kojto 112:6f327212ef96 4084
Kojto 112:6f327212ef96 4085 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
Kojto 112:6f327212ef96 4086 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 112:6f327212ef96 4087 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 112:6f327212ef96 4088
Kojto 112:6f327212ef96 4089 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
Kojto 112:6f327212ef96 4090
Kojto 112:6f327212ef96 4091 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
Kojto 112:6f327212ef96 4092 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4093 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4094
Kojto 112:6f327212ef96 4095 /****************** Bit definition for FMC_SDCR2 register ******************/
Kojto 112:6f327212ef96 4096 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
Kojto 112:6f327212ef96 4097 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 4098 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 4099
Kojto 112:6f327212ef96 4100 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
Kojto 112:6f327212ef96 4101 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 112:6f327212ef96 4102 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 112:6f327212ef96 4103
Kojto 112:6f327212ef96 4104 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
Kojto 112:6f327212ef96 4105 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 4106 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 4107
Kojto 112:6f327212ef96 4108 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
Kojto 112:6f327212ef96 4109
Kojto 112:6f327212ef96 4110 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
Kojto 112:6f327212ef96 4111 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 112:6f327212ef96 4112 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 112:6f327212ef96 4113
Kojto 112:6f327212ef96 4114 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
Kojto 112:6f327212ef96 4115
Kojto 112:6f327212ef96 4116 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
Kojto 112:6f327212ef96 4117 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 112:6f327212ef96 4118 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 112:6f327212ef96 4119
Kojto 112:6f327212ef96 4120 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
Kojto 112:6f327212ef96 4121
Kojto 112:6f327212ef96 4122 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
Kojto 112:6f327212ef96 4123 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4124 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4125
Kojto 112:6f327212ef96 4126 /****************** Bit definition for FMC_SDTR1 register ******************/
Kojto 112:6f327212ef96 4127 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 112:6f327212ef96 4128 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 4129 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 4130 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 4131 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 4132
Kojto 112:6f327212ef96 4133 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 112:6f327212ef96 4134 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 4135 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 4136 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 4137 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 4138
Kojto 112:6f327212ef96 4139 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 112:6f327212ef96 4140 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 4141 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 4142 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 4143 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 4144
Kojto 112:6f327212ef96 4145 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 112:6f327212ef96 4146 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4147 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4148 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4149
Kojto 112:6f327212ef96 4150 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 112:6f327212ef96 4151 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4152 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4153 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4154
Kojto 112:6f327212ef96 4155 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 112:6f327212ef96 4156 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4157 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4158 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4159
Kojto 112:6f327212ef96 4160 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
Kojto 112:6f327212ef96 4161 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4162 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4163 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4164
Kojto 112:6f327212ef96 4165 /****************** Bit definition for FMC_SDTR2 register ******************/
Kojto 112:6f327212ef96 4166 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 112:6f327212ef96 4167 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 4168 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 4169 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 4170 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 4171
Kojto 112:6f327212ef96 4172 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 112:6f327212ef96 4173 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 4174 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 4175 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 4176 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 4177
Kojto 112:6f327212ef96 4178 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 112:6f327212ef96 4179 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 4180 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 4181 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 4182 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 4183
Kojto 112:6f327212ef96 4184 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 112:6f327212ef96 4185 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4186 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4187 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4188
Kojto 112:6f327212ef96 4189 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 112:6f327212ef96 4190 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4191 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4192 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4193
Kojto 112:6f327212ef96 4194 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 112:6f327212ef96 4195 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4196 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4197 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4198
Kojto 112:6f327212ef96 4199 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
Kojto 112:6f327212ef96 4200 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 4201 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 4202 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 4203
Kojto 112:6f327212ef96 4204 /****************** Bit definition for FMC_SDCMR register ******************/
Kojto 112:6f327212ef96 4205 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
Kojto 112:6f327212ef96 4206 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 4207 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 4208 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 4209
Kojto 112:6f327212ef96 4210 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
Kojto 112:6f327212ef96 4211
Kojto 112:6f327212ef96 4212 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
Kojto 112:6f327212ef96 4213
Kojto 112:6f327212ef96 4214 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
Kojto 112:6f327212ef96 4215 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 112:6f327212ef96 4216 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 112:6f327212ef96 4217 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 112:6f327212ef96 4218 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 112:6f327212ef96 4219
Kojto 112:6f327212ef96 4220 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
Kojto 112:6f327212ef96 4221
Kojto 112:6f327212ef96 4222 /****************** Bit definition for FMC_SDRTR register ******************/
Kojto 112:6f327212ef96 4223 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
Kojto 112:6f327212ef96 4224
Kojto 112:6f327212ef96 4225 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
Kojto 112:6f327212ef96 4226
Kojto 112:6f327212ef96 4227 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
Kojto 112:6f327212ef96 4228
Kojto 112:6f327212ef96 4229 /****************** Bit definition for FMC_SDSR register ******************/
Kojto 112:6f327212ef96 4230 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
Kojto 112:6f327212ef96 4231
Kojto 112:6f327212ef96 4232 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
Kojto 112:6f327212ef96 4233 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 112:6f327212ef96 4234 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 112:6f327212ef96 4235
Kojto 112:6f327212ef96 4236 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
Kojto 112:6f327212ef96 4237 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 112:6f327212ef96 4238 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 112:6f327212ef96 4239 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
Kojto 112:6f327212ef96 4240
Kojto 112:6f327212ef96 4241 /******************************************************************************/
Kojto 112:6f327212ef96 4242 /* */
Kojto 112:6f327212ef96 4243 /* General Purpose I/O */
Kojto 112:6f327212ef96 4244 /* */
Kojto 112:6f327212ef96 4245 /******************************************************************************/
Kojto 112:6f327212ef96 4246 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 112:6f327212ef96 4247 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 112:6f327212ef96 4248 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 4249 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 4250
Kojto 112:6f327212ef96 4251 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 112:6f327212ef96 4252 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 4253 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 4254
Kojto 112:6f327212ef96 4255 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 112:6f327212ef96 4256 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 4257 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 4258
Kojto 112:6f327212ef96 4259 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 112:6f327212ef96 4260 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 4261 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 4262
Kojto 112:6f327212ef96 4263 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 112:6f327212ef96 4264 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 4265 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 4266
Kojto 112:6f327212ef96 4267 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 112:6f327212ef96 4268 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 4269 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 4270
Kojto 112:6f327212ef96 4271 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 112:6f327212ef96 4272 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 4273 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 4274
Kojto 112:6f327212ef96 4275 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 112:6f327212ef96 4276 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 4277 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 4278
Kojto 112:6f327212ef96 4279 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 112:6f327212ef96 4280 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 4281 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 4282
Kojto 112:6f327212ef96 4283 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 112:6f327212ef96 4284 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 4285 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 4286
Kojto 112:6f327212ef96 4287 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 112:6f327212ef96 4288 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 4289 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 4290
Kojto 112:6f327212ef96 4291 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 112:6f327212ef96 4292 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 4293 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 4294
Kojto 112:6f327212ef96 4295 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 112:6f327212ef96 4296 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 4297 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 4298
Kojto 112:6f327212ef96 4299 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 112:6f327212ef96 4300 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 4301 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 4302
Kojto 112:6f327212ef96 4303 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 112:6f327212ef96 4304 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 4305 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 4306
Kojto 112:6f327212ef96 4307 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 112:6f327212ef96 4308 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 4309 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 4310
Kojto 112:6f327212ef96 4311 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 112:6f327212ef96 4312 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 4313 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 4314 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 4315 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 4316 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 4317 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 4318 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 4319 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 4320 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 4321 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 4322 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 4323 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 4324 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 4325 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 4326 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 4327 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 4328
Kojto 112:6f327212ef96 4329 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 112:6f327212ef96 4330 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 112:6f327212ef96 4331 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 4332 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 4333
Kojto 112:6f327212ef96 4334 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 112:6f327212ef96 4335 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 4336 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 4337
Kojto 112:6f327212ef96 4338 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 112:6f327212ef96 4339 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 4340 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 4341
Kojto 112:6f327212ef96 4342 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 112:6f327212ef96 4343 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 4344 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 4345
Kojto 112:6f327212ef96 4346 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 112:6f327212ef96 4347 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 4348 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 4349
Kojto 112:6f327212ef96 4350 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 112:6f327212ef96 4351 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 4352 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 4353
Kojto 112:6f327212ef96 4354 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 112:6f327212ef96 4355 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 4356 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 4357
Kojto 112:6f327212ef96 4358 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 112:6f327212ef96 4359 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 4360 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 4361
Kojto 112:6f327212ef96 4362 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 112:6f327212ef96 4363 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 4364 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 4365
Kojto 112:6f327212ef96 4366 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 112:6f327212ef96 4367 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 4368 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 4369
Kojto 112:6f327212ef96 4370 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 112:6f327212ef96 4371 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 4372 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 4373
Kojto 112:6f327212ef96 4374 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 112:6f327212ef96 4375 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 4376 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 4377
Kojto 112:6f327212ef96 4378 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 112:6f327212ef96 4379 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 4380 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 4381
Kojto 112:6f327212ef96 4382 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 112:6f327212ef96 4383 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 4384 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 4385
Kojto 112:6f327212ef96 4386 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 112:6f327212ef96 4387 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 4388 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 4389
Kojto 112:6f327212ef96 4390 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 112:6f327212ef96 4391 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 4392 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 4393
Kojto 112:6f327212ef96 4394 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 112:6f327212ef96 4395 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 112:6f327212ef96 4396 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 4397 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 4398
Kojto 112:6f327212ef96 4399 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 112:6f327212ef96 4400 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 4401 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 4402
Kojto 112:6f327212ef96 4403 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 112:6f327212ef96 4404 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 4405 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 4406
Kojto 112:6f327212ef96 4407 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 112:6f327212ef96 4408 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 4409 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 4410
Kojto 112:6f327212ef96 4411 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 112:6f327212ef96 4412 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 4413 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 4414
Kojto 112:6f327212ef96 4415 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 112:6f327212ef96 4416 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 4417 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 4418
Kojto 112:6f327212ef96 4419 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 112:6f327212ef96 4420 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 4421 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 4422
Kojto 112:6f327212ef96 4423 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 112:6f327212ef96 4424 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 4425 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 4426
Kojto 112:6f327212ef96 4427 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 112:6f327212ef96 4428 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 4429 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 4430
Kojto 112:6f327212ef96 4431 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 112:6f327212ef96 4432 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 4433 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 4434
Kojto 112:6f327212ef96 4435 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 112:6f327212ef96 4436 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 4437 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 4438
Kojto 112:6f327212ef96 4439 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 112:6f327212ef96 4440 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 4441 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 4442
Kojto 112:6f327212ef96 4443 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 112:6f327212ef96 4444 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 4445 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 4446
Kojto 112:6f327212ef96 4447 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 112:6f327212ef96 4448 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 4449 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 4450
Kojto 112:6f327212ef96 4451 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 112:6f327212ef96 4452 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 4453 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 4454
Kojto 112:6f327212ef96 4455 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 112:6f327212ef96 4456 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 4457 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 4458
Kojto 112:6f327212ef96 4459 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 112:6f327212ef96 4460 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 4461 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 4462 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 4463 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 4464 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 4465 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 4466 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 4467 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 4468 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 4469 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 4470 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 4471 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 4472 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 4473 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 4474 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 4475 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 4476 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
Kojto 112:6f327212ef96 4477 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
Kojto 112:6f327212ef96 4478 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
Kojto 112:6f327212ef96 4479 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
Kojto 112:6f327212ef96 4480 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
Kojto 112:6f327212ef96 4481 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
Kojto 112:6f327212ef96 4482 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
Kojto 112:6f327212ef96 4483 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
Kojto 112:6f327212ef96 4484 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
Kojto 112:6f327212ef96 4485 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
Kojto 112:6f327212ef96 4486 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
Kojto 112:6f327212ef96 4487 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
Kojto 112:6f327212ef96 4488 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
Kojto 112:6f327212ef96 4489 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
Kojto 112:6f327212ef96 4490 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
Kojto 112:6f327212ef96 4491 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
Kojto 112:6f327212ef96 4492 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
Kojto 112:6f327212ef96 4493
Kojto 112:6f327212ef96 4494 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 112:6f327212ef96 4495 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 4496 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 4497 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 4498 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 4499 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 4500 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 4501 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 4502 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 4503 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 4504 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 4505 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 4506 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 4507 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 4508 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 4509 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 4510 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 4511 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
Kojto 112:6f327212ef96 4512 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
Kojto 112:6f327212ef96 4513 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
Kojto 112:6f327212ef96 4514 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
Kojto 112:6f327212ef96 4515 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
Kojto 112:6f327212ef96 4516 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
Kojto 112:6f327212ef96 4517 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
Kojto 112:6f327212ef96 4518 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
Kojto 112:6f327212ef96 4519 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
Kojto 112:6f327212ef96 4520 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
Kojto 112:6f327212ef96 4521 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
Kojto 112:6f327212ef96 4522 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
Kojto 112:6f327212ef96 4523 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
Kojto 112:6f327212ef96 4524 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
Kojto 112:6f327212ef96 4525 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
Kojto 112:6f327212ef96 4526 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
Kojto 112:6f327212ef96 4527 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
Kojto 112:6f327212ef96 4528
Kojto 112:6f327212ef96 4529 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 112:6f327212ef96 4530 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 4531 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 4532 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 4533 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 4534 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 4535 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 4536 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 4537 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 4538 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 4539 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 4540 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 4541 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 4542 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 4543 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 4544 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 4545 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 4546 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 4547 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 4548 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 4549 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 4550 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 4551 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 4552 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 4553 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 4554 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 4555 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 4556 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 4557 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 4558 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 4559 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 4560 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 4561 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 4562
Kojto 112:6f327212ef96 4563 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 112:6f327212ef96 4564 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 4565 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 4566 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 4567 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 4568 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 4569 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 4570 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 4571 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 4572 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 4573 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 4574 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 4575 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 4576 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 4577 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 4578 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 4579 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 4580 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 4581
Kojto 112:6f327212ef96 4582 /******************************************************************************/
Kojto 112:6f327212ef96 4583 /* */
Kojto 112:6f327212ef96 4584 /* Inter-integrated Circuit Interface */
Kojto 112:6f327212ef96 4585 /* */
Kojto 112:6f327212ef96 4586 /******************************************************************************/
Kojto 112:6f327212ef96 4587 /******************* Bit definition for I2C_CR1 register ********************/
Kojto 112:6f327212ef96 4588 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
Kojto 112:6f327212ef96 4589 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
Kojto 112:6f327212ef96 4590 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
Kojto 112:6f327212ef96 4591 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
Kojto 112:6f327212ef96 4592 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
Kojto 112:6f327212ef96 4593 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
Kojto 112:6f327212ef96 4594 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
Kojto 112:6f327212ef96 4595 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
Kojto 112:6f327212ef96 4596 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
Kojto 112:6f327212ef96 4597 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
Kojto 112:6f327212ef96 4598 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
Kojto 112:6f327212ef96 4599 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
Kojto 112:6f327212ef96 4600 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
Kojto 112:6f327212ef96 4601 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
Kojto 112:6f327212ef96 4602
Kojto 112:6f327212ef96 4603 /******************* Bit definition for I2C_CR2 register ********************/
Kojto 112:6f327212ef96 4604 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
Kojto 112:6f327212ef96 4605 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 4606 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 4607 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 4608 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 4609 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 4610 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 112:6f327212ef96 4611
Kojto 112:6f327212ef96 4612 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
Kojto 112:6f327212ef96 4613 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
Kojto 112:6f327212ef96 4614 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
Kojto 112:6f327212ef96 4615 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
Kojto 112:6f327212ef96 4616 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
Kojto 112:6f327212ef96 4617
Kojto 112:6f327212ef96 4618 /******************* Bit definition for I2C_OAR1 register *******************/
Kojto 112:6f327212ef96 4619 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
Kojto 112:6f327212ef96 4620 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
Kojto 112:6f327212ef96 4621
Kojto 112:6f327212ef96 4622 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 4623 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 4624 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 4625 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 4626 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 4627 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 112:6f327212ef96 4628 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 112:6f327212ef96 4629 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 112:6f327212ef96 4630 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
Kojto 112:6f327212ef96 4631 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
Kojto 112:6f327212ef96 4632
Kojto 112:6f327212ef96 4633 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
Kojto 112:6f327212ef96 4634
Kojto 112:6f327212ef96 4635 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 112:6f327212ef96 4636 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
Kojto 112:6f327212ef96 4637 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
Kojto 112:6f327212ef96 4638
Kojto 112:6f327212ef96 4639 /******************** Bit definition for I2C_DR register ********************/
Kojto 112:6f327212ef96 4640 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
Kojto 112:6f327212ef96 4641
Kojto 112:6f327212ef96 4642 /******************* Bit definition for I2C_SR1 register ********************/
Kojto 112:6f327212ef96 4643 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
Kojto 112:6f327212ef96 4644 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
Kojto 112:6f327212ef96 4645 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
Kojto 112:6f327212ef96 4646 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
Kojto 112:6f327212ef96 4647 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
Kojto 112:6f327212ef96 4648 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
Kojto 112:6f327212ef96 4649 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
Kojto 112:6f327212ef96 4650 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
Kojto 112:6f327212ef96 4651 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
Kojto 112:6f327212ef96 4652 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
Kojto 112:6f327212ef96 4653 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
Kojto 112:6f327212ef96 4654 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
Kojto 112:6f327212ef96 4655 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
Kojto 112:6f327212ef96 4656 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
Kojto 112:6f327212ef96 4657
Kojto 112:6f327212ef96 4658 /******************* Bit definition for I2C_SR2 register ********************/
Kojto 112:6f327212ef96 4659 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
Kojto 112:6f327212ef96 4660 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
Kojto 112:6f327212ef96 4661 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
Kojto 112:6f327212ef96 4662 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
Kojto 112:6f327212ef96 4663 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
Kojto 112:6f327212ef96 4664 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
Kojto 112:6f327212ef96 4665 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
Kojto 112:6f327212ef96 4666 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
Kojto 112:6f327212ef96 4667
Kojto 112:6f327212ef96 4668 /******************* Bit definition for I2C_CCR register ********************/
Kojto 112:6f327212ef96 4669 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
Kojto 112:6f327212ef96 4670 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
Kojto 112:6f327212ef96 4671 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
Kojto 112:6f327212ef96 4672
Kojto 112:6f327212ef96 4673 /****************** Bit definition for I2C_TRISE register *******************/
Kojto 112:6f327212ef96 4674 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
Kojto 112:6f327212ef96 4675
Kojto 112:6f327212ef96 4676 /****************** Bit definition for I2C_FLTR register *******************/
Kojto 112:6f327212ef96 4677 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
Kojto 112:6f327212ef96 4678 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
Kojto 112:6f327212ef96 4679
Kojto 112:6f327212ef96 4680 /******************************************************************************/
Kojto 112:6f327212ef96 4681 /* */
Kojto 112:6f327212ef96 4682 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
Kojto 112:6f327212ef96 4683 /* */
Kojto 112:6f327212ef96 4684 /******************************************************************************/
Kojto 112:6f327212ef96 4685 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 112:6f327212ef96 4686 #define FMPI2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
Kojto 112:6f327212ef96 4687 #define FMPI2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
Kojto 112:6f327212ef96 4688 #define FMPI2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
Kojto 112:6f327212ef96 4689 #define FMPI2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
Kojto 112:6f327212ef96 4690 #define FMPI2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
Kojto 112:6f327212ef96 4691 #define FMPI2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
Kojto 112:6f327212ef96 4692 #define FMPI2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
Kojto 112:6f327212ef96 4693 #define FMPI2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
Kojto 112:6f327212ef96 4694 #define FMPI2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
Kojto 112:6f327212ef96 4695 #define FMPI2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
Kojto 112:6f327212ef96 4696 #define FMPI2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
Kojto 112:6f327212ef96 4697 #define FMPI2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
Kojto 112:6f327212ef96 4698 #define FMPI2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
Kojto 112:6f327212ef96 4699 #define FMPI2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
Kojto 112:6f327212ef96 4700 #define FMPI2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
Kojto 112:6f327212ef96 4701 #define FMPI2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
Kojto 112:6f327212ef96 4702 #define FMPI2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
Kojto 112:6f327212ef96 4703 #define FMPI2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
Kojto 112:6f327212ef96 4704 #define FMPI2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
Kojto 112:6f327212ef96 4705 #define FMPI2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
Kojto 112:6f327212ef96 4706 #define FMPI2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
Kojto 112:6f327212ef96 4707
Kojto 112:6f327212ef96 4708 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 112:6f327212ef96 4709 #define FMPI2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
Kojto 112:6f327212ef96 4710 #define FMPI2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
Kojto 112:6f327212ef96 4711 #define FMPI2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
Kojto 112:6f327212ef96 4712 #define FMPI2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
Kojto 112:6f327212ef96 4713 #define FMPI2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
Kojto 112:6f327212ef96 4714 #define FMPI2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
Kojto 112:6f327212ef96 4715 #define FMPI2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
Kojto 112:6f327212ef96 4716 #define FMPI2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
Kojto 112:6f327212ef96 4717 #define FMPI2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
Kojto 112:6f327212ef96 4718 #define FMPI2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
Kojto 112:6f327212ef96 4719 #define FMPI2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
Kojto 112:6f327212ef96 4720
Kojto 112:6f327212ef96 4721 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 112:6f327212ef96 4722 #define FMPI2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
Kojto 112:6f327212ef96 4723 #define FMPI2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
Kojto 112:6f327212ef96 4724 #define FMPI2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
Kojto 112:6f327212ef96 4725
Kojto 112:6f327212ef96 4726 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 112:6f327212ef96 4727 #define FMPI2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
Kojto 112:6f327212ef96 4728 #define FMPI2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
Kojto 112:6f327212ef96 4729 #define FMPI2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
Kojto 112:6f327212ef96 4730
Kojto 112:6f327212ef96 4731 /******************* Bit definition for I2C_TIMINGR register *******************/
Kojto 112:6f327212ef96 4732 #define FMPI2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
Kojto 112:6f327212ef96 4733 #define FMPI2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
Kojto 112:6f327212ef96 4734 #define FMPI2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
Kojto 112:6f327212ef96 4735 #define FMPI2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
Kojto 112:6f327212ef96 4736 #define FMPI2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
Kojto 112:6f327212ef96 4737
Kojto 112:6f327212ef96 4738 /******************* Bit definition for I2C_TIMEOUTR register *******************/
Kojto 112:6f327212ef96 4739 #define FMPI2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
Kojto 112:6f327212ef96 4740 #define FMPI2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
Kojto 112:6f327212ef96 4741 #define FMPI2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
Kojto 112:6f327212ef96 4742 #define FMPI2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
Kojto 112:6f327212ef96 4743 #define FMPI2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
Kojto 112:6f327212ef96 4744
Kojto 112:6f327212ef96 4745 /****************** Bit definition for I2C_ISR register *********************/
Kojto 112:6f327212ef96 4746 #define FMPI2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
Kojto 112:6f327212ef96 4747 #define FMPI2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
Kojto 112:6f327212ef96 4748 #define FMPI2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
Kojto 112:6f327212ef96 4749 #define FMPI2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
Kojto 112:6f327212ef96 4750 #define FMPI2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
Kojto 112:6f327212ef96 4751 #define FMPI2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
Kojto 112:6f327212ef96 4752 #define FMPI2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
Kojto 112:6f327212ef96 4753 #define FMPI2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
Kojto 112:6f327212ef96 4754 #define FMPI2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
Kojto 112:6f327212ef96 4755 #define FMPI2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
Kojto 112:6f327212ef96 4756 #define FMPI2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
Kojto 112:6f327212ef96 4757 #define FMPI2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
Kojto 112:6f327212ef96 4758 #define FMPI2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
Kojto 112:6f327212ef96 4759 #define FMPI2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
Kojto 112:6f327212ef96 4760 #define FMPI2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
Kojto 112:6f327212ef96 4761 #define FMPI2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
Kojto 112:6f327212ef96 4762 #define FMPI2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
Kojto 112:6f327212ef96 4763
Kojto 112:6f327212ef96 4764 /****************** Bit definition for I2C_ICR register *********************/
Kojto 112:6f327212ef96 4765 #define FMPI2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
Kojto 112:6f327212ef96 4766 #define FMPI2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
Kojto 112:6f327212ef96 4767 #define FMPI2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
Kojto 112:6f327212ef96 4768 #define FMPI2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
Kojto 112:6f327212ef96 4769 #define FMPI2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
Kojto 112:6f327212ef96 4770 #define FMPI2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
Kojto 112:6f327212ef96 4771 #define FMPI2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
Kojto 112:6f327212ef96 4772 #define FMPI2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
Kojto 112:6f327212ef96 4773 #define FMPI2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
Kojto 112:6f327212ef96 4774
Kojto 112:6f327212ef96 4775 /****************** Bit definition for I2C_PECR register *********************/
Kojto 112:6f327212ef96 4776 #define FMPI2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
Kojto 112:6f327212ef96 4777
Kojto 112:6f327212ef96 4778 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 112:6f327212ef96 4779 #define FMPI2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
Kojto 112:6f327212ef96 4780
Kojto 112:6f327212ef96 4781 /****************** Bit definition for I2C_TXDR register *********************/
Kojto 112:6f327212ef96 4782 #define FMPI2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
Kojto 112:6f327212ef96 4783
Kojto 112:6f327212ef96 4784 /******************************************************************************/
Kojto 112:6f327212ef96 4785 /* */
Kojto 112:6f327212ef96 4786 /* Independent WATCHDOG */
Kojto 112:6f327212ef96 4787 /* */
Kojto 112:6f327212ef96 4788 /******************************************************************************/
Kojto 112:6f327212ef96 4789 /******************* Bit definition for IWDG_KR register ********************/
Kojto 112:6f327212ef96 4790 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
Kojto 112:6f327212ef96 4791
Kojto 112:6f327212ef96 4792 /******************* Bit definition for IWDG_PR register ********************/
Kojto 112:6f327212ef96 4793 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
Kojto 112:6f327212ef96 4794 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 112:6f327212ef96 4795 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 112:6f327212ef96 4796 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 112:6f327212ef96 4797
Kojto 112:6f327212ef96 4798 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 112:6f327212ef96 4799 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
Kojto 112:6f327212ef96 4800
Kojto 112:6f327212ef96 4801 /******************* Bit definition for IWDG_SR register ********************/
Kojto 112:6f327212ef96 4802 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
Kojto 112:6f327212ef96 4803 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
Kojto 112:6f327212ef96 4804
Kojto 112:6f327212ef96 4805
Kojto 112:6f327212ef96 4806 /******************************************************************************/
Kojto 112:6f327212ef96 4807 /* */
Kojto 112:6f327212ef96 4808 /* Power Control */
Kojto 112:6f327212ef96 4809 /* */
Kojto 112:6f327212ef96 4810 /******************************************************************************/
Kojto 112:6f327212ef96 4811 /******************** Bit definition for PWR_CR register ********************/
Kojto 112:6f327212ef96 4812 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
Kojto 112:6f327212ef96 4813 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 112:6f327212ef96 4814 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 112:6f327212ef96 4815 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 112:6f327212ef96 4816 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 112:6f327212ef96 4817
Kojto 112:6f327212ef96 4818 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 112:6f327212ef96 4819 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 112:6f327212ef96 4820 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 112:6f327212ef96 4821 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 112:6f327212ef96 4822
Kojto 112:6f327212ef96 4823 /*!< PVD level configuration */
Kojto 112:6f327212ef96 4824 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Kojto 112:6f327212ef96 4825 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Kojto 112:6f327212ef96 4826 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Kojto 112:6f327212ef96 4827 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Kojto 112:6f327212ef96 4828 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Kojto 112:6f327212ef96 4829 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Kojto 112:6f327212ef96 4830 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Kojto 112:6f327212ef96 4831 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Kojto 112:6f327212ef96 4832 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 112:6f327212ef96 4833 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
Kojto 112:6f327212ef96 4834 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
Kojto 112:6f327212ef96 4835 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
Kojto 112:6f327212ef96 4836 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
Kojto 112:6f327212ef96 4837 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
Kojto 112:6f327212ef96 4838 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4839 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4840 #define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
Kojto 112:6f327212ef96 4841 #define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
Kojto 112:6f327212ef96 4842 #define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
Kojto 112:6f327212ef96 4843 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4844 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4845 #define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
Kojto 112:6f327212ef96 4846 #define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
Kojto 112:6f327212ef96 4847
Kojto 112:6f327212ef96 4848 /* Legacy define */
Kojto 112:6f327212ef96 4849 #define PWR_CR_PMODE PWR_CR_VOS
Kojto 112:6f327212ef96 4850 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
Kojto 112:6f327212ef96 4851 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
Kojto 112:6f327212ef96 4852
Kojto 112:6f327212ef96 4853 /******************* Bit definition for PWR_CSR register ********************/
Kojto 112:6f327212ef96 4854 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 112:6f327212ef96 4855 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 112:6f327212ef96 4856 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 112:6f327212ef96 4857 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
Kojto 112:6f327212ef96 4858 #define PWR_CSR_EWUP2 ((uint32_t)0x00000080) /*!< Enable WKUP pin 2 */
Kojto 112:6f327212ef96 4859 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
Kojto 112:6f327212ef96 4860 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
Kojto 112:6f327212ef96 4861 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
Kojto 112:6f327212ef96 4862 #define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
Kojto 112:6f327212ef96 4863 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
Kojto 112:6f327212ef96 4864 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
Kojto 112:6f327212ef96 4865
Kojto 112:6f327212ef96 4866 /* Legacy define */
Kojto 112:6f327212ef96 4867 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
Kojto 112:6f327212ef96 4868
Kojto 112:6f327212ef96 4869 /******************************************************************************/
Kojto 112:6f327212ef96 4870 /* */
Kojto 112:6f327212ef96 4871 /* QUADSPI */
Kojto 112:6f327212ef96 4872 /* */
Kojto 112:6f327212ef96 4873 /******************************************************************************/
Kojto 112:6f327212ef96 4874 /***************** Bit definition for QUADSPI_CR register *******************/
Kojto 112:6f327212ef96 4875 #define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
Kojto 112:6f327212ef96 4876 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
Kojto 112:6f327212ef96 4877 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
Kojto 112:6f327212ef96 4878 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
Kojto 112:6f327212ef96 4879 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< SSHIFT Sample Shift */
Kojto 112:6f327212ef96 4880 #define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
Kojto 112:6f327212ef96 4881 #define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
Kojto 112:6f327212ef96 4882 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
Kojto 112:6f327212ef96 4883 #define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 112:6f327212ef96 4884 #define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 112:6f327212ef96 4885 #define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 112:6f327212ef96 4886 #define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 112:6f327212ef96 4887 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
Kojto 112:6f327212ef96 4888 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
Kojto 112:6f327212ef96 4889 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
Kojto 112:6f327212ef96 4890 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
Kojto 112:6f327212ef96 4891 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
Kojto 112:6f327212ef96 4892 #define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4893 #define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
Kojto 112:6f327212ef96 4894 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
Kojto 112:6f327212ef96 4895 #define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4896 #define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4897 #define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 112:6f327212ef96 4898 #define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Kojto 112:6f327212ef96 4899 #define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
Kojto 112:6f327212ef96 4900 #define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
Kojto 112:6f327212ef96 4901 #define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
Kojto 112:6f327212ef96 4902 #define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
Kojto 112:6f327212ef96 4903
Kojto 112:6f327212ef96 4904 /***************** Bit definition for QUADSPI_DCR register ******************/
Kojto 112:6f327212ef96 4905 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
Kojto 112:6f327212ef96 4906 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
Kojto 112:6f327212ef96 4907 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 112:6f327212ef96 4908 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 112:6f327212ef96 4909 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 112:6f327212ef96 4910 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
Kojto 112:6f327212ef96 4911 #define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4912 #define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4913 #define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 112:6f327212ef96 4914 #define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 112:6f327212ef96 4915 #define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 112:6f327212ef96 4916
Kojto 112:6f327212ef96 4917 /****************** Bit definition for QUADSPI_SR register *******************/
Kojto 112:6f327212ef96 4918 #define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
Kojto 112:6f327212ef96 4919 #define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
Kojto 112:6f327212ef96 4920 #define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
Kojto 112:6f327212ef96 4921 #define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
Kojto 112:6f327212ef96 4922 #define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
Kojto 112:6f327212ef96 4923 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
Kojto 112:6f327212ef96 4924 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00003F00) /*!< FIFO Threshlod Flag */
Kojto 112:6f327212ef96 4925 #define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 112:6f327212ef96 4926 #define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 112:6f327212ef96 4927 #define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 112:6f327212ef96 4928 #define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 112:6f327212ef96 4929 #define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
Kojto 112:6f327212ef96 4930 #define QUADSPI_SR_FLEVEL_5 ((uint32_t)0x00002000) /*!< Bit 5 */
Kojto 112:6f327212ef96 4931
Kojto 112:6f327212ef96 4932 /****************** Bit definition for QUADSPI_FCR register ******************/
Kojto 112:6f327212ef96 4933 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
Kojto 112:6f327212ef96 4934 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
Kojto 112:6f327212ef96 4935 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
Kojto 112:6f327212ef96 4936 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
Kojto 112:6f327212ef96 4937
Kojto 112:6f327212ef96 4938 /****************** Bit definition for QUADSPI_DLR register ******************/
Kojto 112:6f327212ef96 4939 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
Kojto 112:6f327212ef96 4940
Kojto 112:6f327212ef96 4941 /****************** Bit definition for QUADSPI_CCR register ******************/
Kojto 112:6f327212ef96 4942 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
Kojto 112:6f327212ef96 4943 #define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 112:6f327212ef96 4944 #define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 112:6f327212ef96 4945 #define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 112:6f327212ef96 4946 #define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 112:6f327212ef96 4947 #define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 112:6f327212ef96 4948 #define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
Kojto 112:6f327212ef96 4949 #define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
Kojto 112:6f327212ef96 4950 #define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
Kojto 112:6f327212ef96 4951 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
Kojto 112:6f327212ef96 4952 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 112:6f327212ef96 4953 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 112:6f327212ef96 4954 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
Kojto 112:6f327212ef96 4955 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 112:6f327212ef96 4956 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 112:6f327212ef96 4957 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
Kojto 112:6f327212ef96 4958 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4959 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4960 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
Kojto 112:6f327212ef96 4961 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4962 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4963 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
Kojto 112:6f327212ef96 4964 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4965 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4966 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
Kojto 112:6f327212ef96 4967 #define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4968 #define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4969 #define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 112:6f327212ef96 4970 #define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Kojto 112:6f327212ef96 4971 #define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
Kojto 112:6f327212ef96 4972 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
Kojto 112:6f327212ef96 4973 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4974 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4975 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
Kojto 112:6f327212ef96 4976 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 112:6f327212ef96 4977 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 112:6f327212ef96 4978 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
Kojto 112:6f327212ef96 4979 #define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
Kojto 112:6f327212ef96 4980 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
Kojto 112:6f327212ef96 4981 /****************** Bit definition for QUADSPI_AR register *******************/
Kojto 112:6f327212ef96 4982 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
Kojto 112:6f327212ef96 4983
Kojto 112:6f327212ef96 4984 /****************** Bit definition for QUADSPI_ABR register ******************/
Kojto 112:6f327212ef96 4985 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
Kojto 112:6f327212ef96 4986
Kojto 112:6f327212ef96 4987 /****************** Bit definition for QUADSPI_DR register *******************/
Kojto 112:6f327212ef96 4988 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
Kojto 112:6f327212ef96 4989
Kojto 112:6f327212ef96 4990 /****************** Bit definition for QUADSPI_PSMKR register ****************/
Kojto 112:6f327212ef96 4991 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
Kojto 112:6f327212ef96 4992
Kojto 112:6f327212ef96 4993 /****************** Bit definition for QUADSPI_PSMAR register ****************/
Kojto 112:6f327212ef96 4994 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
Kojto 112:6f327212ef96 4995
Kojto 112:6f327212ef96 4996 /****************** Bit definition for QUADSPI_PIR register *****************/
Kojto 112:6f327212ef96 4997 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
Kojto 112:6f327212ef96 4998
Kojto 112:6f327212ef96 4999 /****************** Bit definition for QUADSPI_LPTR register *****************/
Kojto 112:6f327212ef96 5000 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
Kojto 112:6f327212ef96 5001
Kojto 112:6f327212ef96 5002 /******************************************************************************/
Kojto 112:6f327212ef96 5003 /* */
Kojto 112:6f327212ef96 5004 /* Reset and Clock Control */
Kojto 112:6f327212ef96 5005 /* */
Kojto 112:6f327212ef96 5006 /******************************************************************************/
Kojto 112:6f327212ef96 5007 /******************** Bit definition for RCC_CR register ********************/
Kojto 112:6f327212ef96 5008 #define RCC_CR_HSION ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5009 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5010
Kojto 112:6f327212ef96 5011 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
Kojto 112:6f327212ef96 5012 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
Kojto 112:6f327212ef96 5013 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
Kojto 112:6f327212ef96 5014 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
Kojto 112:6f327212ef96 5015 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
Kojto 112:6f327212ef96 5016 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
Kojto 112:6f327212ef96 5017
Kojto 112:6f327212ef96 5018 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
Kojto 112:6f327212ef96 5019 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
Kojto 112:6f327212ef96 5020 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
Kojto 112:6f327212ef96 5021 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
Kojto 112:6f327212ef96 5022 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
Kojto 112:6f327212ef96 5023 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
Kojto 112:6f327212ef96 5024 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
Kojto 112:6f327212ef96 5025 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
Kojto 112:6f327212ef96 5026 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
Kojto 112:6f327212ef96 5027
Kojto 112:6f327212ef96 5028 #define RCC_CR_HSEON ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5029 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5030 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5031 #define RCC_CR_CSSON ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5032 #define RCC_CR_PLLON ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5033 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5034 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5035 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5036 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5037 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5038
Kojto 112:6f327212ef96 5039 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 112:6f327212ef96 5040 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
Kojto 112:6f327212ef96 5041 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5042 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5043 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5044 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5045 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5046 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5047
Kojto 112:6f327212ef96 5048 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
Kojto 112:6f327212ef96 5049 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5050 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5051 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5052 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5053 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5054 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5055 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5056 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5057 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5058
Kojto 112:6f327212ef96 5059 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
Kojto 112:6f327212ef96 5060 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5061 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5062
Kojto 112:6f327212ef96 5063 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5064 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5065 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
Kojto 112:6f327212ef96 5066
Kojto 112:6f327212ef96 5067 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
Kojto 112:6f327212ef96 5068 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5069 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5070 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5071 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5072
Kojto 112:6f327212ef96 5073 #define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
Kojto 112:6f327212ef96 5074 #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5075 #define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5076 #define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 5077
Kojto 112:6f327212ef96 5078
Kojto 112:6f327212ef96 5079 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 112:6f327212ef96 5080 /*!< SW configuration */
Kojto 112:6f327212ef96 5081 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 112:6f327212ef96 5082 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 112:6f327212ef96 5083 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 112:6f327212ef96 5084
Kojto 112:6f327212ef96 5085 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 112:6f327212ef96 5086 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 112:6f327212ef96 5087 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */
Kojto 112:6f327212ef96 5088 #define RCC_CFGR_SW_PLLR ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */
Kojto 112:6f327212ef96 5089
Kojto 112:6f327212ef96 5090 /*!< SWS configuration */
Kojto 112:6f327212ef96 5091 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 112:6f327212ef96 5092 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 112:6f327212ef96 5093 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 112:6f327212ef96 5094
Kojto 112:6f327212ef96 5095 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 112:6f327212ef96 5096 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 112:6f327212ef96 5097 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */
Kojto 112:6f327212ef96 5098 #define RCC_CFGR_SWS_PLLR ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */
Kojto 112:6f327212ef96 5099
Kojto 112:6f327212ef96 5100 /*!< HPRE configuration */
Kojto 112:6f327212ef96 5101 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 112:6f327212ef96 5102 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 112:6f327212ef96 5103 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 112:6f327212ef96 5104 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 112:6f327212ef96 5105 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 112:6f327212ef96 5106
Kojto 112:6f327212ef96 5107 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 112:6f327212ef96 5108 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 112:6f327212ef96 5109 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 112:6f327212ef96 5110 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 112:6f327212ef96 5111 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 112:6f327212ef96 5112 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 112:6f327212ef96 5113 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 112:6f327212ef96 5114 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 112:6f327212ef96 5115 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 112:6f327212ef96 5116
Kojto 112:6f327212ef96 5117 /*!< PPRE1 configuration */
Kojto 112:6f327212ef96 5118 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 112:6f327212ef96 5119 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 112:6f327212ef96 5120 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 112:6f327212ef96 5121 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 112:6f327212ef96 5122
Kojto 112:6f327212ef96 5123 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 112:6f327212ef96 5124 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
Kojto 112:6f327212ef96 5125 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
Kojto 112:6f327212ef96 5126 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
Kojto 112:6f327212ef96 5127 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
Kojto 112:6f327212ef96 5128
Kojto 112:6f327212ef96 5129 /*!< PPRE2 configuration */
Kojto 112:6f327212ef96 5130 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 112:6f327212ef96 5131 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
Kojto 112:6f327212ef96 5132 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
Kojto 112:6f327212ef96 5133 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
Kojto 112:6f327212ef96 5134
Kojto 112:6f327212ef96 5135 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 112:6f327212ef96 5136 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
Kojto 112:6f327212ef96 5137 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
Kojto 112:6f327212ef96 5138 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
Kojto 112:6f327212ef96 5139 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
Kojto 112:6f327212ef96 5140
Kojto 112:6f327212ef96 5141 /*!< RTCPRE configuration */
Kojto 112:6f327212ef96 5142 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
Kojto 112:6f327212ef96 5143 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5144 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5145 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5146 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5147 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5148
Kojto 112:6f327212ef96 5149 /*!< MCO1 configuration */
Kojto 112:6f327212ef96 5150 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
Kojto 112:6f327212ef96 5151 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5152 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5153
Kojto 112:6f327212ef96 5154 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5155
Kojto 112:6f327212ef96 5156 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
Kojto 112:6f327212ef96 5157 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5158 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5159 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5160
Kojto 112:6f327212ef96 5161 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
Kojto 112:6f327212ef96 5162 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5163 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5164 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5165
Kojto 112:6f327212ef96 5166 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
Kojto 112:6f327212ef96 5167 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 5168 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 5169
Kojto 112:6f327212ef96 5170 /******************** Bit definition for RCC_CIR register *******************/
Kojto 112:6f327212ef96 5171 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5172 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5173 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5174 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5175 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5176 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5177 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5178 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5179 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5180 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5181 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5182 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5183 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5184 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5185 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5186 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5187 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5188 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5189 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5190 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5191 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5192 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5193 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5194
Kojto 112:6f327212ef96 5195 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 112:6f327212ef96 5196 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5197 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5198 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5199 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5200 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5201 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5202 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5203 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5204 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5205 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5206 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5207 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5208
Kojto 112:6f327212ef96 5209 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 112:6f327212ef96 5210 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5211 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5212
Kojto 112:6f327212ef96 5213 /******************** Bit definition for RCC_AHB3RSTR register **************/
Kojto 112:6f327212ef96 5214 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5215 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5216
Kojto 112:6f327212ef96 5217 /******************** Bit definition for RCC_APB1RSTR register **************/
Kojto 112:6f327212ef96 5218 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5219 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5220 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5221 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5222 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5223 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5224 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5225 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5226 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5227 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5228 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5229 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5230 #define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5231 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5232 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5233 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5234 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5235 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5236 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5237 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5238 #define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5239 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5240 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5241 #define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5242 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5243 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5244
Kojto 112:6f327212ef96 5245 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 112:6f327212ef96 5246 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5247 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5248 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5249 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5250 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5251 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5252 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5253 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5254 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5255 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5256 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5257 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5258 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5259 #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5260
Kojto 112:6f327212ef96 5261 /* Old SPI1RST bit definition, maintained for legacy purpose */
Kojto 112:6f327212ef96 5262 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
Kojto 112:6f327212ef96 5263
Kojto 112:6f327212ef96 5264 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 112:6f327212ef96 5265 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5266 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5267 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5268 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5269 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5270 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5271 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5272 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5273
Kojto 112:6f327212ef96 5274 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5275 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5276 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5277 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5278
Kojto 112:6f327212ef96 5279 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5280 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 5281
Kojto 112:6f327212ef96 5282 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 112:6f327212ef96 5283 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5284 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5285
Kojto 112:6f327212ef96 5286 /******************** Bit definition for RCC_AHB3ENR register ***************/
Kojto 112:6f327212ef96 5287 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5288 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5289
Kojto 112:6f327212ef96 5290 /******************** Bit definition for RCC_APB1ENR register ***************/
Kojto 112:6f327212ef96 5291 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5292 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5293 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5294 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5295 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5296 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5297 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5298 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5299 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5300 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5301 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5302 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5303 #define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5304 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5305 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5306 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5307 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5308 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5309 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5310 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5311 #define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5312 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5313 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5314 #define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5315 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5316 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5317
Kojto 112:6f327212ef96 5318 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 112:6f327212ef96 5319 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5320 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5321 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5322 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5323 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5324 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5325 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5326 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5327 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5328 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5329 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5330 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5331 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5332 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5333 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5334 #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5335
Kojto 112:6f327212ef96 5336 /******************** Bit definition for RCC_AHB1LPENR register *************/
Kojto 112:6f327212ef96 5337 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5338 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5339 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5340 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5341 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5342 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5343 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5344 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5345 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5346 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5347 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5348
Kojto 112:6f327212ef96 5349 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5350 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5351 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5352 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5353 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5354 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5355 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5356
Kojto 112:6f327212ef96 5357 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5358 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 5359
Kojto 112:6f327212ef96 5360 /******************** Bit definition for RCC_AHB2LPENR register *************/
Kojto 112:6f327212ef96 5361 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5362 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5363
Kojto 112:6f327212ef96 5364 /******************** Bit definition for RCC_AHB3LPENR register *************/
Kojto 112:6f327212ef96 5365 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5366 #define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5367
Kojto 112:6f327212ef96 5368 /******************** Bit definition for RCC_APB1LPENR register *************/
Kojto 112:6f327212ef96 5369 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5370 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5371 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5372 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5373 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5374 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5375 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5376 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5377 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5378 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5379 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5380 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5381 #define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5382 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5383 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5384 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5385 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5386 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5387 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5388 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5389 #define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5390 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5391 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5392 #define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5393 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5394 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5395
Kojto 112:6f327212ef96 5396 /******************** Bit definition for RCC_APB2LPENR register *************/
Kojto 112:6f327212ef96 5397 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5398 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5399 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5400 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5401 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5402 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5403 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5404 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5405 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5406 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5407 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5408 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5409 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5410 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5411 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5412 #define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5413
Kojto 112:6f327212ef96 5414 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 112:6f327212ef96 5415 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5416 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5417 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5418 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5419
Kojto 112:6f327212ef96 5420 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
Kojto 112:6f327212ef96 5421 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5422 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5423
Kojto 112:6f327212ef96 5424 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5425 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5426
Kojto 112:6f327212ef96 5427 /******************** Bit definition for RCC_CSR register *******************/
Kojto 112:6f327212ef96 5428 #define RCC_CSR_LSION ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5429 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5430 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5431 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5432 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5433 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5434 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5435 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5436 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 5437 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 5438
Kojto 112:6f327212ef96 5439 /******************** Bit definition for RCC_SSCGR register *****************/
Kojto 112:6f327212ef96 5440 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
Kojto 112:6f327212ef96 5441 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
Kojto 112:6f327212ef96 5442 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 5443 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 5444
Kojto 112:6f327212ef96 5445 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
Kojto 112:6f327212ef96 5446 #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
Kojto 112:6f327212ef96 5447 #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5448 #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5449 #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5450 #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5451 #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5452 #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5453
Kojto 112:6f327212ef96 5454 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
Kojto 112:6f327212ef96 5455 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5456 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5457 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5458 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5459 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5460 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5461 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5462 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5463 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5464
Kojto 112:6f327212ef96 5465 #define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
Kojto 112:6f327212ef96 5466 #define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5467 #define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5468
Kojto 112:6f327212ef96 5469 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
Kojto 112:6f327212ef96 5470 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5471 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5472 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5473 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5474
Kojto 112:6f327212ef96 5475 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
Kojto 112:6f327212ef96 5476 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5477 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5478 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 5479
Kojto 112:6f327212ef96 5480
Kojto 112:6f327212ef96 5481 /******************** Bit definition for RCC_PLLSAICFGR register ************/
Kojto 112:6f327212ef96 5482 #define RCC_PLLSAICFGR_PLLSAIM ((uint32_t)0x0000003F)
Kojto 112:6f327212ef96 5483 #define RCC_PLLSAICFGR_PLLSAIM_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5484 #define RCC_PLLSAICFGR_PLLSAIM_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5485 #define RCC_PLLSAICFGR_PLLSAIM_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5486 #define RCC_PLLSAICFGR_PLLSAIM_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5487 #define RCC_PLLSAICFGR_PLLSAIM_4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5488 #define RCC_PLLSAICFGR_PLLSAIM_5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5489
Kojto 112:6f327212ef96 5490 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
Kojto 112:6f327212ef96 5491 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5492 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5493 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5494 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5495 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5496 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5497 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5498 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5499 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5500
Kojto 112:6f327212ef96 5501 #define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
Kojto 112:6f327212ef96 5502 #define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5503 #define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5504
Kojto 112:6f327212ef96 5505 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
Kojto 112:6f327212ef96 5506 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5507 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5508 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5509 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5510
Kojto 112:6f327212ef96 5511 /******************** Bit definition for RCC_DCKCFGR register ***************/
Kojto 112:6f327212ef96 5512 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
Kojto 112:6f327212ef96 5513 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
Kojto 112:6f327212ef96 5514 #define RCC_DCKCFGR_SAI1SRC ((uint32_t)0x00300000)
Kojto 112:6f327212ef96 5515 #define RCC_DCKCFGR_SAI1SRC_0 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5516 #define RCC_DCKCFGR_SAI1SRC_1 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5517 #define RCC_DCKCFGR_SAI2SRC ((uint32_t)0x00C00000)
Kojto 112:6f327212ef96 5518 #define RCC_DCKCFGR_SAI2SRC_0 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5519 #define RCC_DCKCFGR_SAI2SRC_1 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5520 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5521 #define RCC_DCKCFGR_I2S1SRC ((uint32_t)0x06000000)
Kojto 112:6f327212ef96 5522 #define RCC_DCKCFGR_I2S1SRC_0 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5523 #define RCC_DCKCFGR_I2S1SRC_1 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5524 #define RCC_DCKCFGR_I2S2SRC ((uint32_t)0x18000000)
Kojto 112:6f327212ef96 5525 #define RCC_DCKCFGR_I2S2SRC_0 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5526 #define RCC_DCKCFGR_I2S2SRC_1 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5527
Kojto 112:6f327212ef96 5528 /******************** Bit definition for RCC_CKGATENR register ***************/
Kojto 112:6f327212ef96 5529 #define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5530 #define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5531 #define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5532 #define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5533 #define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5534 #define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5535 #define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5536
Kojto 112:6f327212ef96 5537 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
Kojto 112:6f327212ef96 5538 #define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
Kojto 112:6f327212ef96 5539 #define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5540 #define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5541 #define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5542 #define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5543 #define RCC_DCKCFGR2_SDIOSEL ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5544 #define RCC_DCKCFGR2_SPDIFRXSEL ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5545
Kojto 112:6f327212ef96 5546 /******************************************************************************/
Kojto 112:6f327212ef96 5547 /* */
Kojto 112:6f327212ef96 5548 /* Real-Time Clock (RTC) */
Kojto 112:6f327212ef96 5549 /* */
Kojto 112:6f327212ef96 5550 /******************************************************************************/
Kojto 112:6f327212ef96 5551 /******************** Bits definition for RTC_TR register *******************/
Kojto 112:6f327212ef96 5552 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5553 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 112:6f327212ef96 5554 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5555 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5556 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 112:6f327212ef96 5557 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5558 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5559 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5560 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5561 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 112:6f327212ef96 5562 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5563 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5564 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5565 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 112:6f327212ef96 5566 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5567 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5568 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5569 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5570 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 112:6f327212ef96 5571 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5572 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5573 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5574 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 112:6f327212ef96 5575 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5576 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5577 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5578 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5579
Kojto 112:6f327212ef96 5580 /******************** Bits definition for RTC_DR register *******************/
Kojto 112:6f327212ef96 5581 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 112:6f327212ef96 5582 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5583 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5584 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5585 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5586 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 112:6f327212ef96 5587 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5588 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5589 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5590 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5591 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 112:6f327212ef96 5592 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5593 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5594 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5595 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5596 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 112:6f327212ef96 5597 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5598 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5599 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5600 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5601 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 112:6f327212ef96 5602 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5603 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5604 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 112:6f327212ef96 5605 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5606 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5607 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5608 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5609
Kojto 112:6f327212ef96 5610 /******************** Bits definition for RTC_CR register *******************/
Kojto 112:6f327212ef96 5611 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5612 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 112:6f327212ef96 5613 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5614 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5615 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5616 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5617 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5618 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5619 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5620 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5621 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5622 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5623 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5624 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5625 #define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5626 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5627 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5628 #define RTC_CR_DCE ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5629 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5630 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5631 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5632 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5633 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto 112:6f327212ef96 5634 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5635 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5636 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5637
Kojto 112:6f327212ef96 5638 /******************** Bits definition for RTC_ISR register ******************/
Kojto 112:6f327212ef96 5639 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5640 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5641 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5642 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5643 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5644 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5645 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5646 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5647 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5648 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5649 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5650 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5651 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5652 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5653 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5654 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5655
Kojto 112:6f327212ef96 5656 /******************** Bits definition for RTC_PRER register *****************/
Kojto 112:6f327212ef96 5657 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 112:6f327212ef96 5658 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto 112:6f327212ef96 5659
Kojto 112:6f327212ef96 5660 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 112:6f327212ef96 5661 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto 112:6f327212ef96 5662
Kojto 112:6f327212ef96 5663 /******************** Bits definition for RTC_CALIBR register ***************/
Kojto 112:6f327212ef96 5664 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5665 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
Kojto 112:6f327212ef96 5666
Kojto 112:6f327212ef96 5667 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 112:6f327212ef96 5668 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 5669 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 5670 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 112:6f327212ef96 5671 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5672 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5673 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 112:6f327212ef96 5674 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5675 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5676 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5677 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5678 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5679 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5680 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 112:6f327212ef96 5681 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5682 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5683 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 112:6f327212ef96 5684 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5685 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5686 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5687 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5688 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5689 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 112:6f327212ef96 5690 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5691 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5692 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5693 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 112:6f327212ef96 5694 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5695 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5696 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5697 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5698 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5699 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 112:6f327212ef96 5700 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5701 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5702 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5703 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 112:6f327212ef96 5704 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5705 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5706 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5707 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5708
Kojto 112:6f327212ef96 5709 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 112:6f327212ef96 5710 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 5711 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
Kojto 112:6f327212ef96 5712 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
Kojto 112:6f327212ef96 5713 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
Kojto 112:6f327212ef96 5714 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
Kojto 112:6f327212ef96 5715 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
Kojto 112:6f327212ef96 5716 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5717 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5718 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5719 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5720 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 5721 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5722 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
Kojto 112:6f327212ef96 5723 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5724 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5725 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
Kojto 112:6f327212ef96 5726 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5727 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5728 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5729 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5730 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5731 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
Kojto 112:6f327212ef96 5732 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5733 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5734 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5735 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
Kojto 112:6f327212ef96 5736 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5737 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5738 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5739 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5740 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5741 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
Kojto 112:6f327212ef96 5742 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5743 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5744 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5745 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
Kojto 112:6f327212ef96 5746 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5747 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5748 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5749 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5750
Kojto 112:6f327212ef96 5751 /******************** Bits definition for RTC_WPR register ******************/
Kojto 112:6f327212ef96 5752 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 112:6f327212ef96 5753
Kojto 112:6f327212ef96 5754 /******************** Bits definition for RTC_SSR register ******************/
Kojto 112:6f327212ef96 5755 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 112:6f327212ef96 5756
Kojto 112:6f327212ef96 5757 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 112:6f327212ef96 5758 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 112:6f327212ef96 5759 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 112:6f327212ef96 5760
Kojto 112:6f327212ef96 5761 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 112:6f327212ef96 5762 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 5763 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 112:6f327212ef96 5764 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 112:6f327212ef96 5765 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 5766 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 112:6f327212ef96 5767 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5768 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5769 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5770 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 112:6f327212ef96 5771 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 112:6f327212ef96 5772 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5773 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5774 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5775 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 112:6f327212ef96 5776 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5777 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5778 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5779 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5780 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 112:6f327212ef96 5781 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5782 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5783 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5784 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 112:6f327212ef96 5785 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5786 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5787 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5788 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5789
Kojto 112:6f327212ef96 5790 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 112:6f327212ef96 5791 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 112:6f327212ef96 5792 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5793 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5794 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5795 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5796 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 112:6f327212ef96 5797 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5798 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5799 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5800 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5801 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 112:6f327212ef96 5802 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5803 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5804 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 112:6f327212ef96 5805 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5806 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5807 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5808 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5809
Kojto 112:6f327212ef96 5810 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 112:6f327212ef96 5811 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 112:6f327212ef96 5812
Kojto 112:6f327212ef96 5813 /******************** Bits definition for RTC_CAL register *****************/
Kojto 112:6f327212ef96 5814 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5815 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5816 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5817 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 112:6f327212ef96 5818 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5819 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5820 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5821 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5822 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5823 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 5824 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 5825 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5826 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5827
Kojto 112:6f327212ef96 5828 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 112:6f327212ef96 5829 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 5830 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 5831 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 5832 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 112:6f327212ef96 5833 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 112:6f327212ef96 5834 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 112:6f327212ef96 5835 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 112:6f327212ef96 5836 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 112:6f327212ef96 5837 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 5838 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 5839 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 112:6f327212ef96 5840 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 5841 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 112:6f327212ef96 5842 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 5843 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 5844 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 5845 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 5846 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 5847 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 5848 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 5849
Kojto 112:6f327212ef96 5850 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 112:6f327212ef96 5851 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 112:6f327212ef96 5852 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5853 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5854 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5855 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5856 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 112:6f327212ef96 5857
Kojto 112:6f327212ef96 5858 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 112:6f327212ef96 5859 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
Kojto 112:6f327212ef96 5860 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 112:6f327212ef96 5861 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 5862 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 5863 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 112:6f327212ef96 5864 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
Kojto 112:6f327212ef96 5865
Kojto 112:6f327212ef96 5866 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 112:6f327212ef96 5867 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5868
Kojto 112:6f327212ef96 5869 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 112:6f327212ef96 5870 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5871
Kojto 112:6f327212ef96 5872 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 112:6f327212ef96 5873 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5874
Kojto 112:6f327212ef96 5875 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 112:6f327212ef96 5876 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5877
Kojto 112:6f327212ef96 5878 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 112:6f327212ef96 5879 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5880
Kojto 112:6f327212ef96 5881 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 112:6f327212ef96 5882 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5883
Kojto 112:6f327212ef96 5884 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 112:6f327212ef96 5885 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5886
Kojto 112:6f327212ef96 5887 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 112:6f327212ef96 5888 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5889
Kojto 112:6f327212ef96 5890 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 112:6f327212ef96 5891 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5892
Kojto 112:6f327212ef96 5893 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 112:6f327212ef96 5894 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5895
Kojto 112:6f327212ef96 5896 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 112:6f327212ef96 5897 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5898
Kojto 112:6f327212ef96 5899 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 112:6f327212ef96 5900 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5901
Kojto 112:6f327212ef96 5902 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 112:6f327212ef96 5903 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5904
Kojto 112:6f327212ef96 5905 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 112:6f327212ef96 5906 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5907
Kojto 112:6f327212ef96 5908 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 112:6f327212ef96 5909 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5910
Kojto 112:6f327212ef96 5911 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 112:6f327212ef96 5912 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5913
Kojto 112:6f327212ef96 5914 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 112:6f327212ef96 5915 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5916
Kojto 112:6f327212ef96 5917 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 112:6f327212ef96 5918 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5919
Kojto 112:6f327212ef96 5920 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 112:6f327212ef96 5921 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5922
Kojto 112:6f327212ef96 5923 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 112:6f327212ef96 5924 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 5925
Kojto 112:6f327212ef96 5926 /******************************************************************************/
Kojto 112:6f327212ef96 5927 /* */
Kojto 112:6f327212ef96 5928 /* Serial Audio Interface */
Kojto 112:6f327212ef96 5929 /* */
Kojto 112:6f327212ef96 5930 /******************************************************************************/
Kojto 112:6f327212ef96 5931 /******************** Bit definition for SAI_GCR register *******************/
Kojto 112:6f327212ef96 5932 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
Kojto 112:6f327212ef96 5933 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 5934 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 5935
Kojto 112:6f327212ef96 5936 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
Kojto 112:6f327212ef96 5937 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 5938 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 5939
Kojto 112:6f327212ef96 5940 /******************* Bit definition for SAI_xCR1 register *******************/
Kojto 112:6f327212ef96 5941 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
Kojto 112:6f327212ef96 5942 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 5943 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 5944
Kojto 112:6f327212ef96 5945 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
Kojto 112:6f327212ef96 5946 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 112:6f327212ef96 5947 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 112:6f327212ef96 5948
Kojto 112:6f327212ef96 5949 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
Kojto 112:6f327212ef96 5950 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 112:6f327212ef96 5951 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 112:6f327212ef96 5952 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 112:6f327212ef96 5953
Kojto 112:6f327212ef96 5954 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
Kojto 112:6f327212ef96 5955 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
Kojto 112:6f327212ef96 5956
Kojto 112:6f327212ef96 5957 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
Kojto 112:6f327212ef96 5958 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 112:6f327212ef96 5959 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 112:6f327212ef96 5960
Kojto 112:6f327212ef96 5961 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
Kojto 112:6f327212ef96 5962 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
Kojto 112:6f327212ef96 5963 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
Kojto 112:6f327212ef96 5964 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
Kojto 112:6f327212ef96 5965 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
Kojto 112:6f327212ef96 5966
Kojto 112:6f327212ef96 5967 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
Kojto 112:6f327212ef96 5968 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 5969 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 5970 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 112:6f327212ef96 5971 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 112:6f327212ef96 5972
Kojto 112:6f327212ef96 5973 /******************* Bit definition for SAI_xCR2 register *******************/
Kojto 112:6f327212ef96 5974 #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
Kojto 112:6f327212ef96 5975 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 5976 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 5977 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 5978
Kojto 112:6f327212ef96 5979 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
Kojto 112:6f327212ef96 5980 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
Kojto 112:6f327212ef96 5981 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
Kojto 112:6f327212ef96 5982 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
Kojto 112:6f327212ef96 5983
Kojto 112:6f327212ef96 5984 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
Kojto 112:6f327212ef96 5985 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 112:6f327212ef96 5986 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 112:6f327212ef96 5987 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
Kojto 112:6f327212ef96 5988 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
Kojto 112:6f327212ef96 5989 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
Kojto 112:6f327212ef96 5990 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
Kojto 112:6f327212ef96 5991
Kojto 112:6f327212ef96 5992 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
Kojto 112:6f327212ef96 5993
Kojto 112:6f327212ef96 5994 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
Kojto 112:6f327212ef96 5995 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 112:6f327212ef96 5996 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 112:6f327212ef96 5997
Kojto 112:6f327212ef96 5998 /****************** Bit definition for SAI_xFRCR register *******************/
Kojto 112:6f327212ef96 5999 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
Kojto 112:6f327212ef96 6000 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 6001 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 6002 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 6003 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 6004 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 6005 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 112:6f327212ef96 6006 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 112:6f327212ef96 6007 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 112:6f327212ef96 6008
Kojto 112:6f327212ef96 6009 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
Kojto 112:6f327212ef96 6010 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 6011 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 6012 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 6013 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 6014 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 112:6f327212ef96 6015 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 112:6f327212ef96 6016 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 112:6f327212ef96 6017
Kojto 112:6f327212ef96 6018 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
Kojto 112:6f327212ef96 6019 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
Kojto 112:6f327212ef96 6020 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
Kojto 112:6f327212ef96 6021
Kojto 112:6f327212ef96 6022 /****************** Bit definition for SAI_xSLOTR register *******************/
Kojto 112:6f327212ef96 6023 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
Kojto 112:6f327212ef96 6024 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 6025 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 6026 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 6027 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 6028 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 6029
Kojto 112:6f327212ef96 6030 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
Kojto 112:6f327212ef96 6031 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 112:6f327212ef96 6032 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 112:6f327212ef96 6033
Kojto 112:6f327212ef96 6034 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
Kojto 112:6f327212ef96 6035 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 6036 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 6037 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 112:6f327212ef96 6038 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 112:6f327212ef96 6039
Kojto 112:6f327212ef96 6040 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
Kojto 112:6f327212ef96 6041
Kojto 112:6f327212ef96 6042 /******************* Bit definition for SAI_xIMR register *******************/
Kojto 112:6f327212ef96 6043 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
Kojto 112:6f327212ef96 6044 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
Kojto 112:6f327212ef96 6045 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
Kojto 112:6f327212ef96 6046 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
Kojto 112:6f327212ef96 6047 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
Kojto 112:6f327212ef96 6048 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
Kojto 112:6f327212ef96 6049 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
Kojto 112:6f327212ef96 6050
Kojto 112:6f327212ef96 6051 /******************** Bit definition for SAI_xSR register *******************/
Kojto 112:6f327212ef96 6052 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
Kojto 112:6f327212ef96 6053 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
Kojto 112:6f327212ef96 6054 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
Kojto 112:6f327212ef96 6055 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
Kojto 112:6f327212ef96 6056 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
Kojto 112:6f327212ef96 6057 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
Kojto 112:6f327212ef96 6058 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
Kojto 112:6f327212ef96 6059
Kojto 112:6f327212ef96 6060 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
Kojto 112:6f327212ef96 6061 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 6062 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 6063 #define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 6064
Kojto 112:6f327212ef96 6065 /****************** Bit definition for SAI_xCLRFR register ******************/
Kojto 112:6f327212ef96 6066 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
Kojto 112:6f327212ef96 6067 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
Kojto 112:6f327212ef96 6068 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
Kojto 112:6f327212ef96 6069 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
Kojto 112:6f327212ef96 6070 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
Kojto 112:6f327212ef96 6071 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
Kojto 112:6f327212ef96 6072 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
Kojto 112:6f327212ef96 6073
Kojto 112:6f327212ef96 6074 /****************** Bit definition for SAI_xDR register ******************/
Kojto 112:6f327212ef96 6075 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
Kojto 112:6f327212ef96 6076
Kojto 112:6f327212ef96 6077 /******************************************************************************/
Kojto 112:6f327212ef96 6078 /* */
Kojto 112:6f327212ef96 6079 /* SPDIF-RX Interface */
Kojto 112:6f327212ef96 6080 /* */
Kojto 112:6f327212ef96 6081 /******************************************************************************/
Kojto 112:6f327212ef96 6082 /******************** Bit definition for SPDIFRX_CR register *******************/
Kojto 112:6f327212ef96 6083 #define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */
Kojto 112:6f327212ef96 6084 #define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */
Kojto 112:6f327212ef96 6085 #define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */
Kojto 112:6f327212ef96 6086 #define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */
Kojto 112:6f327212ef96 6087 #define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */
Kojto 112:6f327212ef96 6088 #define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */
Kojto 112:6f327212ef96 6089 #define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */
Kojto 112:6f327212ef96 6090 #define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */
Kojto 112:6f327212ef96 6091 #define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */
Kojto 112:6f327212ef96 6092 #define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */
Kojto 112:6f327212ef96 6093 #define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */
Kojto 112:6f327212ef96 6094 #define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */
Kojto 112:6f327212ef96 6095 #define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIFRX input selection */
Kojto 112:6f327212ef96 6096
Kojto 112:6f327212ef96 6097 /******************* Bit definition for SPDIFRX_IMR register *******************/
Kojto 112:6f327212ef96 6098 #define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */
Kojto 112:6f327212ef96 6099 #define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */
Kojto 112:6f327212ef96 6100 #define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */
Kojto 112:6f327212ef96 6101 #define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */
Kojto 112:6f327212ef96 6102 #define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */
Kojto 112:6f327212ef96 6103 #define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */
Kojto 112:6f327212ef96 6104 #define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */
Kojto 112:6f327212ef96 6105
Kojto 112:6f327212ef96 6106 /******************* Bit definition for SPDIFRX_SR register *******************/
Kojto 112:6f327212ef96 6107 #define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */
Kojto 112:6f327212ef96 6108 #define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */
Kojto 112:6f327212ef96 6109 #define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */
Kojto 112:6f327212ef96 6110 #define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */
Kojto 112:6f327212ef96 6111 #define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */
Kojto 112:6f327212ef96 6112 #define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */
Kojto 112:6f327212ef96 6113 #define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */
Kojto 112:6f327212ef96 6114 #define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */
Kojto 112:6f327212ef96 6115 #define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */
Kojto 112:6f327212ef96 6116 #define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with SPDIFRX_clk */
Kojto 112:6f327212ef96 6117
Kojto 112:6f327212ef96 6118 /******************* Bit definition for SPDIFRX_IFCR register *******************/
Kojto 112:6f327212ef96 6119 #define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */
Kojto 112:6f327212ef96 6120 #define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */
Kojto 112:6f327212ef96 6121 #define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */
Kojto 112:6f327212ef96 6122 #define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */
Kojto 112:6f327212ef96 6123
Kojto 112:6f327212ef96 6124 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
Kojto 112:6f327212ef96 6125 #define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */
Kojto 112:6f327212ef96 6126 #define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */
Kojto 112:6f327212ef96 6127 #define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */
Kojto 112:6f327212ef96 6128 #define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */
Kojto 112:6f327212ef96 6129 #define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */
Kojto 112:6f327212ef96 6130 #define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */
Kojto 112:6f327212ef96 6131
Kojto 112:6f327212ef96 6132 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
Kojto 112:6f327212ef96 6133 #define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */
Kojto 112:6f327212ef96 6134 #define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */
Kojto 112:6f327212ef96 6135 #define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */
Kojto 112:6f327212ef96 6136 #define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */
Kojto 112:6f327212ef96 6137 #define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */
Kojto 112:6f327212ef96 6138 #define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */
Kojto 112:6f327212ef96 6139
Kojto 112:6f327212ef96 6140 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
Kojto 112:6f327212ef96 6141 #define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */
Kojto 112:6f327212ef96 6142 #define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */
Kojto 112:6f327212ef96 6143
Kojto 112:6f327212ef96 6144 /******************* Bit definition for SPDIFRX_CSR register *******************/
Kojto 112:6f327212ef96 6145 #define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */
Kojto 112:6f327212ef96 6146 #define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */
Kojto 112:6f327212ef96 6147 #define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */
Kojto 112:6f327212ef96 6148
Kojto 112:6f327212ef96 6149 /******************* Bit definition for SPDIFRX_DIR register *******************/
Kojto 112:6f327212ef96 6150 #define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */
Kojto 112:6f327212ef96 6151 #define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */
Kojto 112:6f327212ef96 6152
Kojto 112:6f327212ef96 6153
Kojto 112:6f327212ef96 6154 /******************************************************************************/
Kojto 112:6f327212ef96 6155 /* */
Kojto 112:6f327212ef96 6156 /* SD host Interface */
Kojto 112:6f327212ef96 6157 /* */
Kojto 112:6f327212ef96 6158 /******************************************************************************/
Kojto 112:6f327212ef96 6159 /****************** Bit definition for SDIO_POWER register ******************/
Kojto 112:6f327212ef96 6160 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 112:6f327212ef96 6161 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 112:6f327212ef96 6162 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 112:6f327212ef96 6163
Kojto 112:6f327212ef96 6164 /****************** Bit definition for SDIO_CLKCR register ******************/
Kojto 112:6f327212ef96 6165 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
Kojto 112:6f327212ef96 6166 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
Kojto 112:6f327212ef96 6167 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
Kojto 112:6f327212ef96 6168 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
Kojto 112:6f327212ef96 6169
Kojto 112:6f327212ef96 6170 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 112:6f327212ef96 6171 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
Kojto 112:6f327212ef96 6172 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
Kojto 112:6f327212ef96 6173
Kojto 112:6f327212ef96 6174 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
Kojto 112:6f327212ef96 6175 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
Kojto 112:6f327212ef96 6176
Kojto 112:6f327212ef96 6177 /******************* Bit definition for SDIO_ARG register *******************/
Kojto 112:6f327212ef96 6178 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
Kojto 112:6f327212ef96 6179
Kojto 112:6f327212ef96 6180 /******************* Bit definition for SDIO_CMD register *******************/
Kojto 112:6f327212ef96 6181 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
Kojto 112:6f327212ef96 6182
Kojto 112:6f327212ef96 6183 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
Kojto 112:6f327212ef96 6184 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
Kojto 112:6f327212ef96 6185 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
Kojto 112:6f327212ef96 6186
Kojto 112:6f327212ef96 6187 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
Kojto 112:6f327212ef96 6188 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 112:6f327212ef96 6189 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
Kojto 112:6f327212ef96 6190 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
Kojto 112:6f327212ef96 6191
Kojto 112:6f327212ef96 6192 /***************** Bit definition for SDIO_RESPCMD register *****************/
Kojto 112:6f327212ef96 6193 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
Kojto 112:6f327212ef96 6194
Kojto 112:6f327212ef96 6195 /****************** Bit definition for SDIO_RESP0 register ******************/
Kojto 112:6f327212ef96 6196 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 112:6f327212ef96 6197
Kojto 112:6f327212ef96 6198 /****************** Bit definition for SDIO_RESP1 register ******************/
Kojto 112:6f327212ef96 6199 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 112:6f327212ef96 6200
Kojto 112:6f327212ef96 6201 /****************** Bit definition for SDIO_RESP2 register ******************/
Kojto 112:6f327212ef96 6202 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 112:6f327212ef96 6203
Kojto 112:6f327212ef96 6204 /****************** Bit definition for SDIO_RESP3 register ******************/
Kojto 112:6f327212ef96 6205 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 112:6f327212ef96 6206
Kojto 112:6f327212ef96 6207 /****************** Bit definition for SDIO_RESP4 register ******************/
Kojto 112:6f327212ef96 6208 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 112:6f327212ef96 6209
Kojto 112:6f327212ef96 6210 /****************** Bit definition for SDIO_DTIMER register *****************/
Kojto 112:6f327212ef96 6211 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
Kojto 112:6f327212ef96 6212
Kojto 112:6f327212ef96 6213 /****************** Bit definition for SDIO_DLEN register *******************/
Kojto 112:6f327212ef96 6214 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
Kojto 112:6f327212ef96 6215
Kojto 112:6f327212ef96 6216 /****************** Bit definition for SDIO_DCTRL register ******************/
Kojto 112:6f327212ef96 6217 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
Kojto 112:6f327212ef96 6218 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
Kojto 112:6f327212ef96 6219 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
Kojto 112:6f327212ef96 6220 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
Kojto 112:6f327212ef96 6221
Kojto 112:6f327212ef96 6222 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 112:6f327212ef96 6223 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 112:6f327212ef96 6224 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 112:6f327212ef96 6225 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 112:6f327212ef96 6226 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 112:6f327212ef96 6227
Kojto 112:6f327212ef96 6228 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
Kojto 112:6f327212ef96 6229 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
Kojto 112:6f327212ef96 6230 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
Kojto 112:6f327212ef96 6231 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
Kojto 112:6f327212ef96 6232
Kojto 112:6f327212ef96 6233 /****************** Bit definition for SDIO_DCOUNT register *****************/
Kojto 112:6f327212ef96 6234 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
Kojto 112:6f327212ef96 6235
Kojto 112:6f327212ef96 6236 /****************** Bit definition for SDIO_STA register ********************/
Kojto 112:6f327212ef96 6237 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
Kojto 112:6f327212ef96 6238 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
Kojto 112:6f327212ef96 6239 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
Kojto 112:6f327212ef96 6240 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
Kojto 112:6f327212ef96 6241 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
Kojto 112:6f327212ef96 6242 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
Kojto 112:6f327212ef96 6243 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
Kojto 112:6f327212ef96 6244 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
Kojto 112:6f327212ef96 6245 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
Kojto 112:6f327212ef96 6246 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
Kojto 112:6f327212ef96 6247 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
Kojto 112:6f327212ef96 6248 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
Kojto 112:6f327212ef96 6249 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
Kojto 112:6f327212ef96 6250 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 112:6f327212ef96 6251 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 112:6f327212ef96 6252 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
Kojto 112:6f327212ef96 6253 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
Kojto 112:6f327212ef96 6254 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
Kojto 112:6f327212ef96 6255 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
Kojto 112:6f327212ef96 6256 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
Kojto 112:6f327212ef96 6257 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
Kojto 112:6f327212ef96 6258 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
Kojto 112:6f327212ef96 6259
Kojto 112:6f327212ef96 6260 /******************* Bit definition for SDIO_ICR register *******************/
Kojto 112:6f327212ef96 6261 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
Kojto 112:6f327212ef96 6262 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
Kojto 112:6f327212ef96 6263 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
Kojto 112:6f327212ef96 6264 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
Kojto 112:6f327212ef96 6265 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
Kojto 112:6f327212ef96 6266 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
Kojto 112:6f327212ef96 6267 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
Kojto 112:6f327212ef96 6268 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
Kojto 112:6f327212ef96 6269 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
Kojto 112:6f327212ef96 6270 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
Kojto 112:6f327212ef96 6271 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
Kojto 112:6f327212ef96 6272
Kojto 112:6f327212ef96 6273 /****************** Bit definition for SDIO_MASK register *******************/
Kojto 112:6f327212ef96 6274 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
Kojto 112:6f327212ef96 6275 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
Kojto 112:6f327212ef96 6276 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
Kojto 112:6f327212ef96 6277 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
Kojto 112:6f327212ef96 6278 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
Kojto 112:6f327212ef96 6279 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
Kojto 112:6f327212ef96 6280 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
Kojto 112:6f327212ef96 6281 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
Kojto 112:6f327212ef96 6282 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
Kojto 112:6f327212ef96 6283 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
Kojto 112:6f327212ef96 6284 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
Kojto 112:6f327212ef96 6285 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
Kojto 112:6f327212ef96 6286 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
Kojto 112:6f327212ef96 6287 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
Kojto 112:6f327212ef96 6288 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
Kojto 112:6f327212ef96 6289 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
Kojto 112:6f327212ef96 6290 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
Kojto 112:6f327212ef96 6291 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
Kojto 112:6f327212ef96 6292 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
Kojto 112:6f327212ef96 6293 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
Kojto 112:6f327212ef96 6294 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
Kojto 112:6f327212ef96 6295 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
Kojto 112:6f327212ef96 6296
Kojto 112:6f327212ef96 6297 /***************** Bit definition for SDIO_FIFOCNT register *****************/
Kojto 112:6f327212ef96 6298 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
Kojto 112:6f327212ef96 6299
Kojto 112:6f327212ef96 6300 /****************** Bit definition for SDIO_FIFO register *******************/
Kojto 112:6f327212ef96 6301 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
Kojto 112:6f327212ef96 6302
Kojto 112:6f327212ef96 6303 /******************************************************************************/
Kojto 112:6f327212ef96 6304 /* */
Kojto 112:6f327212ef96 6305 /* Serial Peripheral Interface */
Kojto 112:6f327212ef96 6306 /* */
Kojto 112:6f327212ef96 6307 /******************************************************************************/
Kojto 112:6f327212ef96 6308 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 112:6f327212ef96 6309 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
Kojto 112:6f327212ef96 6310 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
Kojto 112:6f327212ef96 6311 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
Kojto 112:6f327212ef96 6312
Kojto 112:6f327212ef96 6313 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
Kojto 112:6f327212ef96 6314 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 112:6f327212ef96 6315 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 112:6f327212ef96 6316 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 112:6f327212ef96 6317
Kojto 112:6f327212ef96 6318 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
Kojto 112:6f327212ef96 6319 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
Kojto 112:6f327212ef96 6320 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
Kojto 112:6f327212ef96 6321 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
Kojto 112:6f327212ef96 6322 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
Kojto 112:6f327212ef96 6323 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
Kojto 112:6f327212ef96 6324 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
Kojto 112:6f327212ef96 6325 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
Kojto 112:6f327212ef96 6326 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
Kojto 112:6f327212ef96 6327 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
Kojto 112:6f327212ef96 6328
Kojto 112:6f327212ef96 6329 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 112:6f327212ef96 6330 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
Kojto 112:6f327212ef96 6331 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
Kojto 112:6f327212ef96 6332 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
Kojto 112:6f327212ef96 6333 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
Kojto 112:6f327212ef96 6334 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
Kojto 112:6f327212ef96 6335 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
Kojto 112:6f327212ef96 6336 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
Kojto 112:6f327212ef96 6337
Kojto 112:6f327212ef96 6338 /******************** Bit definition for SPI_SR register ********************/
Kojto 112:6f327212ef96 6339 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
Kojto 112:6f327212ef96 6340 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
Kojto 112:6f327212ef96 6341 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
Kojto 112:6f327212ef96 6342 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
Kojto 112:6f327212ef96 6343 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
Kojto 112:6f327212ef96 6344 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
Kojto 112:6f327212ef96 6345 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
Kojto 112:6f327212ef96 6346 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
Kojto 112:6f327212ef96 6347 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
Kojto 112:6f327212ef96 6348
Kojto 112:6f327212ef96 6349 /******************** Bit definition for SPI_DR register ********************/
Kojto 112:6f327212ef96 6350 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
Kojto 112:6f327212ef96 6351
Kojto 112:6f327212ef96 6352 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 112:6f327212ef96 6353 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
Kojto 112:6f327212ef96 6354
Kojto 112:6f327212ef96 6355 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 112:6f327212ef96 6356 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
Kojto 112:6f327212ef96 6357
Kojto 112:6f327212ef96 6358 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 112:6f327212ef96 6359 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
Kojto 112:6f327212ef96 6360
Kojto 112:6f327212ef96 6361 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 112:6f327212ef96 6362 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
Kojto 112:6f327212ef96 6363
Kojto 112:6f327212ef96 6364 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 112:6f327212ef96 6365 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 112:6f327212ef96 6366 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 112:6f327212ef96 6367
Kojto 112:6f327212ef96 6368 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
Kojto 112:6f327212ef96 6369
Kojto 112:6f327212ef96 6370 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 112:6f327212ef96 6371 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 6372 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 6373
Kojto 112:6f327212ef96 6374 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
Kojto 112:6f327212ef96 6375
Kojto 112:6f327212ef96 6376 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 112:6f327212ef96 6377 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 112:6f327212ef96 6378 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 112:6f327212ef96 6379
Kojto 112:6f327212ef96 6380 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
Kojto 112:6f327212ef96 6381 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
Kojto 112:6f327212ef96 6382 #define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
Kojto 112:6f327212ef96 6383
Kojto 112:6f327212ef96 6384 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 112:6f327212ef96 6385 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
Kojto 112:6f327212ef96 6386 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
Kojto 112:6f327212ef96 6387 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
Kojto 112:6f327212ef96 6388
Kojto 112:6f327212ef96 6389 /******************************************************************************/
Kojto 112:6f327212ef96 6390 /* */
Kojto 112:6f327212ef96 6391 /* SYSCFG */
Kojto 112:6f327212ef96 6392 /* */
Kojto 112:6f327212ef96 6393 /******************************************************************************/
Kojto 112:6f327212ef96 6394 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 112:6f327212ef96 6395 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
Kojto 112:6f327212ef96 6396 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 6397 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 6398 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 6399
Kojto 112:6f327212ef96 6400 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
Kojto 112:6f327212ef96 6401 #define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
Kojto 112:6f327212ef96 6402
Kojto 112:6f327212ef96 6403 /****************** Bit definition for SYSCFG_PMC register ******************/
Kojto 112:6f327212ef96 6404 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
Kojto 112:6f327212ef96 6405 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
Kojto 112:6f327212ef96 6406 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
Kojto 112:6f327212ef96 6407 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
Kojto 112:6f327212ef96 6408
Kojto 112:6f327212ef96 6409 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 112:6f327212ef96 6410 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
Kojto 112:6f327212ef96 6411 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
Kojto 112:6f327212ef96 6412 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
Kojto 112:6f327212ef96 6413 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
Kojto 112:6f327212ef96 6414 /**
Kojto 112:6f327212ef96 6415 * @brief EXTI0 configuration
Kojto 112:6f327212ef96 6416 */
Kojto 112:6f327212ef96 6417 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
Kojto 112:6f327212ef96 6418 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
Kojto 112:6f327212ef96 6419 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
Kojto 112:6f327212ef96 6420 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
Kojto 112:6f327212ef96 6421 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
Kojto 112:6f327212ef96 6422 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
Kojto 112:6f327212ef96 6423 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
Kojto 112:6f327212ef96 6424 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
Kojto 112:6f327212ef96 6425 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
Kojto 112:6f327212ef96 6426 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
Kojto 112:6f327212ef96 6427 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
Kojto 112:6f327212ef96 6428
Kojto 112:6f327212ef96 6429 /**
Kojto 112:6f327212ef96 6430 * @brief EXTI1 configuration
Kojto 112:6f327212ef96 6431 */
Kojto 112:6f327212ef96 6432 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
Kojto 112:6f327212ef96 6433 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
Kojto 112:6f327212ef96 6434 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
Kojto 112:6f327212ef96 6435 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
Kojto 112:6f327212ef96 6436 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
Kojto 112:6f327212ef96 6437 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
Kojto 112:6f327212ef96 6438 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
Kojto 112:6f327212ef96 6439 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
Kojto 112:6f327212ef96 6440 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
Kojto 112:6f327212ef96 6441 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
Kojto 112:6f327212ef96 6442 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
Kojto 112:6f327212ef96 6443
Kojto 112:6f327212ef96 6444
Kojto 112:6f327212ef96 6445 /**
Kojto 112:6f327212ef96 6446 * @brief EXTI2 configuration
Kojto 112:6f327212ef96 6447 */
Kojto 112:6f327212ef96 6448 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
Kojto 112:6f327212ef96 6449 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
Kojto 112:6f327212ef96 6450 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
Kojto 112:6f327212ef96 6451 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
Kojto 112:6f327212ef96 6452 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
Kojto 112:6f327212ef96 6453 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
Kojto 112:6f327212ef96 6454 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
Kojto 112:6f327212ef96 6455 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
Kojto 112:6f327212ef96 6456 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
Kojto 112:6f327212ef96 6457 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
Kojto 112:6f327212ef96 6458 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
Kojto 112:6f327212ef96 6459
Kojto 112:6f327212ef96 6460
Kojto 112:6f327212ef96 6461 /**
Kojto 112:6f327212ef96 6462 * @brief EXTI3 configuration
Kojto 112:6f327212ef96 6463 */
Kojto 112:6f327212ef96 6464 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
Kojto 112:6f327212ef96 6465 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
Kojto 112:6f327212ef96 6466 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
Kojto 112:6f327212ef96 6467 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
Kojto 112:6f327212ef96 6468 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
Kojto 112:6f327212ef96 6469 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
Kojto 112:6f327212ef96 6470 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
Kojto 112:6f327212ef96 6471 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
Kojto 112:6f327212ef96 6472 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
Kojto 112:6f327212ef96 6473 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
Kojto 112:6f327212ef96 6474 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
Kojto 112:6f327212ef96 6475
Kojto 112:6f327212ef96 6476
Kojto 112:6f327212ef96 6477 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 112:6f327212ef96 6478 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
Kojto 112:6f327212ef96 6479 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
Kojto 112:6f327212ef96 6480 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
Kojto 112:6f327212ef96 6481 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
Kojto 112:6f327212ef96 6482 /**
Kojto 112:6f327212ef96 6483 * @brief EXTI4 configuration
Kojto 112:6f327212ef96 6484 */
Kojto 112:6f327212ef96 6485 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
Kojto 112:6f327212ef96 6486 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
Kojto 112:6f327212ef96 6487 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
Kojto 112:6f327212ef96 6488 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
Kojto 112:6f327212ef96 6489 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
Kojto 112:6f327212ef96 6490 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
Kojto 112:6f327212ef96 6491 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
Kojto 112:6f327212ef96 6492 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
Kojto 112:6f327212ef96 6493 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
Kojto 112:6f327212ef96 6494 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
Kojto 112:6f327212ef96 6495 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
Kojto 112:6f327212ef96 6496
Kojto 112:6f327212ef96 6497 /**
Kojto 112:6f327212ef96 6498 * @brief EXTI5 configuration
Kojto 112:6f327212ef96 6499 */
Kojto 112:6f327212ef96 6500 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
Kojto 112:6f327212ef96 6501 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
Kojto 112:6f327212ef96 6502 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
Kojto 112:6f327212ef96 6503 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
Kojto 112:6f327212ef96 6504 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
Kojto 112:6f327212ef96 6505 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
Kojto 112:6f327212ef96 6506 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
Kojto 112:6f327212ef96 6507 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
Kojto 112:6f327212ef96 6508 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
Kojto 112:6f327212ef96 6509 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
Kojto 112:6f327212ef96 6510 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
Kojto 112:6f327212ef96 6511
Kojto 112:6f327212ef96 6512 /**
Kojto 112:6f327212ef96 6513 * @brief EXTI6 configuration
Kojto 112:6f327212ef96 6514 */
Kojto 112:6f327212ef96 6515 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
Kojto 112:6f327212ef96 6516 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
Kojto 112:6f327212ef96 6517 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
Kojto 112:6f327212ef96 6518 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
Kojto 112:6f327212ef96 6519 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
Kojto 112:6f327212ef96 6520 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
Kojto 112:6f327212ef96 6521 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
Kojto 112:6f327212ef96 6522 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
Kojto 112:6f327212ef96 6523 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
Kojto 112:6f327212ef96 6524 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
Kojto 112:6f327212ef96 6525 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
Kojto 112:6f327212ef96 6526
Kojto 112:6f327212ef96 6527
Kojto 112:6f327212ef96 6528 /**
Kojto 112:6f327212ef96 6529 * @brief EXTI7 configuration
Kojto 112:6f327212ef96 6530 */
Kojto 112:6f327212ef96 6531 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
Kojto 112:6f327212ef96 6532 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
Kojto 112:6f327212ef96 6533 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
Kojto 112:6f327212ef96 6534 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
Kojto 112:6f327212ef96 6535 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
Kojto 112:6f327212ef96 6536 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
Kojto 112:6f327212ef96 6537 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
Kojto 112:6f327212ef96 6538 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
Kojto 112:6f327212ef96 6539 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
Kojto 112:6f327212ef96 6540 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
Kojto 112:6f327212ef96 6541 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
Kojto 112:6f327212ef96 6542
Kojto 112:6f327212ef96 6543 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 112:6f327212ef96 6544 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
Kojto 112:6f327212ef96 6545 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
Kojto 112:6f327212ef96 6546 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
Kojto 112:6f327212ef96 6547 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
Kojto 112:6f327212ef96 6548
Kojto 112:6f327212ef96 6549 /**
Kojto 112:6f327212ef96 6550 * @brief EXTI8 configuration
Kojto 112:6f327212ef96 6551 */
Kojto 112:6f327212ef96 6552 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
Kojto 112:6f327212ef96 6553 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
Kojto 112:6f327212ef96 6554 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
Kojto 112:6f327212ef96 6555 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
Kojto 112:6f327212ef96 6556 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
Kojto 112:6f327212ef96 6557 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
Kojto 112:6f327212ef96 6558 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
Kojto 112:6f327212ef96 6559 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
Kojto 112:6f327212ef96 6560 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
Kojto 112:6f327212ef96 6561 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
Kojto 112:6f327212ef96 6562
Kojto 112:6f327212ef96 6563 /**
Kojto 112:6f327212ef96 6564 * @brief EXTI9 configuration
Kojto 112:6f327212ef96 6565 */
Kojto 112:6f327212ef96 6566 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
Kojto 112:6f327212ef96 6567 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
Kojto 112:6f327212ef96 6568 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
Kojto 112:6f327212ef96 6569 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
Kojto 112:6f327212ef96 6570 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
Kojto 112:6f327212ef96 6571 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
Kojto 112:6f327212ef96 6572 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
Kojto 112:6f327212ef96 6573 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
Kojto 112:6f327212ef96 6574 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
Kojto 112:6f327212ef96 6575 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
Kojto 112:6f327212ef96 6576
Kojto 112:6f327212ef96 6577
Kojto 112:6f327212ef96 6578 /**
Kojto 112:6f327212ef96 6579 * @brief EXTI10 configuration
Kojto 112:6f327212ef96 6580 */
Kojto 112:6f327212ef96 6581 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
Kojto 112:6f327212ef96 6582 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
Kojto 112:6f327212ef96 6583 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
Kojto 112:6f327212ef96 6584 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
Kojto 112:6f327212ef96 6585 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
Kojto 112:6f327212ef96 6586 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
Kojto 112:6f327212ef96 6587 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
Kojto 112:6f327212ef96 6588 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
Kojto 112:6f327212ef96 6589 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
Kojto 112:6f327212ef96 6590 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
Kojto 112:6f327212ef96 6591
Kojto 112:6f327212ef96 6592
Kojto 112:6f327212ef96 6593 /**
Kojto 112:6f327212ef96 6594 * @brief EXTI11 configuration
Kojto 112:6f327212ef96 6595 */
Kojto 112:6f327212ef96 6596 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
Kojto 112:6f327212ef96 6597 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
Kojto 112:6f327212ef96 6598 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
Kojto 112:6f327212ef96 6599 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
Kojto 112:6f327212ef96 6600 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
Kojto 112:6f327212ef96 6601 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
Kojto 112:6f327212ef96 6602 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
Kojto 112:6f327212ef96 6603 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
Kojto 112:6f327212ef96 6604 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
Kojto 112:6f327212ef96 6605 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
Kojto 112:6f327212ef96 6606
Kojto 112:6f327212ef96 6607
Kojto 112:6f327212ef96 6608 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 112:6f327212ef96 6609 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
Kojto 112:6f327212ef96 6610 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
Kojto 112:6f327212ef96 6611 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
Kojto 112:6f327212ef96 6612 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
Kojto 112:6f327212ef96 6613 /**
Kojto 112:6f327212ef96 6614 * @brief EXTI12 configuration
Kojto 112:6f327212ef96 6615 */
Kojto 112:6f327212ef96 6616 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
Kojto 112:6f327212ef96 6617 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
Kojto 112:6f327212ef96 6618 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
Kojto 112:6f327212ef96 6619 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
Kojto 112:6f327212ef96 6620 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
Kojto 112:6f327212ef96 6621 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
Kojto 112:6f327212ef96 6622 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
Kojto 112:6f327212ef96 6623 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
Kojto 112:6f327212ef96 6624 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
Kojto 112:6f327212ef96 6625 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
Kojto 112:6f327212ef96 6626
Kojto 112:6f327212ef96 6627
Kojto 112:6f327212ef96 6628 /**
Kojto 112:6f327212ef96 6629 * @brief EXTI13 configuration
Kojto 112:6f327212ef96 6630 */
Kojto 112:6f327212ef96 6631 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
Kojto 112:6f327212ef96 6632 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
Kojto 112:6f327212ef96 6633 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
Kojto 112:6f327212ef96 6634 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
Kojto 112:6f327212ef96 6635 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
Kojto 112:6f327212ef96 6636 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
Kojto 112:6f327212ef96 6637 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
Kojto 112:6f327212ef96 6638 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
Kojto 112:6f327212ef96 6639 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
Kojto 112:6f327212ef96 6640 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
Kojto 112:6f327212ef96 6641
Kojto 112:6f327212ef96 6642
Kojto 112:6f327212ef96 6643 /**
Kojto 112:6f327212ef96 6644 * @brief EXTI14 configuration
Kojto 112:6f327212ef96 6645 */
Kojto 112:6f327212ef96 6646 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
Kojto 112:6f327212ef96 6647 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
Kojto 112:6f327212ef96 6648 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
Kojto 112:6f327212ef96 6649 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
Kojto 112:6f327212ef96 6650 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
Kojto 112:6f327212ef96 6651 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
Kojto 112:6f327212ef96 6652 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
Kojto 112:6f327212ef96 6653 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
Kojto 112:6f327212ef96 6654 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
Kojto 112:6f327212ef96 6655 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
Kojto 112:6f327212ef96 6656
Kojto 112:6f327212ef96 6657
Kojto 112:6f327212ef96 6658 /**
Kojto 112:6f327212ef96 6659 * @brief EXTI15 configuration
Kojto 112:6f327212ef96 6660 */
Kojto 112:6f327212ef96 6661 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
Kojto 112:6f327212ef96 6662 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
Kojto 112:6f327212ef96 6663 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
Kojto 112:6f327212ef96 6664 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
Kojto 112:6f327212ef96 6665 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
Kojto 112:6f327212ef96 6666 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
Kojto 112:6f327212ef96 6667 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
Kojto 112:6f327212ef96 6668 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
Kojto 112:6f327212ef96 6669 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
Kojto 112:6f327212ef96 6670 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
Kojto 112:6f327212ef96 6671
Kojto 112:6f327212ef96 6672 /****************** Bit definition for SYSCFG_CMPCR register ****************/
Kojto 112:6f327212ef96 6673 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
Kojto 112:6f327212ef96 6674 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
Kojto 112:6f327212ef96 6675
Kojto 112:6f327212ef96 6676 /****************** Bit definition for SYSCFG_CFGR register ****************/
Kojto 112:6f327212ef96 6677 #define SYSCFG_CFGR_FMPI2C1_SCL ((uint32_t)0x00000001) /*!<FM+ drive capability for FMPI2C1_SCL pin */
Kojto 112:6f327212ef96 6678 #define SYSCFG_CFGR_FMPI2C1_SDA ((uint32_t)0x00000002) /*!<FM+ drive capability for FMPI2C1_SDA pin */
Kojto 112:6f327212ef96 6679
Kojto 112:6f327212ef96 6680 /******************************************************************************/
Kojto 112:6f327212ef96 6681 /* */
Kojto 112:6f327212ef96 6682 /* TIM */
Kojto 112:6f327212ef96 6683 /* */
Kojto 112:6f327212ef96 6684 /******************************************************************************/
Kojto 112:6f327212ef96 6685 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 112:6f327212ef96 6686 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
Kojto 112:6f327212ef96 6687 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
Kojto 112:6f327212ef96 6688 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
Kojto 112:6f327212ef96 6689 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
Kojto 112:6f327212ef96 6690 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
Kojto 112:6f327212ef96 6691
Kojto 112:6f327212ef96 6692 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 112:6f327212ef96 6693 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
Kojto 112:6f327212ef96 6694 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
Kojto 112:6f327212ef96 6695
Kojto 112:6f327212ef96 6696 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
Kojto 112:6f327212ef96 6697
Kojto 112:6f327212ef96 6698 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
Kojto 112:6f327212ef96 6699 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 112:6f327212ef96 6700 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 112:6f327212ef96 6701
Kojto 112:6f327212ef96 6702 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 112:6f327212ef96 6703 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
Kojto 112:6f327212ef96 6704 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
Kojto 112:6f327212ef96 6705 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
Kojto 112:6f327212ef96 6706
Kojto 112:6f327212ef96 6707 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 112:6f327212ef96 6708 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 112:6f327212ef96 6709 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 112:6f327212ef96 6710 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 112:6f327212ef96 6711
Kojto 112:6f327212ef96 6712 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
Kojto 112:6f327212ef96 6713 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
Kojto 112:6f327212ef96 6714 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
Kojto 112:6f327212ef96 6715 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
Kojto 112:6f327212ef96 6716 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
Kojto 112:6f327212ef96 6717 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
Kojto 112:6f327212ef96 6718 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
Kojto 112:6f327212ef96 6719 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
Kojto 112:6f327212ef96 6720
Kojto 112:6f327212ef96 6721 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 112:6f327212ef96 6722 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 112:6f327212ef96 6723 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 112:6f327212ef96 6724 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 112:6f327212ef96 6725 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 112:6f327212ef96 6726
Kojto 112:6f327212ef96 6727 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 112:6f327212ef96 6728 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 112:6f327212ef96 6729 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 112:6f327212ef96 6730 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 112:6f327212ef96 6731
Kojto 112:6f327212ef96 6732 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
Kojto 112:6f327212ef96 6733
Kojto 112:6f327212ef96 6734 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 112:6f327212ef96 6735 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 112:6f327212ef96 6736 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 112:6f327212ef96 6737 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 112:6f327212ef96 6738 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 112:6f327212ef96 6739
Kojto 112:6f327212ef96 6740 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 112:6f327212ef96 6741 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 112:6f327212ef96 6742 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 112:6f327212ef96 6743
Kojto 112:6f327212ef96 6744 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
Kojto 112:6f327212ef96 6745 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
Kojto 112:6f327212ef96 6746
Kojto 112:6f327212ef96 6747 /******************* Bit definition for TIM_DIER register *******************/
Kojto 112:6f327212ef96 6748 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
Kojto 112:6f327212ef96 6749 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
Kojto 112:6f327212ef96 6750 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
Kojto 112:6f327212ef96 6751 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
Kojto 112:6f327212ef96 6752 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
Kojto 112:6f327212ef96 6753 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
Kojto 112:6f327212ef96 6754 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
Kojto 112:6f327212ef96 6755 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
Kojto 112:6f327212ef96 6756 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
Kojto 112:6f327212ef96 6757 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
Kojto 112:6f327212ef96 6758 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
Kojto 112:6f327212ef96 6759 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
Kojto 112:6f327212ef96 6760 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
Kojto 112:6f327212ef96 6761 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
Kojto 112:6f327212ef96 6762 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
Kojto 112:6f327212ef96 6763
Kojto 112:6f327212ef96 6764 /******************** Bit definition for TIM_SR register ********************/
Kojto 112:6f327212ef96 6765 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
Kojto 112:6f327212ef96 6766 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 112:6f327212ef96 6767 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 112:6f327212ef96 6768 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 112:6f327212ef96 6769 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 112:6f327212ef96 6770 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
Kojto 112:6f327212ef96 6771 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
Kojto 112:6f327212ef96 6772 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
Kojto 112:6f327212ef96 6773 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 112:6f327212ef96 6774 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 112:6f327212ef96 6775 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 112:6f327212ef96 6776 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 112:6f327212ef96 6777
Kojto 112:6f327212ef96 6778 /******************* Bit definition for TIM_EGR register ********************/
Kojto 112:6f327212ef96 6779 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
Kojto 112:6f327212ef96 6780 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
Kojto 112:6f327212ef96 6781 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
Kojto 112:6f327212ef96 6782 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
Kojto 112:6f327212ef96 6783 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
Kojto 112:6f327212ef96 6784 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
Kojto 112:6f327212ef96 6785 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
Kojto 112:6f327212ef96 6786 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
Kojto 112:6f327212ef96 6787
Kojto 112:6f327212ef96 6788 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 112:6f327212ef96 6789 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 112:6f327212ef96 6790 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 112:6f327212ef96 6791 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 112:6f327212ef96 6792
Kojto 112:6f327212ef96 6793 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
Kojto 112:6f327212ef96 6794 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
Kojto 112:6f327212ef96 6795
Kojto 112:6f327212ef96 6796 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 112:6f327212ef96 6797 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 112:6f327212ef96 6798 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 112:6f327212ef96 6799 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 112:6f327212ef96 6800
Kojto 112:6f327212ef96 6801 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
Kojto 112:6f327212ef96 6802
Kojto 112:6f327212ef96 6803 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 112:6f327212ef96 6804 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 112:6f327212ef96 6805 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 112:6f327212ef96 6806
Kojto 112:6f327212ef96 6807 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
Kojto 112:6f327212ef96 6808 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
Kojto 112:6f327212ef96 6809
Kojto 112:6f327212ef96 6810 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 112:6f327212ef96 6811 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 112:6f327212ef96 6812 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 112:6f327212ef96 6813 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 112:6f327212ef96 6814
Kojto 112:6f327212ef96 6815 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
Kojto 112:6f327212ef96 6816
Kojto 112:6f327212ef96 6817 /*----------------------------------------------------------------------------*/
Kojto 112:6f327212ef96 6818
Kojto 112:6f327212ef96 6819 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 112:6f327212ef96 6820 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 112:6f327212ef96 6821 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 112:6f327212ef96 6822
Kojto 112:6f327212ef96 6823 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 112:6f327212ef96 6824 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 112:6f327212ef96 6825 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 112:6f327212ef96 6826 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 112:6f327212ef96 6827 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 112:6f327212ef96 6828
Kojto 112:6f327212ef96 6829 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 112:6f327212ef96 6830 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 112:6f327212ef96 6831 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 112:6f327212ef96 6832
Kojto 112:6f327212ef96 6833 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 112:6f327212ef96 6834 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 112:6f327212ef96 6835 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 112:6f327212ef96 6836 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 112:6f327212ef96 6837 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 112:6f327212ef96 6838
Kojto 112:6f327212ef96 6839 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 112:6f327212ef96 6840 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 112:6f327212ef96 6841 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 112:6f327212ef96 6842 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 112:6f327212ef96 6843
Kojto 112:6f327212ef96 6844 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
Kojto 112:6f327212ef96 6845 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
Kojto 112:6f327212ef96 6846
Kojto 112:6f327212ef96 6847 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 112:6f327212ef96 6848 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 112:6f327212ef96 6849 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 112:6f327212ef96 6850 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 112:6f327212ef96 6851
Kojto 112:6f327212ef96 6852 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
Kojto 112:6f327212ef96 6853
Kojto 112:6f327212ef96 6854 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 112:6f327212ef96 6855 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 112:6f327212ef96 6856 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 112:6f327212ef96 6857
Kojto 112:6f327212ef96 6858 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
Kojto 112:6f327212ef96 6859 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
Kojto 112:6f327212ef96 6860
Kojto 112:6f327212ef96 6861 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 112:6f327212ef96 6862 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 112:6f327212ef96 6863 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 112:6f327212ef96 6864 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 112:6f327212ef96 6865
Kojto 112:6f327212ef96 6866 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
Kojto 112:6f327212ef96 6867
Kojto 112:6f327212ef96 6868 /*----------------------------------------------------------------------------*/
Kojto 112:6f327212ef96 6869
Kojto 112:6f327212ef96 6870 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 112:6f327212ef96 6871 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 112:6f327212ef96 6872 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 112:6f327212ef96 6873
Kojto 112:6f327212ef96 6874 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 112:6f327212ef96 6875 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 112:6f327212ef96 6876 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 112:6f327212ef96 6877 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 112:6f327212ef96 6878 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 112:6f327212ef96 6879
Kojto 112:6f327212ef96 6880 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 112:6f327212ef96 6881 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 112:6f327212ef96 6882 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 112:6f327212ef96 6883
Kojto 112:6f327212ef96 6884 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 112:6f327212ef96 6885 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 112:6f327212ef96 6886 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 112:6f327212ef96 6887 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 112:6f327212ef96 6888 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 112:6f327212ef96 6889
Kojto 112:6f327212ef96 6890 /******************* Bit definition for TIM_CCER register *******************/
Kojto 112:6f327212ef96 6891 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
Kojto 112:6f327212ef96 6892 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
Kojto 112:6f327212ef96 6893 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 112:6f327212ef96 6894 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 112:6f327212ef96 6895 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
Kojto 112:6f327212ef96 6896 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
Kojto 112:6f327212ef96 6897 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 112:6f327212ef96 6898 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 112:6f327212ef96 6899 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
Kojto 112:6f327212ef96 6900 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
Kojto 112:6f327212ef96 6901 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 112:6f327212ef96 6902 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 112:6f327212ef96 6903 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
Kojto 112:6f327212ef96 6904 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
Kojto 112:6f327212ef96 6905 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 112:6f327212ef96 6906
Kojto 112:6f327212ef96 6907 /******************* Bit definition for TIM_CNT register ********************/
Kojto 112:6f327212ef96 6908 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
Kojto 112:6f327212ef96 6909
Kojto 112:6f327212ef96 6910 /******************* Bit definition for TIM_PSC register ********************/
Kojto 112:6f327212ef96 6911 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
Kojto 112:6f327212ef96 6912
Kojto 112:6f327212ef96 6913 /******************* Bit definition for TIM_ARR register ********************/
Kojto 112:6f327212ef96 6914 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
Kojto 112:6f327212ef96 6915
Kojto 112:6f327212ef96 6916 /******************* Bit definition for TIM_RCR register ********************/
Kojto 112:6f327212ef96 6917 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
Kojto 112:6f327212ef96 6918
Kojto 112:6f327212ef96 6919 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 112:6f327212ef96 6920 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
Kojto 112:6f327212ef96 6921
Kojto 112:6f327212ef96 6922 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 112:6f327212ef96 6923 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
Kojto 112:6f327212ef96 6924
Kojto 112:6f327212ef96 6925 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 112:6f327212ef96 6926 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
Kojto 112:6f327212ef96 6927
Kojto 112:6f327212ef96 6928 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 112:6f327212ef96 6929 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
Kojto 112:6f327212ef96 6930
Kojto 112:6f327212ef96 6931 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 112:6f327212ef96 6932 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 112:6f327212ef96 6933 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 112:6f327212ef96 6934 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 112:6f327212ef96 6935 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 112:6f327212ef96 6936 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 112:6f327212ef96 6937 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 112:6f327212ef96 6938 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 112:6f327212ef96 6939 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 112:6f327212ef96 6940 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
Kojto 112:6f327212ef96 6941
Kojto 112:6f327212ef96 6942 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 112:6f327212ef96 6943 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 112:6f327212ef96 6944 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 112:6f327212ef96 6945
Kojto 112:6f327212ef96 6946 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
Kojto 112:6f327212ef96 6947 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
Kojto 112:6f327212ef96 6948 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
Kojto 112:6f327212ef96 6949 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
Kojto 112:6f327212ef96 6950 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
Kojto 112:6f327212ef96 6951 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
Kojto 112:6f327212ef96 6952
Kojto 112:6f327212ef96 6953 /******************* Bit definition for TIM_DCR register ********************/
Kojto 112:6f327212ef96 6954 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 112:6f327212ef96 6955 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 112:6f327212ef96 6956 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 112:6f327212ef96 6957 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 112:6f327212ef96 6958 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 112:6f327212ef96 6959 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 112:6f327212ef96 6960
Kojto 112:6f327212ef96 6961 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 112:6f327212ef96 6962 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 112:6f327212ef96 6963 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 112:6f327212ef96 6964 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 112:6f327212ef96 6965 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 112:6f327212ef96 6966 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
Kojto 112:6f327212ef96 6967
Kojto 112:6f327212ef96 6968 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 112:6f327212ef96 6969 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
Kojto 112:6f327212ef96 6970
Kojto 112:6f327212ef96 6971 /******************* Bit definition for TIM_OR register *********************/
Kojto 112:6f327212ef96 6972 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
Kojto 112:6f327212ef96 6973 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
Kojto 112:6f327212ef96 6974 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
Kojto 112:6f327212ef96 6975 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
Kojto 112:6f327212ef96 6976 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 112:6f327212ef96 6977 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 112:6f327212ef96 6978
Kojto 112:6f327212ef96 6979
Kojto 112:6f327212ef96 6980 /******************************************************************************/
Kojto 112:6f327212ef96 6981 /* */
Kojto 112:6f327212ef96 6982 /* Universal Synchronous Asynchronous Receiver Transmitter */
Kojto 112:6f327212ef96 6983 /* */
Kojto 112:6f327212ef96 6984 /******************************************************************************/
Kojto 112:6f327212ef96 6985 /******************* Bit definition for USART_SR register *******************/
Kojto 112:6f327212ef96 6986 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
Kojto 112:6f327212ef96 6987 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
Kojto 112:6f327212ef96 6988 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
Kojto 112:6f327212ef96 6989 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
Kojto 112:6f327212ef96 6990 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
Kojto 112:6f327212ef96 6991 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
Kojto 112:6f327212ef96 6992 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
Kojto 112:6f327212ef96 6993 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
Kojto 112:6f327212ef96 6994 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
Kojto 112:6f327212ef96 6995 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
Kojto 112:6f327212ef96 6996
Kojto 112:6f327212ef96 6997 /******************* Bit definition for USART_DR register *******************/
Kojto 112:6f327212ef96 6998 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
Kojto 112:6f327212ef96 6999
Kojto 112:6f327212ef96 7000 /****************** Bit definition for USART_BRR register *******************/
Kojto 112:6f327212ef96 7001 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
Kojto 112:6f327212ef96 7002 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
Kojto 112:6f327212ef96 7003
Kojto 112:6f327212ef96 7004 /****************** Bit definition for USART_CR1 register *******************/
Kojto 112:6f327212ef96 7005 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
Kojto 112:6f327212ef96 7006 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
Kojto 112:6f327212ef96 7007 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
Kojto 112:6f327212ef96 7008 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
Kojto 112:6f327212ef96 7009 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
Kojto 112:6f327212ef96 7010 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
Kojto 112:6f327212ef96 7011 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
Kojto 112:6f327212ef96 7012 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
Kojto 112:6f327212ef96 7013 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
Kojto 112:6f327212ef96 7014 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
Kojto 112:6f327212ef96 7015 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
Kojto 112:6f327212ef96 7016 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
Kojto 112:6f327212ef96 7017 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
Kojto 112:6f327212ef96 7018 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
Kojto 112:6f327212ef96 7019 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
Kojto 112:6f327212ef96 7020
Kojto 112:6f327212ef96 7021 /****************** Bit definition for USART_CR2 register *******************/
Kojto 112:6f327212ef96 7022 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
Kojto 112:6f327212ef96 7023 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
Kojto 112:6f327212ef96 7024 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
Kojto 112:6f327212ef96 7025 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
Kojto 112:6f327212ef96 7026 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
Kojto 112:6f327212ef96 7027 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
Kojto 112:6f327212ef96 7028 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
Kojto 112:6f327212ef96 7029
Kojto 112:6f327212ef96 7030 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
Kojto 112:6f327212ef96 7031 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7032 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7033
Kojto 112:6f327212ef96 7034 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
Kojto 112:6f327212ef96 7035
Kojto 112:6f327212ef96 7036 /****************** Bit definition for USART_CR3 register *******************/
Kojto 112:6f327212ef96 7037 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
Kojto 112:6f327212ef96 7038 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
Kojto 112:6f327212ef96 7039 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
Kojto 112:6f327212ef96 7040 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
Kojto 112:6f327212ef96 7041 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
Kojto 112:6f327212ef96 7042 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
Kojto 112:6f327212ef96 7043 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
Kojto 112:6f327212ef96 7044 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
Kojto 112:6f327212ef96 7045 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
Kojto 112:6f327212ef96 7046 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
Kojto 112:6f327212ef96 7047 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
Kojto 112:6f327212ef96 7048 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
Kojto 112:6f327212ef96 7049
Kojto 112:6f327212ef96 7050 /****************** Bit definition for USART_GTPR register ******************/
Kojto 112:6f327212ef96 7051 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
Kojto 112:6f327212ef96 7052 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7053 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7054 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 112:6f327212ef96 7055 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 112:6f327212ef96 7056 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 112:6f327212ef96 7057 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 112:6f327212ef96 7058 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 112:6f327212ef96 7059 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
Kojto 112:6f327212ef96 7060
Kojto 112:6f327212ef96 7061 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
Kojto 112:6f327212ef96 7062
Kojto 112:6f327212ef96 7063 /******************************************************************************/
Kojto 112:6f327212ef96 7064 /* */
Kojto 112:6f327212ef96 7065 /* Window WATCHDOG */
Kojto 112:6f327212ef96 7066 /* */
Kojto 112:6f327212ef96 7067 /******************************************************************************/
Kojto 112:6f327212ef96 7068 /******************* Bit definition for WWDG_CR register ********************/
Kojto 112:6f327212ef96 7069 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 112:6f327212ef96 7070 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 112:6f327212ef96 7071 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 112:6f327212ef96 7072 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 112:6f327212ef96 7073 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
Kojto 112:6f327212ef96 7074 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
Kojto 112:6f327212ef96 7075 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
Kojto 112:6f327212ef96 7076 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
Kojto 112:6f327212ef96 7077
Kojto 112:6f327212ef96 7078 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Kojto 112:6f327212ef96 7079
Kojto 112:6f327212ef96 7080 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 112:6f327212ef96 7081 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 112:6f327212ef96 7082 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7083 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7084 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 112:6f327212ef96 7085 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 112:6f327212ef96 7086 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 112:6f327212ef96 7087 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 112:6f327212ef96 7088 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 112:6f327212ef96 7089
Kojto 112:6f327212ef96 7090 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 112:6f327212ef96 7091 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
Kojto 112:6f327212ef96 7092 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
Kojto 112:6f327212ef96 7093
Kojto 112:6f327212ef96 7094 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Kojto 112:6f327212ef96 7095
Kojto 112:6f327212ef96 7096 /******************* Bit definition for WWDG_SR register ********************/
Kojto 112:6f327212ef96 7097 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Kojto 112:6f327212ef96 7098
Kojto 112:6f327212ef96 7099
Kojto 112:6f327212ef96 7100 /******************************************************************************/
Kojto 112:6f327212ef96 7101 /* */
Kojto 112:6f327212ef96 7102 /* DBG */
Kojto 112:6f327212ef96 7103 /* */
Kojto 112:6f327212ef96 7104 /******************************************************************************/
Kojto 112:6f327212ef96 7105 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 112:6f327212ef96 7106 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
Kojto 112:6f327212ef96 7107 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
Kojto 112:6f327212ef96 7108
Kojto 112:6f327212ef96 7109 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 112:6f327212ef96 7110 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 7111 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 7112 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 7113 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 7114
Kojto 112:6f327212ef96 7115 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
Kojto 112:6f327212ef96 7116 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
Kojto 112:6f327212ef96 7117 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
Kojto 112:6f327212ef96 7118
Kojto 112:6f327212ef96 7119 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 112:6f327212ef96 7120 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 7121 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 7122 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
Kojto 112:6f327212ef96 7123 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
Kojto 112:6f327212ef96 7124 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
Kojto 112:6f327212ef96 7125 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
Kojto 112:6f327212ef96 7126 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
Kojto 112:6f327212ef96 7127 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
Kojto 112:6f327212ef96 7128 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
Kojto 112:6f327212ef96 7129 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
Kojto 112:6f327212ef96 7130 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
Kojto 112:6f327212ef96 7131 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
Kojto 112:6f327212ef96 7132 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
Kojto 112:6f327212ef96 7133 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
Kojto 112:6f327212ef96 7134 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
Kojto 112:6f327212ef96 7135 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
Kojto 112:6f327212ef96 7136 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
Kojto 112:6f327212ef96 7137 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
Kojto 112:6f327212ef96 7138 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
Kojto 112:6f327212ef96 7139
Kojto 112:6f327212ef96 7140 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 112:6f327212ef96 7141 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
Kojto 112:6f327212ef96 7142 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
Kojto 112:6f327212ef96 7143 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
Kojto 112:6f327212ef96 7144 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
Kojto 112:6f327212ef96 7145 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
Kojto 112:6f327212ef96 7146
Kojto 112:6f327212ef96 7147
Kojto 112:6f327212ef96 7148 /******************************************************************************/
Kojto 112:6f327212ef96 7149 /* */
Kojto 112:6f327212ef96 7150 /* USB_OTG */
Kojto 112:6f327212ef96 7151 /* */
Kojto 112:6f327212ef96 7152 /******************************************************************************/
Kojto 112:6f327212ef96 7153 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
Kojto 112:6f327212ef96 7154 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
Kojto 112:6f327212ef96 7155 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
Kojto 112:6f327212ef96 7156 #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
Kojto 112:6f327212ef96 7157 #define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
Kojto 112:6f327212ef96 7158 #define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
Kojto 112:6f327212ef96 7159 #define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
Kojto 112:6f327212ef96 7160 #define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
Kojto 112:6f327212ef96 7161 #define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
Kojto 112:6f327212ef96 7162 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
Kojto 112:6f327212ef96 7163 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
Kojto 112:6f327212ef96 7164 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
Kojto 112:6f327212ef96 7165 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
Kojto 112:6f327212ef96 7166 #define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
Kojto 112:6f327212ef96 7167 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
Kojto 112:6f327212ef96 7168 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
Kojto 112:6f327212ef96 7169 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
Kojto 112:6f327212ef96 7170 #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
Kojto 112:6f327212ef96 7171 #define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
Kojto 112:6f327212ef96 7172
Kojto 112:6f327212ef96 7173 /******************** Bit definition forUSB_OTG_HCFG register ********************/
Kojto 112:6f327212ef96 7174
Kojto 112:6f327212ef96 7175 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
Kojto 112:6f327212ef96 7176 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7177 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7178 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
Kojto 112:6f327212ef96 7179
Kojto 112:6f327212ef96 7180 /******************** Bit definition forUSB_OTG_DCFG register ********************/
Kojto 112:6f327212ef96 7181
Kojto 112:6f327212ef96 7182 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
Kojto 112:6f327212ef96 7183 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7184 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7185 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
Kojto 112:6f327212ef96 7186
Kojto 112:6f327212ef96 7187 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
Kojto 112:6f327212ef96 7188 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 7189 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 7190 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 7191 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 112:6f327212ef96 7192 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
Kojto 112:6f327212ef96 7193 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
Kojto 112:6f327212ef96 7194 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
Kojto 112:6f327212ef96 7195
Kojto 112:6f327212ef96 7196 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
Kojto 112:6f327212ef96 7197 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 112:6f327212ef96 7198 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7199
Kojto 112:6f327212ef96 7200 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
Kojto 112:6f327212ef96 7201 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7202 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7203
Kojto 112:6f327212ef96 7204 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
Kojto 112:6f327212ef96 7205 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
Kojto 112:6f327212ef96 7206 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
Kojto 112:6f327212ef96 7207 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
Kojto 112:6f327212ef96 7208
Kojto 112:6f327212ef96 7209 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
Kojto 112:6f327212ef96 7210 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
Kojto 112:6f327212ef96 7211 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
Kojto 112:6f327212ef96 7212 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
Kojto 112:6f327212ef96 7213 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
Kojto 112:6f327212ef96 7214 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
Kojto 112:6f327212ef96 7215 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
Kojto 112:6f327212ef96 7216 #define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
Kojto 112:6f327212ef96 7217
Kojto 112:6f327212ef96 7218 /******************** Bit definition forUSB_OTG_DCTL register ********************/
Kojto 112:6f327212ef96 7219 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
Kojto 112:6f327212ef96 7220 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
Kojto 112:6f327212ef96 7221 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
Kojto 112:6f327212ef96 7222 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
Kojto 112:6f327212ef96 7223
Kojto 112:6f327212ef96 7224 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
Kojto 112:6f327212ef96 7225 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 112:6f327212ef96 7226 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 112:6f327212ef96 7227 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 112:6f327212ef96 7228 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
Kojto 112:6f327212ef96 7229 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
Kojto 112:6f327212ef96 7230 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
Kojto 112:6f327212ef96 7231 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
Kojto 112:6f327212ef96 7232 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
Kojto 112:6f327212ef96 7233
Kojto 112:6f327212ef96 7234 /******************** Bit definition forUSB_OTG_HFIR register ********************/
Kojto 112:6f327212ef96 7235 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
Kojto 112:6f327212ef96 7236
Kojto 112:6f327212ef96 7237 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
Kojto 112:6f327212ef96 7238 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
Kojto 112:6f327212ef96 7239 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
Kojto 112:6f327212ef96 7240
Kojto 112:6f327212ef96 7241 /******************** Bit definition forUSB_OTG_DSTS register ********************/
Kojto 112:6f327212ef96 7242 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
Kojto 112:6f327212ef96 7243
Kojto 112:6f327212ef96 7244 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
Kojto 112:6f327212ef96 7245 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 112:6f327212ef96 7246 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 112:6f327212ef96 7247 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
Kojto 112:6f327212ef96 7248 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
Kojto 112:6f327212ef96 7249
Kojto 112:6f327212ef96 7250 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
Kojto 112:6f327212ef96 7251 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
Kojto 112:6f327212ef96 7252 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
Kojto 112:6f327212ef96 7253 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 112:6f327212ef96 7254 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 112:6f327212ef96 7255 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
Kojto 112:6f327212ef96 7256 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
Kojto 112:6f327212ef96 7257 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
Kojto 112:6f327212ef96 7258 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
Kojto 112:6f327212ef96 7259 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
Kojto 112:6f327212ef96 7260
Kojto 112:6f327212ef96 7261 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
Kojto 112:6f327212ef96 7262
Kojto 112:6f327212ef96 7263 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
Kojto 112:6f327212ef96 7264 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7265 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7266 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 7267 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
Kojto 112:6f327212ef96 7268 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
Kojto 112:6f327212ef96 7269 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
Kojto 112:6f327212ef96 7270 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
Kojto 112:6f327212ef96 7271 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 112:6f327212ef96 7272 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 112:6f327212ef96 7273 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7274 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7275 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
Kojto 112:6f327212ef96 7276 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
Kojto 112:6f327212ef96 7277 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
Kojto 112:6f327212ef96 7278 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
Kojto 112:6f327212ef96 7279 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
Kojto 112:6f327212ef96 7280 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
Kojto 112:6f327212ef96 7281 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
Kojto 112:6f327212ef96 7282 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
Kojto 112:6f327212ef96 7283 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
Kojto 112:6f327212ef96 7284 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
Kojto 112:6f327212ef96 7285 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
Kojto 112:6f327212ef96 7286 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
Kojto 112:6f327212ef96 7287 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
Kojto 112:6f327212ef96 7288
Kojto 112:6f327212ef96 7289 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
Kojto 112:6f327212ef96 7290 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
Kojto 112:6f327212ef96 7291 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
Kojto 112:6f327212ef96 7292 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
Kojto 112:6f327212ef96 7293 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
Kojto 112:6f327212ef96 7294 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
Kojto 112:6f327212ef96 7295 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
Kojto 112:6f327212ef96 7296 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 112:6f327212ef96 7297 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 112:6f327212ef96 7298 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 112:6f327212ef96 7299 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
Kojto 112:6f327212ef96 7300 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
Kojto 112:6f327212ef96 7301 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
Kojto 112:6f327212ef96 7302 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
Kojto 112:6f327212ef96 7303
Kojto 112:6f327212ef96 7304 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
Kojto 112:6f327212ef96 7305 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 112:6f327212ef96 7306 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 112:6f327212ef96 7307 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 112:6f327212ef96 7308 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 112:6f327212ef96 7309 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 112:6f327212ef96 7310 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 112:6f327212ef96 7311 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 112:6f327212ef96 7312 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 112:6f327212ef96 7313
Kojto 112:6f327212ef96 7314 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
Kojto 112:6f327212ef96 7315 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
Kojto 112:6f327212ef96 7316 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
Kojto 112:6f327212ef96 7317 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7318 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7319 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7320 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7321 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 112:6f327212ef96 7322 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 112:6f327212ef96 7323 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 112:6f327212ef96 7324 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 112:6f327212ef96 7325
Kojto 112:6f327212ef96 7326 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
Kojto 112:6f327212ef96 7327 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7328 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7329 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7330 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7331 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 112:6f327212ef96 7332 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 112:6f327212ef96 7333 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 112:6f327212ef96 7334 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 112:6f327212ef96 7335
Kojto 112:6f327212ef96 7336 /******************** Bit definition forUSB_OTG_HAINT register ********************/
Kojto 112:6f327212ef96 7337 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
Kojto 112:6f327212ef96 7338
Kojto 112:6f327212ef96 7339 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
Kojto 112:6f327212ef96 7340 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 112:6f327212ef96 7341 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 112:6f327212ef96 7342 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
Kojto 112:6f327212ef96 7343 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
Kojto 112:6f327212ef96 7344 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
Kojto 112:6f327212ef96 7345 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 112:6f327212ef96 7346 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 112:6f327212ef96 7347
Kojto 112:6f327212ef96 7348 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
Kojto 112:6f327212ef96 7349 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
Kojto 112:6f327212ef96 7350 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
Kojto 112:6f327212ef96 7351 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
Kojto 112:6f327212ef96 7352 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
Kojto 112:6f327212ef96 7353 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
Kojto 112:6f327212ef96 7354 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
Kojto 112:6f327212ef96 7355 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
Kojto 112:6f327212ef96 7356 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
Kojto 112:6f327212ef96 7357 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
Kojto 112:6f327212ef96 7358 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
Kojto 112:6f327212ef96 7359 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
Kojto 112:6f327212ef96 7360 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
Kojto 112:6f327212ef96 7361 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
Kojto 112:6f327212ef96 7362 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
Kojto 112:6f327212ef96 7363 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
Kojto 112:6f327212ef96 7364 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
Kojto 112:6f327212ef96 7365 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
Kojto 112:6f327212ef96 7366 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
Kojto 112:6f327212ef96 7367 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
Kojto 112:6f327212ef96 7368 #define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
Kojto 112:6f327212ef96 7369 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
Kojto 112:6f327212ef96 7370 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
Kojto 112:6f327212ef96 7371 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
Kojto 112:6f327212ef96 7372 #define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
Kojto 112:6f327212ef96 7373 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
Kojto 112:6f327212ef96 7374 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
Kojto 112:6f327212ef96 7375 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
Kojto 112:6f327212ef96 7376 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
Kojto 112:6f327212ef96 7377
Kojto 112:6f327212ef96 7378 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
Kojto 112:6f327212ef96 7379 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
Kojto 112:6f327212ef96 7380 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
Kojto 112:6f327212ef96 7381 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
Kojto 112:6f327212ef96 7382 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
Kojto 112:6f327212ef96 7383 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
Kojto 112:6f327212ef96 7384 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
Kojto 112:6f327212ef96 7385 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
Kojto 112:6f327212ef96 7386 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
Kojto 112:6f327212ef96 7387 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
Kojto 112:6f327212ef96 7388 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
Kojto 112:6f327212ef96 7389 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
Kojto 112:6f327212ef96 7390 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
Kojto 112:6f327212ef96 7391 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
Kojto 112:6f327212ef96 7392 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
Kojto 112:6f327212ef96 7393 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
Kojto 112:6f327212ef96 7394 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
Kojto 112:6f327212ef96 7395 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
Kojto 112:6f327212ef96 7396 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
Kojto 112:6f327212ef96 7397 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
Kojto 112:6f327212ef96 7398 #define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
Kojto 112:6f327212ef96 7399 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
Kojto 112:6f327212ef96 7400 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
Kojto 112:6f327212ef96 7401 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
Kojto 112:6f327212ef96 7402 #define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
Kojto 112:6f327212ef96 7403 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
Kojto 112:6f327212ef96 7404 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
Kojto 112:6f327212ef96 7405 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
Kojto 112:6f327212ef96 7406 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
Kojto 112:6f327212ef96 7407
Kojto 112:6f327212ef96 7408 /******************** Bit definition forUSB_OTG_DAINT register ********************/
Kojto 112:6f327212ef96 7409 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
Kojto 112:6f327212ef96 7410 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
Kojto 112:6f327212ef96 7411
Kojto 112:6f327212ef96 7412 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
Kojto 112:6f327212ef96 7413 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
Kojto 112:6f327212ef96 7414
Kojto 112:6f327212ef96 7415 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
Kojto 112:6f327212ef96 7416 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
Kojto 112:6f327212ef96 7417 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
Kojto 112:6f327212ef96 7418 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
Kojto 112:6f327212ef96 7419 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
Kojto 112:6f327212ef96 7420
Kojto 112:6f327212ef96 7421 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
Kojto 112:6f327212ef96 7422 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
Kojto 112:6f327212ef96 7423 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
Kojto 112:6f327212ef96 7424
Kojto 112:6f327212ef96 7425 /******************** Bit definition for OTG register ********************/
Kojto 112:6f327212ef96 7426
Kojto 112:6f327212ef96 7427 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 112:6f327212ef96 7428 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7429 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7430 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 7431 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 7432 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 112:6f327212ef96 7433
Kojto 112:6f327212ef96 7434 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 112:6f327212ef96 7435 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7436 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7437
Kojto 112:6f327212ef96 7438 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 112:6f327212ef96 7439 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7440 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7441 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7442 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7443
Kojto 112:6f327212ef96 7444 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 112:6f327212ef96 7445 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7446 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7447 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 7448 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 7449
Kojto 112:6f327212ef96 7450 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 112:6f327212ef96 7451 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7452 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7453 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7454 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7455
Kojto 112:6f327212ef96 7456 /******************** Bit definition for OTG register ********************/
Kojto 112:6f327212ef96 7457
Kojto 112:6f327212ef96 7458 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 112:6f327212ef96 7459 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7460 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7461 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 7462 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 7463 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 112:6f327212ef96 7464
Kojto 112:6f327212ef96 7465 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 112:6f327212ef96 7466 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7467 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7468
Kojto 112:6f327212ef96 7469 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 112:6f327212ef96 7470 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7471 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7472 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7473 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7474
Kojto 112:6f327212ef96 7475 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 112:6f327212ef96 7476 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7477 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7478 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 7479 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 7480
Kojto 112:6f327212ef96 7481 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 112:6f327212ef96 7482 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7483 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7484 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7485 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7486
Kojto 112:6f327212ef96 7487 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
Kojto 112:6f327212ef96 7488 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
Kojto 112:6f327212ef96 7489
Kojto 112:6f327212ef96 7490 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
Kojto 112:6f327212ef96 7491 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
Kojto 112:6f327212ef96 7492
Kojto 112:6f327212ef96 7493 /******************** Bit definition for OTG register ********************/
Kojto 112:6f327212ef96 7494 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
Kojto 112:6f327212ef96 7495 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
Kojto 112:6f327212ef96 7496 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
Kojto 112:6f327212ef96 7497 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
Kojto 112:6f327212ef96 7498
Kojto 112:6f327212ef96 7499 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
Kojto 112:6f327212ef96 7500 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
Kojto 112:6f327212ef96 7501
Kojto 112:6f327212ef96 7502 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
Kojto 112:6f327212ef96 7503 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
Kojto 112:6f327212ef96 7504
Kojto 112:6f327212ef96 7505 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
Kojto 112:6f327212ef96 7506 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7507 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7508 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7509 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7510 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 112:6f327212ef96 7511 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 112:6f327212ef96 7512 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 112:6f327212ef96 7513 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 112:6f327212ef96 7514
Kojto 112:6f327212ef96 7515 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
Kojto 112:6f327212ef96 7516 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7517 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7518 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7519 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7520 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 112:6f327212ef96 7521 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 112:6f327212ef96 7522 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 112:6f327212ef96 7523
Kojto 112:6f327212ef96 7524 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
Kojto 112:6f327212ef96 7525 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
Kojto 112:6f327212ef96 7526 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
Kojto 112:6f327212ef96 7527
Kojto 112:6f327212ef96 7528 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
Kojto 112:6f327212ef96 7529 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 112:6f327212ef96 7530 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 112:6f327212ef96 7531 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
Kojto 112:6f327212ef96 7532 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
Kojto 112:6f327212ef96 7533 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
Kojto 112:6f327212ef96 7534 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
Kojto 112:6f327212ef96 7535 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
Kojto 112:6f327212ef96 7536 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
Kojto 112:6f327212ef96 7537 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
Kojto 112:6f327212ef96 7538 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
Kojto 112:6f327212ef96 7539
Kojto 112:6f327212ef96 7540 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
Kojto 112:6f327212ef96 7541 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7542 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7543 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7544 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7545 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
Kojto 112:6f327212ef96 7546 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
Kojto 112:6f327212ef96 7547 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
Kojto 112:6f327212ef96 7548 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
Kojto 112:6f327212ef96 7549 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
Kojto 112:6f327212ef96 7550 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
Kojto 112:6f327212ef96 7551
Kojto 112:6f327212ef96 7552 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
Kojto 112:6f327212ef96 7553 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
Kojto 112:6f327212ef96 7554
Kojto 112:6f327212ef96 7555 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
Kojto 112:6f327212ef96 7556 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
Kojto 112:6f327212ef96 7557 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
Kojto 112:6f327212ef96 7558
Kojto 112:6f327212ef96 7559 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
Kojto 112:6f327212ef96 7560 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down control */
Kojto 112:6f327212ef96 7561 #define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
Kojto 112:6f327212ef96 7562
Kojto 112:6f327212ef96 7563 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
Kojto 112:6f327212ef96 7564 #define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
Kojto 112:6f327212ef96 7565 #define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
Kojto 112:6f327212ef96 7566
Kojto 112:6f327212ef96 7567 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
Kojto 112:6f327212ef96 7568 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
Kojto 112:6f327212ef96 7569 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
Kojto 112:6f327212ef96 7570
Kojto 112:6f327212ef96 7571 /******************** Bit definition forUSB_OTG_CID register ********************/
Kojto 112:6f327212ef96 7572 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
Kojto 112:6f327212ef96 7573
Kojto 112:6f327212ef96 7574 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
Kojto 112:6f327212ef96 7575 #define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
Kojto 112:6f327212ef96 7576 #define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
Kojto 112:6f327212ef96 7577 #define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
Kojto 112:6f327212ef96 7578 #define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
Kojto 112:6f327212ef96 7579 #define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
Kojto 112:6f327212ef96 7580 #define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
Kojto 112:6f327212ef96 7581 #define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
Kojto 112:6f327212ef96 7582 #define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
Kojto 112:6f327212ef96 7583 #define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
Kojto 112:6f327212ef96 7584 #define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
Kojto 112:6f327212ef96 7585 #define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
Kojto 112:6f327212ef96 7586 #define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
Kojto 112:6f327212ef96 7587 #define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
Kojto 112:6f327212ef96 7588 #define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
Kojto 112:6f327212ef96 7589 #define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
Kojto 112:6f327212ef96 7590
Kojto 112:6f327212ef96 7591 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
Kojto 112:6f327212ef96 7592 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 112:6f327212ef96 7593 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 112:6f327212ef96 7594 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 112:6f327212ef96 7595 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 112:6f327212ef96 7596 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 112:6f327212ef96 7597 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 112:6f327212ef96 7598 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 112:6f327212ef96 7599 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 112:6f327212ef96 7600 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 112:6f327212ef96 7601
Kojto 112:6f327212ef96 7602 /******************** Bit definition forUSB_OTG_HPRT register ********************/
Kojto 112:6f327212ef96 7603 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
Kojto 112:6f327212ef96 7604 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
Kojto 112:6f327212ef96 7605 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
Kojto 112:6f327212ef96 7606 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
Kojto 112:6f327212ef96 7607 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
Kojto 112:6f327212ef96 7608 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
Kojto 112:6f327212ef96 7609 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
Kojto 112:6f327212ef96 7610 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
Kojto 112:6f327212ef96 7611 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
Kojto 112:6f327212ef96 7612
Kojto 112:6f327212ef96 7613 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
Kojto 112:6f327212ef96 7614 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 112:6f327212ef96 7615 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 112:6f327212ef96 7616 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
Kojto 112:6f327212ef96 7617
Kojto 112:6f327212ef96 7618 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
Kojto 112:6f327212ef96 7619 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7620 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7621 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7622 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7623
Kojto 112:6f327212ef96 7624 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
Kojto 112:6f327212ef96 7625 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7626 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7627
Kojto 112:6f327212ef96 7628 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
Kojto 112:6f327212ef96 7629 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 112:6f327212ef96 7630 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 112:6f327212ef96 7631 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
Kojto 112:6f327212ef96 7632 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 112:6f327212ef96 7633 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 112:6f327212ef96 7634 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 112:6f327212ef96 7635 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 112:6f327212ef96 7636 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 112:6f327212ef96 7637 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
Kojto 112:6f327212ef96 7638 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 112:6f327212ef96 7639 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
Kojto 112:6f327212ef96 7640
Kojto 112:6f327212ef96 7641 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
Kojto 112:6f327212ef96 7642 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
Kojto 112:6f327212ef96 7643 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
Kojto 112:6f327212ef96 7644
Kojto 112:6f327212ef96 7645 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
Kojto 112:6f327212ef96 7646 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 112:6f327212ef96 7647 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 112:6f327212ef96 7648 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
Kojto 112:6f327212ef96 7649 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 112:6f327212ef96 7650
Kojto 112:6f327212ef96 7651 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 112:6f327212ef96 7652 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7653 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7654 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 112:6f327212ef96 7655
Kojto 112:6f327212ef96 7656 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
Kojto 112:6f327212ef96 7657 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7658 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7659 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7660 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7661 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 112:6f327212ef96 7662 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 112:6f327212ef96 7663 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 112:6f327212ef96 7664 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 112:6f327212ef96 7665 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 112:6f327212ef96 7666 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 112:6f327212ef96 7667
Kojto 112:6f327212ef96 7668 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
Kojto 112:6f327212ef96 7669 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 112:6f327212ef96 7670
Kojto 112:6f327212ef96 7671 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
Kojto 112:6f327212ef96 7672 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 112:6f327212ef96 7673 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7674 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7675 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7676 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
Kojto 112:6f327212ef96 7677 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
Kojto 112:6f327212ef96 7678
Kojto 112:6f327212ef96 7679 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 112:6f327212ef96 7680 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7681 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7682
Kojto 112:6f327212ef96 7683 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
Kojto 112:6f327212ef96 7684 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7685 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7686
Kojto 112:6f327212ef96 7687 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
Kojto 112:6f327212ef96 7688 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7689 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7690 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 112:6f327212ef96 7691 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 112:6f327212ef96 7692 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
Kojto 112:6f327212ef96 7693 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
Kojto 112:6f327212ef96 7694 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
Kojto 112:6f327212ef96 7695 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
Kojto 112:6f327212ef96 7696 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
Kojto 112:6f327212ef96 7697 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
Kojto 112:6f327212ef96 7698
Kojto 112:6f327212ef96 7699 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
Kojto 112:6f327212ef96 7700
Kojto 112:6f327212ef96 7701 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
Kojto 112:6f327212ef96 7702 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 112:6f327212ef96 7703 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 112:6f327212ef96 7704 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 112:6f327212ef96 7705 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 112:6f327212ef96 7706 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 112:6f327212ef96 7707 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 112:6f327212ef96 7708 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 112:6f327212ef96 7709
Kojto 112:6f327212ef96 7710 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
Kojto 112:6f327212ef96 7711 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 112:6f327212ef96 7712 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 112:6f327212ef96 7713 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
Kojto 112:6f327212ef96 7714 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
Kojto 112:6f327212ef96 7715 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
Kojto 112:6f327212ef96 7716 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
Kojto 112:6f327212ef96 7717 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
Kojto 112:6f327212ef96 7718
Kojto 112:6f327212ef96 7719 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
Kojto 112:6f327212ef96 7720 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7721 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7722 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
Kojto 112:6f327212ef96 7723 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
Kojto 112:6f327212ef96 7724
Kojto 112:6f327212ef96 7725 /******************** Bit definition forUSB_OTG_HCINT register ********************/
Kojto 112:6f327212ef96 7726 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
Kojto 112:6f327212ef96 7727 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
Kojto 112:6f327212ef96 7728 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 112:6f327212ef96 7729 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
Kojto 112:6f327212ef96 7730 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
Kojto 112:6f327212ef96 7731 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
Kojto 112:6f327212ef96 7732 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
Kojto 112:6f327212ef96 7733 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
Kojto 112:6f327212ef96 7734 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
Kojto 112:6f327212ef96 7735 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
Kojto 112:6f327212ef96 7736 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
Kojto 112:6f327212ef96 7737
Kojto 112:6f327212ef96 7738 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
Kojto 112:6f327212ef96 7739 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 112:6f327212ef96 7740 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 112:6f327212ef96 7741 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
Kojto 112:6f327212ef96 7742 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
Kojto 112:6f327212ef96 7743 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
Kojto 112:6f327212ef96 7744 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
Kojto 112:6f327212ef96 7745 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
Kojto 112:6f327212ef96 7746 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
Kojto 112:6f327212ef96 7747 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
Kojto 112:6f327212ef96 7748 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
Kojto 112:6f327212ef96 7749 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
Kojto 112:6f327212ef96 7750
Kojto 112:6f327212ef96 7751 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
Kojto 112:6f327212ef96 7752 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
Kojto 112:6f327212ef96 7753 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
Kojto 112:6f327212ef96 7754 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 112:6f327212ef96 7755 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
Kojto 112:6f327212ef96 7756 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
Kojto 112:6f327212ef96 7757 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
Kojto 112:6f327212ef96 7758 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
Kojto 112:6f327212ef96 7759 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
Kojto 112:6f327212ef96 7760 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
Kojto 112:6f327212ef96 7761 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
Kojto 112:6f327212ef96 7762 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
Kojto 112:6f327212ef96 7763
Kojto 112:6f327212ef96 7764 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
Kojto 112:6f327212ef96 7765
Kojto 112:6f327212ef96 7766 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 112:6f327212ef96 7767 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 112:6f327212ef96 7768 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
Kojto 112:6f327212ef96 7769 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
Kojto 112:6f327212ef96 7770 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 112:6f327212ef96 7771 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 112:6f327212ef96 7772 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
Kojto 112:6f327212ef96 7773 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
Kojto 112:6f327212ef96 7774 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7775 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7776
Kojto 112:6f327212ef96 7777 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
Kojto 112:6f327212ef96 7778 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 112:6f327212ef96 7779
Kojto 112:6f327212ef96 7780 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
Kojto 112:6f327212ef96 7781 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 112:6f327212ef96 7782
Kojto 112:6f327212ef96 7783 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
Kojto 112:6f327212ef96 7784 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
Kojto 112:6f327212ef96 7785
Kojto 112:6f327212ef96 7786 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
Kojto 112:6f327212ef96 7787 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
Kojto 112:6f327212ef96 7788 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
Kojto 112:6f327212ef96 7789
Kojto 112:6f327212ef96 7790 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
Kojto 112:6f327212ef96 7791
Kojto 112:6f327212ef96 7792 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
Kojto 112:6f327212ef96 7793 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 112:6f327212ef96 7794 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 112:6f327212ef96 7795 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 112:6f327212ef96 7796 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 112:6f327212ef96 7797 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 112:6f327212ef96 7798 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7799 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7800 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
Kojto 112:6f327212ef96 7801 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 112:6f327212ef96 7802 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 112:6f327212ef96 7803 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 112:6f327212ef96 7804 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 112:6f327212ef96 7805 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 112:6f327212ef96 7806
Kojto 112:6f327212ef96 7807 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
Kojto 112:6f327212ef96 7808 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 112:6f327212ef96 7809 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 112:6f327212ef96 7810 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
Kojto 112:6f327212ef96 7811 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
Kojto 112:6f327212ef96 7812 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
Kojto 112:6f327212ef96 7813 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
Kojto 112:6f327212ef96 7814
Kojto 112:6f327212ef96 7815 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
Kojto 112:6f327212ef96 7816
Kojto 112:6f327212ef96 7817 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 112:6f327212ef96 7818 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 112:6f327212ef96 7819
Kojto 112:6f327212ef96 7820 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
Kojto 112:6f327212ef96 7821 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 112:6f327212ef96 7822 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 112:6f327212ef96 7823
Kojto 112:6f327212ef96 7824 /******************** Bit definition for PCGCCTL register ********************/
Kojto 112:6f327212ef96 7825 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
Kojto 112:6f327212ef96 7826 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 112:6f327212ef96 7827 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 112:6f327212ef96 7828
Kojto 112:6f327212ef96 7829
Kojto 112:6f327212ef96 7830 /**
Kojto 112:6f327212ef96 7831 * @}
Kojto 112:6f327212ef96 7832 */
Kojto 112:6f327212ef96 7833
Kojto 112:6f327212ef96 7834 /**
Kojto 112:6f327212ef96 7835 * @}
Kojto 112:6f327212ef96 7836 */
Kojto 112:6f327212ef96 7837
Kojto 112:6f327212ef96 7838 /** @addtogroup Exported_macros
Kojto 112:6f327212ef96 7839 * @{
Kojto 112:6f327212ef96 7840 */
Kojto 112:6f327212ef96 7841
Kojto 112:6f327212ef96 7842 /******************************* ADC Instances ********************************/
Kojto 112:6f327212ef96 7843 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
Kojto 112:6f327212ef96 7844 ((INSTANCE) == ADC2) || \
Kojto 112:6f327212ef96 7845 ((INSTANCE) == ADC3))
Kojto 112:6f327212ef96 7846
Kojto 112:6f327212ef96 7847 /******************************* CAN Instances ********************************/
Kojto 112:6f327212ef96 7848 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
Kojto 112:6f327212ef96 7849 ((INSTANCE) == CAN2))
Kojto 112:6f327212ef96 7850
Kojto 112:6f327212ef96 7851 /******************************* CRC Instances ********************************/
Kojto 112:6f327212ef96 7852 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 112:6f327212ef96 7853
Kojto 112:6f327212ef96 7854 /******************************* DAC Instances ********************************/
Kojto 112:6f327212ef96 7855 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
Kojto 112:6f327212ef96 7856
Kojto 112:6f327212ef96 7857 /******************************* DCMI Instances *******************************/
Kojto 112:6f327212ef96 7858 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
Kojto 112:6f327212ef96 7859
Kojto 112:6f327212ef96 7860 /******************************** DMA Instances *******************************/
Kojto 112:6f327212ef96 7861 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
Kojto 112:6f327212ef96 7862 ((INSTANCE) == DMA1_Stream1) || \
Kojto 112:6f327212ef96 7863 ((INSTANCE) == DMA1_Stream2) || \
Kojto 112:6f327212ef96 7864 ((INSTANCE) == DMA1_Stream3) || \
Kojto 112:6f327212ef96 7865 ((INSTANCE) == DMA1_Stream4) || \
Kojto 112:6f327212ef96 7866 ((INSTANCE) == DMA1_Stream5) || \
Kojto 112:6f327212ef96 7867 ((INSTANCE) == DMA1_Stream6) || \
Kojto 112:6f327212ef96 7868 ((INSTANCE) == DMA1_Stream7) || \
Kojto 112:6f327212ef96 7869 ((INSTANCE) == DMA2_Stream0) || \
Kojto 112:6f327212ef96 7870 ((INSTANCE) == DMA2_Stream1) || \
Kojto 112:6f327212ef96 7871 ((INSTANCE) == DMA2_Stream2) || \
Kojto 112:6f327212ef96 7872 ((INSTANCE) == DMA2_Stream3) || \
Kojto 112:6f327212ef96 7873 ((INSTANCE) == DMA2_Stream4) || \
Kojto 112:6f327212ef96 7874 ((INSTANCE) == DMA2_Stream5) || \
Kojto 112:6f327212ef96 7875 ((INSTANCE) == DMA2_Stream6) || \
Kojto 112:6f327212ef96 7876 ((INSTANCE) == DMA2_Stream7))
Kojto 112:6f327212ef96 7877
Kojto 112:6f327212ef96 7878 /******************************* GPIO Instances *******************************/
Kojto 112:6f327212ef96 7879 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 112:6f327212ef96 7880 ((INSTANCE) == GPIOB) || \
Kojto 112:6f327212ef96 7881 ((INSTANCE) == GPIOC) || \
Kojto 112:6f327212ef96 7882 ((INSTANCE) == GPIOD) || \
Kojto 112:6f327212ef96 7883 ((INSTANCE) == GPIOE) || \
Kojto 112:6f327212ef96 7884 ((INSTANCE) == GPIOF) || \
Kojto 112:6f327212ef96 7885 ((INSTANCE) == GPIOG) || \
Kojto 112:6f327212ef96 7886 ((INSTANCE) == GPIOH))
Kojto 112:6f327212ef96 7887
Kojto 112:6f327212ef96 7888 /******************************** I2C Instances *******************************/
Kojto 112:6f327212ef96 7889 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 112:6f327212ef96 7890 ((INSTANCE) == I2C2) || \
Kojto 112:6f327212ef96 7891 ((INSTANCE) == I2C3))
Kojto 112:6f327212ef96 7892
Kojto 112:6f327212ef96 7893 /******************************** I2S Instances *******************************/
Kojto 112:6f327212ef96 7894 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 112:6f327212ef96 7895 ((INSTANCE) == SPI2) || \
Kojto 112:6f327212ef96 7896 ((INSTANCE) == SPI3))
Kojto 112:6f327212ef96 7897
Kojto 112:6f327212ef96 7898 /****************************** RTC Instances *********************************/
Kojto 112:6f327212ef96 7899 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 112:6f327212ef96 7900
Kojto 112:6f327212ef96 7901 /******************************* SAI Instances ********************************/
Kojto 112:6f327212ef96 7902 #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
Kojto 112:6f327212ef96 7903 ((PERIPH) == SAI1_Block_B) || \
Kojto 112:6f327212ef96 7904 ((PERIPH) == SAI2_Block_A) || \
Kojto 112:6f327212ef96 7905 ((PERIPH) == SAI2_Block_B))
Kojto 112:6f327212ef96 7906
Kojto 112:6f327212ef96 7907 /******************************** SPI Instances *******************************/
Kojto 112:6f327212ef96 7908 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 112:6f327212ef96 7909 ((INSTANCE) == SPI2) || \
Kojto 112:6f327212ef96 7910 ((INSTANCE) == SPI3) || \
Kojto 112:6f327212ef96 7911 ((INSTANCE) == SPI4))
Kojto 112:6f327212ef96 7912
Kojto 112:6f327212ef96 7913 /****************** TIM Instances : All supported instances *******************/
Kojto 112:6f327212ef96 7914 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7915 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 7916 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 7917 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 7918 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 7919 ((INSTANCE) == TIM6) || \
Kojto 112:6f327212ef96 7920 ((INSTANCE) == TIM7) || \
Kojto 112:6f327212ef96 7921 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 7922 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 7923 ((INSTANCE) == TIM10) || \
Kojto 112:6f327212ef96 7924 ((INSTANCE) == TIM11) || \
Kojto 112:6f327212ef96 7925 ((INSTANCE) == TIM12) || \
Kojto 112:6f327212ef96 7926 ((INSTANCE) == TIM13) || \
Kojto 112:6f327212ef96 7927 ((INSTANCE) == TIM14))
Kojto 112:6f327212ef96 7928
Kojto 112:6f327212ef96 7929 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 112:6f327212ef96 7930 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7931 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 7932 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 7933 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 7934 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 7935 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 7936 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 7937 ((INSTANCE) == TIM10) || \
Kojto 112:6f327212ef96 7938 ((INSTANCE) == TIM11) || \
Kojto 112:6f327212ef96 7939 ((INSTANCE) == TIM12) || \
Kojto 112:6f327212ef96 7940 ((INSTANCE) == TIM13) || \
Kojto 112:6f327212ef96 7941 ((INSTANCE) == TIM14))
Kojto 112:6f327212ef96 7942
Kojto 112:6f327212ef96 7943 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 112:6f327212ef96 7944 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7945 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 7946 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 7947 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 7948 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 7949 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 7950 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 7951 ((INSTANCE) == TIM12))
Kojto 112:6f327212ef96 7952
Kojto 112:6f327212ef96 7953 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 112:6f327212ef96 7954 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7955 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 7956 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 7957 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 7958 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 7959 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 7960
Kojto 112:6f327212ef96 7961 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 112:6f327212ef96 7962 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7963 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 7964 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 7965 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 7966 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 7967 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 7968
Kojto 112:6f327212ef96 7969 /******************** TIM Instances : Advanced-control timers *****************/
Kojto 112:6f327212ef96 7970 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7971 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 7972
Kojto 112:6f327212ef96 7973 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 112:6f327212ef96 7974 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7975 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 7976 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 7977 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 7978 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 7979 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 7980
Kojto 112:6f327212ef96 7981 /****************** TIM Instances : DMA requests generation (UDE) *************/
Kojto 112:6f327212ef96 7982 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7983 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 7984 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 7985 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 7986 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 7987 ((INSTANCE) == TIM6) || \
Kojto 112:6f327212ef96 7988 ((INSTANCE) == TIM7) || \
Kojto 112:6f327212ef96 7989 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 7990
Kojto 112:6f327212ef96 7991 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
Kojto 112:6f327212ef96 7992 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 7993 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 7994 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 7995 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 7996 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 7997 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 7998
Kojto 112:6f327212ef96 7999 /************ TIM Instances : DMA requests generation (COMDE) *****************/
Kojto 112:6f327212ef96 8000 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8001 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8002 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8003 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8004 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8005 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8006
Kojto 112:6f327212ef96 8007 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 112:6f327212ef96 8008 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8009 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8010 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8011 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8012 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8013 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8014
Kojto 112:6f327212ef96 8015 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
Kojto 112:6f327212ef96 8016 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8017 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8018 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8019 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8020 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8021 ((INSTANCE) == TIM6) || \
Kojto 112:6f327212ef96 8022 ((INSTANCE) == TIM7) || \
Kojto 112:6f327212ef96 8023 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 8024 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 8025 ((INSTANCE) == TIM12))
Kojto 112:6f327212ef96 8026
Kojto 112:6f327212ef96 8027 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 112:6f327212ef96 8028 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8029 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8030 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8031 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8032 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8033 ((INSTANCE) == TIM8) || \
Kojto 112:6f327212ef96 8034 ((INSTANCE) == TIM9) || \
Kojto 112:6f327212ef96 8035 ((INSTANCE) == TIM12))
Kojto 112:6f327212ef96 8036
Kojto 112:6f327212ef96 8037 /********************** TIM Instances : 32 bit Counter ************************/
Kojto 112:6f327212ef96 8038 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8039 ((INSTANCE) == TIM5))
Kojto 112:6f327212ef96 8040
Kojto 112:6f327212ef96 8041 /***************** TIM Instances : external trigger input availabe ************/
Kojto 112:6f327212ef96 8042 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
Kojto 112:6f327212ef96 8043 ((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8044 ((INSTANCE) == TIM3) || \
Kojto 112:6f327212ef96 8045 ((INSTANCE) == TIM4) || \
Kojto 112:6f327212ef96 8046 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8047 ((INSTANCE) == TIM8))
Kojto 112:6f327212ef96 8048
Kojto 112:6f327212ef96 8049 /****************** TIM Instances : remapping capability **********************/
Kojto 112:6f327212ef96 8050 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 112:6f327212ef96 8051 ((INSTANCE) == TIM5) || \
Kojto 112:6f327212ef96 8052 ((INSTANCE) == TIM11))
Kojto 112:6f327212ef96 8053
Kojto 112:6f327212ef96 8054 /******************* TIM Instances : output(s) available **********************/
Kojto 112:6f327212ef96 8055 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 112:6f327212ef96 8056 ((((INSTANCE) == TIM1) && \
Kojto 112:6f327212ef96 8057 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8058 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8059 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8060 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8061 || \
Kojto 112:6f327212ef96 8062 (((INSTANCE) == TIM2) && \
Kojto 112:6f327212ef96 8063 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8064 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8065 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8066 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8067 || \
Kojto 112:6f327212ef96 8068 (((INSTANCE) == TIM3) && \
Kojto 112:6f327212ef96 8069 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8070 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8071 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8072 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8073 || \
Kojto 112:6f327212ef96 8074 (((INSTANCE) == TIM4) && \
Kojto 112:6f327212ef96 8075 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8076 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8077 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8078 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8079 || \
Kojto 112:6f327212ef96 8080 (((INSTANCE) == TIM5) && \
Kojto 112:6f327212ef96 8081 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8082 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8083 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8084 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8085 || \
Kojto 112:6f327212ef96 8086 (((INSTANCE) == TIM8) && \
Kojto 112:6f327212ef96 8087 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8088 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8089 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 112:6f327212ef96 8090 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 112:6f327212ef96 8091 || \
Kojto 112:6f327212ef96 8092 (((INSTANCE) == TIM9) && \
Kojto 112:6f327212ef96 8093 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8094 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 112:6f327212ef96 8095 || \
Kojto 112:6f327212ef96 8096 (((INSTANCE) == TIM10) && \
Kojto 112:6f327212ef96 8097 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 112:6f327212ef96 8098 || \
Kojto 112:6f327212ef96 8099 (((INSTANCE) == TIM11) && \
Kojto 112:6f327212ef96 8100 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 112:6f327212ef96 8101 || \
Kojto 112:6f327212ef96 8102 (((INSTANCE) == TIM12) && \
Kojto 112:6f327212ef96 8103 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8104 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 112:6f327212ef96 8105 || \
Kojto 112:6f327212ef96 8106 (((INSTANCE) == TIM13) && \
Kojto 112:6f327212ef96 8107 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 112:6f327212ef96 8108 || \
Kojto 112:6f327212ef96 8109 (((INSTANCE) == TIM14) && \
Kojto 112:6f327212ef96 8110 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 112:6f327212ef96 8111
Kojto 112:6f327212ef96 8112 /************ TIM Instances : complementary output(s) available ***************/
Kojto 112:6f327212ef96 8113 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 112:6f327212ef96 8114 ((((INSTANCE) == TIM1) && \
Kojto 112:6f327212ef96 8115 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8116 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8117 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 112:6f327212ef96 8118 || \
Kojto 112:6f327212ef96 8119 (((INSTANCE) == TIM8) && \
Kojto 112:6f327212ef96 8120 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 112:6f327212ef96 8121 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 112:6f327212ef96 8122 ((CHANNEL) == TIM_CHANNEL_3))))
Kojto 112:6f327212ef96 8123
Kojto 112:6f327212ef96 8124 /******************** USART Instances : Synchronous mode **********************/
Kojto 112:6f327212ef96 8125 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8126 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8127 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8128 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8129
Kojto 112:6f327212ef96 8130 /******************** UART Instances : Asynchronous mode **********************/
Kojto 112:6f327212ef96 8131 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8132 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8133 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8134 ((INSTANCE) == UART4) || \
Kojto 112:6f327212ef96 8135 ((INSTANCE) == UART5) || \
Kojto 112:6f327212ef96 8136 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8137
Kojto 112:6f327212ef96 8138 /****************** UART Instances : Hardware Flow control ********************/
Kojto 112:6f327212ef96 8139 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8140 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8141 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8142 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8143
Kojto 112:6f327212ef96 8144 /********************* UART Instances : Smard card mode ***********************/
Kojto 112:6f327212ef96 8145 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8146 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8147 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8148 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8149
Kojto 112:6f327212ef96 8150 /*********************** UART Instances : IRDA mode ***************************/
Kojto 112:6f327212ef96 8151 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 112:6f327212ef96 8152 ((INSTANCE) == USART2) || \
Kojto 112:6f327212ef96 8153 ((INSTANCE) == USART3) || \
Kojto 112:6f327212ef96 8154 ((INSTANCE) == UART4) || \
Kojto 112:6f327212ef96 8155 ((INSTANCE) == UART5) || \
Kojto 112:6f327212ef96 8156 ((INSTANCE) == USART6))
Kojto 112:6f327212ef96 8157
Kojto 112:6f327212ef96 8158 /****************************** SDIO Instances ********************************/
Kojto 112:6f327212ef96 8159 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
Kojto 112:6f327212ef96 8160
Kojto 112:6f327212ef96 8161 /****************************** IWDG Instances ********************************/
Kojto 112:6f327212ef96 8162 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 112:6f327212ef96 8163
Kojto 112:6f327212ef96 8164 /****************************** WWDG Instances ********************************/
Kojto 112:6f327212ef96 8165 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 112:6f327212ef96 8166
Kojto 112:6f327212ef96 8167 /****************************** QSPI Instances ********************************/
Kojto 112:6f327212ef96 8168 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
Kojto 112:6f327212ef96 8169
Kojto 112:6f327212ef96 8170 /******************************* CEC Instances ********************************/
Kojto 112:6f327212ef96 8171 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
Kojto 112:6f327212ef96 8172
Kojto 112:6f327212ef96 8173 /***************************** FMPI2C Instances *******************************/
Kojto 112:6f327212ef96 8174 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
Kojto 112:6f327212ef96 8175
Kojto 112:6f327212ef96 8176 /******************************* SPDIFRX Instances ********************************/
Kojto 112:6f327212ef96 8177 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
Kojto 112:6f327212ef96 8178
Kojto 112:6f327212ef96 8179 /****************************** USB Exported Constants ************************/
Kojto 112:6f327212ef96 8180 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
Kojto 112:6f327212ef96 8181 #define USB_OTG_FS_MAX_IN_ENDPOINTS 5 /* Including EP0 */
Kojto 112:6f327212ef96 8182 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 5 /* Including EP0 */
Kojto 112:6f327212ef96 8183 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
Kojto 112:6f327212ef96 8184
Kojto 112:6f327212ef96 8185 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16
Kojto 112:6f327212ef96 8186 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
Kojto 112:6f327212ef96 8187 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
Kojto 112:6f327212ef96 8188 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
Kojto 112:6f327212ef96 8189
Kojto 112:6f327212ef96 8190 /**
Kojto 112:6f327212ef96 8191 * @}
Kojto 112:6f327212ef96 8192 */
Kojto 112:6f327212ef96 8193
Kojto 112:6f327212ef96 8194 /**
Kojto 112:6f327212ef96 8195 * @}
Kojto 112:6f327212ef96 8196 */
Kojto 112:6f327212ef96 8197
Kojto 112:6f327212ef96 8198 /**
Kojto 112:6f327212ef96 8199 * @}
Kojto 112:6f327212ef96 8200 */
Kojto 112:6f327212ef96 8201
Kojto 112:6f327212ef96 8202 #ifdef __cplusplus
Kojto 112:6f327212ef96 8203 }
Kojto 112:6f327212ef96 8204 #endif /* __cplusplus */
Kojto 112:6f327212ef96 8205
Kojto 112:6f327212ef96 8206 #endif /* __STM32F446xx_H */
Kojto 112:6f327212ef96 8207
Kojto 112:6f327212ef96 8208
Kojto 112:6f327212ef96 8209
Kojto 112:6f327212ef96 8210 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/