Elijah Orr / mbed-renbed

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TARGET_LPC4088/LPC407x_8x_177x_8x.h@65:5798e58a58b1, 2013-08-12 (annotated)

Committer:
bogdanm
Date:
Mon Aug 12 13:17:46 2013 +0300
Revision:
65:5798e58a58b1
Child:
66:9c8f0e3462fb
New target (LPC4088), new features (interrupt chaining), bug fixes (KL25Z I2C).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 65:5798e58a58b1 1 /****************************************************************************************************//**
bogdanm 65:5798e58a58b1 2 * $Id$ LPC407x_8x_177x_8x.h 2012-04-25
bogdanm 65:5798e58a58b1 3 *//**
bogdanm 65:5798e58a58b1 4 * @file LPC407x_8x_177x_8x.h
bogdanm 65:5798e58a58b1 5 *
bogdanm 65:5798e58a58b1 6 * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
bogdanm 65:5798e58a58b1 7 * NXP LPC407x_8x_177x_8x.
bogdanm 65:5798e58a58b1 8 * @version V0.7
bogdanm 65:5798e58a58b1 9 * @date 20. June 2012
bogdanm 65:5798e58a58b1 10 * @author NXP MCU SW Application Team
bogdanm 65:5798e58a58b1 11 *
bogdanm 65:5798e58a58b1 12 * Copyright(C) 2012, NXP Semiconductor
bogdanm 65:5798e58a58b1 13 * All rights reserved.
bogdanm 65:5798e58a58b1 14 *
bogdanm 65:5798e58a58b1 15 ***********************************************************************
bogdanm 65:5798e58a58b1 16 * Software that is described herein is for illustrative purposes only
bogdanm 65:5798e58a58b1 17 * which provides customers with programming information regarding the
bogdanm 65:5798e58a58b1 18 * products. This software is supplied "AS IS" without any warranties.
bogdanm 65:5798e58a58b1 19 * NXP Semiconductors assumes no responsibility or liability for the
bogdanm 65:5798e58a58b1 20 * use of the software, conveys no license or title under any patent,
bogdanm 65:5798e58a58b1 21 * copyright, or mask work right to the product. NXP Semiconductors
bogdanm 65:5798e58a58b1 22 * reserves the right to make changes in the software without
bogdanm 65:5798e58a58b1 23 * notification. NXP Semiconductors also make no representation or
bogdanm 65:5798e58a58b1 24 * warranty that such application will be suitable for the specified
bogdanm 65:5798e58a58b1 25 * use without further testing or modification.
bogdanm 65:5798e58a58b1 26 * Permission to use, copy, modify, and distribute this software and its
bogdanm 65:5798e58a58b1 27 * documentation is hereby granted, under NXP Semiconductors'
bogdanm 65:5798e58a58b1 28 * relevant copyright in the software, without fee, provided that it
bogdanm 65:5798e58a58b1 29 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 65:5798e58a58b1 30 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 65:5798e58a58b1 31 * this code.
bogdanm 65:5798e58a58b1 32 **********************************************************************/
bogdanm 65:5798e58a58b1 33
bogdanm 65:5798e58a58b1 34 #ifndef __LPC407x_8x_177x_8x_H__
bogdanm 65:5798e58a58b1 35 #define __LPC407x_8x_177x_8x_H__
bogdanm 65:5798e58a58b1 36
bogdanm 65:5798e58a58b1 37 #define CORE_M4
bogdanm 65:5798e58a58b1 38
bogdanm 65:5798e58a58b1 39 // ##################
bogdanm 65:5798e58a58b1 40 // Code Red - excluded extern "C" as unrequired
bogdanm 65:5798e58a58b1 41 // ##################
bogdanm 65:5798e58a58b1 42 #if 0
bogdanm 65:5798e58a58b1 43 #ifdef __cplusplus
bogdanm 65:5798e58a58b1 44 extern "C" {
bogdanm 65:5798e58a58b1 45 #endif
bogdanm 65:5798e58a58b1 46 #endif
bogdanm 65:5798e58a58b1 47
bogdanm 65:5798e58a58b1 48
bogdanm 65:5798e58a58b1 49 /* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm 65:5798e58a58b1 50
bogdanm 65:5798e58a58b1 51 typedef enum IRQn
bogdanm 65:5798e58a58b1 52 {
bogdanm 65:5798e58a58b1 53 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
bogdanm 65:5798e58a58b1 54 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 65:5798e58a58b1 55 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 65:5798e58a58b1 56 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
bogdanm 65:5798e58a58b1 57 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
bogdanm 65:5798e58a58b1 58 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
bogdanm 65:5798e58a58b1 59 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
bogdanm 65:5798e58a58b1 60 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
bogdanm 65:5798e58a58b1 61 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
bogdanm 65:5798e58a58b1 62 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
bogdanm 65:5798e58a58b1 63 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
bogdanm 65:5798e58a58b1 64
bogdanm 65:5798e58a58b1 65 /****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
bogdanm 65:5798e58a58b1 66 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
bogdanm 65:5798e58a58b1 67 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
bogdanm 65:5798e58a58b1 68 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
bogdanm 65:5798e58a58b1 69 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
bogdanm 65:5798e58a58b1 70 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
bogdanm 65:5798e58a58b1 71 UART0_IRQn = 5, /*!< UART0 Interrupt */
bogdanm 65:5798e58a58b1 72 UART1_IRQn = 6, /*!< UART1 Interrupt */
bogdanm 65:5798e58a58b1 73 UART2_IRQn = 7, /*!< UART2 Interrupt */
bogdanm 65:5798e58a58b1 74 UART3_IRQn = 8, /*!< UART3 Interrupt */
bogdanm 65:5798e58a58b1 75 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
bogdanm 65:5798e58a58b1 76 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
bogdanm 65:5798e58a58b1 77 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
bogdanm 65:5798e58a58b1 78 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
bogdanm 65:5798e58a58b1 79 Reserved0_IRQn = 13, /*!< Reserved */
bogdanm 65:5798e58a58b1 80 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
bogdanm 65:5798e58a58b1 81 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
bogdanm 65:5798e58a58b1 82 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
bogdanm 65:5798e58a58b1 83 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
bogdanm 65:5798e58a58b1 84 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
bogdanm 65:5798e58a58b1 85 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
bogdanm 65:5798e58a58b1 86 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
bogdanm 65:5798e58a58b1 87 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
bogdanm 65:5798e58a58b1 88 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
bogdanm 65:5798e58a58b1 89 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
bogdanm 65:5798e58a58b1 90 USB_IRQn = 24, /*!< USB Interrupt */
bogdanm 65:5798e58a58b1 91 CAN_IRQn = 25, /*!< CAN Interrupt */
bogdanm 65:5798e58a58b1 92 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
bogdanm 65:5798e58a58b1 93 I2S_IRQn = 27, /*!< I2S Interrupt */
bogdanm 65:5798e58a58b1 94 ENET_IRQn = 28, /*!< Ethernet Interrupt */
bogdanm 65:5798e58a58b1 95 MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
bogdanm 65:5798e58a58b1 96 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
bogdanm 65:5798e58a58b1 97 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
bogdanm 65:5798e58a58b1 98 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
bogdanm 65:5798e58a58b1 99 USBActivity_IRQn = 33, /*!< USB Activity interrupt */
bogdanm 65:5798e58a58b1 100 CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
bogdanm 65:5798e58a58b1 101 UART4_IRQn = 35, /*!< UART4 Interrupt */
bogdanm 65:5798e58a58b1 102 SSP2_IRQn = 36, /*!< SSP2 Interrupt */
bogdanm 65:5798e58a58b1 103 LCD_IRQn = 37, /*!< LCD Interrupt */
bogdanm 65:5798e58a58b1 104 GPIO_IRQn = 38, /*!< GPIO Interrupt */
bogdanm 65:5798e58a58b1 105 PWM0_IRQn = 39, /*!< 39 PWM0 */
bogdanm 65:5798e58a58b1 106 EEPROM_IRQn = 40, /*!< 40 EEPROM */
bogdanm 65:5798e58a58b1 107 CMP0_IRQn = 41, /*!< 41 CMP0 */
bogdanm 65:5798e58a58b1 108 CMP1_IRQn = 42 /*!< 42 CMP1 */
bogdanm 65:5798e58a58b1 109 } IRQn_Type;
bogdanm 65:5798e58a58b1 110
bogdanm 65:5798e58a58b1 111 /* ================================================================================ */
bogdanm 65:5798e58a58b1 112 /* ================ Processor and Core Peripheral Section ================ */
bogdanm 65:5798e58a58b1 113 /* ================================================================================ */
bogdanm 65:5798e58a58b1 114 #ifdef CORE_M4
bogdanm 65:5798e58a58b1 115 /* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
bogdanm 65:5798e58a58b1 116 #define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
bogdanm 65:5798e58a58b1 117 #define __MPU_PRESENT 1 /*!< MPU present or not */
bogdanm 65:5798e58a58b1 118 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
bogdanm 65:5798e58a58b1 119 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 65:5798e58a58b1 120 #define __FPU_PRESENT 1 /*!< FPU present or not */
bogdanm 65:5798e58a58b1 121
bogdanm 65:5798e58a58b1 122
bogdanm 65:5798e58a58b1 123 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
bogdanm 65:5798e58a58b1 124 #else
bogdanm 65:5798e58a58b1 125 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
bogdanm 65:5798e58a58b1 126 #define __MPU_PRESENT 1 /*!< MPU present or not */
bogdanm 65:5798e58a58b1 127 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
bogdanm 65:5798e58a58b1 128 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 65:5798e58a58b1 129
bogdanm 65:5798e58a58b1 130
bogdanm 65:5798e58a58b1 131 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
bogdanm 65:5798e58a58b1 132
bogdanm 65:5798e58a58b1 133 #endif
bogdanm 65:5798e58a58b1 134
bogdanm 65:5798e58a58b1 135 #include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
bogdanm 65:5798e58a58b1 136
bogdanm 65:5798e58a58b1 137
bogdanm 65:5798e58a58b1 138
bogdanm 65:5798e58a58b1 139
bogdanm 65:5798e58a58b1 140
bogdanm 65:5798e58a58b1 141
bogdanm 65:5798e58a58b1 142 /* ================================================================================ */
bogdanm 65:5798e58a58b1 143 /* ================ Device Specific Peripheral Section ================ */
bogdanm 65:5798e58a58b1 144 /* ================================================================================ */
bogdanm 65:5798e58a58b1 145
bogdanm 65:5798e58a58b1 146 #if defined ( __CC_ARM )
bogdanm 65:5798e58a58b1 147 #pragma anon_unions
bogdanm 65:5798e58a58b1 148 #endif
bogdanm 65:5798e58a58b1 149
bogdanm 65:5798e58a58b1 150 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
bogdanm 65:5798e58a58b1 151 typedef struct /* Common Registers */
bogdanm 65:5798e58a58b1 152 {
bogdanm 65:5798e58a58b1 153 __I uint32_t IntStat;
bogdanm 65:5798e58a58b1 154 __I uint32_t IntTCStat;
bogdanm 65:5798e58a58b1 155 __O uint32_t IntTCClear;
bogdanm 65:5798e58a58b1 156 __I uint32_t IntErrStat;
bogdanm 65:5798e58a58b1 157 __O uint32_t IntErrClr;
bogdanm 65:5798e58a58b1 158 __I uint32_t RawIntTCStat;
bogdanm 65:5798e58a58b1 159 __I uint32_t RawIntErrStat;
bogdanm 65:5798e58a58b1 160 __I uint32_t EnbldChns;
bogdanm 65:5798e58a58b1 161 __IO uint32_t SoftBReq;
bogdanm 65:5798e58a58b1 162 __IO uint32_t SoftSReq;
bogdanm 65:5798e58a58b1 163 __IO uint32_t SoftLBReq;
bogdanm 65:5798e58a58b1 164 __IO uint32_t SoftLSReq;
bogdanm 65:5798e58a58b1 165 __IO uint32_t Config;
bogdanm 65:5798e58a58b1 166 __IO uint32_t Sync;
bogdanm 65:5798e58a58b1 167 } LPC_GPDMA_TypeDef;
bogdanm 65:5798e58a58b1 168
bogdanm 65:5798e58a58b1 169 typedef struct /* Channel Registers */
bogdanm 65:5798e58a58b1 170 {
bogdanm 65:5798e58a58b1 171 __IO uint32_t CSrcAddr;
bogdanm 65:5798e58a58b1 172 __IO uint32_t CDestAddr;
bogdanm 65:5798e58a58b1 173 __IO uint32_t CLLI;
bogdanm 65:5798e58a58b1 174 __IO uint32_t CControl;
bogdanm 65:5798e58a58b1 175 __IO uint32_t CConfig;
bogdanm 65:5798e58a58b1 176 } LPC_GPDMACH_TypeDef;
bogdanm 65:5798e58a58b1 177
bogdanm 65:5798e58a58b1 178 /*------------- System Control (SC) ------------------------------------------*/
bogdanm 65:5798e58a58b1 179 typedef struct
bogdanm 65:5798e58a58b1 180 {
bogdanm 65:5798e58a58b1 181 __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
bogdanm 65:5798e58a58b1 182 uint32_t RESERVED0[31];
bogdanm 65:5798e58a58b1 183 __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
bogdanm 65:5798e58a58b1 184 __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
bogdanm 65:5798e58a58b1 185 __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
bogdanm 65:5798e58a58b1 186 __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
bogdanm 65:5798e58a58b1 187 uint32_t RESERVED1[4];
bogdanm 65:5798e58a58b1 188 __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
bogdanm 65:5798e58a58b1 189 __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
bogdanm 65:5798e58a58b1 190 __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
bogdanm 65:5798e58a58b1 191 __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
bogdanm 65:5798e58a58b1 192 uint32_t RESERVED2[4];
bogdanm 65:5798e58a58b1 193 __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
bogdanm 65:5798e58a58b1 194 __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
bogdanm 65:5798e58a58b1 195 __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
bogdanm 65:5798e58a58b1 196 uint32_t RESERVED3[13];
bogdanm 65:5798e58a58b1 197 __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
bogdanm 65:5798e58a58b1 198 __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
bogdanm 65:5798e58a58b1 199 __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
bogdanm 65:5798e58a58b1 200 __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
bogdanm 65:5798e58a58b1 201 __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
bogdanm 65:5798e58a58b1 202 __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
bogdanm 65:5798e58a58b1 203 uint32_t RESERVED4[10];
bogdanm 65:5798e58a58b1 204 __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
bogdanm 65:5798e58a58b1 205 uint32_t RESERVED5[1];
bogdanm 65:5798e58a58b1 206 __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
bogdanm 65:5798e58a58b1 207 __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
bogdanm 65:5798e58a58b1 208 uint32_t RESERVED6[12];
bogdanm 65:5798e58a58b1 209 __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
bogdanm 65:5798e58a58b1 210 uint32_t RESERVED7[7];
bogdanm 65:5798e58a58b1 211 __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
bogdanm 65:5798e58a58b1 212 __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
bogdanm 65:5798e58a58b1 213 __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
bogdanm 65:5798e58a58b1 214 uint32_t RESERVED8;
bogdanm 65:5798e58a58b1 215 __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
bogdanm 65:5798e58a58b1 216 __IO uint32_t SPIFICLKSEL;
bogdanm 65:5798e58a58b1 217 __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
bogdanm 65:5798e58a58b1 218 uint32_t RESERVED10[1];
bogdanm 65:5798e58a58b1 219 __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
bogdanm 65:5798e58a58b1 220 __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
bogdanm 65:5798e58a58b1 221 __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
bogdanm 65:5798e58a58b1 222 __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
bogdanm 65:5798e58a58b1 223 __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
bogdanm 65:5798e58a58b1 224 uint32_t RESERVED11[2];
bogdanm 65:5798e58a58b1 225 __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
bogdanm 65:5798e58a58b1 226 __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
bogdanm 65:5798e58a58b1 227 } LPC_SC_TypeDef;
bogdanm 65:5798e58a58b1 228 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
bogdanm 65:5798e58a58b1 229 typedef struct
bogdanm 65:5798e58a58b1 230 {
bogdanm 65:5798e58a58b1 231 __IO uint32_t MAC1; /* MAC Registers */
bogdanm 65:5798e58a58b1 232 __IO uint32_t MAC2;
bogdanm 65:5798e58a58b1 233 __IO uint32_t IPGT;
bogdanm 65:5798e58a58b1 234 __IO uint32_t IPGR;
bogdanm 65:5798e58a58b1 235 __IO uint32_t CLRT;
bogdanm 65:5798e58a58b1 236 __IO uint32_t MAXF;
bogdanm 65:5798e58a58b1 237 __IO uint32_t SUPP;
bogdanm 65:5798e58a58b1 238 __IO uint32_t TEST;
bogdanm 65:5798e58a58b1 239 __IO uint32_t MCFG;
bogdanm 65:5798e58a58b1 240 __IO uint32_t MCMD;
bogdanm 65:5798e58a58b1 241 __IO uint32_t MADR;
bogdanm 65:5798e58a58b1 242 __O uint32_t MWTD;
bogdanm 65:5798e58a58b1 243 __I uint32_t MRDD;
bogdanm 65:5798e58a58b1 244 __I uint32_t MIND;
bogdanm 65:5798e58a58b1 245 uint32_t RESERVED0[2];
bogdanm 65:5798e58a58b1 246 __IO uint32_t SA0;
bogdanm 65:5798e58a58b1 247 __IO uint32_t SA1;
bogdanm 65:5798e58a58b1 248 __IO uint32_t SA2;
bogdanm 65:5798e58a58b1 249 uint32_t RESERVED1[45];
bogdanm 65:5798e58a58b1 250 __IO uint32_t Command; /* Control Registers */
bogdanm 65:5798e58a58b1 251 __I uint32_t Status;
bogdanm 65:5798e58a58b1 252 __IO uint32_t RxDescriptor;
bogdanm 65:5798e58a58b1 253 __IO uint32_t RxStatus;
bogdanm 65:5798e58a58b1 254 __IO uint32_t RxDescriptorNumber;
bogdanm 65:5798e58a58b1 255 __I uint32_t RxProduceIndex;
bogdanm 65:5798e58a58b1 256 __IO uint32_t RxConsumeIndex;
bogdanm 65:5798e58a58b1 257 __IO uint32_t TxDescriptor;
bogdanm 65:5798e58a58b1 258 __IO uint32_t TxStatus;
bogdanm 65:5798e58a58b1 259 __IO uint32_t TxDescriptorNumber;
bogdanm 65:5798e58a58b1 260 __IO uint32_t TxProduceIndex;
bogdanm 65:5798e58a58b1 261 __I uint32_t TxConsumeIndex;
bogdanm 65:5798e58a58b1 262 uint32_t RESERVED2[10];
bogdanm 65:5798e58a58b1 263 __I uint32_t TSV0;
bogdanm 65:5798e58a58b1 264 __I uint32_t TSV1;
bogdanm 65:5798e58a58b1 265 __I uint32_t RSV;
bogdanm 65:5798e58a58b1 266 uint32_t RESERVED3[3];
bogdanm 65:5798e58a58b1 267 __IO uint32_t FlowControlCounter;
bogdanm 65:5798e58a58b1 268 __I uint32_t FlowControlStatus;
bogdanm 65:5798e58a58b1 269 uint32_t RESERVED4[34];
bogdanm 65:5798e58a58b1 270 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
bogdanm 65:5798e58a58b1 271 __I uint32_t RxFilterWoLStatus;
bogdanm 65:5798e58a58b1 272 __O uint32_t RxFilterWoLClear;
bogdanm 65:5798e58a58b1 273 uint32_t RESERVED5;
bogdanm 65:5798e58a58b1 274 __IO uint32_t HashFilterL;
bogdanm 65:5798e58a58b1 275 __IO uint32_t HashFilterH;
bogdanm 65:5798e58a58b1 276 uint32_t RESERVED6[882];
bogdanm 65:5798e58a58b1 277 __I uint32_t IntStatus; /* Module Control Registers */
bogdanm 65:5798e58a58b1 278 __IO uint32_t IntEnable;
bogdanm 65:5798e58a58b1 279 __O uint32_t IntClear;
bogdanm 65:5798e58a58b1 280 __O uint32_t IntSet;
bogdanm 65:5798e58a58b1 281 uint32_t RESERVED7;
bogdanm 65:5798e58a58b1 282 __IO uint32_t PowerDown;
bogdanm 65:5798e58a58b1 283 uint32_t RESERVED8;
bogdanm 65:5798e58a58b1 284 __IO uint32_t Module_ID;
bogdanm 65:5798e58a58b1 285 } LPC_EMAC_TypeDef;
bogdanm 65:5798e58a58b1 286
bogdanm 65:5798e58a58b1 287 /*------------- LCD controller (LCD) -----------------------------------------*/
bogdanm 65:5798e58a58b1 288 typedef struct
bogdanm 65:5798e58a58b1 289 {
bogdanm 65:5798e58a58b1 290 __IO uint32_t TIMH; /* LCD Registers */
bogdanm 65:5798e58a58b1 291 __IO uint32_t TIMV;
bogdanm 65:5798e58a58b1 292 __IO uint32_t POL;
bogdanm 65:5798e58a58b1 293 __IO uint32_t LE;
bogdanm 65:5798e58a58b1 294 __IO uint32_t UPBASE;
bogdanm 65:5798e58a58b1 295 __IO uint32_t LPBASE;
bogdanm 65:5798e58a58b1 296 __IO uint32_t CTRL;
bogdanm 65:5798e58a58b1 297 __IO uint32_t INTMSK;
bogdanm 65:5798e58a58b1 298 __I uint32_t INTRAW;
bogdanm 65:5798e58a58b1 299 __I uint32_t INTSTAT;
bogdanm 65:5798e58a58b1 300 __O uint32_t INTCLR;
bogdanm 65:5798e58a58b1 301 __I uint32_t UPCURR;
bogdanm 65:5798e58a58b1 302 __I uint32_t LPCURR;
bogdanm 65:5798e58a58b1 303 uint32_t RESERVED0[115];
bogdanm 65:5798e58a58b1 304 __IO uint32_t PAL[128];
bogdanm 65:5798e58a58b1 305 uint32_t RESERVED1[256];
bogdanm 65:5798e58a58b1 306 __IO uint32_t CRSR_IMG[256];
bogdanm 65:5798e58a58b1 307 __IO uint32_t CRSR_CTRL;
bogdanm 65:5798e58a58b1 308 __IO uint32_t CRSR_CFG;
bogdanm 65:5798e58a58b1 309 __IO uint32_t CRSR_PAL0;
bogdanm 65:5798e58a58b1 310 __IO uint32_t CRSR_PAL1;
bogdanm 65:5798e58a58b1 311 __IO uint32_t CRSR_XY;
bogdanm 65:5798e58a58b1 312 __IO uint32_t CRSR_CLIP;
bogdanm 65:5798e58a58b1 313 uint32_t RESERVED2[2];
bogdanm 65:5798e58a58b1 314 __IO uint32_t CRSR_INTMSK;
bogdanm 65:5798e58a58b1 315 __O uint32_t CRSR_INTCLR;
bogdanm 65:5798e58a58b1 316 __I uint32_t CRSR_INTRAW;
bogdanm 65:5798e58a58b1 317 __I uint32_t CRSR_INTSTAT;
bogdanm 65:5798e58a58b1 318 } LPC_LCD_TypeDef;
bogdanm 65:5798e58a58b1 319
bogdanm 65:5798e58a58b1 320 /*------------- Universal Serial Bus (USB) -----------------------------------*/
bogdanm 65:5798e58a58b1 321 typedef struct
bogdanm 65:5798e58a58b1 322 {
bogdanm 65:5798e58a58b1 323 __I uint32_t Revision; /* USB Host Registers */
bogdanm 65:5798e58a58b1 324 __IO uint32_t Control;
bogdanm 65:5798e58a58b1 325 __IO uint32_t CommandStatus;
bogdanm 65:5798e58a58b1 326 __IO uint32_t InterruptStatus;
bogdanm 65:5798e58a58b1 327 __IO uint32_t InterruptEnable;
bogdanm 65:5798e58a58b1 328 __IO uint32_t InterruptDisable;
bogdanm 65:5798e58a58b1 329 __IO uint32_t HCCA;
bogdanm 65:5798e58a58b1 330 __I uint32_t PeriodCurrentED;
bogdanm 65:5798e58a58b1 331 __IO uint32_t ControlHeadED;
bogdanm 65:5798e58a58b1 332 __IO uint32_t ControlCurrentED;
bogdanm 65:5798e58a58b1 333 __IO uint32_t BulkHeadED;
bogdanm 65:5798e58a58b1 334 __IO uint32_t BulkCurrentED;
bogdanm 65:5798e58a58b1 335 __I uint32_t DoneHead;
bogdanm 65:5798e58a58b1 336 __IO uint32_t FmInterval;
bogdanm 65:5798e58a58b1 337 __I uint32_t FmRemaining;
bogdanm 65:5798e58a58b1 338 __I uint32_t FmNumber;
bogdanm 65:5798e58a58b1 339 __IO uint32_t PeriodicStart;
bogdanm 65:5798e58a58b1 340 __IO uint32_t LSTreshold;
bogdanm 65:5798e58a58b1 341 __IO uint32_t RhDescriptorA;
bogdanm 65:5798e58a58b1 342 __IO uint32_t RhDescriptorB;
bogdanm 65:5798e58a58b1 343 __IO uint32_t RhStatus;
bogdanm 65:5798e58a58b1 344 __IO uint32_t RhPortStatus1;
bogdanm 65:5798e58a58b1 345 __IO uint32_t RhPortStatus2;
bogdanm 65:5798e58a58b1 346 uint32_t RESERVED0[40];
bogdanm 65:5798e58a58b1 347 __I uint32_t Module_ID;
bogdanm 65:5798e58a58b1 348
bogdanm 65:5798e58a58b1 349 __I uint32_t IntSt; /* USB On-The-Go Registers */
bogdanm 65:5798e58a58b1 350 __IO uint32_t IntEn;
bogdanm 65:5798e58a58b1 351 __O uint32_t IntSet;
bogdanm 65:5798e58a58b1 352 __O uint32_t IntClr;
bogdanm 65:5798e58a58b1 353 __IO uint32_t StCtrl;
bogdanm 65:5798e58a58b1 354 __IO uint32_t Tmr;
bogdanm 65:5798e58a58b1 355 uint32_t RESERVED1[58];
bogdanm 65:5798e58a58b1 356
bogdanm 65:5798e58a58b1 357 __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
bogdanm 65:5798e58a58b1 358 __IO uint32_t DevIntEn;
bogdanm 65:5798e58a58b1 359 __O uint32_t DevIntClr;
bogdanm 65:5798e58a58b1 360 __O uint32_t DevIntSet;
bogdanm 65:5798e58a58b1 361
bogdanm 65:5798e58a58b1 362 __O uint32_t CmdCode; /* USB Device SIE Command Registers */
bogdanm 65:5798e58a58b1 363 __I uint32_t CmdData;
bogdanm 65:5798e58a58b1 364
bogdanm 65:5798e58a58b1 365 __I uint32_t RxData; /* USB Device Transfer Registers */
bogdanm 65:5798e58a58b1 366 __O uint32_t TxData;
bogdanm 65:5798e58a58b1 367 __I uint32_t RxPLen;
bogdanm 65:5798e58a58b1 368 __O uint32_t TxPLen;
bogdanm 65:5798e58a58b1 369 __IO uint32_t Ctrl;
bogdanm 65:5798e58a58b1 370 __O uint32_t DevIntPri;
bogdanm 65:5798e58a58b1 371
bogdanm 65:5798e58a58b1 372 __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
bogdanm 65:5798e58a58b1 373 __IO uint32_t EpIntEn;
bogdanm 65:5798e58a58b1 374 __O uint32_t EpIntClr;
bogdanm 65:5798e58a58b1 375 __O uint32_t EpIntSet;
bogdanm 65:5798e58a58b1 376 __O uint32_t EpIntPri;
bogdanm 65:5798e58a58b1 377
bogdanm 65:5798e58a58b1 378 __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
bogdanm 65:5798e58a58b1 379 __O uint32_t EpInd;
bogdanm 65:5798e58a58b1 380 __IO uint32_t MaxPSize;
bogdanm 65:5798e58a58b1 381
bogdanm 65:5798e58a58b1 382 __I uint32_t DMARSt; /* USB Device DMA Registers */
bogdanm 65:5798e58a58b1 383 __O uint32_t DMARClr;
bogdanm 65:5798e58a58b1 384 __O uint32_t DMARSet;
bogdanm 65:5798e58a58b1 385 uint32_t RESERVED2[9];
bogdanm 65:5798e58a58b1 386 __IO uint32_t UDCAH;
bogdanm 65:5798e58a58b1 387 __I uint32_t EpDMASt;
bogdanm 65:5798e58a58b1 388 __O uint32_t EpDMAEn;
bogdanm 65:5798e58a58b1 389 __O uint32_t EpDMADis;
bogdanm 65:5798e58a58b1 390 __I uint32_t DMAIntSt;
bogdanm 65:5798e58a58b1 391 __IO uint32_t DMAIntEn;
bogdanm 65:5798e58a58b1 392 uint32_t RESERVED3[2];
bogdanm 65:5798e58a58b1 393 __I uint32_t EoTIntSt;
bogdanm 65:5798e58a58b1 394 __O uint32_t EoTIntClr;
bogdanm 65:5798e58a58b1 395 __O uint32_t EoTIntSet;
bogdanm 65:5798e58a58b1 396 __I uint32_t NDDRIntSt;
bogdanm 65:5798e58a58b1 397 __O uint32_t NDDRIntClr;
bogdanm 65:5798e58a58b1 398 __O uint32_t NDDRIntSet;
bogdanm 65:5798e58a58b1 399 __I uint32_t SysErrIntSt;
bogdanm 65:5798e58a58b1 400 __O uint32_t SysErrIntClr;
bogdanm 65:5798e58a58b1 401 __O uint32_t SysErrIntSet;
bogdanm 65:5798e58a58b1 402 uint32_t RESERVED4[15];
bogdanm 65:5798e58a58b1 403
bogdanm 65:5798e58a58b1 404 union {
bogdanm 65:5798e58a58b1 405 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
bogdanm 65:5798e58a58b1 406 __O uint32_t I2C_TX;
bogdanm 65:5798e58a58b1 407 };
bogdanm 65:5798e58a58b1 408 __IO uint32_t I2C_STS;
bogdanm 65:5798e58a58b1 409 __IO uint32_t I2C_CTL;
bogdanm 65:5798e58a58b1 410 __IO uint32_t I2C_CLKHI;
bogdanm 65:5798e58a58b1 411 __O uint32_t I2C_CLKLO;
bogdanm 65:5798e58a58b1 412 uint32_t RESERVED5[824];
bogdanm 65:5798e58a58b1 413
bogdanm 65:5798e58a58b1 414 union {
bogdanm 65:5798e58a58b1 415 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
bogdanm 65:5798e58a58b1 416 __IO uint32_t OTGClkCtrl;
bogdanm 65:5798e58a58b1 417 };
bogdanm 65:5798e58a58b1 418 union {
bogdanm 65:5798e58a58b1 419 __I uint32_t USBClkSt;
bogdanm 65:5798e58a58b1 420 __I uint32_t OTGClkSt;
bogdanm 65:5798e58a58b1 421 };
bogdanm 65:5798e58a58b1 422 } LPC_USB_TypeDef;
bogdanm 65:5798e58a58b1 423
bogdanm 65:5798e58a58b1 424 /*------------- CRC Engine (CRC) -----------------------------------------*/
bogdanm 65:5798e58a58b1 425 typedef struct
bogdanm 65:5798e58a58b1 426 {
bogdanm 65:5798e58a58b1 427 __IO uint32_t MODE;
bogdanm 65:5798e58a58b1 428 __IO uint32_t SEED;
bogdanm 65:5798e58a58b1 429 union {
bogdanm 65:5798e58a58b1 430 __I uint32_t SUM;
bogdanm 65:5798e58a58b1 431 struct {
bogdanm 65:5798e58a58b1 432 __O uint32_t DATA;
bogdanm 65:5798e58a58b1 433 } WR_DATA_DWORD;
bogdanm 65:5798e58a58b1 434
bogdanm 65:5798e58a58b1 435 struct {
bogdanm 65:5798e58a58b1 436 __O uint16_t DATA;
bogdanm 65:5798e58a58b1 437 uint16_t RESERVED;
bogdanm 65:5798e58a58b1 438 }WR_DATA_WORD;
bogdanm 65:5798e58a58b1 439
bogdanm 65:5798e58a58b1 440 struct {
bogdanm 65:5798e58a58b1 441 __O uint8_t DATA;
bogdanm 65:5798e58a58b1 442 uint8_t RESERVED[3];
bogdanm 65:5798e58a58b1 443 }WR_DATA_BYTE;
bogdanm 65:5798e58a58b1 444 };
bogdanm 65:5798e58a58b1 445 } LPC_CRC_TypeDef;
bogdanm 65:5798e58a58b1 446 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 65:5798e58a58b1 447 typedef struct
bogdanm 65:5798e58a58b1 448 {
bogdanm 65:5798e58a58b1 449 __IO uint32_t DIR;
bogdanm 65:5798e58a58b1 450 uint32_t RESERVED0[3];
bogdanm 65:5798e58a58b1 451 __IO uint32_t MASK;
bogdanm 65:5798e58a58b1 452 __IO uint32_t PIN;
bogdanm 65:5798e58a58b1 453 __IO uint32_t SET;
bogdanm 65:5798e58a58b1 454 __O uint32_t CLR;
bogdanm 65:5798e58a58b1 455 } LPC_GPIO_TypeDef;
bogdanm 65:5798e58a58b1 456
bogdanm 65:5798e58a58b1 457 typedef struct
bogdanm 65:5798e58a58b1 458 {
bogdanm 65:5798e58a58b1 459 __I uint32_t IntStatus;
bogdanm 65:5798e58a58b1 460 __I uint32_t IO0IntStatR;
bogdanm 65:5798e58a58b1 461 __I uint32_t IO0IntStatF;
bogdanm 65:5798e58a58b1 462 __O uint32_t IO0IntClr;
bogdanm 65:5798e58a58b1 463 __IO uint32_t IO0IntEnR;
bogdanm 65:5798e58a58b1 464 __IO uint32_t IO0IntEnF;
bogdanm 65:5798e58a58b1 465 uint32_t RESERVED0[3];
bogdanm 65:5798e58a58b1 466 __I uint32_t IO2IntStatR;
bogdanm 65:5798e58a58b1 467 __I uint32_t IO2IntStatF;
bogdanm 65:5798e58a58b1 468 __O uint32_t IO2IntClr;
bogdanm 65:5798e58a58b1 469 __IO uint32_t IO2IntEnR;
bogdanm 65:5798e58a58b1 470 __IO uint32_t IO2IntEnF;
bogdanm 65:5798e58a58b1 471 } LPC_GPIOINT_TypeDef;
bogdanm 65:5798e58a58b1 472
bogdanm 65:5798e58a58b1 473 /*------------- External Memory Controller (EMC) -----------------------------*/
bogdanm 65:5798e58a58b1 474 typedef struct
bogdanm 65:5798e58a58b1 475 {
bogdanm 65:5798e58a58b1 476 __IO uint32_t Control;
bogdanm 65:5798e58a58b1 477 __I uint32_t Status;
bogdanm 65:5798e58a58b1 478 __IO uint32_t Config;
bogdanm 65:5798e58a58b1 479 uint32_t RESERVED0[5];
bogdanm 65:5798e58a58b1 480 __IO uint32_t DynamicControl;
bogdanm 65:5798e58a58b1 481 __IO uint32_t DynamicRefresh;
bogdanm 65:5798e58a58b1 482 __IO uint32_t DynamicReadConfig;
bogdanm 65:5798e58a58b1 483 uint32_t RESERVED1[1];
bogdanm 65:5798e58a58b1 484 __IO uint32_t DynamicRP;
bogdanm 65:5798e58a58b1 485 __IO uint32_t DynamicRAS;
bogdanm 65:5798e58a58b1 486 __IO uint32_t DynamicSREX;
bogdanm 65:5798e58a58b1 487 __IO uint32_t DynamicAPR;
bogdanm 65:5798e58a58b1 488 __IO uint32_t DynamicDAL;
bogdanm 65:5798e58a58b1 489 __IO uint32_t DynamicWR;
bogdanm 65:5798e58a58b1 490 __IO uint32_t DynamicRC;
bogdanm 65:5798e58a58b1 491 __IO uint32_t DynamicRFC;
bogdanm 65:5798e58a58b1 492 __IO uint32_t DynamicXSR;
bogdanm 65:5798e58a58b1 493 __IO uint32_t DynamicRRD;
bogdanm 65:5798e58a58b1 494 __IO uint32_t DynamicMRD;
bogdanm 65:5798e58a58b1 495 uint32_t RESERVED2[9];
bogdanm 65:5798e58a58b1 496 __IO uint32_t StaticExtendedWait;
bogdanm 65:5798e58a58b1 497 uint32_t RESERVED3[31];
bogdanm 65:5798e58a58b1 498 __IO uint32_t DynamicConfig0;
bogdanm 65:5798e58a58b1 499 __IO uint32_t DynamicRasCas0;
bogdanm 65:5798e58a58b1 500 uint32_t RESERVED4[6];
bogdanm 65:5798e58a58b1 501 __IO uint32_t DynamicConfig1;
bogdanm 65:5798e58a58b1 502 __IO uint32_t DynamicRasCas1;
bogdanm 65:5798e58a58b1 503 uint32_t RESERVED5[6];
bogdanm 65:5798e58a58b1 504 __IO uint32_t DynamicConfig2;
bogdanm 65:5798e58a58b1 505 __IO uint32_t DynamicRasCas2;
bogdanm 65:5798e58a58b1 506 uint32_t RESERVED6[6];
bogdanm 65:5798e58a58b1 507 __IO uint32_t DynamicConfig3;
bogdanm 65:5798e58a58b1 508 __IO uint32_t DynamicRasCas3;
bogdanm 65:5798e58a58b1 509 uint32_t RESERVED7[38];
bogdanm 65:5798e58a58b1 510 __IO uint32_t StaticConfig0;
bogdanm 65:5798e58a58b1 511 __IO uint32_t StaticWaitWen0;
bogdanm 65:5798e58a58b1 512 __IO uint32_t StaticWaitOen0;
bogdanm 65:5798e58a58b1 513 __IO uint32_t StaticWaitRd0;
bogdanm 65:5798e58a58b1 514 __IO uint32_t StaticWaitPage0;
bogdanm 65:5798e58a58b1 515 __IO uint32_t StaticWaitWr0;
bogdanm 65:5798e58a58b1 516 __IO uint32_t StaticWaitTurn0;
bogdanm 65:5798e58a58b1 517 uint32_t RESERVED8[1];
bogdanm 65:5798e58a58b1 518 __IO uint32_t StaticConfig1;
bogdanm 65:5798e58a58b1 519 __IO uint32_t StaticWaitWen1;
bogdanm 65:5798e58a58b1 520 __IO uint32_t StaticWaitOen1;
bogdanm 65:5798e58a58b1 521 __IO uint32_t StaticWaitRd1;
bogdanm 65:5798e58a58b1 522 __IO uint32_t StaticWaitPage1;
bogdanm 65:5798e58a58b1 523 __IO uint32_t StaticWaitWr1;
bogdanm 65:5798e58a58b1 524 __IO uint32_t StaticWaitTurn1;
bogdanm 65:5798e58a58b1 525 uint32_t RESERVED9[1];
bogdanm 65:5798e58a58b1 526 __IO uint32_t StaticConfig2;
bogdanm 65:5798e58a58b1 527 __IO uint32_t StaticWaitWen2;
bogdanm 65:5798e58a58b1 528 __IO uint32_t StaticWaitOen2;
bogdanm 65:5798e58a58b1 529 __IO uint32_t StaticWaitRd2;
bogdanm 65:5798e58a58b1 530 __IO uint32_t StaticWaitPage2;
bogdanm 65:5798e58a58b1 531 __IO uint32_t StaticWaitWr2;
bogdanm 65:5798e58a58b1 532 __IO uint32_t StaticWaitTurn2;
bogdanm 65:5798e58a58b1 533 uint32_t RESERVED10[1];
bogdanm 65:5798e58a58b1 534 __IO uint32_t StaticConfig3;
bogdanm 65:5798e58a58b1 535 __IO uint32_t StaticWaitWen3;
bogdanm 65:5798e58a58b1 536 __IO uint32_t StaticWaitOen3;
bogdanm 65:5798e58a58b1 537 __IO uint32_t StaticWaitRd3;
bogdanm 65:5798e58a58b1 538 __IO uint32_t StaticWaitPage3;
bogdanm 65:5798e58a58b1 539 __IO uint32_t StaticWaitWr3;
bogdanm 65:5798e58a58b1 540 __IO uint32_t StaticWaitTurn3;
bogdanm 65:5798e58a58b1 541 } LPC_EMC_TypeDef;
bogdanm 65:5798e58a58b1 542
bogdanm 65:5798e58a58b1 543 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 65:5798e58a58b1 544 typedef struct
bogdanm 65:5798e58a58b1 545 {
bogdanm 65:5798e58a58b1 546 __IO uint8_t MOD;
bogdanm 65:5798e58a58b1 547 uint8_t RESERVED0[3];
bogdanm 65:5798e58a58b1 548 __IO uint32_t TC;
bogdanm 65:5798e58a58b1 549 __O uint8_t FEED;
bogdanm 65:5798e58a58b1 550 uint8_t RESERVED1[3];
bogdanm 65:5798e58a58b1 551 __I uint32_t TV;
bogdanm 65:5798e58a58b1 552 uint32_t RESERVED2;
bogdanm 65:5798e58a58b1 553 __IO uint32_t WARNINT;
bogdanm 65:5798e58a58b1 554 __IO uint32_t WINDOW;
bogdanm 65:5798e58a58b1 555 } LPC_WDT_TypeDef;
bogdanm 65:5798e58a58b1 556
bogdanm 65:5798e58a58b1 557 /*------------- Timer (TIM) --------------------------------------------------*/
bogdanm 65:5798e58a58b1 558 typedef struct
bogdanm 65:5798e58a58b1 559 {
bogdanm 65:5798e58a58b1 560 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
bogdanm 65:5798e58a58b1 561 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
bogdanm 65:5798e58a58b1 562 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
bogdanm 65:5798e58a58b1 563 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
bogdanm 65:5798e58a58b1 564 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
bogdanm 65:5798e58a58b1 565 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
bogdanm 65:5798e58a58b1 566 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
bogdanm 65:5798e58a58b1 567 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
bogdanm 65:5798e58a58b1 568 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
bogdanm 65:5798e58a58b1 569 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
bogdanm 65:5798e58a58b1 570 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
bogdanm 65:5798e58a58b1 571 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
bogdanm 65:5798e58a58b1 572 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
bogdanm 65:5798e58a58b1 573 uint32_t RESERVED0[2];
bogdanm 65:5798e58a58b1 574 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
bogdanm 65:5798e58a58b1 575 uint32_t RESERVED1[12];
bogdanm 65:5798e58a58b1 576 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
bogdanm 65:5798e58a58b1 577 } LPC_TIM_TypeDef;
bogdanm 65:5798e58a58b1 578
bogdanm 65:5798e58a58b1 579
bogdanm 65:5798e58a58b1 580 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
bogdanm 65:5798e58a58b1 581 typedef struct
bogdanm 65:5798e58a58b1 582 {
bogdanm 65:5798e58a58b1 583 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
bogdanm 65:5798e58a58b1 584 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
bogdanm 65:5798e58a58b1 585 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
bogdanm 65:5798e58a58b1 586 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
bogdanm 65:5798e58a58b1 587 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
bogdanm 65:5798e58a58b1 588 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
bogdanm 65:5798e58a58b1 589 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
bogdanm 65:5798e58a58b1 590 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
bogdanm 65:5798e58a58b1 591 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
bogdanm 65:5798e58a58b1 592 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
bogdanm 65:5798e58a58b1 593 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
bogdanm 65:5798e58a58b1 594 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
bogdanm 65:5798e58a58b1 595 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
bogdanm 65:5798e58a58b1 596 __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
bogdanm 65:5798e58a58b1 597 __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
bogdanm 65:5798e58a58b1 598 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 599 __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
bogdanm 65:5798e58a58b1 600 __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
bogdanm 65:5798e58a58b1 601 __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
bogdanm 65:5798e58a58b1 602 __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
bogdanm 65:5798e58a58b1 603 __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
bogdanm 65:5798e58a58b1 604 uint32_t RESERVED1[7];
bogdanm 65:5798e58a58b1 605 __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
bogdanm 65:5798e58a58b1 606 } LPC_PWM_TypeDef;
bogdanm 65:5798e58a58b1 607
bogdanm 65:5798e58a58b1 608 /*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
bogdanm 65:5798e58a58b1 609 /* There are three types of UARTs on the chip:
bogdanm 65:5798e58a58b1 610 (1) UART0,UART2, and UART3 are the standard UART.
bogdanm 65:5798e58a58b1 611 (2) UART1 is the standard with modem capability.
bogdanm 65:5798e58a58b1 612 (3) USART(UART4) is the sync/async UART with smart card capability.
bogdanm 65:5798e58a58b1 613 More details can be found on the Users Manual. */
bogdanm 65:5798e58a58b1 614
bogdanm 65:5798e58a58b1 615 #if 0
bogdanm 65:5798e58a58b1 616 typedef struct
bogdanm 65:5798e58a58b1 617 {
bogdanm 65:5798e58a58b1 618 union {
bogdanm 65:5798e58a58b1 619 __I uint8_t RBR;
bogdanm 65:5798e58a58b1 620 __O uint8_t THR;
bogdanm 65:5798e58a58b1 621 __IO uint8_t DLL;
bogdanm 65:5798e58a58b1 622 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 623 };
bogdanm 65:5798e58a58b1 624 union {
bogdanm 65:5798e58a58b1 625 __IO uint8_t DLM;
bogdanm 65:5798e58a58b1 626 __IO uint32_t IER;
bogdanm 65:5798e58a58b1 627 };
bogdanm 65:5798e58a58b1 628 union {
bogdanm 65:5798e58a58b1 629 __I uint32_t IIR;
bogdanm 65:5798e58a58b1 630 __O uint8_t FCR;
bogdanm 65:5798e58a58b1 631 };
bogdanm 65:5798e58a58b1 632 __IO uint8_t LCR;
bogdanm 65:5798e58a58b1 633 uint8_t RESERVED1[7];
bogdanm 65:5798e58a58b1 634 __I uint8_t LSR;
bogdanm 65:5798e58a58b1 635 uint8_t RESERVED2[7];
bogdanm 65:5798e58a58b1 636 __IO uint8_t SCR;
bogdanm 65:5798e58a58b1 637 uint8_t RESERVED3[3];
bogdanm 65:5798e58a58b1 638 __IO uint32_t ACR;
bogdanm 65:5798e58a58b1 639 __IO uint8_t ICR;
bogdanm 65:5798e58a58b1 640 uint8_t RESERVED4[3];
bogdanm 65:5798e58a58b1 641 __IO uint8_t FDR;
bogdanm 65:5798e58a58b1 642 uint8_t RESERVED5[7];
bogdanm 65:5798e58a58b1 643 __IO uint8_t TER;
bogdanm 65:5798e58a58b1 644 uint8_t RESERVED6[39];
bogdanm 65:5798e58a58b1 645 __I uint8_t FIFOLVL;
bogdanm 65:5798e58a58b1 646 } LPC_UART_TypeDef;
bogdanm 65:5798e58a58b1 647 #else
bogdanm 65:5798e58a58b1 648 typedef struct
bogdanm 65:5798e58a58b1 649 {
bogdanm 65:5798e58a58b1 650 union
bogdanm 65:5798e58a58b1 651 {
bogdanm 65:5798e58a58b1 652 __I uint8_t RBR;
bogdanm 65:5798e58a58b1 653 __O uint8_t THR;
bogdanm 65:5798e58a58b1 654 __IO uint8_t DLL;
bogdanm 65:5798e58a58b1 655 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 656 };
bogdanm 65:5798e58a58b1 657 union
bogdanm 65:5798e58a58b1 658 {
bogdanm 65:5798e58a58b1 659 __IO uint8_t DLM;
bogdanm 65:5798e58a58b1 660 __IO uint32_t IER;
bogdanm 65:5798e58a58b1 661 };
bogdanm 65:5798e58a58b1 662 union
bogdanm 65:5798e58a58b1 663 {
bogdanm 65:5798e58a58b1 664 __I uint32_t IIR;
bogdanm 65:5798e58a58b1 665 __O uint8_t FCR;
bogdanm 65:5798e58a58b1 666 };
bogdanm 65:5798e58a58b1 667 __IO uint8_t LCR;
bogdanm 65:5798e58a58b1 668 uint8_t RESERVED1[7];//Reserved
bogdanm 65:5798e58a58b1 669 __I uint8_t LSR;
bogdanm 65:5798e58a58b1 670 uint8_t RESERVED2[7];//Reserved
bogdanm 65:5798e58a58b1 671 __IO uint8_t SCR;
bogdanm 65:5798e58a58b1 672 uint8_t RESERVED3[3];//Reserved
bogdanm 65:5798e58a58b1 673 __IO uint32_t ACR;
bogdanm 65:5798e58a58b1 674 __IO uint8_t ICR;
bogdanm 65:5798e58a58b1 675 uint8_t RESERVED4[3];//Reserved
bogdanm 65:5798e58a58b1 676 __IO uint8_t FDR;
bogdanm 65:5798e58a58b1 677 uint8_t RESERVED5[7];//Reserved
bogdanm 65:5798e58a58b1 678 __IO uint8_t TER;
bogdanm 65:5798e58a58b1 679 uint8_t RESERVED8[27];//Reserved
bogdanm 65:5798e58a58b1 680 __IO uint8_t RS485CTRL;
bogdanm 65:5798e58a58b1 681 uint8_t RESERVED9[3];//Reserved
bogdanm 65:5798e58a58b1 682 __IO uint8_t ADRMATCH;
bogdanm 65:5798e58a58b1 683 uint8_t RESERVED10[3];//Reserved
bogdanm 65:5798e58a58b1 684 __IO uint8_t RS485DLY;
bogdanm 65:5798e58a58b1 685 uint8_t RESERVED11[3];//Reserved
bogdanm 65:5798e58a58b1 686 __I uint8_t FIFOLVL;
bogdanm 65:5798e58a58b1 687 }LPC_UART_TypeDef;
bogdanm 65:5798e58a58b1 688 #endif
bogdanm 65:5798e58a58b1 689
bogdanm 65:5798e58a58b1 690
bogdanm 65:5798e58a58b1 691 typedef struct
bogdanm 65:5798e58a58b1 692 {
bogdanm 65:5798e58a58b1 693 union {
bogdanm 65:5798e58a58b1 694 __I uint8_t RBR;
bogdanm 65:5798e58a58b1 695 __O uint8_t THR;
bogdanm 65:5798e58a58b1 696 __IO uint8_t DLL;
bogdanm 65:5798e58a58b1 697 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 698 };
bogdanm 65:5798e58a58b1 699 union {
bogdanm 65:5798e58a58b1 700 __IO uint8_t DLM;
bogdanm 65:5798e58a58b1 701 __IO uint32_t IER;
bogdanm 65:5798e58a58b1 702 };
bogdanm 65:5798e58a58b1 703 union {
bogdanm 65:5798e58a58b1 704 __I uint32_t IIR;
bogdanm 65:5798e58a58b1 705 __O uint8_t FCR;
bogdanm 65:5798e58a58b1 706 };
bogdanm 65:5798e58a58b1 707 __IO uint8_t LCR;
bogdanm 65:5798e58a58b1 708 uint8_t RESERVED1[3];
bogdanm 65:5798e58a58b1 709 __IO uint8_t MCR;
bogdanm 65:5798e58a58b1 710 uint8_t RESERVED2[3];
bogdanm 65:5798e58a58b1 711 __I uint8_t LSR;
bogdanm 65:5798e58a58b1 712 uint8_t RESERVED3[3];
bogdanm 65:5798e58a58b1 713 __I uint8_t MSR;
bogdanm 65:5798e58a58b1 714 uint8_t RESERVED4[3];
bogdanm 65:5798e58a58b1 715 __IO uint8_t SCR;
bogdanm 65:5798e58a58b1 716 uint8_t RESERVED5[3];
bogdanm 65:5798e58a58b1 717 __IO uint32_t ACR;
bogdanm 65:5798e58a58b1 718 uint32_t RESERVED6;
bogdanm 65:5798e58a58b1 719 __IO uint32_t FDR;
bogdanm 65:5798e58a58b1 720 uint32_t RESERVED7;
bogdanm 65:5798e58a58b1 721 __IO uint8_t TER;
bogdanm 65:5798e58a58b1 722 uint8_t RESERVED8[27];
bogdanm 65:5798e58a58b1 723 __IO uint8_t RS485CTRL;
bogdanm 65:5798e58a58b1 724 uint8_t RESERVED9[3];
bogdanm 65:5798e58a58b1 725 __IO uint8_t ADRMATCH;
bogdanm 65:5798e58a58b1 726 uint8_t RESERVED10[3];
bogdanm 65:5798e58a58b1 727 __IO uint8_t RS485DLY;
bogdanm 65:5798e58a58b1 728 uint8_t RESERVED11[3];
bogdanm 65:5798e58a58b1 729 __I uint8_t FIFOLVL;
bogdanm 65:5798e58a58b1 730 } LPC_UART1_TypeDef;
bogdanm 65:5798e58a58b1 731
bogdanm 65:5798e58a58b1 732 typedef struct
bogdanm 65:5798e58a58b1 733 {
bogdanm 65:5798e58a58b1 734 union {
bogdanm 65:5798e58a58b1 735 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
bogdanm 65:5798e58a58b1 736 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
bogdanm 65:5798e58a58b1 737 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
bogdanm 65:5798e58a58b1 738 };
bogdanm 65:5798e58a58b1 739 union {
bogdanm 65:5798e58a58b1 740 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
bogdanm 65:5798e58a58b1 741 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
bogdanm 65:5798e58a58b1 742 };
bogdanm 65:5798e58a58b1 743 union {
bogdanm 65:5798e58a58b1 744 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
bogdanm 65:5798e58a58b1 745 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
bogdanm 65:5798e58a58b1 746 };
bogdanm 65:5798e58a58b1 747 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
bogdanm 65:5798e58a58b1 748 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
bogdanm 65:5798e58a58b1 749 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
bogdanm 65:5798e58a58b1 750 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
bogdanm 65:5798e58a58b1 751 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
bogdanm 65:5798e58a58b1 752 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
bogdanm 65:5798e58a58b1 753 __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
bogdanm 65:5798e58a58b1 754 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
bogdanm 65:5798e58a58b1 755 __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
bogdanm 65:5798e58a58b1 756 __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
bogdanm 65:5798e58a58b1 757 __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
bogdanm 65:5798e58a58b1 758 uint32_t RESERVED0[2];
bogdanm 65:5798e58a58b1 759 __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
bogdanm 65:5798e58a58b1 760 uint32_t RESERVED1;
bogdanm 65:5798e58a58b1 761 __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
bogdanm 65:5798e58a58b1 762 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
bogdanm 65:5798e58a58b1 763 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
bogdanm 65:5798e58a58b1 764 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
bogdanm 65:5798e58a58b1 765 __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
bogdanm 65:5798e58a58b1 766 __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
bogdanm 65:5798e58a58b1 767 uint32_t RESERVED2[989];
bogdanm 65:5798e58a58b1 768 __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
bogdanm 65:5798e58a58b1 769 __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
bogdanm 65:5798e58a58b1 770 __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
bogdanm 65:5798e58a58b1 771 __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
bogdanm 65:5798e58a58b1 772 __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
bogdanm 65:5798e58a58b1 773 __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
bogdanm 65:5798e58a58b1 774 __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
bogdanm 65:5798e58a58b1 775 uint32_t RESERVED3[3];
bogdanm 65:5798e58a58b1 776 __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
bogdanm 65:5798e58a58b1 777 } LPC_UART4_TypeDef;
bogdanm 65:5798e58a58b1 778 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 65:5798e58a58b1 779 typedef struct
bogdanm 65:5798e58a58b1 780 {
bogdanm 65:5798e58a58b1 781 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
bogdanm 65:5798e58a58b1 782 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
bogdanm 65:5798e58a58b1 783 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
bogdanm 65:5798e58a58b1 784 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
bogdanm 65:5798e58a58b1 785 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
bogdanm 65:5798e58a58b1 786 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
bogdanm 65:5798e58a58b1 787 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
bogdanm 65:5798e58a58b1 788 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
bogdanm 65:5798e58a58b1 789 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
bogdanm 65:5798e58a58b1 790 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
bogdanm 65:5798e58a58b1 791 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
bogdanm 65:5798e58a58b1 792 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
bogdanm 65:5798e58a58b1 793 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
bogdanm 65:5798e58a58b1 794 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
bogdanm 65:5798e58a58b1 795 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
bogdanm 65:5798e58a58b1 796 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
bogdanm 65:5798e58a58b1 797 } LPC_I2C_TypeDef;
bogdanm 65:5798e58a58b1 798
bogdanm 65:5798e58a58b1 799 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
bogdanm 65:5798e58a58b1 800 typedef struct
bogdanm 65:5798e58a58b1 801 {
bogdanm 65:5798e58a58b1 802 __IO uint8_t ILR;
bogdanm 65:5798e58a58b1 803 uint8_t RESERVED0[7];
bogdanm 65:5798e58a58b1 804 __IO uint8_t CCR;
bogdanm 65:5798e58a58b1 805 uint8_t RESERVED1[3];
bogdanm 65:5798e58a58b1 806 __IO uint8_t CIIR;
bogdanm 65:5798e58a58b1 807 uint8_t RESERVED2[3];
bogdanm 65:5798e58a58b1 808 __IO uint8_t AMR;
bogdanm 65:5798e58a58b1 809 uint8_t RESERVED3[3];
bogdanm 65:5798e58a58b1 810 __I uint32_t CTIME0;
bogdanm 65:5798e58a58b1 811 __I uint32_t CTIME1;
bogdanm 65:5798e58a58b1 812 __I uint32_t CTIME2;
bogdanm 65:5798e58a58b1 813 __IO uint8_t SEC;
bogdanm 65:5798e58a58b1 814 uint8_t RESERVED4[3];
bogdanm 65:5798e58a58b1 815 __IO uint8_t MIN;
bogdanm 65:5798e58a58b1 816 uint8_t RESERVED5[3];
bogdanm 65:5798e58a58b1 817 __IO uint8_t HOUR;
bogdanm 65:5798e58a58b1 818 uint8_t RESERVED6[3];
bogdanm 65:5798e58a58b1 819 __IO uint8_t DOM;
bogdanm 65:5798e58a58b1 820 uint8_t RESERVED7[3];
bogdanm 65:5798e58a58b1 821 __IO uint8_t DOW;
bogdanm 65:5798e58a58b1 822 uint8_t RESERVED8[3];
bogdanm 65:5798e58a58b1 823 __IO uint16_t DOY;
bogdanm 65:5798e58a58b1 824 uint16_t RESERVED9;
bogdanm 65:5798e58a58b1 825 __IO uint8_t MONTH;
bogdanm 65:5798e58a58b1 826 uint8_t RESERVED10[3];
bogdanm 65:5798e58a58b1 827 __IO uint16_t YEAR;
bogdanm 65:5798e58a58b1 828 uint16_t RESERVED11;
bogdanm 65:5798e58a58b1 829 __IO uint32_t CALIBRATION;
bogdanm 65:5798e58a58b1 830 __IO uint32_t GPREG0;
bogdanm 65:5798e58a58b1 831 __IO uint32_t GPREG1;
bogdanm 65:5798e58a58b1 832 __IO uint32_t GPREG2;
bogdanm 65:5798e58a58b1 833 __IO uint32_t GPREG3;
bogdanm 65:5798e58a58b1 834 __IO uint32_t GPREG4;
bogdanm 65:5798e58a58b1 835 __IO uint8_t RTC_AUXEN;
bogdanm 65:5798e58a58b1 836 uint8_t RESERVED12[3];
bogdanm 65:5798e58a58b1 837 __IO uint8_t RTC_AUX;
bogdanm 65:5798e58a58b1 838 uint8_t RESERVED13[3];
bogdanm 65:5798e58a58b1 839 __IO uint8_t ALSEC;
bogdanm 65:5798e58a58b1 840 uint8_t RESERVED14[3];
bogdanm 65:5798e58a58b1 841 __IO uint8_t ALMIN;
bogdanm 65:5798e58a58b1 842 uint8_t RESERVED15[3];
bogdanm 65:5798e58a58b1 843 __IO uint8_t ALHOUR;
bogdanm 65:5798e58a58b1 844 uint8_t RESERVED16[3];
bogdanm 65:5798e58a58b1 845 __IO uint8_t ALDOM;
bogdanm 65:5798e58a58b1 846 uint8_t RESERVED17[3];
bogdanm 65:5798e58a58b1 847 __IO uint8_t ALDOW;
bogdanm 65:5798e58a58b1 848 uint8_t RESERVED18[3];
bogdanm 65:5798e58a58b1 849 __IO uint16_t ALDOY;
bogdanm 65:5798e58a58b1 850 uint16_t RESERVED19;
bogdanm 65:5798e58a58b1 851 __IO uint8_t ALMON;
bogdanm 65:5798e58a58b1 852 uint8_t RESERVED20[3];
bogdanm 65:5798e58a58b1 853 __IO uint16_t ALYEAR;
bogdanm 65:5798e58a58b1 854 uint16_t RESERVED21;
bogdanm 65:5798e58a58b1 855 __IO uint32_t ERSTATUS;
bogdanm 65:5798e58a58b1 856 __IO uint32_t ERCONTROL;
bogdanm 65:5798e58a58b1 857 __IO uint32_t ERCOUNTERS;
bogdanm 65:5798e58a58b1 858 uint32_t RESERVED22;
bogdanm 65:5798e58a58b1 859 __IO uint32_t ERFIRSTSTAMP0;
bogdanm 65:5798e58a58b1 860 __IO uint32_t ERFIRSTSTAMP1;
bogdanm 65:5798e58a58b1 861 __IO uint32_t ERFIRSTSTAMP2;
bogdanm 65:5798e58a58b1 862 uint32_t RESERVED23;
bogdanm 65:5798e58a58b1 863 __IO uint32_t ERLASTSTAMP0;
bogdanm 65:5798e58a58b1 864 __IO uint32_t ERLASTSTAMP1;
bogdanm 65:5798e58a58b1 865 __IO uint32_t ERLASTSTAMP2;
bogdanm 65:5798e58a58b1 866 } LPC_RTC_TypeDef;
bogdanm 65:5798e58a58b1 867
bogdanm 65:5798e58a58b1 868
bogdanm 65:5798e58a58b1 869
bogdanm 65:5798e58a58b1 870 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
bogdanm 65:5798e58a58b1 871 typedef struct
bogdanm 65:5798e58a58b1 872 {
bogdanm 65:5798e58a58b1 873 __IO uint32_t P0_0; /* 0x000 */
bogdanm 65:5798e58a58b1 874 __IO uint32_t P0_1;
bogdanm 65:5798e58a58b1 875 __IO uint32_t P0_2;
bogdanm 65:5798e58a58b1 876 __IO uint32_t P0_3;
bogdanm 65:5798e58a58b1 877 __IO uint32_t P0_4;
bogdanm 65:5798e58a58b1 878 __IO uint32_t P0_5;
bogdanm 65:5798e58a58b1 879 __IO uint32_t P0_6;
bogdanm 65:5798e58a58b1 880 __IO uint32_t P0_7;
bogdanm 65:5798e58a58b1 881
bogdanm 65:5798e58a58b1 882 __IO uint32_t P0_8; /* 0x020 */
bogdanm 65:5798e58a58b1 883 __IO uint32_t P0_9;
bogdanm 65:5798e58a58b1 884 __IO uint32_t P0_10;
bogdanm 65:5798e58a58b1 885 __IO uint32_t P0_11;
bogdanm 65:5798e58a58b1 886 __IO uint32_t P0_12;
bogdanm 65:5798e58a58b1 887 __IO uint32_t P0_13;
bogdanm 65:5798e58a58b1 888 __IO uint32_t P0_14;
bogdanm 65:5798e58a58b1 889 __IO uint32_t P0_15;
bogdanm 65:5798e58a58b1 890
bogdanm 65:5798e58a58b1 891 __IO uint32_t P0_16; /* 0x040 */
bogdanm 65:5798e58a58b1 892 __IO uint32_t P0_17;
bogdanm 65:5798e58a58b1 893 __IO uint32_t P0_18;
bogdanm 65:5798e58a58b1 894 __IO uint32_t P0_19;
bogdanm 65:5798e58a58b1 895 __IO uint32_t P0_20;
bogdanm 65:5798e58a58b1 896 __IO uint32_t P0_21;
bogdanm 65:5798e58a58b1 897 __IO uint32_t P0_22;
bogdanm 65:5798e58a58b1 898 __IO uint32_t P0_23;
bogdanm 65:5798e58a58b1 899
bogdanm 65:5798e58a58b1 900 __IO uint32_t P0_24; /* 0x060 */
bogdanm 65:5798e58a58b1 901 __IO uint32_t P0_25;
bogdanm 65:5798e58a58b1 902 __IO uint32_t P0_26;
bogdanm 65:5798e58a58b1 903 __IO uint32_t P0_27;
bogdanm 65:5798e58a58b1 904 __IO uint32_t P0_28;
bogdanm 65:5798e58a58b1 905 __IO uint32_t P0_29;
bogdanm 65:5798e58a58b1 906 __IO uint32_t P0_30;
bogdanm 65:5798e58a58b1 907 __IO uint32_t P0_31;
bogdanm 65:5798e58a58b1 908
bogdanm 65:5798e58a58b1 909 __IO uint32_t P1_0; /* 0x080 */
bogdanm 65:5798e58a58b1 910 __IO uint32_t P1_1;
bogdanm 65:5798e58a58b1 911 __IO uint32_t P1_2;
bogdanm 65:5798e58a58b1 912 __IO uint32_t P1_3;
bogdanm 65:5798e58a58b1 913 __IO uint32_t P1_4;
bogdanm 65:5798e58a58b1 914 __IO uint32_t P1_5;
bogdanm 65:5798e58a58b1 915 __IO uint32_t P1_6;
bogdanm 65:5798e58a58b1 916 __IO uint32_t P1_7;
bogdanm 65:5798e58a58b1 917
bogdanm 65:5798e58a58b1 918 __IO uint32_t P1_8; /* 0x0A0 */
bogdanm 65:5798e58a58b1 919 __IO uint32_t P1_9;
bogdanm 65:5798e58a58b1 920 __IO uint32_t P1_10;
bogdanm 65:5798e58a58b1 921 __IO uint32_t P1_11;
bogdanm 65:5798e58a58b1 922 __IO uint32_t P1_12;
bogdanm 65:5798e58a58b1 923 __IO uint32_t P1_13;
bogdanm 65:5798e58a58b1 924 __IO uint32_t P1_14;
bogdanm 65:5798e58a58b1 925 __IO uint32_t P1_15;
bogdanm 65:5798e58a58b1 926
bogdanm 65:5798e58a58b1 927 __IO uint32_t P1_16; /* 0x0C0 */
bogdanm 65:5798e58a58b1 928 __IO uint32_t P1_17;
bogdanm 65:5798e58a58b1 929 __IO uint32_t P1_18;
bogdanm 65:5798e58a58b1 930 __IO uint32_t P1_19;
bogdanm 65:5798e58a58b1 931 __IO uint32_t P1_20;
bogdanm 65:5798e58a58b1 932 __IO uint32_t P1_21;
bogdanm 65:5798e58a58b1 933 __IO uint32_t P1_22;
bogdanm 65:5798e58a58b1 934 __IO uint32_t P1_23;
bogdanm 65:5798e58a58b1 935
bogdanm 65:5798e58a58b1 936 __IO uint32_t P1_24; /* 0x0E0 */
bogdanm 65:5798e58a58b1 937 __IO uint32_t P1_25;
bogdanm 65:5798e58a58b1 938 __IO uint32_t P1_26;
bogdanm 65:5798e58a58b1 939 __IO uint32_t P1_27;
bogdanm 65:5798e58a58b1 940 __IO uint32_t P1_28;
bogdanm 65:5798e58a58b1 941 __IO uint32_t P1_29;
bogdanm 65:5798e58a58b1 942 __IO uint32_t P1_30;
bogdanm 65:5798e58a58b1 943 __IO uint32_t P1_31;
bogdanm 65:5798e58a58b1 944
bogdanm 65:5798e58a58b1 945 __IO uint32_t P2_0; /* 0x100 */
bogdanm 65:5798e58a58b1 946 __IO uint32_t P2_1;
bogdanm 65:5798e58a58b1 947 __IO uint32_t P2_2;
bogdanm 65:5798e58a58b1 948 __IO uint32_t P2_3;
bogdanm 65:5798e58a58b1 949 __IO uint32_t P2_4;
bogdanm 65:5798e58a58b1 950 __IO uint32_t P2_5;
bogdanm 65:5798e58a58b1 951 __IO uint32_t P2_6;
bogdanm 65:5798e58a58b1 952 __IO uint32_t P2_7;
bogdanm 65:5798e58a58b1 953
bogdanm 65:5798e58a58b1 954 __IO uint32_t P2_8; /* 0x120 */
bogdanm 65:5798e58a58b1 955 __IO uint32_t P2_9;
bogdanm 65:5798e58a58b1 956 __IO uint32_t P2_10;
bogdanm 65:5798e58a58b1 957 __IO uint32_t P2_11;
bogdanm 65:5798e58a58b1 958 __IO uint32_t P2_12;
bogdanm 65:5798e58a58b1 959 __IO uint32_t P2_13;
bogdanm 65:5798e58a58b1 960 __IO uint32_t P2_14;
bogdanm 65:5798e58a58b1 961 __IO uint32_t P2_15;
bogdanm 65:5798e58a58b1 962
bogdanm 65:5798e58a58b1 963 __IO uint32_t P2_16; /* 0x140 */
bogdanm 65:5798e58a58b1 964 __IO uint32_t P2_17;
bogdanm 65:5798e58a58b1 965 __IO uint32_t P2_18;
bogdanm 65:5798e58a58b1 966 __IO uint32_t P2_19;
bogdanm 65:5798e58a58b1 967 __IO uint32_t P2_20;
bogdanm 65:5798e58a58b1 968 __IO uint32_t P2_21;
bogdanm 65:5798e58a58b1 969 __IO uint32_t P2_22;
bogdanm 65:5798e58a58b1 970 __IO uint32_t P2_23;
bogdanm 65:5798e58a58b1 971
bogdanm 65:5798e58a58b1 972 __IO uint32_t P2_24; /* 0x160 */
bogdanm 65:5798e58a58b1 973 __IO uint32_t P2_25;
bogdanm 65:5798e58a58b1 974 __IO uint32_t P2_26;
bogdanm 65:5798e58a58b1 975 __IO uint32_t P2_27;
bogdanm 65:5798e58a58b1 976 __IO uint32_t P2_28;
bogdanm 65:5798e58a58b1 977 __IO uint32_t P2_29;
bogdanm 65:5798e58a58b1 978 __IO uint32_t P2_30;
bogdanm 65:5798e58a58b1 979 __IO uint32_t P2_31;
bogdanm 65:5798e58a58b1 980
bogdanm 65:5798e58a58b1 981 __IO uint32_t P3_0; /* 0x180 */
bogdanm 65:5798e58a58b1 982 __IO uint32_t P3_1;
bogdanm 65:5798e58a58b1 983 __IO uint32_t P3_2;
bogdanm 65:5798e58a58b1 984 __IO uint32_t P3_3;
bogdanm 65:5798e58a58b1 985 __IO uint32_t P3_4;
bogdanm 65:5798e58a58b1 986 __IO uint32_t P3_5;
bogdanm 65:5798e58a58b1 987 __IO uint32_t P3_6;
bogdanm 65:5798e58a58b1 988 __IO uint32_t P3_7;
bogdanm 65:5798e58a58b1 989
bogdanm 65:5798e58a58b1 990 __IO uint32_t P3_8; /* 0x1A0 */
bogdanm 65:5798e58a58b1 991 __IO uint32_t P3_9;
bogdanm 65:5798e58a58b1 992 __IO uint32_t P3_10;
bogdanm 65:5798e58a58b1 993 __IO uint32_t P3_11;
bogdanm 65:5798e58a58b1 994 __IO uint32_t P3_12;
bogdanm 65:5798e58a58b1 995 __IO uint32_t P3_13;
bogdanm 65:5798e58a58b1 996 __IO uint32_t P3_14;
bogdanm 65:5798e58a58b1 997 __IO uint32_t P3_15;
bogdanm 65:5798e58a58b1 998
bogdanm 65:5798e58a58b1 999 __IO uint32_t P3_16; /* 0x1C0 */
bogdanm 65:5798e58a58b1 1000 __IO uint32_t P3_17;
bogdanm 65:5798e58a58b1 1001 __IO uint32_t P3_18;
bogdanm 65:5798e58a58b1 1002 __IO uint32_t P3_19;
bogdanm 65:5798e58a58b1 1003 __IO uint32_t P3_20;
bogdanm 65:5798e58a58b1 1004 __IO uint32_t P3_21;
bogdanm 65:5798e58a58b1 1005 __IO uint32_t P3_22;
bogdanm 65:5798e58a58b1 1006 __IO uint32_t P3_23;
bogdanm 65:5798e58a58b1 1007
bogdanm 65:5798e58a58b1 1008 __IO uint32_t P3_24; /* 0x1E0 */
bogdanm 65:5798e58a58b1 1009 __IO uint32_t P3_25;
bogdanm 65:5798e58a58b1 1010 __IO uint32_t P3_26;
bogdanm 65:5798e58a58b1 1011 __IO uint32_t P3_27;
bogdanm 65:5798e58a58b1 1012 __IO uint32_t P3_28;
bogdanm 65:5798e58a58b1 1013 __IO uint32_t P3_29;
bogdanm 65:5798e58a58b1 1014 __IO uint32_t P3_30;
bogdanm 65:5798e58a58b1 1015 __IO uint32_t P3_31;
bogdanm 65:5798e58a58b1 1016
bogdanm 65:5798e58a58b1 1017 __IO uint32_t P4_0; /* 0x200 */
bogdanm 65:5798e58a58b1 1018 __IO uint32_t P4_1;
bogdanm 65:5798e58a58b1 1019 __IO uint32_t P4_2;
bogdanm 65:5798e58a58b1 1020 __IO uint32_t P4_3;
bogdanm 65:5798e58a58b1 1021 __IO uint32_t P4_4;
bogdanm 65:5798e58a58b1 1022 __IO uint32_t P4_5;
bogdanm 65:5798e58a58b1 1023 __IO uint32_t P4_6;
bogdanm 65:5798e58a58b1 1024 __IO uint32_t P4_7;
bogdanm 65:5798e58a58b1 1025
bogdanm 65:5798e58a58b1 1026 __IO uint32_t P4_8; /* 0x220 */
bogdanm 65:5798e58a58b1 1027 __IO uint32_t P4_9;
bogdanm 65:5798e58a58b1 1028 __IO uint32_t P4_10;
bogdanm 65:5798e58a58b1 1029 __IO uint32_t P4_11;
bogdanm 65:5798e58a58b1 1030 __IO uint32_t P4_12;
bogdanm 65:5798e58a58b1 1031 __IO uint32_t P4_13;
bogdanm 65:5798e58a58b1 1032 __IO uint32_t P4_14;
bogdanm 65:5798e58a58b1 1033 __IO uint32_t P4_15;
bogdanm 65:5798e58a58b1 1034
bogdanm 65:5798e58a58b1 1035 __IO uint32_t P4_16; /* 0x240 */
bogdanm 65:5798e58a58b1 1036 __IO uint32_t P4_17;
bogdanm 65:5798e58a58b1 1037 __IO uint32_t P4_18;
bogdanm 65:5798e58a58b1 1038 __IO uint32_t P4_19;
bogdanm 65:5798e58a58b1 1039 __IO uint32_t P4_20;
bogdanm 65:5798e58a58b1 1040 __IO uint32_t P4_21;
bogdanm 65:5798e58a58b1 1041 __IO uint32_t P4_22;
bogdanm 65:5798e58a58b1 1042 __IO uint32_t P4_23;
bogdanm 65:5798e58a58b1 1043
bogdanm 65:5798e58a58b1 1044 __IO uint32_t P4_24; /* 0x260 */
bogdanm 65:5798e58a58b1 1045 __IO uint32_t P4_25;
bogdanm 65:5798e58a58b1 1046 __IO uint32_t P4_26;
bogdanm 65:5798e58a58b1 1047 __IO uint32_t P4_27;
bogdanm 65:5798e58a58b1 1048 __IO uint32_t P4_28;
bogdanm 65:5798e58a58b1 1049 __IO uint32_t P4_29;
bogdanm 65:5798e58a58b1 1050 __IO uint32_t P4_30;
bogdanm 65:5798e58a58b1 1051 __IO uint32_t P4_31;
bogdanm 65:5798e58a58b1 1052
bogdanm 65:5798e58a58b1 1053 __IO uint32_t P5_0; /* 0x280 */
bogdanm 65:5798e58a58b1 1054 __IO uint32_t P5_1;
bogdanm 65:5798e58a58b1 1055 __IO uint32_t P5_2;
bogdanm 65:5798e58a58b1 1056 __IO uint32_t P5_3;
bogdanm 65:5798e58a58b1 1057 __IO uint32_t P5_4; /* 0x290 */
bogdanm 65:5798e58a58b1 1058 } LPC_IOCON_TypeDef;
bogdanm 65:5798e58a58b1 1059
bogdanm 65:5798e58a58b1 1060
bogdanm 65:5798e58a58b1 1061
bogdanm 65:5798e58a58b1 1062
bogdanm 65:5798e58a58b1 1063
bogdanm 65:5798e58a58b1 1064
bogdanm 65:5798e58a58b1 1065 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 65:5798e58a58b1 1066 typedef struct
bogdanm 65:5798e58a58b1 1067 {
bogdanm 65:5798e58a58b1 1068 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
bogdanm 65:5798e58a58b1 1069 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
bogdanm 65:5798e58a58b1 1070 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
bogdanm 65:5798e58a58b1 1071 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
bogdanm 65:5798e58a58b1 1072 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
bogdanm 65:5798e58a58b1 1073 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
bogdanm 65:5798e58a58b1 1074 __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
bogdanm 65:5798e58a58b1 1075 __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
bogdanm 65:5798e58a58b1 1076 __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
bogdanm 65:5798e58a58b1 1077 __IO uint32_t DMACR;
bogdanm 65:5798e58a58b1 1078 } LPC_SSP_TypeDef;
bogdanm 65:5798e58a58b1 1079
bogdanm 65:5798e58a58b1 1080 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 65:5798e58a58b1 1081 typedef struct
bogdanm 65:5798e58a58b1 1082 {
bogdanm 65:5798e58a58b1 1083 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
bogdanm 65:5798e58a58b1 1084 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
bogdanm 65:5798e58a58b1 1085 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 1086 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
bogdanm 65:5798e58a58b1 1087 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
bogdanm 65:5798e58a58b1 1088 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
bogdanm 65:5798e58a58b1 1089 __IO uint32_t ADTRM;
bogdanm 65:5798e58a58b1 1090 } LPC_ADC_TypeDef;
bogdanm 65:5798e58a58b1 1091
bogdanm 65:5798e58a58b1 1092 /*------------- Controller Area Network (CAN) --------------------------------*/
bogdanm 65:5798e58a58b1 1093 typedef struct
bogdanm 65:5798e58a58b1 1094 {
bogdanm 65:5798e58a58b1 1095 __IO uint32_t mask[512]; /* ID Masks */
bogdanm 65:5798e58a58b1 1096 } LPC_CANAF_RAM_TypeDef;
bogdanm 65:5798e58a58b1 1097
bogdanm 65:5798e58a58b1 1098 typedef struct /* Acceptance Filter Registers */
bogdanm 65:5798e58a58b1 1099 {
bogdanm 65:5798e58a58b1 1100 ///Offset: 0x00000000 - Acceptance Filter Register
bogdanm 65:5798e58a58b1 1101 __IO uint32_t AFMR;
bogdanm 65:5798e58a58b1 1102
bogdanm 65:5798e58a58b1 1103 ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
bogdanm 65:5798e58a58b1 1104 __IO uint32_t SFF_sa;
bogdanm 65:5798e58a58b1 1105
bogdanm 65:5798e58a58b1 1106 ///Offset: 0x00000008 - Standard Frame Group Start Address Register
bogdanm 65:5798e58a58b1 1107 __IO uint32_t SFF_GRP_sa;
bogdanm 65:5798e58a58b1 1108
bogdanm 65:5798e58a58b1 1109 ///Offset: 0x0000000C - Extended Frame Start Address Register
bogdanm 65:5798e58a58b1 1110 __IO uint32_t EFF_sa;
bogdanm 65:5798e58a58b1 1111
bogdanm 65:5798e58a58b1 1112 ///Offset: 0x00000010 - Extended Frame Group Start Address Register
bogdanm 65:5798e58a58b1 1113 __IO uint32_t EFF_GRP_sa;
bogdanm 65:5798e58a58b1 1114
bogdanm 65:5798e58a58b1 1115 ///Offset: 0x00000014 - End of AF Tables register
bogdanm 65:5798e58a58b1 1116 __IO uint32_t ENDofTable;
bogdanm 65:5798e58a58b1 1117
bogdanm 65:5798e58a58b1 1118 ///Offset: 0x00000018 - LUT Error Address register
bogdanm 65:5798e58a58b1 1119 __I uint32_t LUTerrAd;
bogdanm 65:5798e58a58b1 1120
bogdanm 65:5798e58a58b1 1121 ///Offset: 0x0000001C - LUT Error Register
bogdanm 65:5798e58a58b1 1122 __I uint32_t LUTerr;
bogdanm 65:5798e58a58b1 1123
bogdanm 65:5798e58a58b1 1124 ///Offset: 0x00000020 - CAN Central Transmit Status Register
bogdanm 65:5798e58a58b1 1125 __IO uint32_t FCANIE;
bogdanm 65:5798e58a58b1 1126
bogdanm 65:5798e58a58b1 1127 ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
bogdanm 65:5798e58a58b1 1128 __IO uint32_t FCANIC0;
bogdanm 65:5798e58a58b1 1129
bogdanm 65:5798e58a58b1 1130 ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
bogdanm 65:5798e58a58b1 1131 __IO uint32_t FCANIC1;
bogdanm 65:5798e58a58b1 1132 } LPC_CANAF_TypeDef;
bogdanm 65:5798e58a58b1 1133
bogdanm 65:5798e58a58b1 1134 typedef struct /* Central Registers */
bogdanm 65:5798e58a58b1 1135 {
bogdanm 65:5798e58a58b1 1136 __I uint32_t TxSR;
bogdanm 65:5798e58a58b1 1137 __I uint32_t RxSR;
bogdanm 65:5798e58a58b1 1138 __I uint32_t MSR;
bogdanm 65:5798e58a58b1 1139 } LPC_CANCR_TypeDef;
bogdanm 65:5798e58a58b1 1140
bogdanm 65:5798e58a58b1 1141 typedef struct /* Controller Registers */
bogdanm 65:5798e58a58b1 1142 {
bogdanm 65:5798e58a58b1 1143 ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
bogdanm 65:5798e58a58b1 1144 __IO uint32_t MOD;
bogdanm 65:5798e58a58b1 1145
bogdanm 65:5798e58a58b1 1146 ///Offset: 0x00000004 - Command bits that affect the state
bogdanm 65:5798e58a58b1 1147 __O uint32_t CMR;
bogdanm 65:5798e58a58b1 1148
bogdanm 65:5798e58a58b1 1149 ///Offset: 0x00000008 - Global Controller Status and Error Counters
bogdanm 65:5798e58a58b1 1150 __IO uint32_t GSR;
bogdanm 65:5798e58a58b1 1151
bogdanm 65:5798e58a58b1 1152 ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
bogdanm 65:5798e58a58b1 1153 __I uint32_t ICR;
bogdanm 65:5798e58a58b1 1154
bogdanm 65:5798e58a58b1 1155 ///Offset: 0x00000010 - Interrupt Enable Register
bogdanm 65:5798e58a58b1 1156 __IO uint32_t IER;
bogdanm 65:5798e58a58b1 1157
bogdanm 65:5798e58a58b1 1158 ///Offset: 0x00000014 - Bus Timing Register
bogdanm 65:5798e58a58b1 1159 __IO uint32_t BTR;
bogdanm 65:5798e58a58b1 1160
bogdanm 65:5798e58a58b1 1161 ///Offset: 0x00000018 - Error Warning Limit
bogdanm 65:5798e58a58b1 1162 __IO uint32_t EWL;
bogdanm 65:5798e58a58b1 1163
bogdanm 65:5798e58a58b1 1164 ///Offset: 0x0000001C - Status Register
bogdanm 65:5798e58a58b1 1165 __I uint32_t SR;
bogdanm 65:5798e58a58b1 1166
bogdanm 65:5798e58a58b1 1167 ///Offset: 0x00000020 - Receive frame status
bogdanm 65:5798e58a58b1 1168 __IO uint32_t RFS;
bogdanm 65:5798e58a58b1 1169
bogdanm 65:5798e58a58b1 1170 ///Offset: 0x00000024 - Received Identifier
bogdanm 65:5798e58a58b1 1171 __IO uint32_t RID;
bogdanm 65:5798e58a58b1 1172
bogdanm 65:5798e58a58b1 1173 ///Offset: 0x00000028 - Received data bytes 1-4
bogdanm 65:5798e58a58b1 1174 __IO uint32_t RDA;
bogdanm 65:5798e58a58b1 1175
bogdanm 65:5798e58a58b1 1176 ///Offset: 0x0000002C - Received data bytes 5-8
bogdanm 65:5798e58a58b1 1177 __IO uint32_t RDB;
bogdanm 65:5798e58a58b1 1178
bogdanm 65:5798e58a58b1 1179 ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
bogdanm 65:5798e58a58b1 1180 __IO uint32_t TFI1;
bogdanm 65:5798e58a58b1 1181
bogdanm 65:5798e58a58b1 1182 ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
bogdanm 65:5798e58a58b1 1183 __IO uint32_t TID1;
bogdanm 65:5798e58a58b1 1184
bogdanm 65:5798e58a58b1 1185 ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
bogdanm 65:5798e58a58b1 1186 __IO uint32_t TDA1;
bogdanm 65:5798e58a58b1 1187
bogdanm 65:5798e58a58b1 1188 ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
bogdanm 65:5798e58a58b1 1189 __IO uint32_t TDB1;
bogdanm 65:5798e58a58b1 1190
bogdanm 65:5798e58a58b1 1191 ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
bogdanm 65:5798e58a58b1 1192 __IO uint32_t TFI2;
bogdanm 65:5798e58a58b1 1193
bogdanm 65:5798e58a58b1 1194 ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
bogdanm 65:5798e58a58b1 1195 __IO uint32_t TID2;
bogdanm 65:5798e58a58b1 1196
bogdanm 65:5798e58a58b1 1197 ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
bogdanm 65:5798e58a58b1 1198 __IO uint32_t TDA2;
bogdanm 65:5798e58a58b1 1199
bogdanm 65:5798e58a58b1 1200 ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
bogdanm 65:5798e58a58b1 1201 __IO uint32_t TDB2;
bogdanm 65:5798e58a58b1 1202
bogdanm 65:5798e58a58b1 1203 ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
bogdanm 65:5798e58a58b1 1204 __IO uint32_t TFI3;
bogdanm 65:5798e58a58b1 1205
bogdanm 65:5798e58a58b1 1206 ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
bogdanm 65:5798e58a58b1 1207 __IO uint32_t TID3;
bogdanm 65:5798e58a58b1 1208
bogdanm 65:5798e58a58b1 1209 ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
bogdanm 65:5798e58a58b1 1210 __IO uint32_t TDA3;
bogdanm 65:5798e58a58b1 1211
bogdanm 65:5798e58a58b1 1212 ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
bogdanm 65:5798e58a58b1 1213 __IO uint32_t TDB3;
bogdanm 65:5798e58a58b1 1214 } LPC_CAN_TypeDef;
bogdanm 65:5798e58a58b1 1215
bogdanm 65:5798e58a58b1 1216 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
bogdanm 65:5798e58a58b1 1217 typedef struct
bogdanm 65:5798e58a58b1 1218 {
bogdanm 65:5798e58a58b1 1219 __IO uint32_t CR;
bogdanm 65:5798e58a58b1 1220 __IO uint32_t CTRL;
bogdanm 65:5798e58a58b1 1221 __IO uint32_t CNTVAL;
bogdanm 65:5798e58a58b1 1222 } LPC_DAC_TypeDef;
bogdanm 65:5798e58a58b1 1223
bogdanm 65:5798e58a58b1 1224
bogdanm 65:5798e58a58b1 1225 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
bogdanm 65:5798e58a58b1 1226 typedef struct
bogdanm 65:5798e58a58b1 1227 {
bogdanm 65:5798e58a58b1 1228 __IO uint32_t DAO;
bogdanm 65:5798e58a58b1 1229 __IO uint32_t DAI;
bogdanm 65:5798e58a58b1 1230 __O uint32_t TXFIFO;
bogdanm 65:5798e58a58b1 1231 __I uint32_t RXFIFO;
bogdanm 65:5798e58a58b1 1232 __I uint32_t STATE;
bogdanm 65:5798e58a58b1 1233 __IO uint32_t DMA1;
bogdanm 65:5798e58a58b1 1234 __IO uint32_t DMA2;
bogdanm 65:5798e58a58b1 1235 __IO uint32_t IRQ;
bogdanm 65:5798e58a58b1 1236 __IO uint32_t TXRATE;
bogdanm 65:5798e58a58b1 1237 __IO uint32_t RXRATE;
bogdanm 65:5798e58a58b1 1238 __IO uint32_t TXBITRATE;
bogdanm 65:5798e58a58b1 1239 __IO uint32_t RXBITRATE;
bogdanm 65:5798e58a58b1 1240 __IO uint32_t TXMODE;
bogdanm 65:5798e58a58b1 1241 __IO uint32_t RXMODE;
bogdanm 65:5798e58a58b1 1242 } LPC_I2S_TypeDef;
bogdanm 65:5798e58a58b1 1243
bogdanm 65:5798e58a58b1 1244
bogdanm 65:5798e58a58b1 1245
bogdanm 65:5798e58a58b1 1246
bogdanm 65:5798e58a58b1 1247
bogdanm 65:5798e58a58b1 1248
bogdanm 65:5798e58a58b1 1249 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
bogdanm 65:5798e58a58b1 1250 typedef struct
bogdanm 65:5798e58a58b1 1251 {
bogdanm 65:5798e58a58b1 1252 __I uint32_t CON;
bogdanm 65:5798e58a58b1 1253 __O uint32_t CON_SET;
bogdanm 65:5798e58a58b1 1254 __O uint32_t CON_CLR;
bogdanm 65:5798e58a58b1 1255 __I uint32_t CAPCON;
bogdanm 65:5798e58a58b1 1256 __O uint32_t CAPCON_SET;
bogdanm 65:5798e58a58b1 1257 __O uint32_t CAPCON_CLR;
bogdanm 65:5798e58a58b1 1258 __IO uint32_t TC0;
bogdanm 65:5798e58a58b1 1259 __IO uint32_t TC1;
bogdanm 65:5798e58a58b1 1260 __IO uint32_t TC2;
bogdanm 65:5798e58a58b1 1261 __IO uint32_t LIM0;
bogdanm 65:5798e58a58b1 1262 __IO uint32_t LIM1;
bogdanm 65:5798e58a58b1 1263 __IO uint32_t LIM2;
bogdanm 65:5798e58a58b1 1264 __IO uint32_t MAT0;
bogdanm 65:5798e58a58b1 1265 __IO uint32_t MAT1;
bogdanm 65:5798e58a58b1 1266 __IO uint32_t MAT2;
bogdanm 65:5798e58a58b1 1267 __IO uint32_t DT;
bogdanm 65:5798e58a58b1 1268 __IO uint32_t CP;
bogdanm 65:5798e58a58b1 1269 __IO uint32_t CAP0;
bogdanm 65:5798e58a58b1 1270 __IO uint32_t CAP1;
bogdanm 65:5798e58a58b1 1271 __IO uint32_t CAP2;
bogdanm 65:5798e58a58b1 1272 __I uint32_t INTEN;
bogdanm 65:5798e58a58b1 1273 __O uint32_t INTEN_SET;
bogdanm 65:5798e58a58b1 1274 __O uint32_t INTEN_CLR;
bogdanm 65:5798e58a58b1 1275 __I uint32_t CNTCON;
bogdanm 65:5798e58a58b1 1276 __O uint32_t CNTCON_SET;
bogdanm 65:5798e58a58b1 1277 __O uint32_t CNTCON_CLR;
bogdanm 65:5798e58a58b1 1278 __I uint32_t INTF;
bogdanm 65:5798e58a58b1 1279 __O uint32_t INTF_SET;
bogdanm 65:5798e58a58b1 1280 __O uint32_t INTF_CLR;
bogdanm 65:5798e58a58b1 1281 __O uint32_t CAP_CLR;
bogdanm 65:5798e58a58b1 1282 } LPC_MCPWM_TypeDef;
bogdanm 65:5798e58a58b1 1283
bogdanm 65:5798e58a58b1 1284 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
bogdanm 65:5798e58a58b1 1285 typedef struct
bogdanm 65:5798e58a58b1 1286 {
bogdanm 65:5798e58a58b1 1287 __O uint32_t CON;
bogdanm 65:5798e58a58b1 1288 __I uint32_t STAT;
bogdanm 65:5798e58a58b1 1289 __IO uint32_t CONF;
bogdanm 65:5798e58a58b1 1290 __I uint32_t POS;
bogdanm 65:5798e58a58b1 1291 __IO uint32_t MAXPOS;
bogdanm 65:5798e58a58b1 1292 __IO uint32_t CMPOS0;
bogdanm 65:5798e58a58b1 1293 __IO uint32_t CMPOS1;
bogdanm 65:5798e58a58b1 1294 __IO uint32_t CMPOS2;
bogdanm 65:5798e58a58b1 1295 __I uint32_t INXCNT;
bogdanm 65:5798e58a58b1 1296 __IO uint32_t INXCMP0;
bogdanm 65:5798e58a58b1 1297 __IO uint32_t LOAD;
bogdanm 65:5798e58a58b1 1298 __I uint32_t TIME;
bogdanm 65:5798e58a58b1 1299 __I uint32_t VEL;
bogdanm 65:5798e58a58b1 1300 __I uint32_t CAP;
bogdanm 65:5798e58a58b1 1301 __IO uint32_t VELCOMP;
bogdanm 65:5798e58a58b1 1302 __IO uint32_t FILTERPHA;
bogdanm 65:5798e58a58b1 1303 __IO uint32_t FILTERPHB;
bogdanm 65:5798e58a58b1 1304 __IO uint32_t FILTERINX;
bogdanm 65:5798e58a58b1 1305 __IO uint32_t WINDOW;
bogdanm 65:5798e58a58b1 1306 __IO uint32_t INXCMP1;
bogdanm 65:5798e58a58b1 1307 __IO uint32_t INXCMP2;
bogdanm 65:5798e58a58b1 1308 uint32_t RESERVED0[993];
bogdanm 65:5798e58a58b1 1309 __O uint32_t IEC;
bogdanm 65:5798e58a58b1 1310 __O uint32_t IES;
bogdanm 65:5798e58a58b1 1311 __I uint32_t INTSTAT;
bogdanm 65:5798e58a58b1 1312 __I uint32_t IE;
bogdanm 65:5798e58a58b1 1313 __O uint32_t CLR;
bogdanm 65:5798e58a58b1 1314 __O uint32_t SET;
bogdanm 65:5798e58a58b1 1315 } LPC_QEI_TypeDef;
bogdanm 65:5798e58a58b1 1316
bogdanm 65:5798e58a58b1 1317 /*------------- SD/MMC card Interface (MCI)-----------------------------------*/
bogdanm 65:5798e58a58b1 1318 typedef struct
bogdanm 65:5798e58a58b1 1319 {
bogdanm 65:5798e58a58b1 1320 __IO uint32_t POWER;
bogdanm 65:5798e58a58b1 1321 __IO uint32_t CLOCK;
bogdanm 65:5798e58a58b1 1322 __IO uint32_t ARGUMENT;
bogdanm 65:5798e58a58b1 1323 __IO uint32_t COMMAND;
bogdanm 65:5798e58a58b1 1324 __I uint32_t RESP_CMD;
bogdanm 65:5798e58a58b1 1325 __I uint32_t RESP0;
bogdanm 65:5798e58a58b1 1326 __I uint32_t RESP1;
bogdanm 65:5798e58a58b1 1327 __I uint32_t RESP2;
bogdanm 65:5798e58a58b1 1328 __I uint32_t RESP3;
bogdanm 65:5798e58a58b1 1329 __IO uint32_t DATATMR;
bogdanm 65:5798e58a58b1 1330 __IO uint32_t DATALEN;
bogdanm 65:5798e58a58b1 1331 __IO uint32_t DATACTRL;
bogdanm 65:5798e58a58b1 1332 __I uint32_t DATACNT;
bogdanm 65:5798e58a58b1 1333 __I uint32_t STATUS;
bogdanm 65:5798e58a58b1 1334 __O uint32_t CLEAR;
bogdanm 65:5798e58a58b1 1335 __IO uint32_t MASK0;
bogdanm 65:5798e58a58b1 1336 uint32_t RESERVED0[2];
bogdanm 65:5798e58a58b1 1337 __I uint32_t FIFOCNT;
bogdanm 65:5798e58a58b1 1338 uint32_t RESERVED1[13];
bogdanm 65:5798e58a58b1 1339 __IO uint32_t FIFO[16];
bogdanm 65:5798e58a58b1 1340 } LPC_MCI_TypeDef;
bogdanm 65:5798e58a58b1 1341
bogdanm 65:5798e58a58b1 1342
bogdanm 65:5798e58a58b1 1343
bogdanm 65:5798e58a58b1 1344
bogdanm 65:5798e58a58b1 1345
bogdanm 65:5798e58a58b1 1346
bogdanm 65:5798e58a58b1 1347
bogdanm 65:5798e58a58b1 1348
bogdanm 65:5798e58a58b1 1349
bogdanm 65:5798e58a58b1 1350
bogdanm 65:5798e58a58b1 1351 /*------------- EEPROM Controller (EEPROM) -----------------------------------*/
bogdanm 65:5798e58a58b1 1352 typedef struct
bogdanm 65:5798e58a58b1 1353 {
bogdanm 65:5798e58a58b1 1354 __IO uint32_t CMD; /* 0x0080 */
bogdanm 65:5798e58a58b1 1355 __IO uint32_t ADDR;
bogdanm 65:5798e58a58b1 1356 __IO uint32_t WDATA;
bogdanm 65:5798e58a58b1 1357 __IO uint32_t RDATA;
bogdanm 65:5798e58a58b1 1358 __IO uint32_t WSTATE; /* 0x0090 */
bogdanm 65:5798e58a58b1 1359 __IO uint32_t CLKDIV;
bogdanm 65:5798e58a58b1 1360 __IO uint32_t PWRDWN; /* 0x0098 */
bogdanm 65:5798e58a58b1 1361 uint32_t RESERVED0[975];
bogdanm 65:5798e58a58b1 1362 __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
bogdanm 65:5798e58a58b1 1363 __IO uint32_t INT_SET_ENABLE;
bogdanm 65:5798e58a58b1 1364 __IO uint32_t INT_STATUS; /* 0x0FE0 */
bogdanm 65:5798e58a58b1 1365 __IO uint32_t INT_ENABLE;
bogdanm 65:5798e58a58b1 1366 __IO uint32_t INT_CLR_STATUS;
bogdanm 65:5798e58a58b1 1367 __IO uint32_t INT_SET_STATUS;
bogdanm 65:5798e58a58b1 1368 } LPC_EEPROM_TypeDef;
bogdanm 65:5798e58a58b1 1369
bogdanm 65:5798e58a58b1 1370
bogdanm 65:5798e58a58b1 1371 /*------------- COMPARATOR ----------------------------------------------------*/
bogdanm 65:5798e58a58b1 1372
bogdanm 65:5798e58a58b1 1373 typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
bogdanm 65:5798e58a58b1 1374 __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
bogdanm 65:5798e58a58b1 1375 __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
bogdanm 65:5798e58a58b1 1376 __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
bogdanm 65:5798e58a58b1 1377 } LPC_COMPARATOR_Type;
bogdanm 65:5798e58a58b1 1378
bogdanm 65:5798e58a58b1 1379
bogdanm 65:5798e58a58b1 1380 #if defined ( __CC_ARM )
bogdanm 65:5798e58a58b1 1381 #pragma no_anon_unions
bogdanm 65:5798e58a58b1 1382 #endif
bogdanm 65:5798e58a58b1 1383
bogdanm 65:5798e58a58b1 1384 /******************************************************************************/
bogdanm 65:5798e58a58b1 1385 /* Peripheral memory map */
bogdanm 65:5798e58a58b1 1386 /******************************************************************************/
bogdanm 65:5798e58a58b1 1387 /* Base addresses */
bogdanm 65:5798e58a58b1 1388 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 65:5798e58a58b1 1389 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 65:5798e58a58b1 1390 #define LPC_PERI_RAM_BASE (0x20000000UL)
bogdanm 65:5798e58a58b1 1391 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 65:5798e58a58b1 1392 #define LPC_APB1_BASE (0x40080000UL)
bogdanm 65:5798e58a58b1 1393 #define LPC_AHBRAM1_BASE (0x20004000UL)
bogdanm 65:5798e58a58b1 1394 #define LPC_AHB_BASE (0x20080000UL)
bogdanm 65:5798e58a58b1 1395 #define LPC_CM3_BASE (0xE0000000UL)
bogdanm 65:5798e58a58b1 1396
bogdanm 65:5798e58a58b1 1397 /* APB0 peripherals */
bogdanm 65:5798e58a58b1 1398 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 65:5798e58a58b1 1399 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 65:5798e58a58b1 1400 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 65:5798e58a58b1 1401 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 65:5798e58a58b1 1402 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
bogdanm 65:5798e58a58b1 1403 #define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
bogdanm 65:5798e58a58b1 1404 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
bogdanm 65:5798e58a58b1 1405 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
bogdanm 65:5798e58a58b1 1406 #define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
bogdanm 65:5798e58a58b1 1407 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
bogdanm 65:5798e58a58b1 1408 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
bogdanm 65:5798e58a58b1 1409 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
bogdanm 65:5798e58a58b1 1410 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
bogdanm 65:5798e58a58b1 1411 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
bogdanm 65:5798e58a58b1 1412 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
bogdanm 65:5798e58a58b1 1413 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
bogdanm 65:5798e58a58b1 1414 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 65:5798e58a58b1 1415 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 65:5798e58a58b1 1416 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 65:5798e58a58b1 1417 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
bogdanm 65:5798e58a58b1 1418
bogdanm 65:5798e58a58b1 1419 /* APB1 peripherals */
bogdanm 65:5798e58a58b1 1420 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
bogdanm 65:5798e58a58b1 1421 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
bogdanm 65:5798e58a58b1 1422 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
bogdanm 65:5798e58a58b1 1423 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
bogdanm 65:5798e58a58b1 1424 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
bogdanm 65:5798e58a58b1 1425 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
bogdanm 65:5798e58a58b1 1426 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
bogdanm 65:5798e58a58b1 1427 #define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
bogdanm 65:5798e58a58b1 1428 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
bogdanm 65:5798e58a58b1 1429 #define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
bogdanm 65:5798e58a58b1 1430 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
bogdanm 65:5798e58a58b1 1431 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
bogdanm 65:5798e58a58b1 1432 #define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
bogdanm 65:5798e58a58b1 1433 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
bogdanm 65:5798e58a58b1 1434
bogdanm 65:5798e58a58b1 1435 /* AHB peripherals */
bogdanm 65:5798e58a58b1 1436 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 65:5798e58a58b1 1437 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
bogdanm 65:5798e58a58b1 1438 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
bogdanm 65:5798e58a58b1 1439 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
bogdanm 65:5798e58a58b1 1440 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
bogdanm 65:5798e58a58b1 1441 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
bogdanm 65:5798e58a58b1 1442 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
bogdanm 65:5798e58a58b1 1443 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
bogdanm 65:5798e58a58b1 1444 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
bogdanm 65:5798e58a58b1 1445 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
bogdanm 65:5798e58a58b1 1446 #define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
bogdanm 65:5798e58a58b1 1447 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
bogdanm 65:5798e58a58b1 1448 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
bogdanm 65:5798e58a58b1 1449 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
bogdanm 65:5798e58a58b1 1450 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
bogdanm 65:5798e58a58b1 1451 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
bogdanm 65:5798e58a58b1 1452 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
bogdanm 65:5798e58a58b1 1453 #define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
bogdanm 65:5798e58a58b1 1454 #define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
bogdanm 65:5798e58a58b1 1455 #define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
bogdanm 65:5798e58a58b1 1456
bogdanm 65:5798e58a58b1 1457 #define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
bogdanm 65:5798e58a58b1 1458
bogdanm 65:5798e58a58b1 1459
bogdanm 65:5798e58a58b1 1460 /******************************************************************************/
bogdanm 65:5798e58a58b1 1461 /* Peripheral declaration */
bogdanm 65:5798e58a58b1 1462 /******************************************************************************/
bogdanm 65:5798e58a58b1 1463 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
bogdanm 65:5798e58a58b1 1464 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
bogdanm 65:5798e58a58b1 1465 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
bogdanm 65:5798e58a58b1 1466 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
bogdanm 65:5798e58a58b1 1467 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
bogdanm 65:5798e58a58b1 1468 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
bogdanm 65:5798e58a58b1 1469 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
bogdanm 65:5798e58a58b1 1470 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
bogdanm 65:5798e58a58b1 1471 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
bogdanm 65:5798e58a58b1 1472 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
bogdanm 65:5798e58a58b1 1473 #define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
bogdanm 65:5798e58a58b1 1474 #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
bogdanm 65:5798e58a58b1 1475 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
bogdanm 65:5798e58a58b1 1476 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
bogdanm 65:5798e58a58b1 1477 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
bogdanm 65:5798e58a58b1 1478 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
bogdanm 65:5798e58a58b1 1479 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
bogdanm 65:5798e58a58b1 1480 #define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
bogdanm 65:5798e58a58b1 1481 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
bogdanm 65:5798e58a58b1 1482 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
bogdanm 65:5798e58a58b1 1483 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
bogdanm 65:5798e58a58b1 1484 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
bogdanm 65:5798e58a58b1 1485 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
bogdanm 65:5798e58a58b1 1486 #define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
bogdanm 65:5798e58a58b1 1487 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
bogdanm 65:5798e58a58b1 1488 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
bogdanm 65:5798e58a58b1 1489 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
bogdanm 65:5798e58a58b1 1490 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
bogdanm 65:5798e58a58b1 1491 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
bogdanm 65:5798e58a58b1 1492 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
bogdanm 65:5798e58a58b1 1493 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
bogdanm 65:5798e58a58b1 1494 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
bogdanm 65:5798e58a58b1 1495 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
bogdanm 65:5798e58a58b1 1496 #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
bogdanm 65:5798e58a58b1 1497 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
bogdanm 65:5798e58a58b1 1498 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
bogdanm 65:5798e58a58b1 1499 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
bogdanm 65:5798e58a58b1 1500 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
bogdanm 65:5798e58a58b1 1501 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
bogdanm 65:5798e58a58b1 1502 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
bogdanm 65:5798e58a58b1 1503 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
bogdanm 65:5798e58a58b1 1504 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
bogdanm 65:5798e58a58b1 1505 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
bogdanm 65:5798e58a58b1 1506 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
bogdanm 65:5798e58a58b1 1507 #define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
bogdanm 65:5798e58a58b1 1508 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
bogdanm 65:5798e58a58b1 1509 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
bogdanm 65:5798e58a58b1 1510 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
bogdanm 65:5798e58a58b1 1511 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
bogdanm 65:5798e58a58b1 1512 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
bogdanm 65:5798e58a58b1 1513 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
bogdanm 65:5798e58a58b1 1514 #define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
bogdanm 65:5798e58a58b1 1515 #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
bogdanm 65:5798e58a58b1 1516 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
bogdanm 65:5798e58a58b1 1517 #define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
bogdanm 65:5798e58a58b1 1518
bogdanm 65:5798e58a58b1 1519
bogdanm 65:5798e58a58b1 1520
bogdanm 65:5798e58a58b1 1521 #endif // __LPC407x_8x_177x_8x_H__