Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_SAMR21G18A/comp_rtc.h@111:4336505e4b1c, 2015-12-15 (annotated)

Committer:
Kojto
Date:
Tue Dec 15 14:39:38 2015 +0000
Revision:
111:4336505e4b1c
Release 111 of the mbed library



Changes:

- new platforms - Atmel targets (SAMR21G18A, SAMD21J18A, SAMD21G18A)

- Streams - add var argument (vprintf, vscanf)

- MAXWSNENV - BLE stack library additio

- LPC1768 - fix slave read

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Component description for RTC
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_RTC_COMPONENT_
Kojto 111:4336505e4b1c 45 #define _SAMR21_RTC_COMPONENT_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========================================================================== */
Kojto 111:4336505e4b1c 48 /** SOFTWARE API DEFINITION FOR RTC */
Kojto 111:4336505e4b1c 49 /* ========================================================================== */
Kojto 111:4336505e4b1c 50 /** \addtogroup SAMR21_RTC Real-Time Counter */
Kojto 111:4336505e4b1c 51 /*@{*/
Kojto 111:4336505e4b1c 52
Kojto 111:4336505e4b1c 53 #define RTC_U2202
Kojto 111:4336505e4b1c 54 #define REV_RTC 0x101
Kojto 111:4336505e4b1c 55
Kojto 111:4336505e4b1c 56 /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
Kojto 111:4336505e4b1c 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 58 typedef union {
Kojto 111:4336505e4b1c 59 struct {
Kojto 111:4336505e4b1c 60 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 61 uint16_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 62 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
Kojto 111:4336505e4b1c 63 uint16_t :3; /*!< bit: 4.. 6 Reserved */
Kojto 111:4336505e4b1c 64 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
Kojto 111:4336505e4b1c 65 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
Kojto 111:4336505e4b1c 66 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 67 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 68 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 69 } RTC_MODE0_CTRL_Type;
Kojto 111:4336505e4b1c 70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 71
Kojto 111:4336505e4b1c 72 #define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
Kojto 111:4336505e4b1c 73 #define RTC_MODE0_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
Kojto 111:4336505e4b1c 74
Kojto 111:4336505e4b1c 75 #define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */
Kojto 111:4336505e4b1c 76 #define RTC_MODE0_CTRL_SWRST (0x1ul << RTC_MODE0_CTRL_SWRST_Pos)
Kojto 111:4336505e4b1c 77 #define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */
Kojto 111:4336505e4b1c 78 #define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
Kojto 111:4336505e4b1c 79 #define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */
Kojto 111:4336505e4b1c 80 #define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 81 #define RTC_MODE0_CTRL_MODE(value) (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))
Kojto 111:4336505e4b1c 82 #define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
Kojto 111:4336505e4b1c 83 #define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
Kojto 111:4336505e4b1c 84 #define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
Kojto 111:4336505e4b1c 85 #define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 86 #define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 87 #define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 88 #define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */
Kojto 111:4336505e4b1c 89 #define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
Kojto 111:4336505e4b1c 90 #define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */
Kojto 111:4336505e4b1c 91 #define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 92 #define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))
Kojto 111:4336505e4b1c 93 #define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
Kojto 111:4336505e4b1c 94 #define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
Kojto 111:4336505e4b1c 95 #define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
Kojto 111:4336505e4b1c 96 #define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
Kojto 111:4336505e4b1c 97 #define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
Kojto 111:4336505e4b1c 98 #define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
Kojto 111:4336505e4b1c 99 #define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
Kojto 111:4336505e4b1c 100 #define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
Kojto 111:4336505e4b1c 101 #define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
Kojto 111:4336505e4b1c 102 #define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
Kojto 111:4336505e4b1c 103 #define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
Kojto 111:4336505e4b1c 104 #define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 105 #define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 106 #define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 107 #define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 108 #define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 109 #define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 110 #define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 111 #define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 112 #define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 113 #define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 114 #define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 115 #define RTC_MODE0_CTRL_MASK 0x0F8Ful /**< \brief (RTC_MODE0_CTRL) MASK Register */
Kojto 111:4336505e4b1c 116
Kojto 111:4336505e4b1c 117 /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
Kojto 111:4336505e4b1c 118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 119 typedef union {
Kojto 111:4336505e4b1c 120 struct {
Kojto 111:4336505e4b1c 121 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 122 uint16_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 123 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
Kojto 111:4336505e4b1c 124 uint16_t :4; /*!< bit: 4.. 7 Reserved */
Kojto 111:4336505e4b1c 125 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
Kojto 111:4336505e4b1c 126 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 127 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 128 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 129 } RTC_MODE1_CTRL_Type;
Kojto 111:4336505e4b1c 130 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 131
Kojto 111:4336505e4b1c 132 #define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
Kojto 111:4336505e4b1c 133 #define RTC_MODE1_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
Kojto 111:4336505e4b1c 134
Kojto 111:4336505e4b1c 135 #define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */
Kojto 111:4336505e4b1c 136 #define RTC_MODE1_CTRL_SWRST (0x1ul << RTC_MODE1_CTRL_SWRST_Pos)
Kojto 111:4336505e4b1c 137 #define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */
Kojto 111:4336505e4b1c 138 #define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
Kojto 111:4336505e4b1c 139 #define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */
Kojto 111:4336505e4b1c 140 #define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 141 #define RTC_MODE1_CTRL_MODE(value) (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))
Kojto 111:4336505e4b1c 142 #define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
Kojto 111:4336505e4b1c 143 #define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
Kojto 111:4336505e4b1c 144 #define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
Kojto 111:4336505e4b1c 145 #define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 146 #define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 147 #define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 148 #define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */
Kojto 111:4336505e4b1c 149 #define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 150 #define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))
Kojto 111:4336505e4b1c 151 #define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
Kojto 111:4336505e4b1c 152 #define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
Kojto 111:4336505e4b1c 153 #define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
Kojto 111:4336505e4b1c 154 #define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
Kojto 111:4336505e4b1c 155 #define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
Kojto 111:4336505e4b1c 156 #define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
Kojto 111:4336505e4b1c 157 #define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
Kojto 111:4336505e4b1c 158 #define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
Kojto 111:4336505e4b1c 159 #define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
Kojto 111:4336505e4b1c 160 #define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
Kojto 111:4336505e4b1c 161 #define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
Kojto 111:4336505e4b1c 162 #define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 163 #define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 164 #define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 165 #define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 166 #define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 167 #define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 168 #define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 169 #define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 170 #define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 171 #define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 172 #define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 173 #define RTC_MODE1_CTRL_MASK 0x0F0Ful /**< \brief (RTC_MODE1_CTRL) MASK Register */
Kojto 111:4336505e4b1c 174
Kojto 111:4336505e4b1c 175 /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
Kojto 111:4336505e4b1c 176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 177 typedef union {
Kojto 111:4336505e4b1c 178 struct {
Kojto 111:4336505e4b1c 179 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
Kojto 111:4336505e4b1c 180 uint16_t ENABLE:1; /*!< bit: 1 Enable */
Kojto 111:4336505e4b1c 181 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
Kojto 111:4336505e4b1c 182 uint16_t :2; /*!< bit: 4.. 5 Reserved */
Kojto 111:4336505e4b1c 183 uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
Kojto 111:4336505e4b1c 184 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
Kojto 111:4336505e4b1c 185 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
Kojto 111:4336505e4b1c 186 uint16_t :4; /*!< bit: 12..15 Reserved */
Kojto 111:4336505e4b1c 187 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 188 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 189 } RTC_MODE2_CTRL_Type;
Kojto 111:4336505e4b1c 190 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 191
Kojto 111:4336505e4b1c 192 #define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
Kojto 111:4336505e4b1c 193 #define RTC_MODE2_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
Kojto 111:4336505e4b1c 194
Kojto 111:4336505e4b1c 195 #define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */
Kojto 111:4336505e4b1c 196 #define RTC_MODE2_CTRL_SWRST (0x1ul << RTC_MODE2_CTRL_SWRST_Pos)
Kojto 111:4336505e4b1c 197 #define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */
Kojto 111:4336505e4b1c 198 #define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
Kojto 111:4336505e4b1c 199 #define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */
Kojto 111:4336505e4b1c 200 #define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 201 #define RTC_MODE2_CTRL_MODE(value) (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))
Kojto 111:4336505e4b1c 202 #define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
Kojto 111:4336505e4b1c 203 #define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
Kojto 111:4336505e4b1c 204 #define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
Kojto 111:4336505e4b1c 205 #define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 206 #define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 207 #define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
Kojto 111:4336505e4b1c 208 #define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */
Kojto 111:4336505e4b1c 209 #define RTC_MODE2_CTRL_CLKREP (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos)
Kojto 111:4336505e4b1c 210 #define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */
Kojto 111:4336505e4b1c 211 #define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
Kojto 111:4336505e4b1c 212 #define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */
Kojto 111:4336505e4b1c 213 #define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 214 #define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))
Kojto 111:4336505e4b1c 215 #define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
Kojto 111:4336505e4b1c 216 #define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
Kojto 111:4336505e4b1c 217 #define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
Kojto 111:4336505e4b1c 218 #define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
Kojto 111:4336505e4b1c 219 #define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
Kojto 111:4336505e4b1c 220 #define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
Kojto 111:4336505e4b1c 221 #define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
Kojto 111:4336505e4b1c 222 #define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
Kojto 111:4336505e4b1c 223 #define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
Kojto 111:4336505e4b1c 224 #define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
Kojto 111:4336505e4b1c 225 #define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
Kojto 111:4336505e4b1c 226 #define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 227 #define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 228 #define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 229 #define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 230 #define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 231 #define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 232 #define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 233 #define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 234 #define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 235 #define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 236 #define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
Kojto 111:4336505e4b1c 237 #define RTC_MODE2_CTRL_MASK 0x0FCFul /**< \brief (RTC_MODE2_CTRL) MASK Register */
Kojto 111:4336505e4b1c 238
Kojto 111:4336505e4b1c 239 /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
Kojto 111:4336505e4b1c 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 241 typedef union {
Kojto 111:4336505e4b1c 242 struct {
Kojto 111:4336505e4b1c 243 uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
Kojto 111:4336505e4b1c 244 uint16_t :8; /*!< bit: 6..13 Reserved */
Kojto 111:4336505e4b1c 245 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
Kojto 111:4336505e4b1c 246 uint16_t RREQ:1; /*!< bit: 15 Read Request */
Kojto 111:4336505e4b1c 247 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 248 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 249 } RTC_READREQ_Type;
Kojto 111:4336505e4b1c 250 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 251
Kojto 111:4336505e4b1c 252 #define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */
Kojto 111:4336505e4b1c 253 #define RTC_READREQ_RESETVALUE 0x0010ul /**< \brief (RTC_READREQ reset_value) Read Request */
Kojto 111:4336505e4b1c 254
Kojto 111:4336505e4b1c 255 #define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */
Kojto 111:4336505e4b1c 256 #define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos)
Kojto 111:4336505e4b1c 257 #define RTC_READREQ_ADDR(value) (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))
Kojto 111:4336505e4b1c 258 #define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */
Kojto 111:4336505e4b1c 259 #define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos)
Kojto 111:4336505e4b1c 260 #define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */
Kojto 111:4336505e4b1c 261 #define RTC_READREQ_RREQ (0x1ul << RTC_READREQ_RREQ_Pos)
Kojto 111:4336505e4b1c 262 #define RTC_READREQ_MASK 0xC03Ful /**< \brief (RTC_READREQ) MASK Register */
Kojto 111:4336505e4b1c 263
Kojto 111:4336505e4b1c 264 /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
Kojto 111:4336505e4b1c 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 266 typedef union {
Kojto 111:4336505e4b1c 267 struct {
Kojto 111:4336505e4b1c 268 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
Kojto 111:4336505e4b1c 269 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
Kojto 111:4336505e4b1c 270 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
Kojto 111:4336505e4b1c 271 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
Kojto 111:4336505e4b1c 272 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
Kojto 111:4336505e4b1c 273 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
Kojto 111:4336505e4b1c 274 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
Kojto 111:4336505e4b1c 275 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
Kojto 111:4336505e4b1c 276 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
Kojto 111:4336505e4b1c 277 uint16_t :6; /*!< bit: 9..14 Reserved */
Kojto 111:4336505e4b1c 278 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
Kojto 111:4336505e4b1c 279 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 280 struct {
Kojto 111:4336505e4b1c 281 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
Kojto 111:4336505e4b1c 282 uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
Kojto 111:4336505e4b1c 283 uint16_t :7; /*!< bit: 9..15 Reserved */
Kojto 111:4336505e4b1c 284 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 285 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 286 } RTC_MODE0_EVCTRL_Type;
Kojto 111:4336505e4b1c 287 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 288
Kojto 111:4336505e4b1c 289 #define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
Kojto 111:4336505e4b1c 290 #define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
Kojto 111:4336505e4b1c 291
Kojto 111:4336505e4b1c 292 #define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
Kojto 111:4336505e4b1c 293 #define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
Kojto 111:4336505e4b1c 294 #define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
Kojto 111:4336505e4b1c 295 #define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
Kojto 111:4336505e4b1c 296 #define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
Kojto 111:4336505e4b1c 297 #define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
Kojto 111:4336505e4b1c 298 #define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
Kojto 111:4336505e4b1c 299 #define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
Kojto 111:4336505e4b1c 300 #define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
Kojto 111:4336505e4b1c 301 #define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
Kojto 111:4336505e4b1c 302 #define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
Kojto 111:4336505e4b1c 303 #define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
Kojto 111:4336505e4b1c 304 #define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
Kojto 111:4336505e4b1c 305 #define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
Kojto 111:4336505e4b1c 306 #define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
Kojto 111:4336505e4b1c 307 #define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
Kojto 111:4336505e4b1c 308 #define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
Kojto 111:4336505e4b1c 309 #define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
Kojto 111:4336505e4b1c 310 #define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
Kojto 111:4336505e4b1c 311 #define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
Kojto 111:4336505e4b1c 312 #define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
Kojto 111:4336505e4b1c 313 #define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
Kojto 111:4336505e4b1c 314 #define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
Kojto 111:4336505e4b1c 315 #define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
Kojto 111:4336505e4b1c 316 #define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
Kojto 111:4336505e4b1c 317 #define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
Kojto 111:4336505e4b1c 318 #define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
Kojto 111:4336505e4b1c 319
Kojto 111:4336505e4b1c 320 /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
Kojto 111:4336505e4b1c 321 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 322 typedef union {
Kojto 111:4336505e4b1c 323 struct {
Kojto 111:4336505e4b1c 324 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
Kojto 111:4336505e4b1c 325 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
Kojto 111:4336505e4b1c 326 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
Kojto 111:4336505e4b1c 327 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
Kojto 111:4336505e4b1c 328 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
Kojto 111:4336505e4b1c 329 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
Kojto 111:4336505e4b1c 330 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
Kojto 111:4336505e4b1c 331 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
Kojto 111:4336505e4b1c 332 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
Kojto 111:4336505e4b1c 333 uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
Kojto 111:4336505e4b1c 334 uint16_t :5; /*!< bit: 10..14 Reserved */
Kojto 111:4336505e4b1c 335 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
Kojto 111:4336505e4b1c 336 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 337 struct {
Kojto 111:4336505e4b1c 338 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
Kojto 111:4336505e4b1c 339 uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
Kojto 111:4336505e4b1c 340 uint16_t :6; /*!< bit: 10..15 Reserved */
Kojto 111:4336505e4b1c 341 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 342 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 343 } RTC_MODE1_EVCTRL_Type;
Kojto 111:4336505e4b1c 344 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 345
Kojto 111:4336505e4b1c 346 #define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
Kojto 111:4336505e4b1c 347 #define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
Kojto 111:4336505e4b1c 348
Kojto 111:4336505e4b1c 349 #define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
Kojto 111:4336505e4b1c 350 #define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
Kojto 111:4336505e4b1c 351 #define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
Kojto 111:4336505e4b1c 352 #define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
Kojto 111:4336505e4b1c 353 #define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
Kojto 111:4336505e4b1c 354 #define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
Kojto 111:4336505e4b1c 355 #define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
Kojto 111:4336505e4b1c 356 #define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
Kojto 111:4336505e4b1c 357 #define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
Kojto 111:4336505e4b1c 358 #define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
Kojto 111:4336505e4b1c 359 #define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
Kojto 111:4336505e4b1c 360 #define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
Kojto 111:4336505e4b1c 361 #define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
Kojto 111:4336505e4b1c 362 #define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
Kojto 111:4336505e4b1c 363 #define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
Kojto 111:4336505e4b1c 364 #define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
Kojto 111:4336505e4b1c 365 #define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
Kojto 111:4336505e4b1c 366 #define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
Kojto 111:4336505e4b1c 367 #define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
Kojto 111:4336505e4b1c 368 #define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
Kojto 111:4336505e4b1c 369 #define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
Kojto 111:4336505e4b1c 370 #define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
Kojto 111:4336505e4b1c 371 #define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
Kojto 111:4336505e4b1c 372 #define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
Kojto 111:4336505e4b1c 373 #define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
Kojto 111:4336505e4b1c 374 #define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
Kojto 111:4336505e4b1c 375 #define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
Kojto 111:4336505e4b1c 376 #define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
Kojto 111:4336505e4b1c 377 #define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
Kojto 111:4336505e4b1c 378
Kojto 111:4336505e4b1c 379 /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
Kojto 111:4336505e4b1c 380 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 381 typedef union {
Kojto 111:4336505e4b1c 382 struct {
Kojto 111:4336505e4b1c 383 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
Kojto 111:4336505e4b1c 384 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
Kojto 111:4336505e4b1c 385 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
Kojto 111:4336505e4b1c 386 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
Kojto 111:4336505e4b1c 387 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
Kojto 111:4336505e4b1c 388 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
Kojto 111:4336505e4b1c 389 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
Kojto 111:4336505e4b1c 390 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
Kojto 111:4336505e4b1c 391 uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
Kojto 111:4336505e4b1c 392 uint16_t :6; /*!< bit: 9..14 Reserved */
Kojto 111:4336505e4b1c 393 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
Kojto 111:4336505e4b1c 394 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 395 struct {
Kojto 111:4336505e4b1c 396 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
Kojto 111:4336505e4b1c 397 uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
Kojto 111:4336505e4b1c 398 uint16_t :7; /*!< bit: 9..15 Reserved */
Kojto 111:4336505e4b1c 399 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 400 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 401 } RTC_MODE2_EVCTRL_Type;
Kojto 111:4336505e4b1c 402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 403
Kojto 111:4336505e4b1c 404 #define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
Kojto 111:4336505e4b1c 405 #define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
Kojto 111:4336505e4b1c 406
Kojto 111:4336505e4b1c 407 #define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
Kojto 111:4336505e4b1c 408 #define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
Kojto 111:4336505e4b1c 409 #define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
Kojto 111:4336505e4b1c 410 #define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
Kojto 111:4336505e4b1c 411 #define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
Kojto 111:4336505e4b1c 412 #define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
Kojto 111:4336505e4b1c 413 #define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
Kojto 111:4336505e4b1c 414 #define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
Kojto 111:4336505e4b1c 415 #define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
Kojto 111:4336505e4b1c 416 #define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
Kojto 111:4336505e4b1c 417 #define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
Kojto 111:4336505e4b1c 418 #define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
Kojto 111:4336505e4b1c 419 #define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
Kojto 111:4336505e4b1c 420 #define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
Kojto 111:4336505e4b1c 421 #define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
Kojto 111:4336505e4b1c 422 #define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
Kojto 111:4336505e4b1c 423 #define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
Kojto 111:4336505e4b1c 424 #define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
Kojto 111:4336505e4b1c 425 #define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
Kojto 111:4336505e4b1c 426 #define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
Kojto 111:4336505e4b1c 427 #define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
Kojto 111:4336505e4b1c 428 #define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
Kojto 111:4336505e4b1c 429 #define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
Kojto 111:4336505e4b1c 430 #define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
Kojto 111:4336505e4b1c 431 #define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
Kojto 111:4336505e4b1c 432 #define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
Kojto 111:4336505e4b1c 433 #define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
Kojto 111:4336505e4b1c 434
Kojto 111:4336505e4b1c 435 /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 436 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 437 typedef union {
Kojto 111:4336505e4b1c 438 struct {
Kojto 111:4336505e4b1c 439 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
Kojto 111:4336505e4b1c 440 uint8_t :5; /*!< bit: 1.. 5 Reserved */
Kojto 111:4336505e4b1c 441 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 442 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 443 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 444 struct {
Kojto 111:4336505e4b1c 445 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
Kojto 111:4336505e4b1c 446 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 447 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 448 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 449 } RTC_MODE0_INTENCLR_Type;
Kojto 111:4336505e4b1c 450 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 451
Kojto 111:4336505e4b1c 452 #define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
Kojto 111:4336505e4b1c 453 #define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
Kojto 111:4336505e4b1c 454
Kojto 111:4336505e4b1c 455 #define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
Kojto 111:4336505e4b1c 456 #define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
Kojto 111:4336505e4b1c 457 #define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
Kojto 111:4336505e4b1c 458 #define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
Kojto 111:4336505e4b1c 459 #define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
Kojto 111:4336505e4b1c 460 #define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 461 #define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 462 #define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 463 #define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos)
Kojto 111:4336505e4b1c 464 #define RTC_MODE0_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 465
Kojto 111:4336505e4b1c 466 /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 467 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 468 typedef union {
Kojto 111:4336505e4b1c 469 struct {
Kojto 111:4336505e4b1c 470 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
Kojto 111:4336505e4b1c 471 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
Kojto 111:4336505e4b1c 472 uint8_t :4; /*!< bit: 2.. 5 Reserved */
Kojto 111:4336505e4b1c 473 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 474 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 475 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 476 struct {
Kojto 111:4336505e4b1c 477 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
Kojto 111:4336505e4b1c 478 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 479 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 480 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 481 } RTC_MODE1_INTENCLR_Type;
Kojto 111:4336505e4b1c 482 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 483
Kojto 111:4336505e4b1c 484 #define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
Kojto 111:4336505e4b1c 485 #define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
Kojto 111:4336505e4b1c 486
Kojto 111:4336505e4b1c 487 #define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
Kojto 111:4336505e4b1c 488 #define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
Kojto 111:4336505e4b1c 489 #define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
Kojto 111:4336505e4b1c 490 #define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
Kojto 111:4336505e4b1c 491 #define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
Kojto 111:4336505e4b1c 492 #define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
Kojto 111:4336505e4b1c 493 #define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
Kojto 111:4336505e4b1c 494 #define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 495 #define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 496 #define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 497 #define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos)
Kojto 111:4336505e4b1c 498 #define RTC_MODE1_INTENCLR_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 499
Kojto 111:4336505e4b1c 500 /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
Kojto 111:4336505e4b1c 501 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 502 typedef union {
Kojto 111:4336505e4b1c 503 struct {
Kojto 111:4336505e4b1c 504 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
Kojto 111:4336505e4b1c 505 uint8_t :5; /*!< bit: 1.. 5 Reserved */
Kojto 111:4336505e4b1c 506 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 507 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 508 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 509 struct {
Kojto 111:4336505e4b1c 510 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
Kojto 111:4336505e4b1c 511 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 512 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 513 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 514 } RTC_MODE2_INTENCLR_Type;
Kojto 111:4336505e4b1c 515 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 516
Kojto 111:4336505e4b1c 517 #define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
Kojto 111:4336505e4b1c 518 #define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
Kojto 111:4336505e4b1c 519
Kojto 111:4336505e4b1c 520 #define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
Kojto 111:4336505e4b1c 521 #define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
Kojto 111:4336505e4b1c 522 #define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
Kojto 111:4336505e4b1c 523 #define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
Kojto 111:4336505e4b1c 524 #define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
Kojto 111:4336505e4b1c 525 #define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 526 #define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 527 #define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 528 #define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos)
Kojto 111:4336505e4b1c 529 #define RTC_MODE2_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
Kojto 111:4336505e4b1c 530
Kojto 111:4336505e4b1c 531 /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 532 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 533 typedef union {
Kojto 111:4336505e4b1c 534 struct {
Kojto 111:4336505e4b1c 535 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
Kojto 111:4336505e4b1c 536 uint8_t :5; /*!< bit: 1.. 5 Reserved */
Kojto 111:4336505e4b1c 537 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 538 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 539 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 540 struct {
Kojto 111:4336505e4b1c 541 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
Kojto 111:4336505e4b1c 542 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 543 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 544 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 545 } RTC_MODE0_INTENSET_Type;
Kojto 111:4336505e4b1c 546 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 547
Kojto 111:4336505e4b1c 548 #define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
Kojto 111:4336505e4b1c 549 #define RTC_MODE0_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
Kojto 111:4336505e4b1c 550
Kojto 111:4336505e4b1c 551 #define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
Kojto 111:4336505e4b1c 552 #define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos)
Kojto 111:4336505e4b1c 553 #define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
Kojto 111:4336505e4b1c 554 #define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
Kojto 111:4336505e4b1c 555 #define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
Kojto 111:4336505e4b1c 556 #define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 557 #define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 558 #define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 559 #define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos)
Kojto 111:4336505e4b1c 560 #define RTC_MODE0_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 561
Kojto 111:4336505e4b1c 562 /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 563 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 564 typedef union {
Kojto 111:4336505e4b1c 565 struct {
Kojto 111:4336505e4b1c 566 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
Kojto 111:4336505e4b1c 567 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
Kojto 111:4336505e4b1c 568 uint8_t :4; /*!< bit: 2.. 5 Reserved */
Kojto 111:4336505e4b1c 569 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 570 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 571 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 572 struct {
Kojto 111:4336505e4b1c 573 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
Kojto 111:4336505e4b1c 574 uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 575 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 576 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 577 } RTC_MODE1_INTENSET_Type;
Kojto 111:4336505e4b1c 578 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 579
Kojto 111:4336505e4b1c 580 #define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
Kojto 111:4336505e4b1c 581 #define RTC_MODE1_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
Kojto 111:4336505e4b1c 582
Kojto 111:4336505e4b1c 583 #define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
Kojto 111:4336505e4b1c 584 #define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos)
Kojto 111:4336505e4b1c 585 #define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
Kojto 111:4336505e4b1c 586 #define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos)
Kojto 111:4336505e4b1c 587 #define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
Kojto 111:4336505e4b1c 588 #define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
Kojto 111:4336505e4b1c 589 #define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
Kojto 111:4336505e4b1c 590 #define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 591 #define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 592 #define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 593 #define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos)
Kojto 111:4336505e4b1c 594 #define RTC_MODE1_INTENSET_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 595
Kojto 111:4336505e4b1c 596 /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
Kojto 111:4336505e4b1c 597 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 598 typedef union {
Kojto 111:4336505e4b1c 599 struct {
Kojto 111:4336505e4b1c 600 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
Kojto 111:4336505e4b1c 601 uint8_t :5; /*!< bit: 1.. 5 Reserved */
Kojto 111:4336505e4b1c 602 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 603 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 604 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 605 struct {
Kojto 111:4336505e4b1c 606 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
Kojto 111:4336505e4b1c 607 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 608 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 609 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 610 } RTC_MODE2_INTENSET_Type;
Kojto 111:4336505e4b1c 611 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 612
Kojto 111:4336505e4b1c 613 #define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
Kojto 111:4336505e4b1c 614 #define RTC_MODE2_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
Kojto 111:4336505e4b1c 615
Kojto 111:4336505e4b1c 616 #define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
Kojto 111:4336505e4b1c 617 #define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
Kojto 111:4336505e4b1c 618 #define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
Kojto 111:4336505e4b1c 619 #define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
Kojto 111:4336505e4b1c 620 #define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
Kojto 111:4336505e4b1c 621 #define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
Kojto 111:4336505e4b1c 622 #define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 623 #define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
Kojto 111:4336505e4b1c 624 #define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos)
Kojto 111:4336505e4b1c 625 #define RTC_MODE2_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENSET) MASK Register */
Kojto 111:4336505e4b1c 626
Kojto 111:4336505e4b1c 627 /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 628 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 629 typedef union { // __I to avoid read-modify-write on write-to-clear register
Kojto 111:4336505e4b1c 630 struct {
Kojto 111:4336505e4b1c 631 __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
Kojto 111:4336505e4b1c 632 __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
Kojto 111:4336505e4b1c 633 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
Kojto 111:4336505e4b1c 634 __I uint8_t OVF:1; /*!< bit: 7 Overflow */
Kojto 111:4336505e4b1c 635 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 636 struct {
Kojto 111:4336505e4b1c 637 __I uint8_t CMP:1; /*!< bit: 0 Compare x */
Kojto 111:4336505e4b1c 638 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 639 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 640 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 641 } RTC_MODE0_INTFLAG_Type;
Kojto 111:4336505e4b1c 642 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 643
Kojto 111:4336505e4b1c 644 #define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 645 #define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 646
Kojto 111:4336505e4b1c 647 #define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
Kojto 111:4336505e4b1c 648 #define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
Kojto 111:4336505e4b1c 649 #define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
Kojto 111:4336505e4b1c 650 #define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
Kojto 111:4336505e4b1c 651 #define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
Kojto 111:4336505e4b1c 652 #define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
Kojto 111:4336505e4b1c 653 #define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 654 #define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
Kojto 111:4336505e4b1c 655 #define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos)
Kojto 111:4336505e4b1c 656 #define RTC_MODE0_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 657
Kojto 111:4336505e4b1c 658 /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 659 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 660 typedef union { // __I to avoid read-modify-write on write-to-clear register
Kojto 111:4336505e4b1c 661 struct {
Kojto 111:4336505e4b1c 662 __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
Kojto 111:4336505e4b1c 663 __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
Kojto 111:4336505e4b1c 664 __I uint8_t :4; /*!< bit: 2.. 5 Reserved */
Kojto 111:4336505e4b1c 665 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
Kojto 111:4336505e4b1c 666 __I uint8_t OVF:1; /*!< bit: 7 Overflow */
Kojto 111:4336505e4b1c 667 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 668 struct {
Kojto 111:4336505e4b1c 669 __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
Kojto 111:4336505e4b1c 670 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
Kojto 111:4336505e4b1c 671 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 672 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 673 } RTC_MODE1_INTFLAG_Type;
Kojto 111:4336505e4b1c 674 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 675
Kojto 111:4336505e4b1c 676 #define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 677 #define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 678
Kojto 111:4336505e4b1c 679 #define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
Kojto 111:4336505e4b1c 680 #define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
Kojto 111:4336505e4b1c 681 #define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
Kojto 111:4336505e4b1c 682 #define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
Kojto 111:4336505e4b1c 683 #define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
Kojto 111:4336505e4b1c 684 #define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
Kojto 111:4336505e4b1c 685 #define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
Kojto 111:4336505e4b1c 686 #define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
Kojto 111:4336505e4b1c 687 #define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 688 #define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
Kojto 111:4336505e4b1c 689 #define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos)
Kojto 111:4336505e4b1c 690 #define RTC_MODE1_INTFLAG_MASK 0xC3ul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 691
Kojto 111:4336505e4b1c 692 /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
Kojto 111:4336505e4b1c 693 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 694 typedef union { // __I to avoid read-modify-write on write-to-clear register
Kojto 111:4336505e4b1c 695 struct {
Kojto 111:4336505e4b1c 696 __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
Kojto 111:4336505e4b1c 697 __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
Kojto 111:4336505e4b1c 698 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
Kojto 111:4336505e4b1c 699 __I uint8_t OVF:1; /*!< bit: 7 Overflow */
Kojto 111:4336505e4b1c 700 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 701 struct {
Kojto 111:4336505e4b1c 702 __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
Kojto 111:4336505e4b1c 703 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 704 } vec; /*!< Structure used for vec access */
Kojto 111:4336505e4b1c 705 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 706 } RTC_MODE2_INTFLAG_Type;
Kojto 111:4336505e4b1c 707 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 708
Kojto 111:4336505e4b1c 709 #define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 710 #define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 711
Kojto 111:4336505e4b1c 712 #define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
Kojto 111:4336505e4b1c 713 #define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
Kojto 111:4336505e4b1c 714 #define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
Kojto 111:4336505e4b1c 715 #define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
Kojto 111:4336505e4b1c 716 #define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
Kojto 111:4336505e4b1c 717 #define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
Kojto 111:4336505e4b1c 718 #define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
Kojto 111:4336505e4b1c 719 #define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
Kojto 111:4336505e4b1c 720 #define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos)
Kojto 111:4336505e4b1c 721 #define RTC_MODE2_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
Kojto 111:4336505e4b1c 722
Kojto 111:4336505e4b1c 723 /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
Kojto 111:4336505e4b1c 724 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 725 typedef union {
Kojto 111:4336505e4b1c 726 struct {
Kojto 111:4336505e4b1c 727 uint8_t :7; /*!< bit: 0.. 6 Reserved */
Kojto 111:4336505e4b1c 728 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
Kojto 111:4336505e4b1c 729 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 730 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 731 } RTC_STATUS_Type;
Kojto 111:4336505e4b1c 732 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 733
Kojto 111:4336505e4b1c 734 #define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */
Kojto 111:4336505e4b1c 735 #define RTC_STATUS_RESETVALUE 0x00ul /**< \brief (RTC_STATUS reset_value) Status */
Kojto 111:4336505e4b1c 736
Kojto 111:4336505e4b1c 737 #define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */
Kojto 111:4336505e4b1c 738 #define RTC_STATUS_SYNCBUSY (0x1ul << RTC_STATUS_SYNCBUSY_Pos)
Kojto 111:4336505e4b1c 739 #define RTC_STATUS_MASK 0x80ul /**< \brief (RTC_STATUS) MASK Register */
Kojto 111:4336505e4b1c 740
Kojto 111:4336505e4b1c 741 /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
Kojto 111:4336505e4b1c 742 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 743 typedef union {
Kojto 111:4336505e4b1c 744 struct {
Kojto 111:4336505e4b1c 745 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
Kojto 111:4336505e4b1c 746 uint8_t :7; /*!< bit: 1.. 7 Reserved */
Kojto 111:4336505e4b1c 747 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 748 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 749 } RTC_DBGCTRL_Type;
Kojto 111:4336505e4b1c 750 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 751
Kojto 111:4336505e4b1c 752 #define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */
Kojto 111:4336505e4b1c 753 #define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
Kojto 111:4336505e4b1c 754
Kojto 111:4336505e4b1c 755 #define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
Kojto 111:4336505e4b1c 756 #define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos)
Kojto 111:4336505e4b1c 757 #define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */
Kojto 111:4336505e4b1c 758
Kojto 111:4336505e4b1c 759 /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
Kojto 111:4336505e4b1c 760 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 761 typedef union {
Kojto 111:4336505e4b1c 762 struct {
Kojto 111:4336505e4b1c 763 uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
Kojto 111:4336505e4b1c 764 uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
Kojto 111:4336505e4b1c 765 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 766 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 767 } RTC_FREQCORR_Type;
Kojto 111:4336505e4b1c 768 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 769
Kojto 111:4336505e4b1c 770 #define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */
Kojto 111:4336505e4b1c 771 #define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
Kojto 111:4336505e4b1c 772
Kojto 111:4336505e4b1c 773 #define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
Kojto 111:4336505e4b1c 774 #define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos)
Kojto 111:4336505e4b1c 775 #define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
Kojto 111:4336505e4b1c 776 #define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
Kojto 111:4336505e4b1c 777 #define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos)
Kojto 111:4336505e4b1c 778 #define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */
Kojto 111:4336505e4b1c 779
Kojto 111:4336505e4b1c 780 /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
Kojto 111:4336505e4b1c 781 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 782 typedef union {
Kojto 111:4336505e4b1c 783 struct {
Kojto 111:4336505e4b1c 784 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
Kojto 111:4336505e4b1c 785 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 786 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 787 } RTC_MODE0_COUNT_Type;
Kojto 111:4336505e4b1c 788 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 789
Kojto 111:4336505e4b1c 790 #define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
Kojto 111:4336505e4b1c 791 #define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
Kojto 111:4336505e4b1c 792
Kojto 111:4336505e4b1c 793 #define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
Kojto 111:4336505e4b1c 794 #define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
Kojto 111:4336505e4b1c 795 #define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
Kojto 111:4336505e4b1c 796 #define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
Kojto 111:4336505e4b1c 797
Kojto 111:4336505e4b1c 798 /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
Kojto 111:4336505e4b1c 799 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 800 typedef union {
Kojto 111:4336505e4b1c 801 struct {
Kojto 111:4336505e4b1c 802 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
Kojto 111:4336505e4b1c 803 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 804 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 805 } RTC_MODE1_COUNT_Type;
Kojto 111:4336505e4b1c 806 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 807
Kojto 111:4336505e4b1c 808 #define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
Kojto 111:4336505e4b1c 809 #define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
Kojto 111:4336505e4b1c 810
Kojto 111:4336505e4b1c 811 #define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
Kojto 111:4336505e4b1c 812 #define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
Kojto 111:4336505e4b1c 813 #define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
Kojto 111:4336505e4b1c 814 #define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */
Kojto 111:4336505e4b1c 815
Kojto 111:4336505e4b1c 816 /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
Kojto 111:4336505e4b1c 817 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 818 typedef union {
Kojto 111:4336505e4b1c 819 struct {
Kojto 111:4336505e4b1c 820 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
Kojto 111:4336505e4b1c 821 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
Kojto 111:4336505e4b1c 822 uint32_t HOUR:5; /*!< bit: 12..16 Hour */
Kojto 111:4336505e4b1c 823 uint32_t DAY:5; /*!< bit: 17..21 Day */
Kojto 111:4336505e4b1c 824 uint32_t MONTH:4; /*!< bit: 22..25 Month */
Kojto 111:4336505e4b1c 825 uint32_t YEAR:6; /*!< bit: 26..31 Year */
Kojto 111:4336505e4b1c 826 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 827 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 828 } RTC_MODE2_CLOCK_Type;
Kojto 111:4336505e4b1c 829 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 830
Kojto 111:4336505e4b1c 831 #define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
Kojto 111:4336505e4b1c 832 #define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
Kojto 111:4336505e4b1c 833
Kojto 111:4336505e4b1c 834 #define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
Kojto 111:4336505e4b1c 835 #define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
Kojto 111:4336505e4b1c 836 #define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
Kojto 111:4336505e4b1c 837 #define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
Kojto 111:4336505e4b1c 838 #define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
Kojto 111:4336505e4b1c 839 #define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
Kojto 111:4336505e4b1c 840 #define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
Kojto 111:4336505e4b1c 841 #define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
Kojto 111:4336505e4b1c 842 #define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
Kojto 111:4336505e4b1c 843 #define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
Kojto 111:4336505e4b1c 844 #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
Kojto 111:4336505e4b1c 845 #define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
Kojto 111:4336505e4b1c 846 #define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
Kojto 111:4336505e4b1c 847 #define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
Kojto 111:4336505e4b1c 848 #define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
Kojto 111:4336505e4b1c 849 #define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
Kojto 111:4336505e4b1c 850 #define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
Kojto 111:4336505e4b1c 851 #define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
Kojto 111:4336505e4b1c 852 #define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
Kojto 111:4336505e4b1c 853 #define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
Kojto 111:4336505e4b1c 854 #define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
Kojto 111:4336505e4b1c 855
Kojto 111:4336505e4b1c 856 /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
Kojto 111:4336505e4b1c 857 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 858 typedef union {
Kojto 111:4336505e4b1c 859 struct {
Kojto 111:4336505e4b1c 860 uint16_t PER:16; /*!< bit: 0..15 Counter Period */
Kojto 111:4336505e4b1c 861 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 862 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 863 } RTC_MODE1_PER_Type;
Kojto 111:4336505e4b1c 864 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 865
Kojto 111:4336505e4b1c 866 #define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
Kojto 111:4336505e4b1c 867 #define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
Kojto 111:4336505e4b1c 868
Kojto 111:4336505e4b1c 869 #define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
Kojto 111:4336505e4b1c 870 #define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos)
Kojto 111:4336505e4b1c 871 #define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
Kojto 111:4336505e4b1c 872 #define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */
Kojto 111:4336505e4b1c 873
Kojto 111:4336505e4b1c 874 /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
Kojto 111:4336505e4b1c 875 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 876 typedef union {
Kojto 111:4336505e4b1c 877 struct {
Kojto 111:4336505e4b1c 878 uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
Kojto 111:4336505e4b1c 879 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 880 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 881 } RTC_MODE0_COMP_Type;
Kojto 111:4336505e4b1c 882 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 883
Kojto 111:4336505e4b1c 884 #define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
Kojto 111:4336505e4b1c 885 #define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
Kojto 111:4336505e4b1c 886
Kojto 111:4336505e4b1c 887 #define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
Kojto 111:4336505e4b1c 888 #define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
Kojto 111:4336505e4b1c 889 #define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
Kojto 111:4336505e4b1c 890 #define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
Kojto 111:4336505e4b1c 891
Kojto 111:4336505e4b1c 892 /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
Kojto 111:4336505e4b1c 893 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 894 typedef union {
Kojto 111:4336505e4b1c 895 struct {
Kojto 111:4336505e4b1c 896 uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
Kojto 111:4336505e4b1c 897 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 898 uint16_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 899 } RTC_MODE1_COMP_Type;
Kojto 111:4336505e4b1c 900 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 901
Kojto 111:4336505e4b1c 902 #define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
Kojto 111:4336505e4b1c 903 #define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
Kojto 111:4336505e4b1c 904
Kojto 111:4336505e4b1c 905 #define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
Kojto 111:4336505e4b1c 906 #define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
Kojto 111:4336505e4b1c 907 #define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
Kojto 111:4336505e4b1c 908 #define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */
Kojto 111:4336505e4b1c 909
Kojto 111:4336505e4b1c 910 /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
Kojto 111:4336505e4b1c 911 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 912 typedef union {
Kojto 111:4336505e4b1c 913 struct {
Kojto 111:4336505e4b1c 914 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
Kojto 111:4336505e4b1c 915 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
Kojto 111:4336505e4b1c 916 uint32_t HOUR:5; /*!< bit: 12..16 Hour */
Kojto 111:4336505e4b1c 917 uint32_t DAY:5; /*!< bit: 17..21 Day */
Kojto 111:4336505e4b1c 918 uint32_t MONTH:4; /*!< bit: 22..25 Month */
Kojto 111:4336505e4b1c 919 uint32_t YEAR:6; /*!< bit: 26..31 Year */
Kojto 111:4336505e4b1c 920 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 921 uint32_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 922 } RTC_MODE2_ALARM_Type;
Kojto 111:4336505e4b1c 923 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 924
Kojto 111:4336505e4b1c 925 #define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
Kojto 111:4336505e4b1c 926 #define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
Kojto 111:4336505e4b1c 927
Kojto 111:4336505e4b1c 928 #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
Kojto 111:4336505e4b1c 929 #define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
Kojto 111:4336505e4b1c 930 #define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
Kojto 111:4336505e4b1c 931 #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
Kojto 111:4336505e4b1c 932 #define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
Kojto 111:4336505e4b1c 933 #define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
Kojto 111:4336505e4b1c 934 #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
Kojto 111:4336505e4b1c 935 #define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
Kojto 111:4336505e4b1c 936 #define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
Kojto 111:4336505e4b1c 937 #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
Kojto 111:4336505e4b1c 938 #define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
Kojto 111:4336505e4b1c 939 #define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
Kojto 111:4336505e4b1c 940 #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
Kojto 111:4336505e4b1c 941 #define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
Kojto 111:4336505e4b1c 942 #define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
Kojto 111:4336505e4b1c 943 #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
Kojto 111:4336505e4b1c 944 #define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
Kojto 111:4336505e4b1c 945 #define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
Kojto 111:4336505e4b1c 946 #define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
Kojto 111:4336505e4b1c 947
Kojto 111:4336505e4b1c 948 /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
Kojto 111:4336505e4b1c 949 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 950 typedef union {
Kojto 111:4336505e4b1c 951 struct {
Kojto 111:4336505e4b1c 952 uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
Kojto 111:4336505e4b1c 953 uint8_t :5; /*!< bit: 3.. 7 Reserved */
Kojto 111:4336505e4b1c 954 } bit; /*!< Structure used for bit access */
Kojto 111:4336505e4b1c 955 uint8_t reg; /*!< Type used for register access */
Kojto 111:4336505e4b1c 956 } RTC_MODE2_MASK_Type;
Kojto 111:4336505e4b1c 957 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 958
Kojto 111:4336505e4b1c 959 #define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
Kojto 111:4336505e4b1c 960 #define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
Kojto 111:4336505e4b1c 961
Kojto 111:4336505e4b1c 962 #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
Kojto 111:4336505e4b1c 963 #define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos)
Kojto 111:4336505e4b1c 964 #define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
Kojto 111:4336505e4b1c 965 #define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
Kojto 111:4336505e4b1c 966 #define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */
Kojto 111:4336505e4b1c 967 #define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
Kojto 111:4336505e4b1c 968 #define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
Kojto 111:4336505e4b1c 969 #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
Kojto 111:4336505e4b1c 970 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
Kojto 111:4336505e4b1c 971 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
Kojto 111:4336505e4b1c 972 #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
Kojto 111:4336505e4b1c 973 #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
Kojto 111:4336505e4b1c 974 #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
Kojto 111:4336505e4b1c 975 #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
Kojto 111:4336505e4b1c 976 #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
Kojto 111:4336505e4b1c 977 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
Kojto 111:4336505e4b1c 978 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
Kojto 111:4336505e4b1c 979 #define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */
Kojto 111:4336505e4b1c 980
Kojto 111:4336505e4b1c 981 /** \brief RtcMode2Alarm hardware registers */
Kojto 111:4336505e4b1c 982 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 983 typedef struct {
Kojto 111:4336505e4b1c 984 __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
Kojto 111:4336505e4b1c 985 __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
Kojto 111:4336505e4b1c 986 RoReg8 Reserved1[0x3];
Kojto 111:4336505e4b1c 987 } RtcMode2Alarm;
Kojto 111:4336505e4b1c 988 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 989
Kojto 111:4336505e4b1c 990 /** \brief RTC_MODE0 hardware registers */
Kojto 111:4336505e4b1c 991 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 992 typedef struct { /* 32-bit Counter with Single 32-bit Compare */
Kojto 111:4336505e4b1c 993 __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
Kojto 111:4336505e4b1c 994 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
Kojto 111:4336505e4b1c 995 __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
Kojto 111:4336505e4b1c 996 __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
Kojto 111:4336505e4b1c 997 __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
Kojto 111:4336505e4b1c 998 __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 999 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 1000 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
Kojto 111:4336505e4b1c 1001 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
Kojto 111:4336505e4b1c 1002 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
Kojto 111:4336505e4b1c 1003 RoReg8 Reserved2[0x3];
Kojto 111:4336505e4b1c 1004 __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
Kojto 111:4336505e4b1c 1005 RoReg8 Reserved3[0x4];
Kojto 111:4336505e4b1c 1006 __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
Kojto 111:4336505e4b1c 1007 } RtcMode0;
Kojto 111:4336505e4b1c 1008 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1009
Kojto 111:4336505e4b1c 1010 /** \brief RTC_MODE1 hardware registers */
Kojto 111:4336505e4b1c 1011 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1012 typedef struct { /* 16-bit Counter with Two 16-bit Compares */
Kojto 111:4336505e4b1c 1013 __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
Kojto 111:4336505e4b1c 1014 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
Kojto 111:4336505e4b1c 1015 __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
Kojto 111:4336505e4b1c 1016 __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
Kojto 111:4336505e4b1c 1017 __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
Kojto 111:4336505e4b1c 1018 __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 1019 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 1020 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
Kojto 111:4336505e4b1c 1021 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
Kojto 111:4336505e4b1c 1022 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
Kojto 111:4336505e4b1c 1023 RoReg8 Reserved2[0x3];
Kojto 111:4336505e4b1c 1024 __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
Kojto 111:4336505e4b1c 1025 RoReg8 Reserved3[0x2];
Kojto 111:4336505e4b1c 1026 __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
Kojto 111:4336505e4b1c 1027 RoReg8 Reserved4[0x2];
Kojto 111:4336505e4b1c 1028 __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
Kojto 111:4336505e4b1c 1029 } RtcMode1;
Kojto 111:4336505e4b1c 1030 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1031
Kojto 111:4336505e4b1c 1032 /** \brief RTC_MODE2 hardware registers */
Kojto 111:4336505e4b1c 1033 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1034 typedef struct { /* Clock/Calendar with Alarm */
Kojto 111:4336505e4b1c 1035 __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
Kojto 111:4336505e4b1c 1036 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
Kojto 111:4336505e4b1c 1037 __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
Kojto 111:4336505e4b1c 1038 __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
Kojto 111:4336505e4b1c 1039 __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
Kojto 111:4336505e4b1c 1040 __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 1041 RoReg8 Reserved1[0x1];
Kojto 111:4336505e4b1c 1042 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
Kojto 111:4336505e4b1c 1043 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
Kojto 111:4336505e4b1c 1044 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
Kojto 111:4336505e4b1c 1045 RoReg8 Reserved2[0x3];
Kojto 111:4336505e4b1c 1046 __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
Kojto 111:4336505e4b1c 1047 RoReg8 Reserved3[0x4];
Kojto 111:4336505e4b1c 1048 RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
Kojto 111:4336505e4b1c 1049 } RtcMode2;
Kojto 111:4336505e4b1c 1050 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1051
Kojto 111:4336505e4b1c 1052 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 1053 typedef union {
Kojto 111:4336505e4b1c 1054 RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
Kojto 111:4336505e4b1c 1055 RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
Kojto 111:4336505e4b1c 1056 RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
Kojto 111:4336505e4b1c 1057 } Rtc;
Kojto 111:4336505e4b1c 1058 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 1059
Kojto 111:4336505e4b1c 1060 /*@}*/
Kojto 111:4336505e4b1c 1061
Kojto 111:4336505e4b1c 1062 #endif /* _SAMR21_RTC_COMPONENT_ */