Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_NUCLEO_F303K8/stm32f3xx_hal_rcc.h@111:4336505e4b1c, 2015-12-15 (annotated)

Committer:
Kojto
Date:
Tue Dec 15 14:39:38 2015 +0000
Revision:
111:4336505e4b1c
Parent:
109:9296ab0bfc11 
Release 111 of the mbed library



Changes:

- new platforms - Atmel targets (SAMR21G18A, SAMD21J18A, SAMD21G18A)

- Streams - add var argument (vprintf, vscanf)

- MAXWSNENV - BLE stack library additio

- LPC1768 - fix slave read

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**
Kojto 109:9296ab0bfc11 2 ******************************************************************************
Kojto 109:9296ab0bfc11 3 * @file stm32f3xx_hal_rcc.h
Kojto 109:9296ab0bfc11 4 * @author MCD Application Team
Kojto 109:9296ab0bfc11 5 * @version V1.1.0
Kojto 109:9296ab0bfc11 6 * @date 12-Sept-2014
Kojto 109:9296ab0bfc11 7 * @brief Header file of RCC HAL module.
Kojto 109:9296ab0bfc11 8 ******************************************************************************
Kojto 109:9296ab0bfc11 9 * @attention
Kojto 109:9296ab0bfc11 10 *
Kojto 109:9296ab0bfc11 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 109:9296ab0bfc11 12 *
Kojto 109:9296ab0bfc11 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 109:9296ab0bfc11 14 * are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 109:9296ab0bfc11 16 * this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 109:9296ab0bfc11 18 * this list of conditions and the following disclaimer in the documentation
Kojto 109:9296ab0bfc11 19 * and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 109:9296ab0bfc11 21 * may be used to endorse or promote products derived from this software
Kojto 109:9296ab0bfc11 22 * without specific prior written permission.
Kojto 109:9296ab0bfc11 23 *
Kojto 109:9296ab0bfc11 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 109:9296ab0bfc11 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 109:9296ab0bfc11 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 109:9296ab0bfc11 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 109:9296ab0bfc11 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 109:9296ab0bfc11 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 109:9296ab0bfc11 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 109:9296ab0bfc11 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 34 *
Kojto 109:9296ab0bfc11 35 ******************************************************************************
Kojto 109:9296ab0bfc11 36 */
Kojto 109:9296ab0bfc11 37
Kojto 109:9296ab0bfc11 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 109:9296ab0bfc11 39 #ifndef __STM32F3xx_HAL_RCC_H
Kojto 109:9296ab0bfc11 40 #define __STM32F3xx_HAL_RCC_H
Kojto 109:9296ab0bfc11 41
Kojto 109:9296ab0bfc11 42 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 43 extern "C" {
Kojto 109:9296ab0bfc11 44 #endif
Kojto 109:9296ab0bfc11 45
Kojto 109:9296ab0bfc11 46 /* Includes ------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 47 #include "stm32f3xx_hal_def.h"
Kojto 109:9296ab0bfc11 48
Kojto 109:9296ab0bfc11 49 /** @addtogroup STM32F3xx_HAL_Driver
Kojto 109:9296ab0bfc11 50 * @{
Kojto 109:9296ab0bfc11 51 */
Kojto 109:9296ab0bfc11 52
Kojto 109:9296ab0bfc11 53 /** @addtogroup RCC
Kojto 109:9296ab0bfc11 54 * @{
Kojto 109:9296ab0bfc11 55 */
Kojto 109:9296ab0bfc11 56
Kojto 109:9296ab0bfc11 57 /* Exported types ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 58
Kojto 109:9296ab0bfc11 59 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 109:9296ab0bfc11 60 * @{
Kojto 109:9296ab0bfc11 61 */
Kojto 109:9296ab0bfc11 62
Kojto 109:9296ab0bfc11 63 /**
Kojto 109:9296ab0bfc11 64 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 109:9296ab0bfc11 65 */
Kojto 109:9296ab0bfc11 66 typedef struct
Kojto 109:9296ab0bfc11 67 {
Kojto 109:9296ab0bfc11 68 uint32_t ClockType; /*!< The clock to be configured.
Kojto 109:9296ab0bfc11 69 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 109:9296ab0bfc11 70
Kojto 109:9296ab0bfc11 71 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto 109:9296ab0bfc11 72 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 109:9296ab0bfc11 73
Kojto 109:9296ab0bfc11 74 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 109:9296ab0bfc11 75 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 109:9296ab0bfc11 76
Kojto 109:9296ab0bfc11 77 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 109:9296ab0bfc11 78 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 109:9296ab0bfc11 79
Kojto 109:9296ab0bfc11 80 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto 109:9296ab0bfc11 81 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 109:9296ab0bfc11 82
Kojto 109:9296ab0bfc11 83 }RCC_ClkInitTypeDef;
Kojto 109:9296ab0bfc11 84
Kojto 109:9296ab0bfc11 85 /**
Kojto 109:9296ab0bfc11 86 * @}
Kojto 109:9296ab0bfc11 87 */
Kojto 109:9296ab0bfc11 88
Kojto 109:9296ab0bfc11 89 /* Exported constants --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 90 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 109:9296ab0bfc11 91 * @{
Kojto 109:9296ab0bfc11 92 */
Kojto 109:9296ab0bfc11 93
Kojto 109:9296ab0bfc11 94 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 109:9296ab0bfc11 95 * @brief RCC registers bit address in the alias region
Kojto 109:9296ab0bfc11 96 * @{
Kojto 109:9296ab0bfc11 97 */
Kojto 109:9296ab0bfc11 98 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 109:9296ab0bfc11 99 /* --- CR Register ---*/
Kojto 109:9296ab0bfc11 100 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto 109:9296ab0bfc11 101 /* Alias word address of HSION bit */
Kojto 109:9296ab0bfc11 102 #define HSION_BitNumber 0
Kojto 109:9296ab0bfc11 103 #define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
Kojto 109:9296ab0bfc11 104 /* Alias word address of HSEON bit */
Kojto 109:9296ab0bfc11 105 #define HSEON_BitNumber 16
Kojto 109:9296ab0bfc11 106 #define CR_HSEON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSEON_BitNumber * 4))
Kojto 109:9296ab0bfc11 107 /* Alias word address of CSSON bit */
Kojto 109:9296ab0bfc11 108 #define CSSON_BitNumber 19
Kojto 109:9296ab0bfc11 109 #define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
Kojto 109:9296ab0bfc11 110 /* Alias word address of PLLON bit */
Kojto 109:9296ab0bfc11 111 #define PLLON_BitNumber 24
Kojto 109:9296ab0bfc11 112 #define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
Kojto 109:9296ab0bfc11 113
Kojto 109:9296ab0bfc11 114 /* --- CFGR Register ---*/
Kojto 109:9296ab0bfc11 115 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
Kojto 109:9296ab0bfc11 116 /* Alias word address of PLLSRC bit */
Kojto 109:9296ab0bfc11 117 #define PLLSRC_BitNumber 16
Kojto 109:9296ab0bfc11 118 #define CFGR_PLLSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (PLLSRC_BitNumber * 4))
Kojto 109:9296ab0bfc11 119
Kojto 109:9296ab0bfc11 120 /* --- CIR Register ---*/
Kojto 109:9296ab0bfc11 121 #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
Kojto 109:9296ab0bfc11 122
Kojto 109:9296ab0bfc11 123 /* --- BDCR Register ---*/
Kojto 109:9296ab0bfc11 124 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
Kojto 109:9296ab0bfc11 125 /* Alias word address of LSEON bit */
Kojto 109:9296ab0bfc11 126 #define LSEON_BitNumber 0
Kojto 109:9296ab0bfc11 127 #define BDCR_LSEON_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (LSEON_BitNumber * 4))
Kojto 109:9296ab0bfc11 128 /* Alias word address of RTCEN bit */
Kojto 109:9296ab0bfc11 129 #define RTCEN_BitNumber 15
Kojto 109:9296ab0bfc11 130 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
Kojto 109:9296ab0bfc11 131 /* Alias word address of BDRST bit */
Kojto 109:9296ab0bfc11 132 #define BDRST_BitNumber 16
Kojto 109:9296ab0bfc11 133 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
Kojto 109:9296ab0bfc11 134
Kojto 109:9296ab0bfc11 135 /* --- CSR Register ---*/
Kojto 109:9296ab0bfc11 136 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
Kojto 109:9296ab0bfc11 137 /* Alias word address of LSION bit */
Kojto 109:9296ab0bfc11 138 #define LSION_BitNumber 0
Kojto 109:9296ab0bfc11 139 #define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
Kojto 109:9296ab0bfc11 140 /* Alias word address of RMVF bit */
Kojto 109:9296ab0bfc11 141 #define RMVF_BitNumber 24
Kojto 109:9296ab0bfc11 142 #define CSR_RMVF_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RMVF_BitNumber * 4))
Kojto 109:9296ab0bfc11 143
Kojto 109:9296ab0bfc11 144 /* CR register byte 2 (Bits[23:16]) base address */
Kojto 109:9296ab0bfc11 145 #define CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
Kojto 109:9296ab0bfc11 146
Kojto 109:9296ab0bfc11 147 /* CIR register byte 1 (Bits[15:8]) base address */
Kojto 109:9296ab0bfc11 148 #define CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
Kojto 109:9296ab0bfc11 149
Kojto 109:9296ab0bfc11 150 /* CIR register byte 2 (Bits[23:16]) base address */
Kojto 109:9296ab0bfc11 151 #define CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
Kojto 109:9296ab0bfc11 152
Kojto 109:9296ab0bfc11 153 /* CSR register byte 1 (Bits[15:8]) base address */
Kojto 109:9296ab0bfc11 154 #define CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
Kojto 109:9296ab0bfc11 155
Kojto 109:9296ab0bfc11 156 /* BDCR register byte 0 (Bits[7:0] base address */
Kojto 109:9296ab0bfc11 157 #define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 109:9296ab0bfc11 158
Kojto 109:9296ab0bfc11 159 /**
Kojto 109:9296ab0bfc11 160 * @}
Kojto 109:9296ab0bfc11 161 */
Kojto 109:9296ab0bfc11 162
Kojto 109:9296ab0bfc11 163 /** @defgroup RCC_Timeout RCC Timeout
Kojto 109:9296ab0bfc11 164 * @{
Kojto 109:9296ab0bfc11 165 */
Kojto 109:9296ab0bfc11 166 /* LSE state change timeout */
Kojto 111:4336505e4b1c 167 #define LSE_TIMEOUT_VALUE ((uint32_t)100) /* 5 s */
Kojto 109:9296ab0bfc11 168
Kojto 109:9296ab0bfc11 169 /* Disable Backup domain write protection state change timeout */
Kojto 109:9296ab0bfc11 170 #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 109:9296ab0bfc11 171 /**
Kojto 109:9296ab0bfc11 172 * @}
Kojto 109:9296ab0bfc11 173 */
Kojto 109:9296ab0bfc11 174
Kojto 109:9296ab0bfc11 175 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
Kojto 109:9296ab0bfc11 176 * @{
Kojto 109:9296ab0bfc11 177 */
Kojto 109:9296ab0bfc11 178 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 179 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 180 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 181 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 182 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 183
Kojto 109:9296ab0bfc11 184 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
Kojto 109:9296ab0bfc11 185 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
Kojto 109:9296ab0bfc11 186 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
Kojto 109:9296ab0bfc11 187 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
Kojto 109:9296ab0bfc11 188 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
Kojto 109:9296ab0bfc11 189 /**
Kojto 109:9296ab0bfc11 190 * @}
Kojto 109:9296ab0bfc11 191 */
Kojto 109:9296ab0bfc11 192
Kojto 109:9296ab0bfc11 193 /** @defgroup RCC_HSE_Config RCC HSE Config
Kojto 109:9296ab0bfc11 194 * @{
Kojto 109:9296ab0bfc11 195 */
Kojto 109:9296ab0bfc11 196 #define RCC_HSE_OFF ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 197 #define RCC_HSE_ON ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 198 #define RCC_HSE_BYPASS ((uint32_t)0x00000005)
Kojto 109:9296ab0bfc11 199
Kojto 109:9296ab0bfc11 200 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 109:9296ab0bfc11 201 ((HSE) == RCC_HSE_BYPASS))
Kojto 109:9296ab0bfc11 202 /**
Kojto 109:9296ab0bfc11 203 * @}
Kojto 109:9296ab0bfc11 204 */
Kojto 109:9296ab0bfc11 205
Kojto 109:9296ab0bfc11 206 /** @defgroup RCC_LSE_Config RCC_LSE_Config
Kojto 109:9296ab0bfc11 207 * @{
Kojto 109:9296ab0bfc11 208 */
Kojto 109:9296ab0bfc11 209 #define RCC_LSE_OFF ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 210 #define RCC_LSE_ON ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 211 #define RCC_LSE_BYPASS ((uint32_t)0x00000005)
Kojto 109:9296ab0bfc11 212
Kojto 109:9296ab0bfc11 213 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 109:9296ab0bfc11 214 ((LSE) == RCC_LSE_BYPASS))
Kojto 109:9296ab0bfc11 215 /**
Kojto 109:9296ab0bfc11 216 * @}
Kojto 109:9296ab0bfc11 217 */
Kojto 109:9296ab0bfc11 218
Kojto 109:9296ab0bfc11 219 /** @defgroup RCC_HSI_Config RCC HSI Config
Kojto 109:9296ab0bfc11 220 * @{
Kojto 109:9296ab0bfc11 221 */
Kojto 109:9296ab0bfc11 222 #define RCC_HSI_OFF ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 223 #define RCC_HSI_ON ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 224
Kojto 109:9296ab0bfc11 225 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 109:9296ab0bfc11 226
Kojto 109:9296ab0bfc11 227 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto 109:9296ab0bfc11 228
Kojto 109:9296ab0bfc11 229 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto 109:9296ab0bfc11 230 /**
Kojto 109:9296ab0bfc11 231 * @}
Kojto 109:9296ab0bfc11 232 */
Kojto 109:9296ab0bfc11 233
Kojto 109:9296ab0bfc11 234 /** @defgroup RCC_LSI_Config RCC LSI Config
Kojto 109:9296ab0bfc11 235 * @{
Kojto 109:9296ab0bfc11 236 */
Kojto 109:9296ab0bfc11 237 #define RCC_LSI_OFF ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 238 #define RCC_LSI_ON ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 239
Kojto 109:9296ab0bfc11 240 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 109:9296ab0bfc11 241 /**
Kojto 109:9296ab0bfc11 242 * @}
Kojto 109:9296ab0bfc11 243 */
Kojto 109:9296ab0bfc11 244
Kojto 109:9296ab0bfc11 245 /** @defgroup RCC_PLL_Config RCC PLL Config
Kojto 109:9296ab0bfc11 246 * @{
Kojto 109:9296ab0bfc11 247 */
Kojto 109:9296ab0bfc11 248 #define RCC_PLL_NONE ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 249 #define RCC_PLL_OFF ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 250 #define RCC_PLL_ON ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 251
Kojto 109:9296ab0bfc11 252 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 109:9296ab0bfc11 253 /**
Kojto 109:9296ab0bfc11 254 * @}
Kojto 109:9296ab0bfc11 255 */
Kojto 109:9296ab0bfc11 256
Kojto 109:9296ab0bfc11 257 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
Kojto 109:9296ab0bfc11 258 * @{
Kojto 109:9296ab0bfc11 259 */
Kojto 109:9296ab0bfc11 260 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
Kojto 109:9296ab0bfc11 261 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
Kojto 109:9296ab0bfc11 262 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
Kojto 109:9296ab0bfc11 263 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
Kojto 109:9296ab0bfc11 264 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
Kojto 109:9296ab0bfc11 265 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
Kojto 109:9296ab0bfc11 266 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
Kojto 109:9296ab0bfc11 267 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
Kojto 109:9296ab0bfc11 268 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
Kojto 109:9296ab0bfc11 269 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
Kojto 109:9296ab0bfc11 270 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
Kojto 109:9296ab0bfc11 271 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
Kojto 109:9296ab0bfc11 272 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
Kojto 109:9296ab0bfc11 273 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
Kojto 109:9296ab0bfc11 274 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
Kojto 109:9296ab0bfc11 275
Kojto 109:9296ab0bfc11 276 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
Kojto 109:9296ab0bfc11 277 ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
Kojto 109:9296ab0bfc11 278 ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
Kojto 109:9296ab0bfc11 279 ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
Kojto 109:9296ab0bfc11 280 ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
Kojto 109:9296ab0bfc11 281 ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
Kojto 109:9296ab0bfc11 282 ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
Kojto 109:9296ab0bfc11 283 ((MUL) == RCC_PLL_MUL16))
Kojto 109:9296ab0bfc11 284 /**
Kojto 109:9296ab0bfc11 285 * @}
Kojto 109:9296ab0bfc11 286 */
Kojto 109:9296ab0bfc11 287
Kojto 109:9296ab0bfc11 288 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto 109:9296ab0bfc11 289 * @{
Kojto 109:9296ab0bfc11 290 */
Kojto 109:9296ab0bfc11 291 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 292 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 293 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 294 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 295
Kojto 109:9296ab0bfc11 296 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
Kojto 109:9296ab0bfc11 297 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
Kojto 109:9296ab0bfc11 298 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
Kojto 109:9296ab0bfc11 299 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
Kojto 109:9296ab0bfc11 300 /**
Kojto 109:9296ab0bfc11 301 * @}
Kojto 109:9296ab0bfc11 302 */
Kojto 109:9296ab0bfc11 303
Kojto 109:9296ab0bfc11 304 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto 109:9296ab0bfc11 305 * @{
Kojto 109:9296ab0bfc11 306 */
Kojto 109:9296ab0bfc11 307 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto 109:9296ab0bfc11 308 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto 109:9296ab0bfc11 309 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 109:9296ab0bfc11 310
Kojto 109:9296ab0bfc11 311 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 312 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 109:9296ab0bfc11 313 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto 109:9296ab0bfc11 314 /**
Kojto 109:9296ab0bfc11 315 * @}
Kojto 109:9296ab0bfc11 316 */
Kojto 109:9296ab0bfc11 317
Kojto 109:9296ab0bfc11 318 /** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
Kojto 109:9296ab0bfc11 319 * @{
Kojto 109:9296ab0bfc11 320 */
Kojto 109:9296ab0bfc11 321 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
Kojto 109:9296ab0bfc11 322 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
Kojto 109:9296ab0bfc11 323 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
Kojto 109:9296ab0bfc11 324
Kojto 109:9296ab0bfc11 325 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
Kojto 109:9296ab0bfc11 326 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
Kojto 109:9296ab0bfc11 327 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)))
Kojto 109:9296ab0bfc11 328 /**
Kojto 109:9296ab0bfc11 329 * @}
Kojto 109:9296ab0bfc11 330 */
Kojto 109:9296ab0bfc11 331
Kojto 109:9296ab0bfc11 332 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
Kojto 109:9296ab0bfc11 333 * @{
Kojto 109:9296ab0bfc11 334 */
Kojto 109:9296ab0bfc11 335 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto 109:9296ab0bfc11 336 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto 109:9296ab0bfc11 337 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto 109:9296ab0bfc11 338 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto 109:9296ab0bfc11 339 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto 109:9296ab0bfc11 340 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto 109:9296ab0bfc11 341 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto 109:9296ab0bfc11 342 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto 109:9296ab0bfc11 343 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto 109:9296ab0bfc11 344
Kojto 109:9296ab0bfc11 345 #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
Kojto 109:9296ab0bfc11 346 ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
Kojto 109:9296ab0bfc11 347 ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
Kojto 109:9296ab0bfc11 348 ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
Kojto 109:9296ab0bfc11 349 ((DIV) == RCC_SYSCLK_DIV512))
Kojto 109:9296ab0bfc11 350 /**
Kojto 109:9296ab0bfc11 351 * @}
Kojto 109:9296ab0bfc11 352 */
Kojto 109:9296ab0bfc11 353
Kojto 109:9296ab0bfc11 354 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
Kojto 109:9296ab0bfc11 355 * @{
Kojto 109:9296ab0bfc11 356 */
Kojto 109:9296ab0bfc11 357 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto 109:9296ab0bfc11 358 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto 109:9296ab0bfc11 359 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto 109:9296ab0bfc11 360 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto 109:9296ab0bfc11 361 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto 109:9296ab0bfc11 362
Kojto 109:9296ab0bfc11 363 #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
Kojto 109:9296ab0bfc11 364 ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
Kojto 109:9296ab0bfc11 365 ((DIV) == RCC_HCLK_DIV16))
Kojto 109:9296ab0bfc11 366 /**
Kojto 109:9296ab0bfc11 367 * @}
Kojto 109:9296ab0bfc11 368 */
Kojto 109:9296ab0bfc11 369
Kojto 109:9296ab0bfc11 370 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
Kojto 109:9296ab0bfc11 371 * @{
Kojto 109:9296ab0bfc11 372 */
Kojto 109:9296ab0bfc11 373 #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
Kojto 109:9296ab0bfc11 374 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
Kojto 109:9296ab0bfc11 375 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
Kojto 109:9296ab0bfc11 376 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
Kojto 109:9296ab0bfc11 377
Kojto 109:9296ab0bfc11 378 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
Kojto 109:9296ab0bfc11 379 ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 380 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 109:9296ab0bfc11 381 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto 109:9296ab0bfc11 382 /**
Kojto 109:9296ab0bfc11 383 * @}
Kojto 109:9296ab0bfc11 384 */
Kojto 109:9296ab0bfc11 385
Kojto 109:9296ab0bfc11 386 /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
Kojto 109:9296ab0bfc11 387 * @{
Kojto 109:9296ab0bfc11 388 */
Kojto 109:9296ab0bfc11 389 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
Kojto 109:9296ab0bfc11 390 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
Kojto 109:9296ab0bfc11 391 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
Kojto 109:9296ab0bfc11 392 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
Kojto 109:9296ab0bfc11 393
Kojto 109:9296ab0bfc11 394 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
Kojto 109:9296ab0bfc11 395 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 396 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 397 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 398 /**
Kojto 109:9296ab0bfc11 399 * @}
Kojto 109:9296ab0bfc11 400 */
Kojto 109:9296ab0bfc11 401
Kojto 109:9296ab0bfc11 402 /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
Kojto 109:9296ab0bfc11 403 * @{
Kojto 109:9296ab0bfc11 404 */
Kojto 109:9296ab0bfc11 405 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
Kojto 109:9296ab0bfc11 406 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
Kojto 109:9296ab0bfc11 407 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
Kojto 109:9296ab0bfc11 408 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
Kojto 109:9296ab0bfc11 409
Kojto 109:9296ab0bfc11 410 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
Kojto 109:9296ab0bfc11 411 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 412 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 413 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 414 /**
Kojto 109:9296ab0bfc11 415 * @}
Kojto 109:9296ab0bfc11 416 */
Kojto 109:9296ab0bfc11 417
Kojto 109:9296ab0bfc11 418 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
Kojto 109:9296ab0bfc11 419 * @{
Kojto 109:9296ab0bfc11 420 */
Kojto 109:9296ab0bfc11 421 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
Kojto 109:9296ab0bfc11 422 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
Kojto 109:9296ab0bfc11 423
Kojto 109:9296ab0bfc11 424 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 425 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
Kojto 109:9296ab0bfc11 426 /**
Kojto 109:9296ab0bfc11 427 * @}
Kojto 109:9296ab0bfc11 428 */
Kojto 109:9296ab0bfc11 429
Kojto 109:9296ab0bfc11 430 /** @defgroup RCC_MCOx_Index RCC MCOx Index
Kojto 109:9296ab0bfc11 431 * @{
Kojto 109:9296ab0bfc11 432 */
Kojto 109:9296ab0bfc11 433 #define RCC_MCO ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 434
Kojto 109:9296ab0bfc11 435 #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
Kojto 109:9296ab0bfc11 436 /**
Kojto 109:9296ab0bfc11 437 * @}
Kojto 109:9296ab0bfc11 438 */
Kojto 109:9296ab0bfc11 439
Kojto 109:9296ab0bfc11 440 /** @defgroup RCC_Interrupt RCC Interrupt
Kojto 109:9296ab0bfc11 441 * @{
Kojto 109:9296ab0bfc11 442 */
Kojto 109:9296ab0bfc11 443 #define RCC_IT_LSIRDY ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 444 #define RCC_IT_LSERDY ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 445 #define RCC_IT_HSIRDY ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 446 #define RCC_IT_HSERDY ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 447 #define RCC_IT_PLLRDY ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 448 #define RCC_IT_CSS ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 449 /**
Kojto 109:9296ab0bfc11 450 * @}
Kojto 109:9296ab0bfc11 451 */
Kojto 109:9296ab0bfc11 452
Kojto 109:9296ab0bfc11 453 /** @defgroup RCC_Flag RCC Flag
Kojto 109:9296ab0bfc11 454 * Elements values convention: 0XXYYYYYb
Kojto 109:9296ab0bfc11 455 * - YYYYY : Flag position in the register
Kojto 109:9296ab0bfc11 456 * - XX : Register index
Kojto 109:9296ab0bfc11 457 * - 01: CR register
Kojto 109:9296ab0bfc11 458 * - 10: BDCR register
Kojto 109:9296ab0bfc11 459 * - 11: CSR register
Kojto 109:9296ab0bfc11 460 * @{
Kojto 109:9296ab0bfc11 461 */
Kojto 109:9296ab0bfc11 462 #define CR_REG_INDEX 1U
Kojto 109:9296ab0bfc11 463 #define BDCR_REG_INDEX 2U
Kojto 109:9296ab0bfc11 464 #define CSR_REG_INDEX 3U
Kojto 109:9296ab0bfc11 465
Kojto 109:9296ab0bfc11 466 /* Flags in the CR register */
Kojto 109:9296ab0bfc11 467 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSIRDY))))
Kojto 109:9296ab0bfc11 468 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_HSERDY))))
Kojto 109:9296ab0bfc11 469 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CR_PLLRDY))))
Kojto 109:9296ab0bfc11 470
Kojto 109:9296ab0bfc11 471 /* Flags in the BDCR register */
Kojto 109:9296ab0bfc11 472 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_BDCR_LSERDY))))
Kojto 109:9296ab0bfc11 473
Kojto 109:9296ab0bfc11 474 /* Flags in the CSR register */
Kojto 109:9296ab0bfc11 475 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LSIRDY))))
Kojto 109:9296ab0bfc11 476 #define RCC_FLAG_RMV ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_RMVF))))
Kojto 109:9296ab0bfc11 477 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_OBLRSTF))))
Kojto 109:9296ab0bfc11 478 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PINRSTF))))
Kojto 109:9296ab0bfc11 479 #define RCC_FLAG_PORRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_PORRSTF))))
Kojto 109:9296ab0bfc11 480 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_SFTRSTF))))
Kojto 109:9296ab0bfc11 481 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_IWDGRSTF))))
Kojto 109:9296ab0bfc11 482 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_WWDGRSTF))))
Kojto 109:9296ab0bfc11 483 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | (uint32_t)(POSITION_VAL(RCC_CSR_LPWRRSTF))))
Kojto 109:9296ab0bfc11 484 /**
Kojto 109:9296ab0bfc11 485 * @}
Kojto 109:9296ab0bfc11 486 */
Kojto 109:9296ab0bfc11 487
Kojto 109:9296ab0bfc11 488 /**
Kojto 109:9296ab0bfc11 489 * @}
Kojto 109:9296ab0bfc11 490 */
Kojto 109:9296ab0bfc11 491 /* Exported macro ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 492
Kojto 109:9296ab0bfc11 493 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 109:9296ab0bfc11 494 * @{
Kojto 109:9296ab0bfc11 495 */
Kojto 109:9296ab0bfc11 496
Kojto 109:9296ab0bfc11 497 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
Kojto 109:9296ab0bfc11 498 * @brief Enable or disable the AHB peripheral clock.
Kojto 109:9296ab0bfc11 499 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 500 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 501 * using it.
Kojto 109:9296ab0bfc11 502 * @{
Kojto 109:9296ab0bfc11 503 */
Kojto 109:9296ab0bfc11 504 #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
Kojto 109:9296ab0bfc11 505 #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
Kojto 109:9296ab0bfc11 506 #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
Kojto 109:9296ab0bfc11 507 #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
Kojto 109:9296ab0bfc11 508 #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
Kojto 109:9296ab0bfc11 509 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
Kojto 109:9296ab0bfc11 510 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
Kojto 109:9296ab0bfc11 511 #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
Kojto 109:9296ab0bfc11 512 #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
Kojto 109:9296ab0bfc11 513 #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
Kojto 109:9296ab0bfc11 514
Kojto 109:9296ab0bfc11 515 #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto 109:9296ab0bfc11 516 #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto 109:9296ab0bfc11 517 #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto 109:9296ab0bfc11 518 #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
Kojto 109:9296ab0bfc11 519 #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
Kojto 109:9296ab0bfc11 520 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto 109:9296ab0bfc11 521 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto 109:9296ab0bfc11 522 #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
Kojto 109:9296ab0bfc11 523 #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
Kojto 109:9296ab0bfc11 524 #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
Kojto 109:9296ab0bfc11 525 /**
Kojto 109:9296ab0bfc11 526 * @}
Kojto 109:9296ab0bfc11 527 */
Kojto 109:9296ab0bfc11 528
Kojto 109:9296ab0bfc11 529 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
Kojto 109:9296ab0bfc11 530 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 109:9296ab0bfc11 531 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 532 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 533 * using it.
Kojto 109:9296ab0bfc11 534 * @{
Kojto 109:9296ab0bfc11 535 */
Kojto 109:9296ab0bfc11 536 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
Kojto 109:9296ab0bfc11 537 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
Kojto 109:9296ab0bfc11 538 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
Kojto 109:9296ab0bfc11 539 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
Kojto 109:9296ab0bfc11 540 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
Kojto 109:9296ab0bfc11 541 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
Kojto 109:9296ab0bfc11 542 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
Kojto 109:9296ab0bfc11 543 #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC1EN))
Kojto 109:9296ab0bfc11 544
Kojto 109:9296ab0bfc11 545 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto 109:9296ab0bfc11 546 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 109:9296ab0bfc11 547 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 109:9296ab0bfc11 548 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 109:9296ab0bfc11 549 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 109:9296ab0bfc11 550 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 109:9296ab0bfc11 551 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 109:9296ab0bfc11 552 #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
Kojto 109:9296ab0bfc11 553 /**
Kojto 109:9296ab0bfc11 554 * @}
Kojto 109:9296ab0bfc11 555 */
Kojto 109:9296ab0bfc11 556
Kojto 109:9296ab0bfc11 557 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
Kojto 109:9296ab0bfc11 558 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 109:9296ab0bfc11 559 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 560 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 561 * using it.
Kojto 109:9296ab0bfc11 562 * @{
Kojto 109:9296ab0bfc11 563 */
Kojto 109:9296ab0bfc11 564 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
Kojto 109:9296ab0bfc11 565 #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
Kojto 109:9296ab0bfc11 566 #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
Kojto 109:9296ab0bfc11 567 #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
Kojto 109:9296ab0bfc11 568 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
Kojto 109:9296ab0bfc11 569
Kojto 109:9296ab0bfc11 570 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 109:9296ab0bfc11 571 #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
Kojto 109:9296ab0bfc11 572 #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
Kojto 109:9296ab0bfc11 573 #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
Kojto 109:9296ab0bfc11 574 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 109:9296ab0bfc11 575 /**
Kojto 109:9296ab0bfc11 576 * @}
Kojto 109:9296ab0bfc11 577 */
Kojto 109:9296ab0bfc11 578
Kojto 109:9296ab0bfc11 579 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
Kojto 109:9296ab0bfc11 580 * @brief Force or release AHB peripheral reset.
Kojto 109:9296ab0bfc11 581 * @{
Kojto 109:9296ab0bfc11 582 */
Kojto 109:9296ab0bfc11 583 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto 109:9296ab0bfc11 584 #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
Kojto 109:9296ab0bfc11 585 #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
Kojto 109:9296ab0bfc11 586 #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
Kojto 109:9296ab0bfc11 587 #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
Kojto 109:9296ab0bfc11 588 #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
Kojto 109:9296ab0bfc11 589 #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
Kojto 109:9296ab0bfc11 590
Kojto 109:9296ab0bfc11 591 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto 109:9296ab0bfc11 592 #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto 109:9296ab0bfc11 593 #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto 109:9296ab0bfc11 594 #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto 109:9296ab0bfc11 595 #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
Kojto 109:9296ab0bfc11 596 #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
Kojto 109:9296ab0bfc11 597 #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
Kojto 109:9296ab0bfc11 598 /**
Kojto 109:9296ab0bfc11 599 * @}
Kojto 109:9296ab0bfc11 600 */
Kojto 109:9296ab0bfc11 601
Kojto 109:9296ab0bfc11 602 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
Kojto 109:9296ab0bfc11 603 * @brief Force or release APB1 peripheral reset.
Kojto 109:9296ab0bfc11 604 * @{
Kojto 109:9296ab0bfc11 605 */
Kojto 109:9296ab0bfc11 606 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 109:9296ab0bfc11 607 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 109:9296ab0bfc11 608 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 109:9296ab0bfc11 609 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 109:9296ab0bfc11 610 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 109:9296ab0bfc11 611 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 109:9296ab0bfc11 612 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 109:9296ab0bfc11 613 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
Kojto 109:9296ab0bfc11 614 #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST))
Kojto 109:9296ab0bfc11 615
Kojto 109:9296ab0bfc11 616 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 109:9296ab0bfc11 617 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto 109:9296ab0bfc11 618 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 109:9296ab0bfc11 619 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 109:9296ab0bfc11 620 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 109:9296ab0bfc11 621 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 109:9296ab0bfc11 622 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 109:9296ab0bfc11 623 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 109:9296ab0bfc11 624 #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
Kojto 109:9296ab0bfc11 625 /**
Kojto 109:9296ab0bfc11 626 * @}
Kojto 109:9296ab0bfc11 627 */
Kojto 109:9296ab0bfc11 628
Kojto 109:9296ab0bfc11 629 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
Kojto 109:9296ab0bfc11 630 * @brief Force or release APB2 peripheral reset.
Kojto 109:9296ab0bfc11 631 * @{
Kojto 109:9296ab0bfc11 632 */
Kojto 109:9296ab0bfc11 633 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 109:9296ab0bfc11 634 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 109:9296ab0bfc11 635 #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
Kojto 109:9296ab0bfc11 636 #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
Kojto 109:9296ab0bfc11 637 #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
Kojto 109:9296ab0bfc11 638 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 109:9296ab0bfc11 639
Kojto 109:9296ab0bfc11 640 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 109:9296ab0bfc11 641 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 109:9296ab0bfc11 642 #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
Kojto 109:9296ab0bfc11 643 #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
Kojto 109:9296ab0bfc11 644 #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
Kojto 109:9296ab0bfc11 645 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 109:9296ab0bfc11 646 /**
Kojto 109:9296ab0bfc11 647 * @}
Kojto 109:9296ab0bfc11 648 */
Kojto 109:9296ab0bfc11 649
Kojto 109:9296ab0bfc11 650 /** @defgroup RCC_HSI_Configuration RCC HSI Configuration
Kojto 109:9296ab0bfc11 651 * @{
Kojto 109:9296ab0bfc11 652 */
Kojto 109:9296ab0bfc11 653
Kojto 109:9296ab0bfc11 654 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 109:9296ab0bfc11 655 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 109:9296ab0bfc11 656 * It is used (enabled by hardware) as system clock source after startup
Kojto 109:9296ab0bfc11 657 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto 109:9296ab0bfc11 658 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 109:9296ab0bfc11 659 * Security System CSS is enabled).
Kojto 109:9296ab0bfc11 660 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 109:9296ab0bfc11 661 * you have to select another source of the system clock then stop the HSI.
Kojto 109:9296ab0bfc11 662 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 109:9296ab0bfc11 663 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 109:9296ab0bfc11 664 * system clock source.
Kojto 109:9296ab0bfc11 665 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 109:9296ab0bfc11 666 * clock cycles.
Kojto 109:9296ab0bfc11 667 */
Kojto 109:9296ab0bfc11 668 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *)CR_HSION_BB = ENABLE)
Kojto 109:9296ab0bfc11 669 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *)CR_HSION_BB = DISABLE)
Kojto 109:9296ab0bfc11 670
Kojto 109:9296ab0bfc11 671
Kojto 109:9296ab0bfc11 672 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 109:9296ab0bfc11 673 * @note The calibration is used to compensate for the variations in voltage
Kojto 109:9296ab0bfc11 674 * and temperature that influence the frequency of the internal HSI RC.
Kojto 109:9296ab0bfc11 675 * @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto 109:9296ab0bfc11 676 * This parameter must be a number between 0 and 0x1F.
Kojto 109:9296ab0bfc11 677 */
Kojto 109:9296ab0bfc11 678 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
Kojto 109:9296ab0bfc11 679 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))
Kojto 109:9296ab0bfc11 680 /**
Kojto 109:9296ab0bfc11 681 * @}
Kojto 109:9296ab0bfc11 682 */
Kojto 109:9296ab0bfc11 683
Kojto 109:9296ab0bfc11 684 /** @defgroup RCC_LSI_Configuration RCC LSI Configuration
Kojto 109:9296ab0bfc11 685 * @{
Kojto 109:9296ab0bfc11 686 */
Kojto 109:9296ab0bfc11 687
Kojto 109:9296ab0bfc11 688 /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 109:9296ab0bfc11 689 * @note After enabling the LSI, the application software should wait on
Kojto 109:9296ab0bfc11 690 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 109:9296ab0bfc11 691 * be used to clock the IWDG and/or the RTC.
Kojto 109:9296ab0bfc11 692 * @note LSI can not be disabled if the IWDG is running.
Kojto 109:9296ab0bfc11 693 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 109:9296ab0bfc11 694 * clock cycles.
Kojto 109:9296ab0bfc11 695 */
Kojto 109:9296ab0bfc11 696 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *)CSR_LSION_BB = ENABLE)
Kojto 109:9296ab0bfc11 697 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *)CSR_LSION_BB = DISABLE)
Kojto 109:9296ab0bfc11 698 /**
Kojto 109:9296ab0bfc11 699 * @}
Kojto 109:9296ab0bfc11 700 */
Kojto 109:9296ab0bfc11 701
Kojto 109:9296ab0bfc11 702 /** @defgroup RCC_HSE_Configuration RCC HSE Configuration
Kojto 109:9296ab0bfc11 703 * @{
Kojto 109:9296ab0bfc11 704 */
Kojto 109:9296ab0bfc11 705
Kojto 109:9296ab0bfc11 706 /**
Kojto 109:9296ab0bfc11 707 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 109:9296ab0bfc11 708 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 109:9296ab0bfc11 709 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 109:9296ab0bfc11 710 * is stable and can be used to clock the PLL and/or system clock.
Kojto 109:9296ab0bfc11 711 * @note HSE state can not be changed if it is used directly or through the
Kojto 109:9296ab0bfc11 712 * PLL as system clock. In this case, you have to select another source
Kojto 109:9296ab0bfc11 713 * of the system clock then change the HSE state (ex. disable it).
Kojto 109:9296ab0bfc11 714 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 109:9296ab0bfc11 715 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
Kojto 109:9296ab0bfc11 716 * was previously enabled you have to enable it again after calling this
Kojto 109:9296ab0bfc11 717 * function.
Kojto 109:9296ab0bfc11 718 * @param __STATE__: specifies the new state of the HSE.
Kojto 109:9296ab0bfc11 719 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 720 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 109:9296ab0bfc11 721 * 6 HSE oscillator clock cycles.
Kojto 109:9296ab0bfc11 722 * @arg RCC_HSE_ON: turn ON the HSE oscillator
Kojto 109:9296ab0bfc11 723 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
Kojto 109:9296ab0bfc11 724 */
Kojto 109:9296ab0bfc11 725 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)CR_BYTE2_ADDRESS = (__STATE__))
Kojto 109:9296ab0bfc11 726 /**
Kojto 109:9296ab0bfc11 727 * @}
Kojto 109:9296ab0bfc11 728 */
Kojto 109:9296ab0bfc11 729
Kojto 109:9296ab0bfc11 730 /** @defgroup RCC_LSE_Configuration RCC LSE Configuration
Kojto 109:9296ab0bfc11 731 * @{
Kojto 109:9296ab0bfc11 732 */
Kojto 109:9296ab0bfc11 733 /**
Kojto 109:9296ab0bfc11 734 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 109:9296ab0bfc11 735 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 109:9296ab0bfc11 736 * this domain after reset, you have to enable write access using
Kojto 109:9296ab0bfc11 737 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 109:9296ab0bfc11 738 * (to be done once after reset).
Kojto 109:9296ab0bfc11 739 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 109:9296ab0bfc11 740 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 109:9296ab0bfc11 741 * is stable and can be used to clock the RTC.
Kojto 109:9296ab0bfc11 742 * @param __STATE__: specifies the new state of the LSE.
Kojto 109:9296ab0bfc11 743 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 744 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 109:9296ab0bfc11 745 * 6 LSE oscillator clock cycles.
Kojto 109:9296ab0bfc11 746 * @arg RCC_LSE_ON: turn ON the LSE oscillator
Kojto 109:9296ab0bfc11 747 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
Kojto 109:9296ab0bfc11 748 */
Kojto 109:9296ab0bfc11 749 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto 109:9296ab0bfc11 750 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
Kojto 109:9296ab0bfc11 751 /**
Kojto 109:9296ab0bfc11 752 * @}
Kojto 109:9296ab0bfc11 753 */
Kojto 109:9296ab0bfc11 754
Kojto 109:9296ab0bfc11 755 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
Kojto 109:9296ab0bfc11 756 * @{
Kojto 109:9296ab0bfc11 757 */
Kojto 109:9296ab0bfc11 758 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto 109:9296ab0bfc11 759 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
Kojto 109:9296ab0bfc11 760 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 761 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 109:9296ab0bfc11 762 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 109:9296ab0bfc11 763 */
Kojto 109:9296ab0bfc11 764 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
Kojto 109:9296ab0bfc11 765 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
Kojto 109:9296ab0bfc11 766
Kojto 109:9296ab0bfc11 767 /** @brief Macro to get the I2C1 clock source.
Kojto 109:9296ab0bfc11 768 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 769 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 109:9296ab0bfc11 770 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 109:9296ab0bfc11 771 */
Kojto 109:9296ab0bfc11 772 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
Kojto 109:9296ab0bfc11 773 /**
Kojto 109:9296ab0bfc11 774 * @}
Kojto 109:9296ab0bfc11 775 */
Kojto 109:9296ab0bfc11 776
Kojto 109:9296ab0bfc11 777 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
Kojto 109:9296ab0bfc11 778 * @{
Kojto 109:9296ab0bfc11 779 */
Kojto 109:9296ab0bfc11 780
Kojto 109:9296ab0bfc11 781 /** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto 109:9296ab0bfc11 782 * @param __USART1CLKSource__: specifies the USART1 clock source.
Kojto 109:9296ab0bfc11 783 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 784 * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
Kojto 109:9296ab0bfc11 785 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 109:9296ab0bfc11 786 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 109:9296ab0bfc11 787 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 109:9296ab0bfc11 788 */
Kojto 109:9296ab0bfc11 789 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
Kojto 109:9296ab0bfc11 790 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
Kojto 109:9296ab0bfc11 791
Kojto 109:9296ab0bfc11 792 /** @brief Macro to get the USART1 clock source.
Kojto 109:9296ab0bfc11 793 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 794 * @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
Kojto 109:9296ab0bfc11 795 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 109:9296ab0bfc11 796 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 109:9296ab0bfc11 797 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 109:9296ab0bfc11 798 */
Kojto 109:9296ab0bfc11 799 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
Kojto 109:9296ab0bfc11 800
Kojto 109:9296ab0bfc11 801 /** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto 109:9296ab0bfc11 802 * @param __USART2CLKSource__: specifies the USART2 clock source.
Kojto 109:9296ab0bfc11 803 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 804 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 109:9296ab0bfc11 805 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 109:9296ab0bfc11 806 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 109:9296ab0bfc11 807 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 109:9296ab0bfc11 808 */
Kojto 109:9296ab0bfc11 809 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
Kojto 109:9296ab0bfc11 810 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
Kojto 109:9296ab0bfc11 811
Kojto 109:9296ab0bfc11 812 /** @brief Macro to get the USART2 clock source.
Kojto 109:9296ab0bfc11 813 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 814 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 109:9296ab0bfc11 815 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 109:9296ab0bfc11 816 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 109:9296ab0bfc11 817 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 109:9296ab0bfc11 818 */
Kojto 109:9296ab0bfc11 819 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Kojto 109:9296ab0bfc11 820
Kojto 109:9296ab0bfc11 821 /** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto 109:9296ab0bfc11 822 * @param __USART3CLKSource__: specifies the USART3 clock source.
Kojto 109:9296ab0bfc11 823 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 824 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 109:9296ab0bfc11 825 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 109:9296ab0bfc11 826 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 109:9296ab0bfc11 827 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 109:9296ab0bfc11 828 */
Kojto 109:9296ab0bfc11 829 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
Kojto 109:9296ab0bfc11 830 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
Kojto 109:9296ab0bfc11 831
Kojto 109:9296ab0bfc11 832 /** @brief Macro to get the USART3 clock source.
Kojto 109:9296ab0bfc11 833 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 834 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 109:9296ab0bfc11 835 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 109:9296ab0bfc11 836 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 109:9296ab0bfc11 837 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 109:9296ab0bfc11 838 */
Kojto 109:9296ab0bfc11 839 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
Kojto 109:9296ab0bfc11 840 /**
Kojto 109:9296ab0bfc11 841 * @}
Kojto 109:9296ab0bfc11 842 */
Kojto 109:9296ab0bfc11 843
Kojto 109:9296ab0bfc11 844 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto 109:9296ab0bfc11 845 * @{
Kojto 109:9296ab0bfc11 846 */
Kojto 109:9296ab0bfc11 847 /** @brief Macros to enable or disable the the RTC clock.
Kojto 109:9296ab0bfc11 848 * @note These macros must be used only after the RTC clock source was selected.
Kojto 109:9296ab0bfc11 849 */
Kojto 109:9296ab0bfc11 850 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = ENABLE)
Kojto 109:9296ab0bfc11 851 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *)BDCR_RTCEN_BB = DISABLE)
Kojto 109:9296ab0bfc11 852
Kojto 109:9296ab0bfc11 853 /** @brief Macro to configure the RTC clock (RTCCLK).
Kojto 109:9296ab0bfc11 854 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 109:9296ab0bfc11 855 * access is denied to this domain after reset, you have to enable write
Kojto 109:9296ab0bfc11 856 * access using the Power Backup Access macro before to configure
Kojto 109:9296ab0bfc11 857 * the RTC clock source (to be done once after reset).
Kojto 109:9296ab0bfc11 858 * @note Once the RTC clock is configured it can't be changed unless the
Kojto 109:9296ab0bfc11 859 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto 109:9296ab0bfc11 860 * a Power On Reset (POR).
Kojto 109:9296ab0bfc11 861 * @param __RTCCLKSource__: specifies the RTC clock source.
Kojto 109:9296ab0bfc11 862 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 863 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
Kojto 109:9296ab0bfc11 864 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto 109:9296ab0bfc11 865 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto 109:9296ab0bfc11 866 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
Kojto 109:9296ab0bfc11 867 *
Kojto 109:9296ab0bfc11 868 * @note If the LSE is used as RTC clock source, the RTC continues to
Kojto 109:9296ab0bfc11 869 * work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto 109:9296ab0bfc11 870 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
Kojto 109:9296ab0bfc11 871 * the RTC cannot be used in STOP and STANDBY modes.
Kojto 109:9296ab0bfc11 872 * @note The system must always be configured so as to get a PCLK frequency greater than or
Kojto 109:9296ab0bfc11 873 * equal to the RTCCLK frequency for a proper operation of the RTC.
Kojto 109:9296ab0bfc11 874 */
Kojto 109:9296ab0bfc11 875 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
Kojto 109:9296ab0bfc11 876 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
Kojto 109:9296ab0bfc11 877
Kojto 109:9296ab0bfc11 878 /** @brief Macro to get the RTC clock source.
Kojto 109:9296ab0bfc11 879 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 880 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
Kojto 109:9296ab0bfc11 881 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto 109:9296ab0bfc11 882 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto 109:9296ab0bfc11 883 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
Kojto 109:9296ab0bfc11 884 */
Kojto 109:9296ab0bfc11 885 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Kojto 109:9296ab0bfc11 886 /**
Kojto 109:9296ab0bfc11 887 * @}
Kojto 109:9296ab0bfc11 888 */
Kojto 109:9296ab0bfc11 889
Kojto 109:9296ab0bfc11 890 /** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
Kojto 109:9296ab0bfc11 891 * @{
Kojto 109:9296ab0bfc11 892 */
Kojto 109:9296ab0bfc11 893
Kojto 109:9296ab0bfc11 894 /** @brief Macro to force or release the Backup domain reset.
Kojto 109:9296ab0bfc11 895 * @note These macros reset the RTC peripheral (including the backup registers)
Kojto 109:9296ab0bfc11 896 * and the RTC clock source selection in RCC_CSR register.
Kojto 109:9296ab0bfc11 897 * @note The BKPSRAM is not affected by this reset.
Kojto 109:9296ab0bfc11 898 */
Kojto 109:9296ab0bfc11 899 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *)BDCR_BDRST_BB = ENABLE)
Kojto 109:9296ab0bfc11 900 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *)BDCR_BDRST_BB = DISABLE)
Kojto 109:9296ab0bfc11 901 /**
Kojto 109:9296ab0bfc11 902 * @}
Kojto 109:9296ab0bfc11 903 */
Kojto 109:9296ab0bfc11 904
Kojto 109:9296ab0bfc11 905 /** @defgroup RCC_PLL_Configuration RCC PLL Configuration
Kojto 109:9296ab0bfc11 906 * @{
Kojto 109:9296ab0bfc11 907 */
Kojto 109:9296ab0bfc11 908
Kojto 109:9296ab0bfc11 909 /** @brief Macro to enable or disable the PLL.
Kojto 109:9296ab0bfc11 910 * @note After enabling the PLL, the application software should wait on
Kojto 109:9296ab0bfc11 911 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 109:9296ab0bfc11 912 * be used as system clock source.
Kojto 109:9296ab0bfc11 913 * @note The PLL can not be disabled if it is used as system clock source
Kojto 109:9296ab0bfc11 914 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 109:9296ab0bfc11 915 */
Kojto 109:9296ab0bfc11 916 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *)CR_PLLON_BB = ENABLE)
Kojto 109:9296ab0bfc11 917 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *)CR_PLLON_BB = DISABLE)
Kojto 109:9296ab0bfc11 918 /**
Kojto 109:9296ab0bfc11 919 * @}
Kojto 109:9296ab0bfc11 920 */
Kojto 109:9296ab0bfc11 921
Kojto 109:9296ab0bfc11 922 /** @defgroup RCC_Get_Clock_source RCC Get Clock source
Kojto 109:9296ab0bfc11 923 * @{
Kojto 109:9296ab0bfc11 924 */
Kojto 109:9296ab0bfc11 925
Kojto 109:9296ab0bfc11 926 /** @brief Macro to get the clock source used as system clock.
Kojto 109:9296ab0bfc11 927 * @retval The clock source used as system clock.
Kojto 109:9296ab0bfc11 928 * The returned value can be one of the following value:
Kojto 109:9296ab0bfc11 929 * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
Kojto 109:9296ab0bfc11 930 * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
Kojto 109:9296ab0bfc11 931 * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
Kojto 109:9296ab0bfc11 932 */
Kojto 109:9296ab0bfc11 933 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
Kojto 109:9296ab0bfc11 934
Kojto 109:9296ab0bfc11 935 /** @brief Macro to get the oscillator used as PLL clock source.
Kojto 109:9296ab0bfc11 936 * @retval The oscillator used as PLL clock source. The returned value can be one
Kojto 109:9296ab0bfc11 937 * of the following:
Kojto 109:9296ab0bfc11 938 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto 109:9296ab0bfc11 939 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto 109:9296ab0bfc11 940 */
Kojto 109:9296ab0bfc11 941 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Kojto 109:9296ab0bfc11 942 /**
Kojto 109:9296ab0bfc11 943 * @}
Kojto 109:9296ab0bfc11 944 */
Kojto 109:9296ab0bfc11 945
Kojto 109:9296ab0bfc11 946 /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
Kojto 109:9296ab0bfc11 947 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 109:9296ab0bfc11 948 * @{
Kojto 109:9296ab0bfc11 949 */
Kojto 109:9296ab0bfc11 950
Kojto 109:9296ab0bfc11 951 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
Kojto 109:9296ab0bfc11 952 * the selected interrupts.).
Kojto 109:9296ab0bfc11 953 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 109:9296ab0bfc11 954 * This parameter can be any combination of the following values:
Kojto 109:9296ab0bfc11 955 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
Kojto 109:9296ab0bfc11 956 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
Kojto 109:9296ab0bfc11 957 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
Kojto 109:9296ab0bfc11 958 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
Kojto 109:9296ab0bfc11 959 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
Kojto 109:9296ab0bfc11 960 */
Kojto 109:9296ab0bfc11 961 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Kojto 109:9296ab0bfc11 962
Kojto 109:9296ab0bfc11 963 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
Kojto 109:9296ab0bfc11 964 * the selected interrupts.).
Kojto 109:9296ab0bfc11 965 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 109:9296ab0bfc11 966 * This parameter can be any combination of the following values:
Kojto 109:9296ab0bfc11 967 * @arg RCC_IT_LSIRDYIE: LSI ready interrupt enable
Kojto 109:9296ab0bfc11 968 * @arg RCC_IT_LSERDYIE: LSE ready interrupt enable
Kojto 109:9296ab0bfc11 969 * @arg RCC_IT_HSIRDYIE: HSI ready interrupt enable
Kojto 109:9296ab0bfc11 970 * @arg RCC_IT_HSERDYIE: HSE ready interrupt enable
Kojto 109:9296ab0bfc11 971 * @arg RCC_IT_PLLRDYIE: PLL ready interrupt enable
Kojto 109:9296ab0bfc11 972 */
Kojto 109:9296ab0bfc11 973 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto 109:9296ab0bfc11 974
Kojto 109:9296ab0bfc11 975 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
Kojto 109:9296ab0bfc11 976 * bits to clear the selected interrupt pending bits.
Kojto 109:9296ab0bfc11 977 * @param __IT__: specifies the interrupt pending bit to clear.
Kojto 109:9296ab0bfc11 978 * This parameter can be any combination of the following values:
Kojto 109:9296ab0bfc11 979 * @arg RCC_IT_LSIRDYC: LSI ready interrupt clear
Kojto 109:9296ab0bfc11 980 * @arg RCC_IT_LSERDYC: LSE ready interrupt clear
Kojto 109:9296ab0bfc11 981 * @arg RCC_IT_HSIRDYC: HSI ready interrupt clear
Kojto 109:9296ab0bfc11 982 * @arg RCC_IT_HSERDYC: HSE ready interrupt clear
Kojto 109:9296ab0bfc11 983 * @arg RCC_IT_PLLRDYC: PLL ready interrupt clear
Kojto 109:9296ab0bfc11 984 * @arg RCC_IT_CSSC: Clock Security System interrupt clear
Kojto 109:9296ab0bfc11 985 */
Kojto 109:9296ab0bfc11 986 #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)CIR_BYTE2_ADDRESS = (__IT__))
Kojto 109:9296ab0bfc11 987
Kojto 109:9296ab0bfc11 988 /** @brief Check the RCC's interrupt has occurred or not.
Kojto 109:9296ab0bfc11 989 * @param __IT__: specifies the RCC interrupt source to check.
Kojto 109:9296ab0bfc11 990 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 991 * @arg RCC_IT_LSIRDYF: LSI ready interrupt flag
Kojto 109:9296ab0bfc11 992 * @arg RCC_IT_LSERDYF: LSE ready interrupt flag
Kojto 109:9296ab0bfc11 993 * @arg RCC_IT_HSIRDYF: HSI ready interrupt flag
Kojto 109:9296ab0bfc11 994 * @arg RCC_IT_HSERDYF: HSE ready interrupt flag
Kojto 109:9296ab0bfc11 995 * @arg RCC_IT_PLLRDYF: PLL ready interrupt flag
Kojto 109:9296ab0bfc11 996 * @arg RCC_IT_CSSF: Clock Security System interrupt flag
Kojto 109:9296ab0bfc11 997 * @retval The new state of __IT__ (TRUE or FALSE).
Kojto 109:9296ab0bfc11 998 */
Kojto 109:9296ab0bfc11 999 #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
Kojto 109:9296ab0bfc11 1000
Kojto 109:9296ab0bfc11 1001 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto 109:9296ab0bfc11 1002 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Kojto 109:9296ab0bfc11 1003 */
Kojto 109:9296ab0bfc11 1004 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)CSR_RMVF_BB = ENABLE)
Kojto 109:9296ab0bfc11 1005
Kojto 109:9296ab0bfc11 1006 /** @brief Check RCC flag is set or not.
Kojto 109:9296ab0bfc11 1007 * @param __FLAG__: specifies the flag to check.
Kojto 109:9296ab0bfc11 1008 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 1009 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Kojto 109:9296ab0bfc11 1010 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
Kojto 109:9296ab0bfc11 1011 * @arg RCC_FLAG_PLLRDY: PLL clock ready
Kojto 109:9296ab0bfc11 1012 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
Kojto 109:9296ab0bfc11 1013 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Kojto 109:9296ab0bfc11 1014 * @arg RCC_FLAG_OBLRST: Option Byte Load reset
Kojto 109:9296ab0bfc11 1015 * @arg RCC_FLAG_PINRST: Pin reset
Kojto 109:9296ab0bfc11 1016 * @arg RCC_FLAG_PORRST: POR/PDR reset
Kojto 109:9296ab0bfc11 1017 * @arg RCC_FLAG_SFTRST: Software reset
Kojto 109:9296ab0bfc11 1018 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
Kojto 109:9296ab0bfc11 1019 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
Kojto 109:9296ab0bfc11 1020 * @arg RCC_FLAG_LPWRRST: Low Power reset
Kojto 109:9296ab0bfc11 1021 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 109:9296ab0bfc11 1022 */
Kojto 109:9296ab0bfc11 1023 #define RCC_FLAG_MASK ((uint32_t)0x0000001F)
Kojto 109:9296ab0bfc11 1024 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
Kojto 109:9296ab0bfc11 1025 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
Kojto 109:9296ab0bfc11 1026 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
Kojto 109:9296ab0bfc11 1027
Kojto 109:9296ab0bfc11 1028
Kojto 109:9296ab0bfc11 1029 /**
Kojto 109:9296ab0bfc11 1030 * @}
Kojto 109:9296ab0bfc11 1031 */
Kojto 109:9296ab0bfc11 1032
Kojto 109:9296ab0bfc11 1033 /**
Kojto 109:9296ab0bfc11 1034 * @}
Kojto 109:9296ab0bfc11 1035 */
Kojto 109:9296ab0bfc11 1036
Kojto 109:9296ab0bfc11 1037 /* Include RCC HAL Extended module */
Kojto 109:9296ab0bfc11 1038 #include "stm32f3xx_hal_rcc_ex.h"
Kojto 109:9296ab0bfc11 1039
Kojto 109:9296ab0bfc11 1040 /* Exported functions --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 1041
Kojto 109:9296ab0bfc11 1042 /** @addtogroup RCC_Exported_Functions
Kojto 109:9296ab0bfc11 1043 * @{
Kojto 109:9296ab0bfc11 1044 */
Kojto 109:9296ab0bfc11 1045
Kojto 109:9296ab0bfc11 1046 /** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 109:9296ab0bfc11 1047 * @{
Kojto 109:9296ab0bfc11 1048 */
Kojto 109:9296ab0bfc11 1049
Kojto 109:9296ab0bfc11 1050 /* Initialization and de-initialization functions ***************************/
Kojto 109:9296ab0bfc11 1051 void HAL_RCC_DeInit(void);
Kojto 109:9296ab0bfc11 1052 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 109:9296ab0bfc11 1053 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 109:9296ab0bfc11 1054
Kojto 109:9296ab0bfc11 1055 /**
Kojto 109:9296ab0bfc11 1056 * @}
Kojto 109:9296ab0bfc11 1057 */
Kojto 109:9296ab0bfc11 1058
Kojto 109:9296ab0bfc11 1059 /** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions
Kojto 109:9296ab0bfc11 1060 * @{
Kojto 109:9296ab0bfc11 1061 */
Kojto 109:9296ab0bfc11 1062
Kojto 109:9296ab0bfc11 1063 /* Peripheral Control functions *********************************************/
Kojto 109:9296ab0bfc11 1064 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 109:9296ab0bfc11 1065 void HAL_RCC_EnableCSS(void);
Kojto 109:9296ab0bfc11 1066 void HAL_RCC_DisableCSS(void);
Kojto 109:9296ab0bfc11 1067 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 109:9296ab0bfc11 1068 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 109:9296ab0bfc11 1069 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 109:9296ab0bfc11 1070 uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto 109:9296ab0bfc11 1071 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 109:9296ab0bfc11 1072 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 109:9296ab0bfc11 1073
Kojto 109:9296ab0bfc11 1074 /* CSS NMI IRQ handler */
Kojto 109:9296ab0bfc11 1075 void HAL_RCC_NMI_IRQHandler(void);
Kojto 109:9296ab0bfc11 1076
Kojto 109:9296ab0bfc11 1077 /* User Callbacks in non blocking mode (IT mode) */
Kojto 109:9296ab0bfc11 1078 void HAL_RCC_CCSCallback(void);
Kojto 109:9296ab0bfc11 1079
Kojto 109:9296ab0bfc11 1080 /**
Kojto 109:9296ab0bfc11 1081 * @}
Kojto 109:9296ab0bfc11 1082 */
Kojto 109:9296ab0bfc11 1083
Kojto 109:9296ab0bfc11 1084 /**
Kojto 109:9296ab0bfc11 1085 * @}
Kojto 109:9296ab0bfc11 1086 */
Kojto 109:9296ab0bfc11 1087
Kojto 109:9296ab0bfc11 1088 /**
Kojto 109:9296ab0bfc11 1089 * @}
Kojto 109:9296ab0bfc11 1090 */
Kojto 109:9296ab0bfc11 1091
Kojto 109:9296ab0bfc11 1092 /**
Kojto 109:9296ab0bfc11 1093 * @}
Kojto 109:9296ab0bfc11 1094 */
Kojto 109:9296ab0bfc11 1095
Kojto 109:9296ab0bfc11 1096 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 1097 }
Kojto 109:9296ab0bfc11 1098 #endif
Kojto 109:9296ab0bfc11 1099
Kojto 109:9296ab0bfc11 1100 #endif /* __STM32F3xx_HAL_RCC_H */
Kojto 109:9296ab0bfc11 1101
Kojto 109:9296ab0bfc11 1102 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/