Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
106:ba1f97679dad
Child:
116:c0f6e94411f5
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_rcc.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
emilmont 77:869cf507173a 7 * @brief Header file of RCC HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_RCC_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_RCC_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
Kojto 99:dbbf35b96557 49 /* Include RCC HAL Extended module */
Kojto 99:dbbf35b96557 50 /* (include on top of file since RCC structures are defined in extended file) */
Kojto 99:dbbf35b96557 51 #include "stm32f4xx_hal_rcc_ex.h"
Kojto 99:dbbf35b96557 52
emilmont 77:869cf507173a 53 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
Kojto 99:dbbf35b96557 57 /** @addtogroup RCC
emilmont 77:869cf507173a 58 * @{
emilmont 77:869cf507173a 59 */
emilmont 77:869cf507173a 60
Kojto 99:dbbf35b96557 61 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 62 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 99:dbbf35b96557 63 * @{
emilmont 77:869cf507173a 64 */
Kojto 99:dbbf35b96557 65
emilmont 77:869cf507173a 66 /**
emilmont 77:869cf507173a 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
emilmont 77:869cf507173a 68 */
emilmont 77:869cf507173a 69 typedef struct
emilmont 77:869cf507173a 70 {
emilmont 77:869cf507173a 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
emilmont 77:869cf507173a 72 This parameter can be a value of @ref RCC_Oscillator_Type */
emilmont 77:869cf507173a 73
emilmont 77:869cf507173a 74 uint32_t HSEState; /*!< The new state of the HSE.
emilmont 77:869cf507173a 75 This parameter can be a value of @ref RCC_HSE_Config */
emilmont 77:869cf507173a 76
emilmont 77:869cf507173a 77 uint32_t LSEState; /*!< The new state of the LSE.
emilmont 77:869cf507173a 78 This parameter can be a value of @ref RCC_LSE_Config */
emilmont 77:869cf507173a 79
emilmont 77:869cf507173a 80 uint32_t HSIState; /*!< The new state of the HSI.
emilmont 77:869cf507173a 81 This parameter can be a value of @ref RCC_HSI_Config */
emilmont 77:869cf507173a 82
emilmont 77:869cf507173a 83 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
emilmont 77:869cf507173a 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 uint32_t LSIState; /*!< The new state of the LSI.
emilmont 77:869cf507173a 87 This parameter can be a value of @ref RCC_LSI_Config */
emilmont 77:869cf507173a 88
emilmont 77:869cf507173a 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
emilmont 77:869cf507173a 90
emilmont 77:869cf507173a 91 }RCC_OscInitTypeDef;
emilmont 77:869cf507173a 92
emilmont 77:869cf507173a 93 /**
emilmont 77:869cf507173a 94 * @brief RCC System, AHB and APB busses clock configuration structure definition
emilmont 77:869cf507173a 95 */
emilmont 77:869cf507173a 96 typedef struct
emilmont 77:869cf507173a 97 {
emilmont 77:869cf507173a 98 uint32_t ClockType; /*!< The clock to be configured.
emilmont 77:869cf507173a 99 This parameter can be a value of @ref RCC_System_Clock_Type */
emilmont 77:869cf507173a 100
emilmont 77:869cf507173a 101 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
emilmont 77:869cf507173a 102 This parameter can be a value of @ref RCC_System_Clock_Source */
emilmont 77:869cf507173a 103
emilmont 77:869cf507173a 104 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
emilmont 77:869cf507173a 105 This parameter can be a value of @ref RCC_AHB_Clock_Source */
emilmont 77:869cf507173a 106
emilmont 77:869cf507173a 107 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
emilmont 77:869cf507173a 108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
emilmont 77:869cf507173a 111 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
emilmont 77:869cf507173a 112
emilmont 77:869cf507173a 113 }RCC_ClkInitTypeDef;
emilmont 77:869cf507173a 114
emilmont 77:869cf507173a 115 /**
emilmont 77:869cf507173a 116 * @}
emilmont 77:869cf507173a 117 */
emilmont 77:869cf507173a 118
Kojto 99:dbbf35b96557 119 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 120 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 99:dbbf35b96557 121 * @{
Kojto 99:dbbf35b96557 122 */
Kojto 99:dbbf35b96557 123
Kojto 99:dbbf35b96557 124 /** @defgroup RCC_Oscillator_Type Oscillator Type
emilmont 77:869cf507173a 125 * @{
emilmont 77:869cf507173a 126 */
bogdanm 81:7d30d6019079 127 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
emilmont 77:869cf507173a 128 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
emilmont 77:869cf507173a 129 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
emilmont 77:869cf507173a 130 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
emilmont 77:869cf507173a 131 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
emilmont 77:869cf507173a 132 /**
emilmont 77:869cf507173a 133 * @}
emilmont 77:869cf507173a 134 */
emilmont 77:869cf507173a 135
Kojto 99:dbbf35b96557 136 /** @defgroup RCC_HSE_Config HSE Config
emilmont 77:869cf507173a 137 * @{
emilmont 77:869cf507173a 138 */
emilmont 77:869cf507173a 139 #define RCC_HSE_OFF ((uint8_t)0x00)
emilmont 77:869cf507173a 140 #define RCC_HSE_ON ((uint8_t)0x01)
emilmont 77:869cf507173a 141 #define RCC_HSE_BYPASS ((uint8_t)0x05)
emilmont 77:869cf507173a 142 /**
emilmont 77:869cf507173a 143 * @}
emilmont 77:869cf507173a 144 */
emilmont 77:869cf507173a 145
Kojto 99:dbbf35b96557 146 /** @defgroup RCC_LSE_Config LSE Config
emilmont 77:869cf507173a 147 * @{
emilmont 77:869cf507173a 148 */
emilmont 77:869cf507173a 149 #define RCC_LSE_OFF ((uint8_t)0x00)
emilmont 77:869cf507173a 150 #define RCC_LSE_ON ((uint8_t)0x01)
emilmont 77:869cf507173a 151 #define RCC_LSE_BYPASS ((uint8_t)0x05)
emilmont 77:869cf507173a 152 /**
emilmont 77:869cf507173a 153 * @}
emilmont 77:869cf507173a 154 */
emilmont 77:869cf507173a 155
Kojto 99:dbbf35b96557 156 /** @defgroup RCC_HSI_Config HSI Config
emilmont 77:869cf507173a 157 * @{
emilmont 77:869cf507173a 158 */
emilmont 77:869cf507173a 159 #define RCC_HSI_OFF ((uint8_t)0x00)
emilmont 77:869cf507173a 160 #define RCC_HSI_ON ((uint8_t)0x01)
emilmont 77:869cf507173a 161 /**
emilmont 77:869cf507173a 162 * @}
emilmont 77:869cf507173a 163 */
emilmont 77:869cf507173a 164
Kojto 99:dbbf35b96557 165 /** @defgroup RCC_LSI_Config LSI Config
emilmont 77:869cf507173a 166 * @{
emilmont 77:869cf507173a 167 */
emilmont 77:869cf507173a 168 #define RCC_LSI_OFF ((uint8_t)0x00)
emilmont 77:869cf507173a 169 #define RCC_LSI_ON ((uint8_t)0x01)
emilmont 77:869cf507173a 170 /**
emilmont 77:869cf507173a 171 * @}
emilmont 77:869cf507173a 172 */
emilmont 77:869cf507173a 173
Kojto 99:dbbf35b96557 174 /** @defgroup RCC_PLL_Config PLL Config
emilmont 77:869cf507173a 175 * @{
emilmont 77:869cf507173a 176 */
emilmont 77:869cf507173a 177 #define RCC_PLL_NONE ((uint8_t)0x00)
emilmont 77:869cf507173a 178 #define RCC_PLL_OFF ((uint8_t)0x01)
emilmont 77:869cf507173a 179 #define RCC_PLL_ON ((uint8_t)0x02)
emilmont 77:869cf507173a 180 /**
emilmont 77:869cf507173a 181 * @}
emilmont 77:869cf507173a 182 */
emilmont 77:869cf507173a 183
Kojto 99:dbbf35b96557 184 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
emilmont 77:869cf507173a 185 * @{
emilmont 77:869cf507173a 186 */
emilmont 77:869cf507173a 187 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 188 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 189 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
emilmont 77:869cf507173a 190 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 191 /**
emilmont 77:869cf507173a 192 * @}
emilmont 77:869cf507173a 193 */
emilmont 77:869cf507173a 194
Kojto 99:dbbf35b96557 195 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
emilmont 77:869cf507173a 196 * @{
emilmont 77:869cf507173a 197 */
emilmont 77:869cf507173a 198 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
emilmont 77:869cf507173a 199 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
emilmont 77:869cf507173a 200 /**
emilmont 77:869cf507173a 201 * @}
emilmont 77:869cf507173a 202 */
emilmont 77:869cf507173a 203
Kojto 99:dbbf35b96557 204 /** @defgroup RCC_System_Clock_Type System Clock Type
emilmont 77:869cf507173a 205 * @{
emilmont 77:869cf507173a 206 */
emilmont 77:869cf507173a 207 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
emilmont 77:869cf507173a 208 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
emilmont 77:869cf507173a 209 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 210 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 211 /**
emilmont 77:869cf507173a 212 * @}
emilmont 77:869cf507173a 213 */
emilmont 77:869cf507173a 214
Kojto 99:dbbf35b96557 215 /** @defgroup RCC_System_Clock_Source System Clock Source
emilmont 77:869cf507173a 216 * @{
emilmont 77:869cf507173a 217 */
emilmont 77:869cf507173a 218 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
emilmont 77:869cf507173a 219 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
emilmont 77:869cf507173a 220 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 99:dbbf35b96557 221 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
emilmont 77:869cf507173a 222 /**
emilmont 77:869cf507173a 223 * @}
Kojto 99:dbbf35b96557 224 */
emilmont 77:869cf507173a 225
Kojto 99:dbbf35b96557 226 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 99:dbbf35b96557 227 * @{
Kojto 99:dbbf35b96557 228 */
Kojto 99:dbbf35b96557 229 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 99:dbbf35b96557 230 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 99:dbbf35b96557 231 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 99:dbbf35b96557 232 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) /*!< PLLR used as system clock */
Kojto 99:dbbf35b96557 233 /**
Kojto 99:dbbf35b96557 234 * @}
Kojto 99:dbbf35b96557 235 */
Kojto 99:dbbf35b96557 236
Kojto 99:dbbf35b96557 237 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
emilmont 77:869cf507173a 238 * @{
emilmont 77:869cf507173a 239 */
emilmont 77:869cf507173a 240 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
emilmont 77:869cf507173a 241 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
emilmont 77:869cf507173a 242 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
emilmont 77:869cf507173a 243 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
emilmont 77:869cf507173a 244 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
emilmont 77:869cf507173a 245 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
emilmont 77:869cf507173a 246 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
emilmont 77:869cf507173a 247 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
emilmont 77:869cf507173a 248 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
emilmont 77:869cf507173a 249 /**
emilmont 77:869cf507173a 250 * @}
emilmont 77:869cf507173a 251 */
emilmont 77:869cf507173a 252
Kojto 99:dbbf35b96557 253 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
emilmont 77:869cf507173a 254 * @{
emilmont 77:869cf507173a 255 */
emilmont 77:869cf507173a 256 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
emilmont 77:869cf507173a 257 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
emilmont 77:869cf507173a 258 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
emilmont 77:869cf507173a 259 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
emilmont 77:869cf507173a 260 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
emilmont 77:869cf507173a 261 /**
emilmont 77:869cf507173a 262 * @}
emilmont 77:869cf507173a 263 */
emilmont 77:869cf507173a 264
Kojto 99:dbbf35b96557 265 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
emilmont 77:869cf507173a 266 * @{
emilmont 77:869cf507173a 267 */
emilmont 77:869cf507173a 268 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
emilmont 77:869cf507173a 269 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
emilmont 77:869cf507173a 270 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
emilmont 77:869cf507173a 271 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
emilmont 77:869cf507173a 272 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
emilmont 77:869cf507173a 273 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
emilmont 77:869cf507173a 274 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
emilmont 77:869cf507173a 275 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
emilmont 77:869cf507173a 276 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
emilmont 77:869cf507173a 277 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
emilmont 77:869cf507173a 278 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
emilmont 77:869cf507173a 279 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
emilmont 77:869cf507173a 280 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
emilmont 77:869cf507173a 281 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
emilmont 77:869cf507173a 282 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
emilmont 77:869cf507173a 283 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
emilmont 77:869cf507173a 284 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
emilmont 77:869cf507173a 285 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
emilmont 77:869cf507173a 286 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
emilmont 77:869cf507173a 287 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
emilmont 77:869cf507173a 288 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
emilmont 77:869cf507173a 289 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
emilmont 77:869cf507173a 290 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
emilmont 77:869cf507173a 291 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
emilmont 77:869cf507173a 292 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
emilmont 77:869cf507173a 293 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
emilmont 77:869cf507173a 294 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
emilmont 77:869cf507173a 295 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
emilmont 77:869cf507173a 296 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
emilmont 77:869cf507173a 297 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
emilmont 77:869cf507173a 298 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
emilmont 77:869cf507173a 299 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
emilmont 77:869cf507173a 300 /**
emilmont 77:869cf507173a 301 * @}
emilmont 77:869cf507173a 302 */
emilmont 77:869cf507173a 303
Kojto 99:dbbf35b96557 304 /** @defgroup RCC_MCO_Index MCO Index
emilmont 77:869cf507173a 305 * @{
emilmont 77:869cf507173a 306 */
emilmont 77:869cf507173a 307 #define RCC_MCO1 ((uint32_t)0x00000000)
emilmont 77:869cf507173a 308 #define RCC_MCO2 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 309 /**
emilmont 77:869cf507173a 310 * @}
emilmont 77:869cf507173a 311 */
emilmont 77:869cf507173a 312
Kojto 99:dbbf35b96557 313 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
emilmont 77:869cf507173a 314 * @{
emilmont 77:869cf507173a 315 */
emilmont 77:869cf507173a 316 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
emilmont 77:869cf507173a 317 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
emilmont 77:869cf507173a 318 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
emilmont 77:869cf507173a 319 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
emilmont 77:869cf507173a 320 /**
emilmont 77:869cf507173a 321 * @}
emilmont 77:869cf507173a 322 */
emilmont 77:869cf507173a 323
Kojto 99:dbbf35b96557 324 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
emilmont 77:869cf507173a 325 * @{
emilmont 77:869cf507173a 326 */
emilmont 77:869cf507173a 327 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
emilmont 77:869cf507173a 328 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
emilmont 77:869cf507173a 329 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
emilmont 77:869cf507173a 330 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
emilmont 77:869cf507173a 331 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
emilmont 77:869cf507173a 332 /**
emilmont 77:869cf507173a 333 * @}
emilmont 77:869cf507173a 334 */
emilmont 77:869cf507173a 335
Kojto 99:dbbf35b96557 336 /** @defgroup RCC_Interrupt Interrupts
emilmont 77:869cf507173a 337 * @{
emilmont 77:869cf507173a 338 */
emilmont 77:869cf507173a 339 #define RCC_IT_LSIRDY ((uint8_t)0x01)
emilmont 77:869cf507173a 340 #define RCC_IT_LSERDY ((uint8_t)0x02)
emilmont 77:869cf507173a 341 #define RCC_IT_HSIRDY ((uint8_t)0x04)
emilmont 77:869cf507173a 342 #define RCC_IT_HSERDY ((uint8_t)0x08)
emilmont 77:869cf507173a 343 #define RCC_IT_PLLRDY ((uint8_t)0x10)
emilmont 77:869cf507173a 344 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
emilmont 77:869cf507173a 345 #define RCC_IT_CSS ((uint8_t)0x80)
emilmont 77:869cf507173a 346 /**
emilmont 77:869cf507173a 347 * @}
emilmont 77:869cf507173a 348 */
emilmont 77:869cf507173a 349
Kojto 99:dbbf35b96557 350 /** @defgroup RCC_Flag Flags
emilmont 77:869cf507173a 351 * Elements values convention: 0XXYYYYYb
emilmont 77:869cf507173a 352 * - YYYYY : Flag position in the register
emilmont 77:869cf507173a 353 * - 0XX : Register index
emilmont 77:869cf507173a 354 * - 01: CR register
emilmont 77:869cf507173a 355 * - 10: BDCR register
emilmont 77:869cf507173a 356 * - 11: CSR register
emilmont 77:869cf507173a 357 * @{
emilmont 77:869cf507173a 358 */
emilmont 77:869cf507173a 359 /* Flags in the CR register */
emilmont 77:869cf507173a 360 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
emilmont 77:869cf507173a 361 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
emilmont 77:869cf507173a 362 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
emilmont 77:869cf507173a 363 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
emilmont 77:869cf507173a 364
emilmont 77:869cf507173a 365 /* Flags in the BDCR register */
emilmont 77:869cf507173a 366 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
emilmont 77:869cf507173a 367
emilmont 77:869cf507173a 368 /* Flags in the CSR register */
emilmont 77:869cf507173a 369 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
emilmont 77:869cf507173a 370 #define RCC_FLAG_BORRST ((uint8_t)0x79)
emilmont 77:869cf507173a 371 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
emilmont 77:869cf507173a 372 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
emilmont 77:869cf507173a 373 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
emilmont 77:869cf507173a 374 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
emilmont 77:869cf507173a 375 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
emilmont 77:869cf507173a 376 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
emilmont 77:869cf507173a 377 /**
emilmont 77:869cf507173a 378 * @}
emilmont 77:869cf507173a 379 */
emilmont 77:869cf507173a 380
emilmont 77:869cf507173a 381 /**
emilmont 77:869cf507173a 382 * @}
Kojto 99:dbbf35b96557 383 */
Kojto 99:dbbf35b96557 384
emilmont 77:869cf507173a 385 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 386 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 99:dbbf35b96557 387 * @{
Kojto 99:dbbf35b96557 388 */
emilmont 77:869cf507173a 389
Kojto 99:dbbf35b96557 390 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 391 * @brief Enable or disable the AHB1 peripheral clock.
emilmont 77:869cf507173a 392 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 393 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 394 * using it.
Kojto 99:dbbf35b96557 395 * @{
emilmont 77:869cf507173a 396 */
Kojto 99:dbbf35b96557 397 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 398 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 399 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 99:dbbf35b96557 400 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 401 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 99:dbbf35b96557 402 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 403 } while(0)
Kojto 99:dbbf35b96557 404 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 405 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 406 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 99:dbbf35b96557 407 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 408 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 99:dbbf35b96557 409 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 410 } while(0)
Kojto 99:dbbf35b96557 411 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 412 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 413 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 99:dbbf35b96557 414 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 415 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 99:dbbf35b96557 416 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 417 } while(0)
Kojto 99:dbbf35b96557 418 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 419 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 420 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 99:dbbf35b96557 421 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 422 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 99:dbbf35b96557 423 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 424 } while(0)
Kojto 99:dbbf35b96557 425 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 426 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 427 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 99:dbbf35b96557 428 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 429 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 99:dbbf35b96557 430 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 431 } while(0)
Kojto 99:dbbf35b96557 432 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 433 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 434 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 99:dbbf35b96557 435 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 436 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 99:dbbf35b96557 437 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 438 } while(0)
emilmont 77:869cf507173a 439
Kojto 99:dbbf35b96557 440 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 99:dbbf35b96557 441 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 99:dbbf35b96557 442 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 99:dbbf35b96557 443 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 99:dbbf35b96557 444 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto 99:dbbf35b96557 445 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
emilmont 77:869cf507173a 446
Kojto 99:dbbf35b96557 447 /**
Kojto 99:dbbf35b96557 448 * @}
Kojto 99:dbbf35b96557 449 */
Kojto 99:dbbf35b96557 450
Kojto 99:dbbf35b96557 451 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 452 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
emilmont 77:869cf507173a 453 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 454 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 455 * using it.
Kojto 99:dbbf35b96557 456 * @{
emilmont 77:869cf507173a 457 */
Kojto 99:dbbf35b96557 458 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 459 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 460 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 99:dbbf35b96557 461 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 462 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 99:dbbf35b96557 463 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 464 } while(0)
Kojto 99:dbbf35b96557 465 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 466 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 467 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 99:dbbf35b96557 468 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 469 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 99:dbbf35b96557 470 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 471 } while(0)
Kojto 99:dbbf35b96557 472 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 473 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 474 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 99:dbbf35b96557 475 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 476 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 99:dbbf35b96557 477 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 478 } while(0)
Kojto 99:dbbf35b96557 479 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 480 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 481 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 99:dbbf35b96557 482 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 483 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 99:dbbf35b96557 484 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 485 } while(0)
Kojto 99:dbbf35b96557 486 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 487 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 99:dbbf35b96557 489 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 99:dbbf35b96557 491 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 492 } while(0)
Kojto 99:dbbf35b96557 493 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 494 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 99:dbbf35b96557 496 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 497 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 99:dbbf35b96557 498 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 499 } while(0)
Kojto 99:dbbf35b96557 500 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 501 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 502 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 99:dbbf35b96557 503 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 504 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 99:dbbf35b96557 505 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 506 } while(0)
Kojto 110:165afa46840b 507
Kojto 99:dbbf35b96557 508 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 99:dbbf35b96557 509 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 99:dbbf35b96557 510 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 99:dbbf35b96557 511 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 99:dbbf35b96557 512 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 99:dbbf35b96557 513 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 99:dbbf35b96557 514 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 99:dbbf35b96557 515 /**
Kojto 99:dbbf35b96557 516 * @}
Kojto 99:dbbf35b96557 517 */
emilmont 77:869cf507173a 518
Kojto 99:dbbf35b96557 519 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 520 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
emilmont 77:869cf507173a 521 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 522 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 523 * using it.
Kojto 99:dbbf35b96557 524 * @{
emilmont 77:869cf507173a 525 */
Kojto 99:dbbf35b96557 526 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 527 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 528 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 99:dbbf35b96557 529 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 530 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 99:dbbf35b96557 531 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 532 } while(0)
Kojto 99:dbbf35b96557 533 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 534 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 535 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 99:dbbf35b96557 536 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 537 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 99:dbbf35b96557 538 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 539 } while(0)
Kojto 99:dbbf35b96557 540 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 541 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 542 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 99:dbbf35b96557 543 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 544 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 99:dbbf35b96557 545 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 546 } while(0)
Kojto 99:dbbf35b96557 547 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 548 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 549 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 99:dbbf35b96557 550 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 551 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 99:dbbf35b96557 552 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 553 } while(0)
Kojto 99:dbbf35b96557 554 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 555 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 556 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 99:dbbf35b96557 557 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 558 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 99:dbbf35b96557 559 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 560 } while(0)
Kojto 99:dbbf35b96557 561 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 562 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 563 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 99:dbbf35b96557 564 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 565 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 99:dbbf35b96557 566 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 567 } while(0)
Kojto 99:dbbf35b96557 568 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 569 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 570 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 99:dbbf35b96557 571 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 572 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 99:dbbf35b96557 573 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 574 } while(0)
Kojto 99:dbbf35b96557 575 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 576 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 577 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 99:dbbf35b96557 578 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 579 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 99:dbbf35b96557 580 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 581 } while(0)
emilmont 77:869cf507173a 582
Kojto 99:dbbf35b96557 583 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 99:dbbf35b96557 584 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 99:dbbf35b96557 585 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 99:dbbf35b96557 586 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 99:dbbf35b96557 587 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 99:dbbf35b96557 588 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 99:dbbf35b96557 589 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 99:dbbf35b96557 590 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 99:dbbf35b96557 591 /**
Kojto 99:dbbf35b96557 592 * @}
Kojto 99:dbbf35b96557 593 */
emilmont 77:869cf507173a 594
Kojto 99:dbbf35b96557 595 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto 99:dbbf35b96557 596 * @brief Force or release AHB1 peripheral reset.
Kojto 99:dbbf35b96557 597 * @{
emilmont 77:869cf507173a 598 */
Kojto 99:dbbf35b96557 599 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto 99:dbbf35b96557 600 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 99:dbbf35b96557 601 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 99:dbbf35b96557 602 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 99:dbbf35b96557 603 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 99:dbbf35b96557 604 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Kojto 99:dbbf35b96557 605 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
emilmont 77:869cf507173a 606
Kojto 99:dbbf35b96557 607 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto 99:dbbf35b96557 608 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 99:dbbf35b96557 609 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 99:dbbf35b96557 610 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 99:dbbf35b96557 611 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 99:dbbf35b96557 612 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto 99:dbbf35b96557 613 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 99:dbbf35b96557 614 /**
Kojto 99:dbbf35b96557 615 * @}
Kojto 99:dbbf35b96557 616 */
emilmont 77:869cf507173a 617
Kojto 99:dbbf35b96557 618 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto 99:dbbf35b96557 619 * @brief Force or release APB1 peripheral reset.
Kojto 99:dbbf35b96557 620 * @{
Kojto 99:dbbf35b96557 621 */
Kojto 99:dbbf35b96557 622 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 99:dbbf35b96557 623 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 99:dbbf35b96557 624 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 99:dbbf35b96557 625 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 99:dbbf35b96557 626 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 99:dbbf35b96557 627 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 99:dbbf35b96557 628 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 99:dbbf35b96557 629 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
emilmont 77:869cf507173a 630
Kojto 99:dbbf35b96557 631 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 99:dbbf35b96557 632 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 99:dbbf35b96557 633 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 99:dbbf35b96557 634 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 99:dbbf35b96557 635 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 99:dbbf35b96557 636 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 99:dbbf35b96557 637 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 99:dbbf35b96557 638 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 99:dbbf35b96557 639 /**
Kojto 99:dbbf35b96557 640 * @}
Kojto 99:dbbf35b96557 641 */
emilmont 77:869cf507173a 642
Kojto 99:dbbf35b96557 643 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto 99:dbbf35b96557 644 * @brief Force or release APB2 peripheral reset.
Kojto 99:dbbf35b96557 645 * @{
emilmont 77:869cf507173a 646 */
Kojto 99:dbbf35b96557 647 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 99:dbbf35b96557 648 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 99:dbbf35b96557 649 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 99:dbbf35b96557 650 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 99:dbbf35b96557 651 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 99:dbbf35b96557 652 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 99:dbbf35b96557 653 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 99:dbbf35b96557 654 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 99:dbbf35b96557 655 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
emilmont 77:869cf507173a 656
Kojto 99:dbbf35b96557 657 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 99:dbbf35b96557 658 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 99:dbbf35b96557 659 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 99:dbbf35b96557 660 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 99:dbbf35b96557 661 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 99:dbbf35b96557 662 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 99:dbbf35b96557 663 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 99:dbbf35b96557 664 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 99:dbbf35b96557 665 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 99:dbbf35b96557 666 /**
Kojto 99:dbbf35b96557 667 * @}
Kojto 99:dbbf35b96557 668 */
emilmont 77:869cf507173a 669
Kojto 99:dbbf35b96557 670 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 671 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 672 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 673 * power consumption.
Kojto 99:dbbf35b96557 674 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 675 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 676 * @{
emilmont 77:869cf507173a 677 */
Kojto 99:dbbf35b96557 678 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 99:dbbf35b96557 679 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 99:dbbf35b96557 680 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 99:dbbf35b96557 681 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 99:dbbf35b96557 682 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Kojto 99:dbbf35b96557 683 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
emilmont 77:869cf507173a 684
Kojto 99:dbbf35b96557 685 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 99:dbbf35b96557 686 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 99:dbbf35b96557 687 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 99:dbbf35b96557 688 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 99:dbbf35b96557 689 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto 99:dbbf35b96557 690 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 99:dbbf35b96557 691 /**
Kojto 99:dbbf35b96557 692 * @}
Kojto 99:dbbf35b96557 693 */
emilmont 77:869cf507173a 694
Kojto 99:dbbf35b96557 695 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 696 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 697 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 698 * power consumption.
Kojto 99:dbbf35b96557 699 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 700 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 701 * @{
emilmont 77:869cf507173a 702 */
Kojto 99:dbbf35b96557 703 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 99:dbbf35b96557 704 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Kojto 99:dbbf35b96557 705 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 99:dbbf35b96557 706 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 99:dbbf35b96557 707 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 99:dbbf35b96557 708 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 99:dbbf35b96557 709 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
emilmont 77:869cf507173a 710
Kojto 99:dbbf35b96557 711 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 99:dbbf35b96557 712 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto 99:dbbf35b96557 713 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 99:dbbf35b96557 714 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 99:dbbf35b96557 715 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 99:dbbf35b96557 716 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 99:dbbf35b96557 717 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto 99:dbbf35b96557 718 /**
Kojto 99:dbbf35b96557 719 * @}
Kojto 99:dbbf35b96557 720 */
emilmont 77:869cf507173a 721
Kojto 99:dbbf35b96557 722 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 723 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 724 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 725 * power consumption.
Kojto 99:dbbf35b96557 726 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 727 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 728 * @{
emilmont 77:869cf507173a 729 */
Kojto 99:dbbf35b96557 730 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 99:dbbf35b96557 731 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 99:dbbf35b96557 732 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 99:dbbf35b96557 733 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 99:dbbf35b96557 734 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 99:dbbf35b96557 735 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto 99:dbbf35b96557 736 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 99:dbbf35b96557 737 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
emilmont 77:869cf507173a 738
Kojto 99:dbbf35b96557 739 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 99:dbbf35b96557 740 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 99:dbbf35b96557 741 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 99:dbbf35b96557 742 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 99:dbbf35b96557 743 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 99:dbbf35b96557 744 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto 99:dbbf35b96557 745 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 99:dbbf35b96557 746 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 99:dbbf35b96557 747 /**
Kojto 99:dbbf35b96557 748 * @}
Kojto 99:dbbf35b96557 749 */
emilmont 77:869cf507173a 750
Kojto 99:dbbf35b96557 751 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 99:dbbf35b96557 752 * @{
Kojto 99:dbbf35b96557 753 */
Kojto 99:dbbf35b96557 754
emilmont 77:869cf507173a 755 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
emilmont 77:869cf507173a 756 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
emilmont 77:869cf507173a 757 * It is used (enabled by hardware) as system clock source after startup
Kojto 99:dbbf35b96557 758 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
emilmont 77:869cf507173a 759 * of the HSE used directly or indirectly as system clock (if the Clock
emilmont 77:869cf507173a 760 * Security System CSS is enabled).
emilmont 77:869cf507173a 761 * @note HSI can not be stopped if it is used as system clock source. In this case,
emilmont 77:869cf507173a 762 * you have to select another source of the system clock then stop the HSI.
emilmont 77:869cf507173a 763 * @note After enabling the HSI, the application software should wait on HSIRDY
emilmont 77:869cf507173a 764 * flag to be set indicating that HSI clock is stable and can be used as
emilmont 77:869cf507173a 765 * system clock source.
emilmont 77:869cf507173a 766 * This parameter can be: ENABLE or DISABLE.
emilmont 77:869cf507173a 767 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
emilmont 77:869cf507173a 768 * clock cycles.
emilmont 77:869cf507173a 769 */
Kojto 99:dbbf35b96557 770 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Kojto 99:dbbf35b96557 771 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
emilmont 77:869cf507173a 772
emilmont 77:869cf507173a 773 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
emilmont 77:869cf507173a 774 * @note The calibration is used to compensate for the variations in voltage
emilmont 77:869cf507173a 775 * and temperature that influence the frequency of the internal HSI RC.
emilmont 77:869cf507173a 776 * @param __HSICalibrationValue__: specifies the calibration trimming value.
emilmont 77:869cf507173a 777 * This parameter must be a number between 0 and 0x1F.
emilmont 77:869cf507173a 778 */
emilmont 77:869cf507173a 779 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
emilmont 77:869cf507173a 780 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto 99:dbbf35b96557 781 /**
Kojto 99:dbbf35b96557 782 * @}
Kojto 99:dbbf35b96557 783 */
Kojto 99:dbbf35b96557 784
Kojto 99:dbbf35b96557 785 /** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto 99:dbbf35b96557 786 * @{
Kojto 99:dbbf35b96557 787 */
emilmont 77:869cf507173a 788
emilmont 77:869cf507173a 789 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
emilmont 77:869cf507173a 790 * @note After enabling the LSI, the application software should wait on
emilmont 77:869cf507173a 791 * LSIRDY flag to be set indicating that LSI clock is stable and can
emilmont 77:869cf507173a 792 * be used to clock the IWDG and/or the RTC.
emilmont 77:869cf507173a 793 * @note LSI can not be disabled if the IWDG is running.
emilmont 77:869cf507173a 794 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
emilmont 77:869cf507173a 795 * clock cycles.
emilmont 77:869cf507173a 796 */
Kojto 99:dbbf35b96557 797 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Kojto 99:dbbf35b96557 798 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Kojto 99:dbbf35b96557 799 /**
Kojto 99:dbbf35b96557 800 * @}
Kojto 99:dbbf35b96557 801 */
Kojto 99:dbbf35b96557 802
Kojto 99:dbbf35b96557 803 /** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto 99:dbbf35b96557 804 * @{
Kojto 99:dbbf35b96557 805 */
emilmont 77:869cf507173a 806
emilmont 77:869cf507173a 807 /**
emilmont 77:869cf507173a 808 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 99:dbbf35b96557 809 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Kojto 99:dbbf35b96557 810 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
emilmont 77:869cf507173a 811 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
emilmont 77:869cf507173a 812 * software should wait on HSERDY flag to be set indicating that HSE clock
emilmont 77:869cf507173a 813 * is stable and can be used to clock the PLL and/or system clock.
emilmont 77:869cf507173a 814 * @note HSE state can not be changed if it is used directly or through the
emilmont 77:869cf507173a 815 * PLL as system clock. In this case, you have to select another source
emilmont 77:869cf507173a 816 * of the system clock then change the HSE state (ex. disable it).
emilmont 77:869cf507173a 817 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
emilmont 77:869cf507173a 818 * @note This function reset the CSSON bit, so if the clock security system(CSS)
emilmont 77:869cf507173a 819 * was previously enabled you have to enable it again after calling this
emilmont 77:869cf507173a 820 * function.
emilmont 77:869cf507173a 821 * @param __STATE__: specifies the new state of the HSE.
emilmont 77:869cf507173a 822 * This parameter can be one of the following values:
emilmont 77:869cf507173a 823 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
emilmont 77:869cf507173a 824 * 6 HSE oscillator clock cycles.
emilmont 77:869cf507173a 825 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
emilmont 77:869cf507173a 826 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
emilmont 77:869cf507173a 827 */
Kojto 99:dbbf35b96557 828 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto 99:dbbf35b96557 829 /**
Kojto 99:dbbf35b96557 830 * @}
Kojto 99:dbbf35b96557 831 */
Kojto 99:dbbf35b96557 832
Kojto 99:dbbf35b96557 833 /** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto 99:dbbf35b96557 834 * @{
Kojto 99:dbbf35b96557 835 */
emilmont 77:869cf507173a 836
emilmont 77:869cf507173a 837 /**
emilmont 77:869cf507173a 838 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 99:dbbf35b96557 839 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto 99:dbbf35b96557 840 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
emilmont 77:869cf507173a 841 * @note As the LSE is in the Backup domain and write access is denied to
emilmont 77:869cf507173a 842 * this domain after reset, you have to enable write access using
emilmont 77:869cf507173a 843 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
emilmont 77:869cf507173a 844 * (to be done once after reset).
emilmont 77:869cf507173a 845 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
emilmont 77:869cf507173a 846 * software should wait on LSERDY flag to be set indicating that LSE clock
emilmont 77:869cf507173a 847 * is stable and can be used to clock the RTC.
emilmont 77:869cf507173a 848 * @param __STATE__: specifies the new state of the LSE.
emilmont 77:869cf507173a 849 * This parameter can be one of the following values:
emilmont 77:869cf507173a 850 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
emilmont 77:869cf507173a 851 * 6 LSE oscillator clock cycles.
emilmont 77:869cf507173a 852 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
emilmont 77:869cf507173a 853 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
emilmont 77:869cf507173a 854 */
Kojto 99:dbbf35b96557 855 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Kojto 99:dbbf35b96557 856
Kojto 99:dbbf35b96557 857 /**
Kojto 99:dbbf35b96557 858 * @}
Kojto 99:dbbf35b96557 859 */
emilmont 77:869cf507173a 860
Kojto 99:dbbf35b96557 861 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto 99:dbbf35b96557 862 * @{
Kojto 99:dbbf35b96557 863 */
Kojto 99:dbbf35b96557 864
Kojto 99:dbbf35b96557 865 /** @brief Macros to enable or disable the RTC clock.
emilmont 77:869cf507173a 866 * @note These macros must be used only after the RTC clock source was selected.
emilmont 77:869cf507173a 867 */
Kojto 99:dbbf35b96557 868 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto 99:dbbf35b96557 869 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
emilmont 77:869cf507173a 870
emilmont 77:869cf507173a 871 /** @brief Macros to configure the RTC clock (RTCCLK).
emilmont 77:869cf507173a 872 * @note As the RTC clock configuration bits are in the Backup domain and write
emilmont 77:869cf507173a 873 * access is denied to this domain after reset, you have to enable write
emilmont 77:869cf507173a 874 * access using the Power Backup Access macro before to configure
emilmont 77:869cf507173a 875 * the RTC clock source (to be done once after reset).
emilmont 77:869cf507173a 876 * @note Once the RTC clock is configured it can't be changed unless the
emilmont 77:869cf507173a 877 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
emilmont 77:869cf507173a 878 * a Power On Reset (POR).
emilmont 77:869cf507173a 879 * @param __RTCCLKSource__: specifies the RTC clock source.
emilmont 77:869cf507173a 880 * This parameter can be one of the following values:
emilmont 77:869cf507173a 881 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
emilmont 77:869cf507173a 882 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
emilmont 77:869cf507173a 883 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
emilmont 77:869cf507173a 884 * as RTC clock, where x:[2,31]
emilmont 77:869cf507173a 885 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 99:dbbf35b96557 886 * work in STOP and STANDBY modes, and can be used as wake-up source.
emilmont 77:869cf507173a 887 * However, when the HSE clock is used as RTC clock source, the RTC
emilmont 77:869cf507173a 888 * cannot be used in STOP and STANDBY modes.
emilmont 77:869cf507173a 889 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
emilmont 77:869cf507173a 890 * RTC clock source).
emilmont 77:869cf507173a 891 */
emilmont 77:869cf507173a 892 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
bogdanm 81:7d30d6019079 893 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm 81:7d30d6019079 894
emilmont 77:869cf507173a 895 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
emilmont 77:869cf507173a 896 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
emilmont 77:869cf507173a 897 } while (0)
emilmont 77:869cf507173a 898
emilmont 77:869cf507173a 899 /** @brief Macros to force or release the Backup domain reset.
emilmont 77:869cf507173a 900 * @note This function resets the RTC peripheral (including the backup registers)
emilmont 77:869cf507173a 901 * and the RTC clock source selection in RCC_CSR register.
emilmont 77:869cf507173a 902 * @note The BKPSRAM is not affected by this reset.
emilmont 77:869cf507173a 903 */
Kojto 99:dbbf35b96557 904 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Kojto 99:dbbf35b96557 905 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Kojto 99:dbbf35b96557 906 /**
Kojto 99:dbbf35b96557 907 * @}
Kojto 99:dbbf35b96557 908 */
Kojto 99:dbbf35b96557 909
Kojto 99:dbbf35b96557 910 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 99:dbbf35b96557 911 * @{
Kojto 99:dbbf35b96557 912 */
emilmont 77:869cf507173a 913
emilmont 77:869cf507173a 914 /** @brief Macros to enable or disable the main PLL.
emilmont 77:869cf507173a 915 * @note After enabling the main PLL, the application software should wait on
emilmont 77:869cf507173a 916 * PLLRDY flag to be set indicating that PLL clock is stable and can
emilmont 77:869cf507173a 917 * be used as system clock source.
emilmont 77:869cf507173a 918 * @note The main PLL can not be disabled if it is used as system clock source
emilmont 77:869cf507173a 919 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
emilmont 77:869cf507173a 920 */
Kojto 99:dbbf35b96557 921 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Kojto 99:dbbf35b96557 922 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
emilmont 77:869cf507173a 923
Kojto 99:dbbf35b96557 924 /** @brief Macro to configure the PLL clock source.
emilmont 77:869cf507173a 925 * @note This function must be used only when the main PLL is disabled.
Kojto 99:dbbf35b96557 926 * @param __PLLSOURCE__: specifies the PLL entry clock source.
emilmont 77:869cf507173a 927 * This parameter can be one of the following values:
emilmont 77:869cf507173a 928 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
emilmont 77:869cf507173a 929 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 99:dbbf35b96557 930 *
Kojto 99:dbbf35b96557 931 */
Kojto 99:dbbf35b96557 932 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 99:dbbf35b96557 933
Kojto 99:dbbf35b96557 934 /** @brief Macro to configure the PLL multiplication factor.
Kojto 99:dbbf35b96557 935 * @note This function must be used only when the main PLL is disabled.
emilmont 77:869cf507173a 936 * @param __PLLM__: specifies the division factor for PLL VCO input clock
emilmont 77:869cf507173a 937 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
emilmont 77:869cf507173a 938 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
emilmont 77:869cf507173a 939 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
emilmont 77:869cf507173a 940 * of 2 MHz to limit PLL jitter.
Kojto 99:dbbf35b96557 941 *
emilmont 77:869cf507173a 942 */
Kojto 99:dbbf35b96557 943 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto 99:dbbf35b96557 944 /**
Kojto 99:dbbf35b96557 945 * @}
Kojto 110:165afa46840b 946 */
Kojto 110:165afa46840b 947
Kojto 99:dbbf35b96557 948 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 99:dbbf35b96557 949 * @{
emilmont 77:869cf507173a 950 */
Kojto 99:dbbf35b96557 951 /**
Kojto 99:dbbf35b96557 952 * @brief Macro to configure the system clock source.
Kojto 99:dbbf35b96557 953 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto 99:dbbf35b96557 954 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 955 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 99:dbbf35b96557 956 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 99:dbbf35b96557 957 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 99:dbbf35b96557 958 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
Kojto 99:dbbf35b96557 959 */
Kojto 99:dbbf35b96557 960 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
emilmont 77:869cf507173a 961
emilmont 77:869cf507173a 962 /** @brief Macro to get the clock source used as system clock.
emilmont 77:869cf507173a 963 * @retval The clock source used as system clock. The returned value can be one
emilmont 77:869cf507173a 964 * of the following:
Kojto 99:dbbf35b96557 965 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 99:dbbf35b96557 966 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 99:dbbf35b96557 967 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 99:dbbf35b96557 968 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
emilmont 77:869cf507173a 969 */
emilmont 77:869cf507173a 970 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
emilmont 77:869cf507173a 971
emilmont 77:869cf507173a 972 /** @brief Macro to get the oscillator used as PLL clock source.
emilmont 77:869cf507173a 973 * @retval The oscillator used as PLL clock source. The returned value can be one
emilmont 77:869cf507173a 974 * of the following:
emilmont 77:869cf507173a 975 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
emilmont 77:869cf507173a 976 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
emilmont 77:869cf507173a 977 */
emilmont 77:869cf507173a 978 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 99:dbbf35b96557 979 /**
Kojto 99:dbbf35b96557 980 * @}
Kojto 99:dbbf35b96557 981 */
Kojto 99:dbbf35b96557 982
Kojto 110:165afa46840b 983 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto 110:165afa46840b 984 * @{
Kojto 110:165afa46840b 985 */
Kojto 110:165afa46840b 986
Kojto 110:165afa46840b 987 /** @brief Macro to configure the MCO1 clock.
Kojto 110:165afa46840b 988 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 110:165afa46840b 989 * This parameter can be one of the following values:
Kojto 110:165afa46840b 990 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Kojto 110:165afa46840b 991 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Kojto 110:165afa46840b 992 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Kojto 110:165afa46840b 993 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Kojto 110:165afa46840b 994 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 110:165afa46840b 995 * This parameter can be one of the following values:
Kojto 110:165afa46840b 996 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 110:165afa46840b 997 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 110:165afa46840b 998 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 110:165afa46840b 999 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 110:165afa46840b 1000 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 110:165afa46840b 1001 */
Kojto 110:165afa46840b 1002
Kojto 110:165afa46840b 1003 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 110:165afa46840b 1004 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 110:165afa46840b 1005
Kojto 110:165afa46840b 1006 /** @brief Macro to configure the MCO2 clock.
Kojto 110:165afa46840b 1007 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 110:165afa46840b 1008 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1009 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Kojto 110:165afa46840b 1010 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
Kojto 110:165afa46840b 1011 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
Kojto 110:165afa46840b 1012 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Kojto 110:165afa46840b 1013 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Kojto 110:165afa46840b 1014 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 110:165afa46840b 1015 * This parameter can be one of the following values:
Kojto 110:165afa46840b 1016 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 110:165afa46840b 1017 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 110:165afa46840b 1018 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 110:165afa46840b 1019 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 110:165afa46840b 1020 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 110:165afa46840b 1021 * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
Kojto 110:165afa46840b 1022 * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
Kojto 110:165afa46840b 1023 */
Kojto 110:165afa46840b 1024
Kojto 110:165afa46840b 1025 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 110:165afa46840b 1026 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (__MCOCLKSOURCE__ | (__MCODIV__ << 3)));
Kojto 110:165afa46840b 1027 /**
Kojto 110:165afa46840b 1028 * @}
Kojto 110:165afa46840b 1029 */
Kojto 110:165afa46840b 1030
Kojto 99:dbbf35b96557 1031 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 99:dbbf35b96557 1032 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 99:dbbf35b96557 1033 * @{
Kojto 99:dbbf35b96557 1034 */
emilmont 77:869cf507173a 1035
emilmont 77:869cf507173a 1036 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
emilmont 77:869cf507173a 1037 * the selected interrupts).
emilmont 77:869cf507173a 1038 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
emilmont 77:869cf507173a 1039 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 1040 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont 77:869cf507173a 1041 * @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont 77:869cf507173a 1042 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont 77:869cf507173a 1043 * @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont 77:869cf507173a 1044 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont 77:869cf507173a 1045 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont 77:869cf507173a 1046 */
Kojto 99:dbbf35b96557 1047 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
emilmont 77:869cf507173a 1048
emilmont 77:869cf507173a 1049 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
emilmont 77:869cf507173a 1050 * the selected interrupts).
emilmont 77:869cf507173a 1051 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
emilmont 77:869cf507173a 1052 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 1053 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont 77:869cf507173a 1054 * @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont 77:869cf507173a 1055 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont 77:869cf507173a 1056 * @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont 77:869cf507173a 1057 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont 77:869cf507173a 1058 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont 77:869cf507173a 1059 */
Kojto 99:dbbf35b96557 1060 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
emilmont 77:869cf507173a 1061
emilmont 77:869cf507173a 1062 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
emilmont 77:869cf507173a 1063 * bits to clear the selected interrupt pending bits.
emilmont 77:869cf507173a 1064 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
emilmont 77:869cf507173a 1065 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 1066 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont 77:869cf507173a 1067 * @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont 77:869cf507173a 1068 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont 77:869cf507173a 1069 * @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont 77:869cf507173a 1070 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont 77:869cf507173a 1071 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont 77:869cf507173a 1072 * @arg RCC_IT_CSS: Clock Security System interrupt
emilmont 77:869cf507173a 1073 */
Kojto 99:dbbf35b96557 1074 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
emilmont 77:869cf507173a 1075
emilmont 77:869cf507173a 1076 /** @brief Check the RCC's interrupt has occurred or not.
emilmont 77:869cf507173a 1077 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
emilmont 77:869cf507173a 1078 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1079 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont 77:869cf507173a 1080 * @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont 77:869cf507173a 1081 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont 77:869cf507173a 1082 * @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont 77:869cf507173a 1083 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont 77:869cf507173a 1084 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont 77:869cf507173a 1085 * @arg RCC_IT_CSS: Clock Security System interrupt
emilmont 77:869cf507173a 1086 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
emilmont 77:869cf507173a 1087 */
emilmont 77:869cf507173a 1088 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
emilmont 77:869cf507173a 1089
emilmont 77:869cf507173a 1090 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
emilmont 77:869cf507173a 1091 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
emilmont 77:869cf507173a 1092 */
bogdanm 81:7d30d6019079 1093 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
emilmont 77:869cf507173a 1094
emilmont 77:869cf507173a 1095 /** @brief Check RCC flag is set or not.
emilmont 77:869cf507173a 1096 * @param __FLAG__: specifies the flag to check.
emilmont 77:869cf507173a 1097 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1098 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
emilmont 77:869cf507173a 1099 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
emilmont 77:869cf507173a 1100 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
emilmont 77:869cf507173a 1101 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
emilmont 77:869cf507173a 1102 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
emilmont 77:869cf507173a 1103 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
emilmont 77:869cf507173a 1104 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
emilmont 77:869cf507173a 1105 * @arg RCC_FLAG_PINRST: Pin reset.
emilmont 77:869cf507173a 1106 * @arg RCC_FLAG_PORRST: POR/PDR reset.
emilmont 77:869cf507173a 1107 * @arg RCC_FLAG_SFTRST: Software reset.
emilmont 77:869cf507173a 1108 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
emilmont 77:869cf507173a 1109 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
emilmont 77:869cf507173a 1110 * @arg RCC_FLAG_LPWRRST: Low Power reset.
emilmont 77:869cf507173a 1111 * @retval The new state of __FLAG__ (TRUE or FALSE).
emilmont 77:869cf507173a 1112 */
emilmont 77:869cf507173a 1113 #define RCC_FLAG_MASK ((uint8_t)0x1F)
emilmont 77:869cf507173a 1114 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
emilmont 77:869cf507173a 1115
Kojto 99:dbbf35b96557 1116 /**
Kojto 99:dbbf35b96557 1117 * @}
Kojto 99:dbbf35b96557 1118 */
Kojto 99:dbbf35b96557 1119
Kojto 99:dbbf35b96557 1120 /**
Kojto 99:dbbf35b96557 1121 * @}
Kojto 99:dbbf35b96557 1122 */
emilmont 77:869cf507173a 1123
emilmont 77:869cf507173a 1124 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 1125 /** @addtogroup RCC_Exported_Functions
Kojto 99:dbbf35b96557 1126 * @{
Kojto 99:dbbf35b96557 1127 */
Kojto 99:dbbf35b96557 1128
Kojto 99:dbbf35b96557 1129 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 99:dbbf35b96557 1130 * @{
Kojto 99:dbbf35b96557 1131 */
emilmont 77:869cf507173a 1132 /* Initialization and de-initialization functions ******************************/
emilmont 77:869cf507173a 1133 void HAL_RCC_DeInit(void);
emilmont 77:869cf507173a 1134 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
emilmont 77:869cf507173a 1135 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 99:dbbf35b96557 1136 /**
Kojto 99:dbbf35b96557 1137 * @}
Kojto 99:dbbf35b96557 1138 */
emilmont 77:869cf507173a 1139
Kojto 99:dbbf35b96557 1140 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 99:dbbf35b96557 1141 * @{
Kojto 99:dbbf35b96557 1142 */
emilmont 77:869cf507173a 1143 /* Peripheral Control functions ************************************************/
emilmont 77:869cf507173a 1144 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
emilmont 77:869cf507173a 1145 void HAL_RCC_EnableCSS(void);
emilmont 77:869cf507173a 1146 void HAL_RCC_DisableCSS(void);
emilmont 77:869cf507173a 1147 uint32_t HAL_RCC_GetSysClockFreq(void);
emilmont 77:869cf507173a 1148 uint32_t HAL_RCC_GetHCLKFreq(void);
emilmont 77:869cf507173a 1149 uint32_t HAL_RCC_GetPCLK1Freq(void);
emilmont 77:869cf507173a 1150 uint32_t HAL_RCC_GetPCLK2Freq(void);
emilmont 77:869cf507173a 1151 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
emilmont 77:869cf507173a 1152 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
emilmont 77:869cf507173a 1153
emilmont 77:869cf507173a 1154 /* CSS NMI IRQ handler */
emilmont 77:869cf507173a 1155 void HAL_RCC_NMI_IRQHandler(void);
emilmont 77:869cf507173a 1156
emilmont 77:869cf507173a 1157 /* User Callbacks in non blocking mode (IT mode) */
Kojto 99:dbbf35b96557 1158 void HAL_RCC_CSSCallback(void);
Kojto 99:dbbf35b96557 1159
Kojto 99:dbbf35b96557 1160 /**
Kojto 99:dbbf35b96557 1161 * @}
Kojto 99:dbbf35b96557 1162 */
Kojto 99:dbbf35b96557 1163
Kojto 99:dbbf35b96557 1164 /**
Kojto 99:dbbf35b96557 1165 * @}
Kojto 99:dbbf35b96557 1166 */
Kojto 99:dbbf35b96557 1167
Kojto 99:dbbf35b96557 1168 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1169 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1170 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1171 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 99:dbbf35b96557 1172 * @{
Kojto 99:dbbf35b96557 1173 */
Kojto 99:dbbf35b96557 1174
Kojto 99:dbbf35b96557 1175 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 99:dbbf35b96557 1176 * @brief RCC registers bit address in the alias region
Kojto 99:dbbf35b96557 1177 * @{
Kojto 99:dbbf35b96557 1178 */
Kojto 99:dbbf35b96557 1179 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 99:dbbf35b96557 1180 /* --- CR Register ---*/
Kojto 99:dbbf35b96557 1181 /* Alias word address of HSION bit */
Kojto 99:dbbf35b96557 1182 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto 99:dbbf35b96557 1183 #define RCC_HSION_BIT_NUMBER 0x00
Kojto 99:dbbf35b96557 1184 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1185 /* Alias word address of CSSON bit */
Kojto 99:dbbf35b96557 1186 #define RCC_CSSON_BIT_NUMBER 0x13
Kojto 99:dbbf35b96557 1187 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1188 /* Alias word address of PLLON bit */
Kojto 99:dbbf35b96557 1189 #define RCC_PLLON_BIT_NUMBER 0x18
Kojto 99:dbbf35b96557 1190 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1191
Kojto 99:dbbf35b96557 1192 /* --- BDCR Register ---*/
Kojto 99:dbbf35b96557 1193 /* Alias word address of RTCEN bit */
Kojto 99:dbbf35b96557 1194 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
Kojto 99:dbbf35b96557 1195 #define RCC_RTCEN_BIT_NUMBER 0x0F
Kojto 99:dbbf35b96557 1196 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1197 /* Alias word address of BDRST bit */
Kojto 99:dbbf35b96557 1198 #define RCC_BDRST_BIT_NUMBER 0x10
Kojto 99:dbbf35b96557 1199 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1200
Kojto 99:dbbf35b96557 1201 /* --- CSR Register ---*/
Kojto 99:dbbf35b96557 1202 /* Alias word address of LSION bit */
Kojto 99:dbbf35b96557 1203 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
Kojto 99:dbbf35b96557 1204 #define RCC_LSION_BIT_NUMBER 0x00
Kojto 99:dbbf35b96557 1205 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1206
Kojto 99:dbbf35b96557 1207 /* CR register byte 3 (Bits[23:16]) base address */
Kojto 99:dbbf35b96557 1208 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
Kojto 99:dbbf35b96557 1209
Kojto 99:dbbf35b96557 1210 /* CIR register byte 2 (Bits[15:8]) base address */
Kojto 99:dbbf35b96557 1211 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
Kojto 99:dbbf35b96557 1212
Kojto 99:dbbf35b96557 1213 /* CIR register byte 3 (Bits[23:16]) base address */
Kojto 99:dbbf35b96557 1214 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
Kojto 99:dbbf35b96557 1215
Kojto 99:dbbf35b96557 1216 /* BDCR register base address */
Kojto 99:dbbf35b96557 1217 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 99:dbbf35b96557 1218
Kojto 99:dbbf35b96557 1219 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto 110:165afa46840b 1220 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 99:dbbf35b96557 1221
Kojto 99:dbbf35b96557 1222 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 99:dbbf35b96557 1223 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 99:dbbf35b96557 1224 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 99:dbbf35b96557 1225
Kojto 99:dbbf35b96557 1226 /**
Kojto 99:dbbf35b96557 1227 * @}
Kojto 99:dbbf35b96557 1228 */
Kojto 99:dbbf35b96557 1229
Kojto 99:dbbf35b96557 1230 /**
Kojto 99:dbbf35b96557 1231 * @}
Kojto 99:dbbf35b96557 1232 */
Kojto 99:dbbf35b96557 1233
Kojto 99:dbbf35b96557 1234 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1235 /** @addtogroup RCC_Private_Macros RCC Private Macros
Kojto 99:dbbf35b96557 1236 * @{
Kojto 99:dbbf35b96557 1237 */
Kojto 99:dbbf35b96557 1238
Kojto 99:dbbf35b96557 1239 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 99:dbbf35b96557 1240 * @{
Kojto 99:dbbf35b96557 1241 */
Kojto 99:dbbf35b96557 1242 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
Kojto 99:dbbf35b96557 1243
Kojto 99:dbbf35b96557 1244 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 99:dbbf35b96557 1245 ((HSE) == RCC_HSE_BYPASS))
Kojto 99:dbbf35b96557 1246
Kojto 99:dbbf35b96557 1247 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 99:dbbf35b96557 1248 ((LSE) == RCC_LSE_BYPASS))
Kojto 99:dbbf35b96557 1249
Kojto 99:dbbf35b96557 1250 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 99:dbbf35b96557 1251
Kojto 99:dbbf35b96557 1252 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 99:dbbf35b96557 1253
Kojto 99:dbbf35b96557 1254 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 99:dbbf35b96557 1255
Kojto 99:dbbf35b96557 1256 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 99:dbbf35b96557 1257 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 99:dbbf35b96557 1258
Kojto 99:dbbf35b96557 1259 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 99:dbbf35b96557 1260 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 99:dbbf35b96557 1261 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Kojto 99:dbbf35b96557 1262 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Kojto 99:dbbf35b96557 1263
Kojto 99:dbbf35b96557 1264 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
Kojto 99:dbbf35b96557 1265
Kojto 99:dbbf35b96557 1266 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto 99:dbbf35b96557 1267
Kojto 99:dbbf35b96557 1268 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
Kojto 99:dbbf35b96557 1269
Kojto 99:dbbf35b96557 1270 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
Kojto 99:dbbf35b96557 1271
Kojto 99:dbbf35b96557 1272 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Kojto 99:dbbf35b96557 1273 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Kojto 99:dbbf35b96557 1274 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Kojto 99:dbbf35b96557 1275 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Kojto 99:dbbf35b96557 1276 ((HCLK) == RCC_SYSCLK_DIV512))
Kojto 99:dbbf35b96557 1277
Kojto 99:dbbf35b96557 1278 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
Kojto 99:dbbf35b96557 1279
Kojto 99:dbbf35b96557 1280 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Kojto 99:dbbf35b96557 1281 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Kojto 99:dbbf35b96557 1282 ((PCLK) == RCC_HCLK_DIV16))
Kojto 99:dbbf35b96557 1283
Kojto 99:dbbf35b96557 1284 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
Kojto 99:dbbf35b96557 1285
Kojto 99:dbbf35b96557 1286 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 99:dbbf35b96557 1287 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto 99:dbbf35b96557 1288
Kojto 99:dbbf35b96557 1289 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 99:dbbf35b96557 1290 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Kojto 99:dbbf35b96557 1291 ((DIV) == RCC_MCODIV_5))
Kojto 99:dbbf35b96557 1292 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto 99:dbbf35b96557 1293
Kojto 99:dbbf35b96557 1294 /**
Kojto 99:dbbf35b96557 1295 * @}
Kojto 99:dbbf35b96557 1296 */
Kojto 99:dbbf35b96557 1297
Kojto 99:dbbf35b96557 1298 /**
Kojto 99:dbbf35b96557 1299 * @}
Kojto 99:dbbf35b96557 1300 */
emilmont 77:869cf507173a 1301
emilmont 77:869cf507173a 1302 /**
emilmont 77:869cf507173a 1303 * @}
emilmont 77:869cf507173a 1304 */
emilmont 77:869cf507173a 1305
emilmont 77:869cf507173a 1306 /**
emilmont 77:869cf507173a 1307 * @}
emilmont 77:869cf507173a 1308 */
emilmont 77:869cf507173a 1309
emilmont 77:869cf507173a 1310 #ifdef __cplusplus
emilmont 77:869cf507173a 1311 }
emilmont 77:869cf507173a 1312 #endif
emilmont 77:869cf507173a 1313
emilmont 77:869cf507173a 1314 #endif /* __STM32F4xx_HAL_RCC_H */
emilmont 77:869cf507173a 1315
emilmont 77:869cf507173a 1316 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/