Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Release 110  of the mbed library

Changes:
- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI
- Nucleo L476 - gcc and uvision template
- k22,k64f targets - ADC channels A addition
- EFM32 - bugfixes in sleep, serial and spi
- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 110:165afa46840b 1 /**
Kojto 110:165afa46840b 2 ******************************************************************************
Kojto 110:165afa46840b 3 * @file stm32f4xx_ll_fmc.h
Kojto 110:165afa46840b 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
Kojto 110:165afa46840b 7 * @brief Header file of FMC HAL module.
Kojto 110:165afa46840b 8 ******************************************************************************
Kojto 110:165afa46840b 9 * @attention
Kojto 110:165afa46840b 10 *
Kojto 110:165afa46840b 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 110:165afa46840b 12 *
Kojto 110:165afa46840b 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 110:165afa46840b 14 * are permitted provided that the following conditions are met:
Kojto 110:165afa46840b 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 110:165afa46840b 16 * this list of conditions and the following disclaimer.
Kojto 110:165afa46840b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 110:165afa46840b 18 * this list of conditions and the following disclaimer in the documentation
Kojto 110:165afa46840b 19 * and/or other materials provided with the distribution.
Kojto 110:165afa46840b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 110:165afa46840b 21 * may be used to endorse or promote products derived from this software
Kojto 110:165afa46840b 22 * without specific prior written permission.
Kojto 110:165afa46840b 23 *
Kojto 110:165afa46840b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 110:165afa46840b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 110:165afa46840b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 110:165afa46840b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 110:165afa46840b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 110:165afa46840b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 110:165afa46840b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 110:165afa46840b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 110:165afa46840b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 110:165afa46840b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 110:165afa46840b 34 *
Kojto 110:165afa46840b 35 ******************************************************************************
Kojto 110:165afa46840b 36 */
Kojto 110:165afa46840b 37
Kojto 110:165afa46840b 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 110:165afa46840b 39 #ifndef __STM32F4xx_LL_FMC_H
Kojto 110:165afa46840b 40 #define __STM32F4xx_LL_FMC_H
Kojto 110:165afa46840b 41
Kojto 110:165afa46840b 42 #ifdef __cplusplus
Kojto 110:165afa46840b 43 extern "C" {
Kojto 110:165afa46840b 44 #endif
Kojto 110:165afa46840b 45
Kojto 110:165afa46840b 46 /* Includes ------------------------------------------------------------------*/
Kojto 110:165afa46840b 47 #include "stm32f4xx_hal_def.h"
Kojto 110:165afa46840b 48
Kojto 110:165afa46840b 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 110:165afa46840b 50 * @{
Kojto 110:165afa46840b 51 */
Kojto 110:165afa46840b 52
Kojto 110:165afa46840b 53 /** @addtogroup FMC_LL
Kojto 110:165afa46840b 54 * @{
Kojto 110:165afa46840b 55 */
Kojto 110:165afa46840b 56 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 57 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 58 /* Private types -------------------------------------------------------------*/
Kojto 110:165afa46840b 59 /** @defgroup FMC_LL_Private_Types FMC Private Types
Kojto 110:165afa46840b 60 * @{
Kojto 110:165afa46840b 61 */
Kojto 110:165afa46840b 62
Kojto 110:165afa46840b 63 /**
Kojto 110:165afa46840b 64 * @brief FMC NORSRAM Configuration Structure definition
Kojto 110:165afa46840b 65 */
Kojto 110:165afa46840b 66 typedef struct
Kojto 110:165afa46840b 67 {
Kojto 110:165afa46840b 68 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
Kojto 110:165afa46840b 69 This parameter can be a value of @ref FMC_NORSRAM_Bank */
Kojto 110:165afa46840b 70
Kojto 110:165afa46840b 71 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
Kojto 110:165afa46840b 72 multiplexed on the data bus or not.
Kojto 110:165afa46840b 73 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
Kojto 110:165afa46840b 74
Kojto 110:165afa46840b 75 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
Kojto 110:165afa46840b 76 the corresponding memory device.
Kojto 110:165afa46840b 77 This parameter can be a value of @ref FMC_Memory_Type */
Kojto 110:165afa46840b 78
Kojto 110:165afa46840b 79 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto 110:165afa46840b 80 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
Kojto 110:165afa46840b 81
Kojto 110:165afa46840b 82 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
Kojto 110:165afa46840b 83 valid only with synchronous burst Flash memories.
Kojto 110:165afa46840b 84 This parameter can be a value of @ref FMC_Burst_Access_Mode */
Kojto 110:165afa46840b 85
Kojto 110:165afa46840b 86 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
Kojto 110:165afa46840b 87 the Flash memory in burst mode.
Kojto 110:165afa46840b 88 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
Kojto 110:165afa46840b 89
Kojto 110:165afa46840b 90 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
Kojto 110:165afa46840b 91 memory, valid only when accessing Flash memories in burst mode.
Kojto 110:165afa46840b 92 This parameter can be a value of @ref FMC_Wrap_Mode
Kojto 110:165afa46840b 93 This mode is not available for the STM32F446/467/479xx devices */
Kojto 110:165afa46840b 94
Kojto 110:165afa46840b 95 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
Kojto 110:165afa46840b 96 clock cycle before the wait state or during the wait state,
Kojto 110:165afa46840b 97 valid only when accessing memories in burst mode.
Kojto 110:165afa46840b 98 This parameter can be a value of @ref FMC_Wait_Timing */
Kojto 110:165afa46840b 99
Kojto 110:165afa46840b 100 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
Kojto 110:165afa46840b 101 This parameter can be a value of @ref FMC_Write_Operation */
Kojto 110:165afa46840b 102
Kojto 110:165afa46840b 103 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
Kojto 110:165afa46840b 104 signal, valid for Flash memory access in burst mode.
Kojto 110:165afa46840b 105 This parameter can be a value of @ref FMC_Wait_Signal */
Kojto 110:165afa46840b 106
Kojto 110:165afa46840b 107 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
Kojto 110:165afa46840b 108 This parameter can be a value of @ref FMC_Extended_Mode */
Kojto 110:165afa46840b 109
Kojto 110:165afa46840b 110 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
Kojto 110:165afa46840b 111 valid only with asynchronous Flash memories.
Kojto 110:165afa46840b 112 This parameter can be a value of @ref FMC_AsynchronousWait */
Kojto 110:165afa46840b 113
Kojto 110:165afa46840b 114 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
Kojto 110:165afa46840b 115 This parameter can be a value of @ref FMC_Write_Burst */
Kojto 110:165afa46840b 116
Kojto 110:165afa46840b 117 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto 110:165afa46840b 118 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 110:165afa46840b 119 through FMC_BCR2..4 registers.
Kojto 110:165afa46840b 120 This parameter can be a value of @ref FMC_Continous_Clock */
Kojto 110:165afa46840b 121
Kojto 110:165afa46840b 122 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto 110:165afa46840b 123 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 110:165afa46840b 124 through FMC_BCR2..4 registers.
Kojto 110:165afa46840b 125 This parameter can be a value of @ref FMC_Write_FIFO
Kojto 110:165afa46840b 126 This mode is available only for the STM32F446/469/479xx devices */
Kojto 110:165afa46840b 127
Kojto 110:165afa46840b 128 uint32_t PageSize; /*!< Specifies the memory page size.
Kojto 110:165afa46840b 129 This parameter can be a value of @ref FMC_Page_Size
Kojto 110:165afa46840b 130 This mode is available only for the STM32F446xx devices */
Kojto 110:165afa46840b 131
Kojto 110:165afa46840b 132 }FMC_NORSRAM_InitTypeDef;
Kojto 110:165afa46840b 133
Kojto 110:165afa46840b 134 /**
Kojto 110:165afa46840b 135 * @brief FMC NORSRAM Timing parameters structure definition
Kojto 110:165afa46840b 136 */
Kojto 110:165afa46840b 137 typedef struct
Kojto 110:165afa46840b 138 {
Kojto 110:165afa46840b 139 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto 110:165afa46840b 140 the duration of the address setup time.
Kojto 110:165afa46840b 141 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto 110:165afa46840b 142 @note This parameter is not used with synchronous NOR Flash memories. */
Kojto 110:165afa46840b 143
Kojto 110:165afa46840b 144 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
Kojto 110:165afa46840b 145 the duration of the address hold time.
Kojto 110:165afa46840b 146 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
Kojto 110:165afa46840b 147 @note This parameter is not used with synchronous NOR Flash memories. */
Kojto 110:165afa46840b 148
Kojto 110:165afa46840b 149 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto 110:165afa46840b 150 the duration of the data setup time.
Kojto 110:165afa46840b 151 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
Kojto 110:165afa46840b 152 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
Kojto 110:165afa46840b 153 NOR Flash memories. */
Kojto 110:165afa46840b 154
Kojto 110:165afa46840b 155 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
Kojto 110:165afa46840b 156 the duration of the bus turnaround.
Kojto 110:165afa46840b 157 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto 110:165afa46840b 158 @note This parameter is only used for multiplexed NOR Flash memories. */
Kojto 110:165afa46840b 159
Kojto 110:165afa46840b 160 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
Kojto 110:165afa46840b 161 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
Kojto 110:165afa46840b 162 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
Kojto 110:165afa46840b 163 accesses. */
Kojto 110:165afa46840b 164
Kojto 110:165afa46840b 165 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
Kojto 110:165afa46840b 166 to the memory before getting the first data.
Kojto 110:165afa46840b 167 The parameter value depends on the memory type as shown below:
Kojto 110:165afa46840b 168 - It must be set to 0 in case of a CRAM
Kojto 110:165afa46840b 169 - It is don't care in asynchronous NOR, SRAM or ROM accesses
Kojto 110:165afa46840b 170 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
Kojto 110:165afa46840b 171 with synchronous burst mode enable */
Kojto 110:165afa46840b 172
Kojto 110:165afa46840b 173 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
Kojto 110:165afa46840b 174 This parameter can be a value of @ref FMC_Access_Mode */
Kojto 110:165afa46840b 175 }FMC_NORSRAM_TimingTypeDef;
Kojto 110:165afa46840b 176
Kojto 110:165afa46840b 177 /**
Kojto 110:165afa46840b 178 * @brief FMC NAND Configuration Structure definition
Kojto 110:165afa46840b 179 */
Kojto 110:165afa46840b 180 typedef struct
Kojto 110:165afa46840b 181 {
Kojto 110:165afa46840b 182 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
Kojto 110:165afa46840b 183 This parameter can be a value of @ref FMC_NAND_Bank */
Kojto 110:165afa46840b 184
Kojto 110:165afa46840b 185 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
Kojto 110:165afa46840b 186 This parameter can be any value of @ref FMC_Wait_feature */
Kojto 110:165afa46840b 187
Kojto 110:165afa46840b 188 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto 110:165afa46840b 189 This parameter can be any value of @ref FMC_NAND_Data_Width */
Kojto 110:165afa46840b 190
Kojto 110:165afa46840b 191 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
Kojto 110:165afa46840b 192 This parameter can be any value of @ref FMC_ECC */
Kojto 110:165afa46840b 193
Kojto 110:165afa46840b 194 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
Kojto 110:165afa46840b 195 This parameter can be any value of @ref FMC_ECC_Page_Size */
Kojto 110:165afa46840b 196
Kojto 110:165afa46840b 197 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 110:165afa46840b 198 delay between CLE low and RE low.
Kojto 110:165afa46840b 199 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 110:165afa46840b 200
Kojto 110:165afa46840b 201 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 110:165afa46840b 202 delay between ALE low and RE low.
Kojto 110:165afa46840b 203 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 110:165afa46840b 204 }FMC_NAND_InitTypeDef;
Kojto 110:165afa46840b 205
Kojto 110:165afa46840b 206 /**
Kojto 110:165afa46840b 207 * @brief FMC NAND/PCCARD Timing parameters structure definition
Kojto 110:165afa46840b 208 */
Kojto 110:165afa46840b 209 typedef struct
Kojto 110:165afa46840b 210 {
Kojto 110:165afa46840b 211 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
Kojto 110:165afa46840b 212 the command assertion for NAND-Flash read or write access
Kojto 110:165afa46840b 213 to common/Attribute or I/O memory space (depending on
Kojto 110:165afa46840b 214 the memory space timing to be configured).
Kojto 110:165afa46840b 215 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 110:165afa46840b 216
Kojto 110:165afa46840b 217 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
Kojto 110:165afa46840b 218 command for NAND-Flash read or write access to
Kojto 110:165afa46840b 219 common/Attribute or I/O memory space (depending on the
Kojto 110:165afa46840b 220 memory space timing to be configured).
Kojto 110:165afa46840b 221 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 110:165afa46840b 222
Kojto 110:165afa46840b 223 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
Kojto 110:165afa46840b 224 (and data for write access) after the command de-assertion
Kojto 110:165afa46840b 225 for NAND-Flash read or write access to common/Attribute
Kojto 110:165afa46840b 226 or I/O memory space (depending on the memory space timing
Kojto 110:165afa46840b 227 to be configured).
Kojto 110:165afa46840b 228 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 110:165afa46840b 229
Kojto 110:165afa46840b 230 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
Kojto 110:165afa46840b 231 data bus is kept in HiZ after the start of a NAND-Flash
Kojto 110:165afa46840b 232 write access to common/Attribute or I/O memory space (depending
Kojto 110:165afa46840b 233 on the memory space timing to be configured).
Kojto 110:165afa46840b 234 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 110:165afa46840b 235 }FMC_NAND_PCC_TimingTypeDef;
Kojto 110:165afa46840b 236
Kojto 110:165afa46840b 237 /**
Kojto 110:165afa46840b 238 * @brief FMC NAND Configuration Structure definition
Kojto 110:165afa46840b 239 */
Kojto 110:165afa46840b 240 typedef struct
Kojto 110:165afa46840b 241 {
Kojto 110:165afa46840b 242 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
Kojto 110:165afa46840b 243 This parameter can be any value of @ref FMC_Wait_feature */
Kojto 110:165afa46840b 244
Kojto 110:165afa46840b 245 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 110:165afa46840b 246 delay between CLE low and RE low.
Kojto 110:165afa46840b 247 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 110:165afa46840b 248
Kojto 110:165afa46840b 249 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 110:165afa46840b 250 delay between ALE low and RE low.
Kojto 110:165afa46840b 251 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 110:165afa46840b 252 }FMC_PCCARD_InitTypeDef;
Kojto 110:165afa46840b 253
Kojto 110:165afa46840b 254 /**
Kojto 110:165afa46840b 255 * @brief FMC SDRAM Configuration Structure definition
Kojto 110:165afa46840b 256 */
Kojto 110:165afa46840b 257 typedef struct
Kojto 110:165afa46840b 258 {
Kojto 110:165afa46840b 259 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
Kojto 110:165afa46840b 260 This parameter can be a value of @ref FMC_SDRAM_Bank */
Kojto 110:165afa46840b 261
Kojto 110:165afa46840b 262 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
Kojto 110:165afa46840b 263 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
Kojto 110:165afa46840b 264
Kojto 110:165afa46840b 265 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
Kojto 110:165afa46840b 266 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
Kojto 110:165afa46840b 267
Kojto 110:165afa46840b 268 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
Kojto 110:165afa46840b 269 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
Kojto 110:165afa46840b 270
Kojto 110:165afa46840b 271 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
Kojto 110:165afa46840b 272 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
Kojto 110:165afa46840b 273
Kojto 110:165afa46840b 274 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
Kojto 110:165afa46840b 275 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
Kojto 110:165afa46840b 276
Kojto 110:165afa46840b 277 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
Kojto 110:165afa46840b 278 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
Kojto 110:165afa46840b 279
Kojto 110:165afa46840b 280 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
Kojto 110:165afa46840b 281 to disable the clock before changing frequency.
Kojto 110:165afa46840b 282 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
Kojto 110:165afa46840b 283
Kojto 110:165afa46840b 284 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
Kojto 110:165afa46840b 285 commands during the CAS latency and stores data in the Read FIFO.
Kojto 110:165afa46840b 286 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
Kojto 110:165afa46840b 287
Kojto 110:165afa46840b 288 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
Kojto 110:165afa46840b 289 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
Kojto 110:165afa46840b 290 }FMC_SDRAM_InitTypeDef;
Kojto 110:165afa46840b 291
Kojto 110:165afa46840b 292 /**
Kojto 110:165afa46840b 293 * @brief FMC SDRAM Timing parameters structure definition
Kojto 110:165afa46840b 294 */
Kojto 110:165afa46840b 295 typedef struct
Kojto 110:165afa46840b 296 {
Kojto 110:165afa46840b 297 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
Kojto 110:165afa46840b 298 an active or Refresh command in number of memory clock cycles.
Kojto 110:165afa46840b 299 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
Kojto 110:165afa46840b 302 issuing the Activate command in number of memory clock cycles.
Kojto 110:165afa46840b 303 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 110:165afa46840b 304
Kojto 110:165afa46840b 305 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
Kojto 110:165afa46840b 306 cycles.
Kojto 110:165afa46840b 307 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
Kojto 110:165afa46840b 310 and the delay between two consecutive Refresh commands in number of
Kojto 110:165afa46840b 311 memory clock cycles.
Kojto 110:165afa46840b 312 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 110:165afa46840b 313
Kojto 110:165afa46840b 314 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
Kojto 110:165afa46840b 315 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 110:165afa46840b 316
Kojto 110:165afa46840b 317 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
Kojto 110:165afa46840b 318 in number of memory clock cycles.
Kojto 110:165afa46840b 319 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
Kojto 110:165afa46840b 322 command in number of memory clock cycles.
Kojto 110:165afa46840b 323 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 110:165afa46840b 324 }FMC_SDRAM_TimingTypeDef;
Kojto 110:165afa46840b 325
Kojto 110:165afa46840b 326 /**
Kojto 110:165afa46840b 327 * @brief SDRAM command parameters structure definition
Kojto 110:165afa46840b 328 */
Kojto 110:165afa46840b 329 typedef struct
Kojto 110:165afa46840b 330 {
Kojto 110:165afa46840b 331 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
Kojto 110:165afa46840b 332 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
Kojto 110:165afa46840b 333
Kojto 110:165afa46840b 334 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
Kojto 110:165afa46840b 335 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
Kojto 110:165afa46840b 336
Kojto 110:165afa46840b 337 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
Kojto 110:165afa46840b 338 in auto refresh mode.
Kojto 110:165afa46840b 339 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 110:165afa46840b 340 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
Kojto 110:165afa46840b 341 }FMC_SDRAM_CommandTypeDef;
Kojto 110:165afa46840b 342 /**
Kojto 110:165afa46840b 343 * @}
Kojto 110:165afa46840b 344 */
Kojto 110:165afa46840b 345
Kojto 110:165afa46840b 346 /* Private constants ---------------------------------------------------------*/
Kojto 110:165afa46840b 347 /** @defgroup FMC_LL_Private_Constants FMC Private Constants
Kojto 110:165afa46840b 348 * @{
Kojto 110:165afa46840b 349 */
Kojto 110:165afa46840b 350
Kojto 110:165afa46840b 351 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto 110:165afa46840b 352 * @{
Kojto 110:165afa46840b 353 */
Kojto 110:165afa46840b 354 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
Kojto 110:165afa46840b 355 * @{
Kojto 110:165afa46840b 356 */
Kojto 110:165afa46840b 357 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 358 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 359 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 360 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
Kojto 110:165afa46840b 361 /**
Kojto 110:165afa46840b 362 * @}
Kojto 110:165afa46840b 363 */
Kojto 110:165afa46840b 364
Kojto 110:165afa46840b 365 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
Kojto 110:165afa46840b 366 * @{
Kojto 110:165afa46840b 367 */
Kojto 110:165afa46840b 368 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 369 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
Kojto 110:165afa46840b 370 /**
Kojto 110:165afa46840b 371 * @}
Kojto 110:165afa46840b 372 */
Kojto 110:165afa46840b 373
Kojto 110:165afa46840b 374 /** @defgroup FMC_Memory_Type FMC Memory Type
Kojto 110:165afa46840b 375 * @{
Kojto 110:165afa46840b 376 */
Kojto 110:165afa46840b 377 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
Kojto 110:165afa46840b 378 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
Kojto 110:165afa46840b 379 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
Kojto 110:165afa46840b 380 /**
Kojto 110:165afa46840b 381 * @}
Kojto 110:165afa46840b 382 */
Kojto 110:165afa46840b 383
Kojto 110:165afa46840b 384 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
Kojto 110:165afa46840b 385 * @{
Kojto 110:165afa46840b 386 */
Kojto 110:165afa46840b 387 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 388 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 389 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 390 /**
Kojto 110:165afa46840b 391 * @}
Kojto 110:165afa46840b 392 */
Kojto 110:165afa46840b 393
Kojto 110:165afa46840b 394 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
Kojto 110:165afa46840b 395 * @{
Kojto 110:165afa46840b 396 */
Kojto 110:165afa46840b 397 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
Kojto 110:165afa46840b 398 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 399 /**
Kojto 110:165afa46840b 400 * @}
Kojto 110:165afa46840b 401 */
Kojto 110:165afa46840b 402
Kojto 110:165afa46840b 403 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
Kojto 110:165afa46840b 404 * @{
Kojto 110:165afa46840b 405 */
Kojto 110:165afa46840b 406 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 407 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
Kojto 110:165afa46840b 408 /**
Kojto 110:165afa46840b 409 * @}
Kojto 110:165afa46840b 410 */
Kojto 110:165afa46840b 411
Kojto 110:165afa46840b 412 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
Kojto 110:165afa46840b 413 * @{
Kojto 110:165afa46840b 414 */
Kojto 110:165afa46840b 415 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
Kojto 110:165afa46840b 416 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
Kojto 110:165afa46840b 417 /**
Kojto 110:165afa46840b 418 * @}
Kojto 110:165afa46840b 419 */
Kojto 110:165afa46840b 420
Kojto 110:165afa46840b 421 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
Kojto 110:165afa46840b 422 * @{
Kojto 110:165afa46840b 423 */
Kojto 110:165afa46840b 424 /** @note This mode is not available for the STM32F446/469/479xx devices
Kojto 110:165afa46840b 425 */
Kojto 110:165afa46840b 426 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 427 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
Kojto 110:165afa46840b 428 /**
Kojto 110:165afa46840b 429 * @}
Kojto 110:165afa46840b 430 */
Kojto 110:165afa46840b 431
Kojto 110:165afa46840b 432 /** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto 110:165afa46840b 433 * @{
Kojto 110:165afa46840b 434 */
Kojto 110:165afa46840b 435 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
Kojto 110:165afa46840b 436 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
Kojto 110:165afa46840b 437 /**
Kojto 110:165afa46840b 438 * @}
Kojto 110:165afa46840b 439 */
Kojto 110:165afa46840b 440
Kojto 110:165afa46840b 441 /** @defgroup FMC_Write_Operation FMC Write Operation
Kojto 110:165afa46840b 442 * @{
Kojto 110:165afa46840b 443 */
Kojto 110:165afa46840b 444 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 445 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
Kojto 110:165afa46840b 446 /**
Kojto 110:165afa46840b 447 * @}
Kojto 110:165afa46840b 448 */
Kojto 110:165afa46840b 449
Kojto 110:165afa46840b 450 /** @defgroup FMC_Wait_Signal FMC Wait Signal
Kojto 110:165afa46840b 451 * @{
Kojto 110:165afa46840b 452 */
Kojto 110:165afa46840b 453 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 454 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
Kojto 110:165afa46840b 455 /**
Kojto 110:165afa46840b 456 * @}
Kojto 110:165afa46840b 457 */
Kojto 110:165afa46840b 458
Kojto 110:165afa46840b 459 /** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto 110:165afa46840b 460 * @{
Kojto 110:165afa46840b 461 */
Kojto 110:165afa46840b 462 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 463 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
Kojto 110:165afa46840b 464 /**
Kojto 110:165afa46840b 465 * @}
Kojto 110:165afa46840b 466 */
Kojto 110:165afa46840b 467
Kojto 110:165afa46840b 468 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
Kojto 110:165afa46840b 469 * @{
Kojto 110:165afa46840b 470 */
Kojto 110:165afa46840b 471 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 472 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
Kojto 110:165afa46840b 473 /**
Kojto 110:165afa46840b 474 * @}
Kojto 110:165afa46840b 475 */
Kojto 110:165afa46840b 476
Kojto 110:165afa46840b 477 /** @defgroup FMC_Page_Size FMC Page Size
Kojto 110:165afa46840b 478 * @note These values are available only for the STM32F446/469/479xx devices.
Kojto 110:165afa46840b 479 * @{
Kojto 110:165afa46840b 480 */
Kojto 110:165afa46840b 481 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 482 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto 110:165afa46840b 483 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto 110:165afa46840b 484 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto 110:165afa46840b 485 /**
Kojto 110:165afa46840b 486 * @}
Kojto 110:165afa46840b 487 */
Kojto 110:165afa46840b 488
Kojto 110:165afa46840b 489 /** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto 110:165afa46840b 490 * @note These values are available only for the STM32F446/469/479xx devices.
Kojto 110:165afa46840b 491 * @{
Kojto 110:165afa46840b 492 */
Kojto 110:165afa46840b 493 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 494 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto 110:165afa46840b 495 /**
Kojto 110:165afa46840b 496 * @}
Kojto 110:165afa46840b 497 */
Kojto 110:165afa46840b 498
Kojto 110:165afa46840b 499 /** @defgroup FMC_Write_Burst FMC Write Burst
Kojto 110:165afa46840b 500 * @{
Kojto 110:165afa46840b 501 */
Kojto 110:165afa46840b 502 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 503 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
Kojto 110:165afa46840b 504 /**
Kojto 110:165afa46840b 505 * @}
Kojto 110:165afa46840b 506 */
Kojto 110:165afa46840b 507
Kojto 110:165afa46840b 508 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
Kojto 110:165afa46840b 509 * @{
Kojto 110:165afa46840b 510 */
Kojto 110:165afa46840b 511 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
Kojto 110:165afa46840b 512 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
Kojto 110:165afa46840b 513 /**
Kojto 110:165afa46840b 514 * @}
Kojto 110:165afa46840b 515 */
Kojto 110:165afa46840b 516
Kojto 110:165afa46840b 517 /** @defgroup FMC_Access_Mode FMC Access Mode
Kojto 110:165afa46840b 518 * @{
Kojto 110:165afa46840b 519 */
Kojto 110:165afa46840b 520 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
Kojto 110:165afa46840b 521 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
Kojto 110:165afa46840b 522 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
Kojto 110:165afa46840b 523 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
Kojto 110:165afa46840b 524 /**
Kojto 110:165afa46840b 525 * @}
Kojto 110:165afa46840b 526 */
Kojto 110:165afa46840b 527
Kojto 110:165afa46840b 528 /**
Kojto 110:165afa46840b 529 * @}
Kojto 110:165afa46840b 530 */
Kojto 110:165afa46840b 531
Kojto 110:165afa46840b 532 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
Kojto 110:165afa46840b 533 * @{
Kojto 110:165afa46840b 534 */
Kojto 110:165afa46840b 535 /** @defgroup FMC_NAND_Bank FMC NAND Bank
Kojto 110:165afa46840b 536 * @{
Kojto 110:165afa46840b 537 */
Kojto 110:165afa46840b 538 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 539 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 540 /**
Kojto 110:165afa46840b 541 * @}
Kojto 110:165afa46840b 542 */
Kojto 110:165afa46840b 543
Kojto 110:165afa46840b 544 /** @defgroup FMC_Wait_feature FMC Wait feature
Kojto 110:165afa46840b 545 * @{
Kojto 110:165afa46840b 546 */
Kojto 110:165afa46840b 547 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 548 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
Kojto 110:165afa46840b 549 /**
Kojto 110:165afa46840b 550 * @}
Kojto 110:165afa46840b 551 */
Kojto 110:165afa46840b 552
Kojto 110:165afa46840b 553 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
Kojto 110:165afa46840b 554 * @{
Kojto 110:165afa46840b 555 */
Kojto 110:165afa46840b 556 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
Kojto 110:165afa46840b 557 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
Kojto 110:165afa46840b 558 /**
Kojto 110:165afa46840b 559 * @}
Kojto 110:165afa46840b 560 */
Kojto 110:165afa46840b 561
Kojto 110:165afa46840b 562 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
Kojto 110:165afa46840b 563 * @{
Kojto 110:165afa46840b 564 */
Kojto 110:165afa46840b 565 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 566 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 567 /**
Kojto 110:165afa46840b 568 * @}
Kojto 110:165afa46840b 569 */
Kojto 110:165afa46840b 570
Kojto 110:165afa46840b 571 /** @defgroup FMC_ECC FMC ECC
Kojto 110:165afa46840b 572 * @{
Kojto 110:165afa46840b 573 */
Kojto 110:165afa46840b 574 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 575 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
Kojto 110:165afa46840b 576 /**
Kojto 110:165afa46840b 577 * @}
Kojto 110:165afa46840b 578 */
Kojto 110:165afa46840b 579
Kojto 110:165afa46840b 580 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
Kojto 110:165afa46840b 581 * @{
Kojto 110:165afa46840b 582 */
Kojto 110:165afa46840b 583 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 584 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
Kojto 110:165afa46840b 585 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
Kojto 110:165afa46840b 586 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
Kojto 110:165afa46840b 587 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
Kojto 110:165afa46840b 588 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
Kojto 110:165afa46840b 589 /**
Kojto 110:165afa46840b 590 * @}
Kojto 110:165afa46840b 591 */
Kojto 110:165afa46840b 592
Kojto 110:165afa46840b 593 /**
Kojto 110:165afa46840b 594 * @}
Kojto 110:165afa46840b 595 */
Kojto 110:165afa46840b 596
Kojto 110:165afa46840b 597 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
Kojto 110:165afa46840b 598 * @{
Kojto 110:165afa46840b 599 */
Kojto 110:165afa46840b 600 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
Kojto 110:165afa46840b 601 * @{
Kojto 110:165afa46840b 602 */
Kojto 110:165afa46840b 603 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 604 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 605 /**
Kojto 110:165afa46840b 606 * @}
Kojto 110:165afa46840b 607 */
Kojto 110:165afa46840b 608
Kojto 110:165afa46840b 609 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
Kojto 110:165afa46840b 610 * @{
Kojto 110:165afa46840b 611 */
Kojto 110:165afa46840b 612 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 613 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
Kojto 110:165afa46840b 614 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
Kojto 110:165afa46840b 615 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
Kojto 110:165afa46840b 616 /**
Kojto 110:165afa46840b 617 * @}
Kojto 110:165afa46840b 618 */
Kojto 110:165afa46840b 619
Kojto 110:165afa46840b 620 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
Kojto 110:165afa46840b 621 * @{
Kojto 110:165afa46840b 622 */
Kojto 110:165afa46840b 623 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 624 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
Kojto 110:165afa46840b 625 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
Kojto 110:165afa46840b 626 /**
Kojto 110:165afa46840b 627 * @}
Kojto 110:165afa46840b 628 */
Kojto 110:165afa46840b 629
Kojto 110:165afa46840b 630 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
Kojto 110:165afa46840b 631 * @{
Kojto 110:165afa46840b 632 */
Kojto 110:165afa46840b 633 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 634 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto 110:165afa46840b 635 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto 110:165afa46840b 636 /**
Kojto 110:165afa46840b 637 * @}
Kojto 110:165afa46840b 638 */
Kojto 110:165afa46840b 639
Kojto 110:165afa46840b 640 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
Kojto 110:165afa46840b 641 * @{
Kojto 110:165afa46840b 642 */
Kojto 110:165afa46840b 643 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 644 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 645 /**
Kojto 110:165afa46840b 646 * @}
Kojto 110:165afa46840b 647 */
Kojto 110:165afa46840b 648
Kojto 110:165afa46840b 649 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
Kojto 110:165afa46840b 650 * @{
Kojto 110:165afa46840b 651 */
Kojto 110:165afa46840b 652 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 653 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
Kojto 110:165afa46840b 654 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
Kojto 110:165afa46840b 655 /**
Kojto 110:165afa46840b 656 * @}
Kojto 110:165afa46840b 657 */
Kojto 110:165afa46840b 658
Kojto 110:165afa46840b 659 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
Kojto 110:165afa46840b 660 * @{
Kojto 110:165afa46840b 661 */
Kojto 110:165afa46840b 662 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 663 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
Kojto 110:165afa46840b 664
Kojto 110:165afa46840b 665 /**
Kojto 110:165afa46840b 666 * @}
Kojto 110:165afa46840b 667 */
Kojto 110:165afa46840b 668
Kojto 110:165afa46840b 669 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
Kojto 110:165afa46840b 670 * @{
Kojto 110:165afa46840b 671 */
Kojto 110:165afa46840b 672 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 673 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
Kojto 110:165afa46840b 674 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
Kojto 110:165afa46840b 675 /**
Kojto 110:165afa46840b 676 * @}
Kojto 110:165afa46840b 677 */
Kojto 110:165afa46840b 678
Kojto 110:165afa46840b 679 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
Kojto 110:165afa46840b 680 * @{
Kojto 110:165afa46840b 681 */
Kojto 110:165afa46840b 682 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 683 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
Kojto 110:165afa46840b 684 /**
Kojto 110:165afa46840b 685 * @}
Kojto 110:165afa46840b 686 */
Kojto 110:165afa46840b 687
Kojto 110:165afa46840b 688 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
Kojto 110:165afa46840b 689 * @{
Kojto 110:165afa46840b 690 */
Kojto 110:165afa46840b 691 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
Kojto 110:165afa46840b 692 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
Kojto 110:165afa46840b 693 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
Kojto 110:165afa46840b 694 /**
Kojto 110:165afa46840b 695 * @}
Kojto 110:165afa46840b 696 */
Kojto 110:165afa46840b 697
Kojto 110:165afa46840b 698 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
Kojto 110:165afa46840b 699 * @{
Kojto 110:165afa46840b 700 */
Kojto 110:165afa46840b 701 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 702 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
Kojto 110:165afa46840b 703 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
Kojto 110:165afa46840b 704 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
Kojto 110:165afa46840b 705 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
Kojto 110:165afa46840b 706 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
Kojto 110:165afa46840b 707 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
Kojto 110:165afa46840b 708 /**
Kojto 110:165afa46840b 709 * @}
Kojto 110:165afa46840b 710 */
Kojto 110:165afa46840b 711
Kojto 110:165afa46840b 712 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
Kojto 110:165afa46840b 713 * @{
Kojto 110:165afa46840b 714 */
Kojto 110:165afa46840b 715 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
Kojto 110:165afa46840b 716 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
Kojto 110:165afa46840b 717 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
Kojto 110:165afa46840b 718 /**
Kojto 110:165afa46840b 719 * @}
Kojto 110:165afa46840b 720 */
Kojto 110:165afa46840b 721
Kojto 110:165afa46840b 722 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
Kojto 110:165afa46840b 723 * @{
Kojto 110:165afa46840b 724 */
Kojto 110:165afa46840b 725 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
Kojto 110:165afa46840b 726 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
Kojto 110:165afa46840b 727 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
Kojto 110:165afa46840b 728 /**
Kojto 110:165afa46840b 729 * @}
Kojto 110:165afa46840b 730 */
Kojto 110:165afa46840b 731
Kojto 110:165afa46840b 732 /**
Kojto 110:165afa46840b 733 * @}
Kojto 110:165afa46840b 734 */
Kojto 110:165afa46840b 735
Kojto 110:165afa46840b 736 /** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
Kojto 110:165afa46840b 737 * @{
Kojto 110:165afa46840b 738 */
Kojto 110:165afa46840b 739 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
Kojto 110:165afa46840b 740 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
Kojto 110:165afa46840b 741 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
Kojto 110:165afa46840b 742 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
Kojto 110:165afa46840b 743 /**
Kojto 110:165afa46840b 744 * @}
Kojto 110:165afa46840b 745 */
Kojto 110:165afa46840b 746
Kojto 110:165afa46840b 747 /** @defgroup FMC_LL_Flag_definition FMC Flag definition
Kojto 110:165afa46840b 748 * @{
Kojto 110:165afa46840b 749 */
Kojto 110:165afa46840b 750 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
Kojto 110:165afa46840b 751 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
Kojto 110:165afa46840b 752 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
Kojto 110:165afa46840b 753 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
Kojto 110:165afa46840b 754 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
Kojto 110:165afa46840b 755 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
Kojto 110:165afa46840b 756 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
Kojto 110:165afa46840b 757 /**
Kojto 110:165afa46840b 758 * @}
Kojto 110:165afa46840b 759 */
Kojto 110:165afa46840b 760
Kojto 110:165afa46840b 761 /** @defgroup FMC_LL_Alias_definition FMC Alias definition
Kojto 110:165afa46840b 762 * @{
Kojto 110:165afa46840b 763 */
Kojto 110:165afa46840b 764 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 765 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto 110:165afa46840b 766 #else
Kojto 110:165afa46840b 767 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
Kojto 110:165afa46840b 768 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
Kojto 110:165afa46840b 769 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 110:165afa46840b 770 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto 110:165afa46840b 771 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto 110:165afa46840b 772 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto 110:165afa46840b 773
Kojto 110:165afa46840b 774
Kojto 110:165afa46840b 775 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 776 #define FMC_NAND_DEVICE FMC_Bank3
Kojto 110:165afa46840b 777 #else
Kojto 110:165afa46840b 778 #define FMC_NAND_DEVICE FMC_Bank2_3
Kojto 110:165afa46840b 779 #define FMC_PCCARD_DEVICE FMC_Bank4
Kojto 110:165afa46840b 780 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 110:165afa46840b 781 #define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto 110:165afa46840b 782 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto 110:165afa46840b 783 #define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto 110:165afa46840b 784 /**
Kojto 110:165afa46840b 785 * @}
Kojto 110:165afa46840b 786 */
Kojto 110:165afa46840b 787
Kojto 110:165afa46840b 788 /**
Kojto 110:165afa46840b 789 * @}
Kojto 110:165afa46840b 790 */
Kojto 110:165afa46840b 791
Kojto 110:165afa46840b 792 /* Private macro -------------------------------------------------------------*/
Kojto 110:165afa46840b 793 /** @defgroup FMC_LL_Private_Macros FMC Private Macros
Kojto 110:165afa46840b 794 * @{
Kojto 110:165afa46840b 795 */
Kojto 110:165afa46840b 796
Kojto 110:165afa46840b 797 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
Kojto 110:165afa46840b 798 * @brief macros to handle NOR device enable/disable and read/write operations
Kojto 110:165afa46840b 799 * @{
Kojto 110:165afa46840b 800 */
Kojto 110:165afa46840b 801 /**
Kojto 110:165afa46840b 802 * @brief Enable the NORSRAM device access.
Kojto 110:165afa46840b 803 * @param __INSTANCE__: FMC_NORSRAM Instance
Kojto 110:165afa46840b 804 * @param __BANK__: FMC_NORSRAM Bank
Kojto 110:165afa46840b 805 * @retval None
Kojto 110:165afa46840b 806 */
Kojto 110:165afa46840b 807 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
Kojto 110:165afa46840b 808
Kojto 110:165afa46840b 809 /**
Kojto 110:165afa46840b 810 * @brief Disable the NORSRAM device access.
Kojto 110:165afa46840b 811 * @param __INSTANCE__: FMC_NORSRAM Instance
Kojto 110:165afa46840b 812 * @param __BANK__: FMC_NORSRAM Bank
Kojto 110:165afa46840b 813 * @retval None
Kojto 110:165afa46840b 814 */
Kojto 110:165afa46840b 815 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
Kojto 110:165afa46840b 816 /**
Kojto 110:165afa46840b 817 * @}
Kojto 110:165afa46840b 818 */
Kojto 110:165afa46840b 819
Kojto 110:165afa46840b 820 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
Kojto 110:165afa46840b 821 * @brief macros to handle NAND device enable/disable
Kojto 110:165afa46840b 822 * @{
Kojto 110:165afa46840b 823 */
Kojto 110:165afa46840b 824 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 825 /**
Kojto 110:165afa46840b 826 * @brief Enable the NAND device access.
Kojto 110:165afa46840b 827 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 828 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 829 * @retval None
Kojto 110:165afa46840b 830 */
Kojto 110:165afa46840b 831 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
Kojto 110:165afa46840b 832
Kojto 110:165afa46840b 833 /**
Kojto 110:165afa46840b 834 * @brief Disable the NAND device access.
Kojto 110:165afa46840b 835 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 836 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 837 * @retval None
Kojto 110:165afa46840b 838 */
Kojto 110:165afa46840b 839 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto 110:165afa46840b 840 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 110:165afa46840b 841 /**
Kojto 110:165afa46840b 842 * @brief Enable the NAND device access.
Kojto 110:165afa46840b 843 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 844 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 845 * @retval None
Kojto 110:165afa46840b 846 */
Kojto 110:165afa46840b 847 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
Kojto 110:165afa46840b 848 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
Kojto 110:165afa46840b 849
Kojto 110:165afa46840b 850 /**
Kojto 110:165afa46840b 851 * @brief Disable the NAND device access.
Kojto 110:165afa46840b 852 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 853 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 854 * @retval None
Kojto 110:165afa46840b 855 */
Kojto 110:165afa46840b 856 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
Kojto 110:165afa46840b 857 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
Kojto 110:165afa46840b 858
Kojto 110:165afa46840b 859 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
Kojto 110:165afa46840b 860 /**
Kojto 110:165afa46840b 861 * @}
Kojto 110:165afa46840b 862 */
Kojto 110:165afa46840b 863 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 110:165afa46840b 864 /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
Kojto 110:165afa46840b 865 * @brief macros to handle SRAM read/write operations
Kojto 110:165afa46840b 866 * @{
Kojto 110:165afa46840b 867 */
Kojto 110:165afa46840b 868 /**
Kojto 110:165afa46840b 869 * @brief Enable the PCCARD device access.
Kojto 110:165afa46840b 870 * @param __INSTANCE__: FMC_PCCARD Instance
Kojto 110:165afa46840b 871 * @retval None
Kojto 110:165afa46840b 872 */
Kojto 110:165afa46840b 873 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
Kojto 110:165afa46840b 874
Kojto 110:165afa46840b 875 /**
Kojto 110:165afa46840b 876 * @brief Disable the PCCARD device access.
Kojto 110:165afa46840b 877 * @param __INSTANCE__: FMC_PCCARD Instance
Kojto 110:165afa46840b 878 * @retval None
Kojto 110:165afa46840b 879 */
Kojto 110:165afa46840b 880 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
Kojto 110:165afa46840b 881 /**
Kojto 110:165afa46840b 882 * @}
Kojto 110:165afa46840b 883 */
Kojto 110:165afa46840b 884 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 110:165afa46840b 885
Kojto 110:165afa46840b 886 /** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
Kojto 110:165afa46840b 887 * @brief macros to handle FMC flags and interrupts
Kojto 110:165afa46840b 888 * @{
Kojto 110:165afa46840b 889 */
Kojto 110:165afa46840b 890 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 891 /**
Kojto 110:165afa46840b 892 * @brief Enable the NAND device interrupt.
Kojto 110:165afa46840b 893 * @param __INSTANCE__: FMC_NAND instance
Kojto 110:165afa46840b 894 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 895 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 110:165afa46840b 896 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 897 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 110:165afa46840b 898 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 110:165afa46840b 899 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 110:165afa46840b 900 * @retval None
Kojto 110:165afa46840b 901 */
Kojto 110:165afa46840b 902 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
Kojto 110:165afa46840b 903
Kojto 110:165afa46840b 904 /**
Kojto 110:165afa46840b 905 * @brief Disable the NAND device interrupt.
Kojto 110:165afa46840b 906 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 907 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 908 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 110:165afa46840b 909 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 910 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 110:165afa46840b 911 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 110:165afa46840b 912 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 110:165afa46840b 913 * @retval None
Kojto 110:165afa46840b 914 */
Kojto 110:165afa46840b 915 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto 110:165afa46840b 916
Kojto 110:165afa46840b 917 /**
Kojto 110:165afa46840b 918 * @brief Get flag status of the NAND device.
Kojto 110:165afa46840b 919 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 920 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 921 * @param __FLAG__: FMC_NAND flag
Kojto 110:165afa46840b 922 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 923 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 110:165afa46840b 924 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 110:165afa46840b 925 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 110:165afa46840b 926 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 110:165afa46840b 927 * @retval The state of FLAG (SET or RESET).
Kojto 110:165afa46840b 928 */
Kojto 110:165afa46840b 929 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto 110:165afa46840b 930 /**
Kojto 110:165afa46840b 931 * @brief Clear flag status of the NAND device.
Kojto 110:165afa46840b 932 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 933 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 934 * @param __FLAG__: FMC_NAND flag
Kojto 110:165afa46840b 935 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 936 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 110:165afa46840b 937 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 110:165afa46840b 938 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 110:165afa46840b 939 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 110:165afa46840b 940 * @retval None
Kojto 110:165afa46840b 941 */
Kojto 110:165afa46840b 942 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto 110:165afa46840b 943 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 110:165afa46840b 944 /**
Kojto 110:165afa46840b 945 * @brief Enable the NAND device interrupt.
Kojto 110:165afa46840b 946 * @param __INSTANCE__: FMC_NAND instance
Kojto 110:165afa46840b 947 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 948 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 110:165afa46840b 949 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 950 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 110:165afa46840b 951 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 110:165afa46840b 952 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 110:165afa46840b 953 * @retval None
Kojto 110:165afa46840b 954 */
Kojto 110:165afa46840b 955 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
Kojto 110:165afa46840b 956 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
Kojto 110:165afa46840b 957
Kojto 110:165afa46840b 958 /**
Kojto 110:165afa46840b 959 * @brief Disable the NAND device interrupt.
Kojto 110:165afa46840b 960 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 961 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 962 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 110:165afa46840b 963 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 964 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 110:165afa46840b 965 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 110:165afa46840b 966 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 110:165afa46840b 967 * @retval None
Kojto 110:165afa46840b 968 */
Kojto 110:165afa46840b 969 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto 110:165afa46840b 970 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto 110:165afa46840b 971
Kojto 110:165afa46840b 972 /**
Kojto 110:165afa46840b 973 * @brief Get flag status of the NAND device.
Kojto 110:165afa46840b 974 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 975 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 976 * @param __FLAG__: FMC_NAND flag
Kojto 110:165afa46840b 977 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 978 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 110:165afa46840b 979 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 110:165afa46840b 980 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 110:165afa46840b 981 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 110:165afa46840b 982 * @retval The state of FLAG (SET or RESET).
Kojto 110:165afa46840b 983 */
Kojto 110:165afa46840b 984 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto 110:165afa46840b 985 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto 110:165afa46840b 986 /**
Kojto 110:165afa46840b 987 * @brief Clear flag status of the NAND device.
Kojto 110:165afa46840b 988 * @param __INSTANCE__: FMC_NAND Instance
Kojto 110:165afa46840b 989 * @param __BANK__: FMC_NAND Bank
Kojto 110:165afa46840b 990 * @param __FLAG__: FMC_NAND flag
Kojto 110:165afa46840b 991 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 992 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 110:165afa46840b 993 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 110:165afa46840b 994 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 110:165afa46840b 995 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 110:165afa46840b 996 * @retval None
Kojto 110:165afa46840b 997 */
Kojto 110:165afa46840b 998 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto 110:165afa46840b 999 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto 110:165afa46840b 1000 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
Kojto 110:165afa46840b 1001
Kojto 110:165afa46840b 1002 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 110:165afa46840b 1003 /**
Kojto 110:165afa46840b 1004 * @brief Enable the PCCARD device interrupt.
Kojto 110:165afa46840b 1005 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 110:165afa46840b 1006 * @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto 110:165afa46840b 1007 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1008 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 110:165afa46840b 1009 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 110:165afa46840b 1010 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 110:165afa46840b 1011 * @retval None
Kojto 110:165afa46840b 1012 */
Kojto 110:165afa46840b 1013 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
Kojto 110:165afa46840b 1014
Kojto 110:165afa46840b 1015 /**
Kojto 110:165afa46840b 1016 * @brief Disable the PCCARD device interrupt.
Kojto 110:165afa46840b 1017 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 110:165afa46840b 1018 * @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto 110:165afa46840b 1019 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1020 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 110:165afa46840b 1021 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 110:165afa46840b 1022 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 110:165afa46840b 1023 * @retval None
Kojto 110:165afa46840b 1024 */
Kojto 110:165afa46840b 1025 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto 110:165afa46840b 1026
Kojto 110:165afa46840b 1027 /**
Kojto 110:165afa46840b 1028 * @brief Get flag status of the PCCARD device.
Kojto 110:165afa46840b 1029 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 110:165afa46840b 1030 * @param __FLAG__: FMC_PCCARD flag
Kojto 110:165afa46840b 1031 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1032 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 110:165afa46840b 1033 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 110:165afa46840b 1034 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 110:165afa46840b 1035 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 110:165afa46840b 1036 * @retval The state of FLAG (SET or RESET).
Kojto 110:165afa46840b 1037 */
Kojto 110:165afa46840b 1038 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto 110:165afa46840b 1039
Kojto 110:165afa46840b 1040 /**
Kojto 110:165afa46840b 1041 * @brief Clear flag status of the PCCARD device.
Kojto 110:165afa46840b 1042 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 110:165afa46840b 1043 * @param __FLAG__: FMC_PCCARD flag
Kojto 110:165afa46840b 1044 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1045 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 110:165afa46840b 1046 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 110:165afa46840b 1047 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 110:165afa46840b 1048 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 110:165afa46840b 1049 * @retval None
Kojto 110:165afa46840b 1050 */
Kojto 110:165afa46840b 1051 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto 110:165afa46840b 1052 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 110:165afa46840b 1053
Kojto 110:165afa46840b 1054 /**
Kojto 110:165afa46840b 1055 * @brief Enable the SDRAM device interrupt.
Kojto 110:165afa46840b 1056 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 110:165afa46840b 1057 * @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto 110:165afa46840b 1058 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1059 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto 110:165afa46840b 1060 * @retval None
Kojto 110:165afa46840b 1061 */
Kojto 110:165afa46840b 1062 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
Kojto 110:165afa46840b 1063
Kojto 110:165afa46840b 1064 /**
Kojto 110:165afa46840b 1065 * @brief Disable the SDRAM device interrupt.
Kojto 110:165afa46840b 1066 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 110:165afa46840b 1067 * @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto 110:165afa46840b 1068 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1069 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto 110:165afa46840b 1070 * @retval None
Kojto 110:165afa46840b 1071 */
Kojto 110:165afa46840b 1072 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
Kojto 110:165afa46840b 1073
Kojto 110:165afa46840b 1074 /**
Kojto 110:165afa46840b 1075 * @brief Get flag status of the SDRAM device.
Kojto 110:165afa46840b 1076 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 110:165afa46840b 1077 * @param __FLAG__: FMC_SDRAM flag
Kojto 110:165afa46840b 1078 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1079 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
Kojto 110:165afa46840b 1080 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
Kojto 110:165afa46840b 1081 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
Kojto 110:165afa46840b 1082 * @retval The state of FLAG (SET or RESET).
Kojto 110:165afa46840b 1083 */
Kojto 110:165afa46840b 1084 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
Kojto 110:165afa46840b 1085
Kojto 110:165afa46840b 1086 /**
Kojto 110:165afa46840b 1087 * @brief Clear flag status of the SDRAM device.
Kojto 110:165afa46840b 1088 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 110:165afa46840b 1089 * @param __FLAG__: FMC_SDRAM flag
Kojto 110:165afa46840b 1090 * This parameter can be any combination of the following values:
Kojto 110:165afa46840b 1091 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
Kojto 110:165afa46840b 1092 * @retval None
Kojto 110:165afa46840b 1093 */
Kojto 110:165afa46840b 1094 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
Kojto 110:165afa46840b 1095 /**
Kojto 110:165afa46840b 1096 * @}
Kojto 110:165afa46840b 1097 */
Kojto 110:165afa46840b 1098
Kojto 110:165afa46840b 1099 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto 110:165afa46840b 1100 * @{
Kojto 110:165afa46840b 1101 */
Kojto 110:165afa46840b 1102 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
Kojto 110:165afa46840b 1103 ((BANK) == FMC_NORSRAM_BANK2) || \
Kojto 110:165afa46840b 1104 ((BANK) == FMC_NORSRAM_BANK3) || \
Kojto 110:165afa46840b 1105 ((BANK) == FMC_NORSRAM_BANK4))
Kojto 110:165afa46840b 1106
Kojto 110:165afa46840b 1107 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
Kojto 110:165afa46840b 1108 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto 110:165afa46840b 1109
Kojto 110:165afa46840b 1110 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
Kojto 110:165afa46840b 1111 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
Kojto 110:165afa46840b 1112 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto 110:165afa46840b 1113
Kojto 110:165afa46840b 1114 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
Kojto 110:165afa46840b 1115 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
Kojto 110:165afa46840b 1116 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto 110:165afa46840b 1117
Kojto 110:165afa46840b 1118 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
Kojto 110:165afa46840b 1119 ((__MODE__) == FMC_ACCESS_MODE_B) || \
Kojto 110:165afa46840b 1120 ((__MODE__) == FMC_ACCESS_MODE_C) || \
Kojto 110:165afa46840b 1121 ((__MODE__) == FMC_ACCESS_MODE_D))
Kojto 110:165afa46840b 1122
Kojto 110:165afa46840b 1123 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
Kojto 110:165afa46840b 1124 ((BANK) == FMC_NAND_BANK3))
Kojto 110:165afa46840b 1125
Kojto 110:165afa46840b 1126 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
Kojto 110:165afa46840b 1127 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto 110:165afa46840b 1128
Kojto 110:165afa46840b 1129 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
Kojto 110:165afa46840b 1130 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto 110:165afa46840b 1131
Kojto 110:165afa46840b 1132 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
Kojto 110:165afa46840b 1133 ((STATE) == FMC_NAND_ECC_ENABLE))
Kojto 110:165afa46840b 1134
Kojto 110:165afa46840b 1135 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
Kojto 110:165afa46840b 1136 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
Kojto 110:165afa46840b 1137 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
Kojto 110:165afa46840b 1138 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
Kojto 110:165afa46840b 1139 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
Kojto 110:165afa46840b 1140 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto 110:165afa46840b 1141
Kojto 110:165afa46840b 1142 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
Kojto 110:165afa46840b 1143
Kojto 110:165afa46840b 1144 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
Kojto 110:165afa46840b 1145
Kojto 110:165afa46840b 1146 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
Kojto 110:165afa46840b 1147
Kojto 110:165afa46840b 1148 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
Kojto 110:165afa46840b 1149
Kojto 110:165afa46840b 1150 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
Kojto 110:165afa46840b 1151
Kojto 110:165afa46840b 1152 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
Kojto 110:165afa46840b 1153
Kojto 110:165afa46840b 1154 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto 110:165afa46840b 1155
Kojto 110:165afa46840b 1156 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto 110:165afa46840b 1157
Kojto 110:165afa46840b 1158 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto 110:165afa46840b 1159
Kojto 110:165afa46840b 1160 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
Kojto 110:165afa46840b 1161
Kojto 110:165afa46840b 1162 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
Kojto 110:165afa46840b 1163 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto 110:165afa46840b 1164
Kojto 110:165afa46840b 1165 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
Kojto 110:165afa46840b 1166 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto 110:165afa46840b 1167
Kojto 110:165afa46840b 1168 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 110:165afa46840b 1169 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
Kojto 110:165afa46840b 1170 ((__MODE__) == FMC_WRAP_MODE_ENABLE))
Kojto 110:165afa46840b 1171 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 110:165afa46840b 1172
Kojto 110:165afa46840b 1173 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
Kojto 110:165afa46840b 1174 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto 110:165afa46840b 1175
Kojto 110:165afa46840b 1176 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
Kojto 110:165afa46840b 1177 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto 110:165afa46840b 1178
Kojto 110:165afa46840b 1179 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
Kojto 110:165afa46840b 1180 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto 110:165afa46840b 1181
Kojto 110:165afa46840b 1182 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
Kojto 110:165afa46840b 1183 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto 110:165afa46840b 1184
Kojto 110:165afa46840b 1185 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
Kojto 110:165afa46840b 1186 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto 110:165afa46840b 1187
Kojto 110:165afa46840b 1188 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
Kojto 110:165afa46840b 1189 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto 110:165afa46840b 1190
Kojto 110:165afa46840b 1191 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
Kojto 110:165afa46840b 1192 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto 110:165afa46840b 1193
Kojto 110:165afa46840b 1194 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
Kojto 110:165afa46840b 1195
Kojto 110:165afa46840b 1196 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
Kojto 110:165afa46840b 1197
Kojto 110:165afa46840b 1198 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
Kojto 110:165afa46840b 1199
Kojto 110:165afa46840b 1200 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
Kojto 110:165afa46840b 1201
Kojto 110:165afa46840b 1202 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
Kojto 110:165afa46840b 1203
Kojto 110:165afa46840b 1204 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
Kojto 110:165afa46840b 1205
Kojto 110:165afa46840b 1206 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
Kojto 110:165afa46840b 1207 ((BANK) == FMC_SDRAM_BANK2))
Kojto 110:165afa46840b 1208
Kojto 110:165afa46840b 1209 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
Kojto 110:165afa46840b 1210 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
Kojto 110:165afa46840b 1211 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
Kojto 110:165afa46840b 1212 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto 110:165afa46840b 1213
Kojto 110:165afa46840b 1214 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
Kojto 110:165afa46840b 1215 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
Kojto 110:165afa46840b 1216 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto 110:165afa46840b 1217
Kojto 110:165afa46840b 1218 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
Kojto 110:165afa46840b 1219 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
Kojto 110:165afa46840b 1220 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto 110:165afa46840b 1221
Kojto 110:165afa46840b 1222 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
Kojto 110:165afa46840b 1223 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto 110:165afa46840b 1224
Kojto 110:165afa46840b 1225
Kojto 110:165afa46840b 1226 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
Kojto 110:165afa46840b 1227 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
Kojto 110:165afa46840b 1228 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto 110:165afa46840b 1229
Kojto 110:165afa46840b 1230 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
Kojto 110:165afa46840b 1231 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
Kojto 110:165afa46840b 1232 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto 110:165afa46840b 1233
Kojto 110:165afa46840b 1234 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
Kojto 110:165afa46840b 1235 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
Kojto 110:165afa46840b 1236
Kojto 110:165afa46840b 1237
Kojto 110:165afa46840b 1238 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
Kojto 110:165afa46840b 1239 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
Kojto 110:165afa46840b 1240 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto 110:165afa46840b 1241
Kojto 110:165afa46840b 1242 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 110:165afa46840b 1243
Kojto 110:165afa46840b 1244 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 110:165afa46840b 1245
Kojto 110:165afa46840b 1246 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto 110:165afa46840b 1247
Kojto 110:165afa46840b 1248 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 110:165afa46840b 1249
Kojto 110:165afa46840b 1250 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto 110:165afa46840b 1251
Kojto 110:165afa46840b 1252 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 110:165afa46840b 1253
Kojto 110:165afa46840b 1254 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 110:165afa46840b 1255
Kojto 110:165afa46840b 1256 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
Kojto 110:165afa46840b 1257 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
Kojto 110:165afa46840b 1258 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
Kojto 110:165afa46840b 1259 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
Kojto 110:165afa46840b 1260 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
Kojto 110:165afa46840b 1261 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
Kojto 110:165afa46840b 1262 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto 110:165afa46840b 1263
Kojto 110:165afa46840b 1264 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
Kojto 110:165afa46840b 1265 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
Kojto 110:165afa46840b 1266 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto 110:165afa46840b 1267
Kojto 110:165afa46840b 1268 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
Kojto 110:165afa46840b 1269
Kojto 110:165afa46840b 1270 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
Kojto 110:165afa46840b 1271
Kojto 110:165afa46840b 1272 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
Kojto 110:165afa46840b 1273
Kojto 110:165afa46840b 1274 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
Kojto 110:165afa46840b 1275
Kojto 110:165afa46840b 1276 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
Kojto 110:165afa46840b 1277 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto 110:165afa46840b 1278
Kojto 110:165afa46840b 1279 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 1280 #define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
Kojto 110:165afa46840b 1281 ((SIZE) == FMC_PAGE_SIZE_128) || \
Kojto 110:165afa46840b 1282 ((SIZE) == FMC_PAGE_SIZE_256) || \
Kojto 110:165afa46840b 1283 ((SIZE) == FMC_PAGE_SIZE_1024))
Kojto 110:165afa46840b 1284
Kojto 110:165afa46840b 1285 #define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
Kojto 110:165afa46840b 1286 ((FIFO) == FMC_WRITE_FIFO_ENABLE))
Kojto 110:165afa46840b 1287 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 110:165afa46840b 1288
Kojto 110:165afa46840b 1289 /**
Kojto 110:165afa46840b 1290 * @}
Kojto 110:165afa46840b 1291 */
Kojto 110:165afa46840b 1292
Kojto 110:165afa46840b 1293 /**
Kojto 110:165afa46840b 1294 * @}
Kojto 110:165afa46840b 1295 */
Kojto 110:165afa46840b 1296
Kojto 110:165afa46840b 1297 /* Private functions ---------------------------------------------------------*/
Kojto 110:165afa46840b 1298 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto 110:165afa46840b 1299 * @{
Kojto 110:165afa46840b 1300 */
Kojto 110:165afa46840b 1301
Kojto 110:165afa46840b 1302 /** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto 110:165afa46840b 1303 * @{
Kojto 110:165afa46840b 1304 */
Kojto 110:165afa46840b 1305 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto 110:165afa46840b 1306 * @{
Kojto 110:165afa46840b 1307 */
Kojto 110:165afa46840b 1308 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
Kojto 110:165afa46840b 1309 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 110:165afa46840b 1310 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto 110:165afa46840b 1311 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
Kojto 110:165afa46840b 1312 /**
Kojto 110:165afa46840b 1313 * @}
Kojto 110:165afa46840b 1314 */
Kojto 110:165afa46840b 1315
Kojto 110:165afa46840b 1316 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto 110:165afa46840b 1317 * @{
Kojto 110:165afa46840b 1318 */
Kojto 110:165afa46840b 1319 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 110:165afa46840b 1320 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 110:165afa46840b 1321 /**
Kojto 110:165afa46840b 1322 * @}
Kojto 110:165afa46840b 1323 */
Kojto 110:165afa46840b 1324 /**
Kojto 110:165afa46840b 1325 * @}
Kojto 110:165afa46840b 1326 */
Kojto 110:165afa46840b 1327
Kojto 110:165afa46840b 1328 /** @defgroup FMC_LL_NAND NAND
Kojto 110:165afa46840b 1329 * @{
Kojto 110:165afa46840b 1330 */
Kojto 110:165afa46840b 1331 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto 110:165afa46840b 1332 * @{
Kojto 110:165afa46840b 1333 */
Kojto 110:165afa46840b 1334 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
Kojto 110:165afa46840b 1335 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 110:165afa46840b 1336 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 110:165afa46840b 1337 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 110:165afa46840b 1338 /**
Kojto 110:165afa46840b 1339 * @}
Kojto 110:165afa46840b 1340 */
Kojto 110:165afa46840b 1341
Kojto 110:165afa46840b 1342 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto 110:165afa46840b 1343 * @{
Kojto 110:165afa46840b 1344 */
Kojto 110:165afa46840b 1345 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 110:165afa46840b 1346 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 110:165afa46840b 1347 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
Kojto 110:165afa46840b 1348
Kojto 110:165afa46840b 1349 /**
Kojto 110:165afa46840b 1350 * @}
Kojto 110:165afa46840b 1351 */
Kojto 110:165afa46840b 1352 /**
Kojto 110:165afa46840b 1353 * @}
Kojto 110:165afa46840b 1354 */
Kojto 110:165afa46840b 1355 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 110:165afa46840b 1356 /** @defgroup FMC_LL_PCCARD PCCARD
Kojto 110:165afa46840b 1357 * @{
Kojto 110:165afa46840b 1358 */
Kojto 110:165afa46840b 1359 /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto 110:165afa46840b 1360 * @{
Kojto 110:165afa46840b 1361 */
Kojto 110:165afa46840b 1362 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
Kojto 110:165afa46840b 1363 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 110:165afa46840b 1364 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 110:165afa46840b 1365 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 110:165afa46840b 1366 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
Kojto 110:165afa46840b 1367 /**
Kojto 110:165afa46840b 1368 * @}
Kojto 110:165afa46840b 1369 */
Kojto 110:165afa46840b 1370 /**
Kojto 110:165afa46840b 1371 * @}
Kojto 110:165afa46840b 1372 */
Kojto 110:165afa46840b 1373 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 110:165afa46840b 1374
Kojto 110:165afa46840b 1375 /** @defgroup FMC_LL_SDRAM SDRAM
Kojto 110:165afa46840b 1376 * @{
Kojto 110:165afa46840b 1377 */
Kojto 110:165afa46840b 1378 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto 110:165afa46840b 1379 * @{
Kojto 110:165afa46840b 1380 */
Kojto 110:165afa46840b 1381 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
Kojto 110:165afa46840b 1382 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 110:165afa46840b 1383 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 110:165afa46840b 1384 /**
Kojto 110:165afa46840b 1385 * @}
Kojto 110:165afa46840b 1386 */
Kojto 110:165afa46840b 1387
Kojto 110:165afa46840b 1388 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto 110:165afa46840b 1389 * @{
Kojto 110:165afa46840b 1390 */
Kojto 110:165afa46840b 1391 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 110:165afa46840b 1392 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 110:165afa46840b 1393 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
Kojto 110:165afa46840b 1394 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
Kojto 110:165afa46840b 1395 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
Kojto 110:165afa46840b 1396 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 110:165afa46840b 1397 /**
Kojto 110:165afa46840b 1398 * @}
Kojto 110:165afa46840b 1399 */
Kojto 110:165afa46840b 1400 /**
Kojto 110:165afa46840b 1401 * @}
Kojto 110:165afa46840b 1402 */
Kojto 110:165afa46840b 1403
Kojto 110:165afa46840b 1404 /**
Kojto 110:165afa46840b 1405 * @}
Kojto 110:165afa46840b 1406 */
Kojto 110:165afa46840b 1407
Kojto 110:165afa46840b 1408 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 110:165afa46840b 1409 /**
Kojto 110:165afa46840b 1410 * @}
Kojto 110:165afa46840b 1411 */
Kojto 110:165afa46840b 1412
Kojto 110:165afa46840b 1413 /**
Kojto 110:165afa46840b 1414 * @}
Kojto 110:165afa46840b 1415 */
Kojto 110:165afa46840b 1416 #ifdef __cplusplus
Kojto 110:165afa46840b 1417 }
Kojto 110:165afa46840b 1418 #endif
Kojto 110:165afa46840b 1419
Kojto 110:165afa46840b 1420 #endif /* __STM32F4xx_LL_FMC_H */
Kojto 110:165afa46840b 1421
Kojto 110:165afa46840b 1422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/