Diff: core/inverter.cpp

Revision:

33:e7b132029bae

Parent:

27:846c08fb3697

--- a/core/inverter.cpp	Mon Mar 16 02:43:19 2015 +0000
+++ b/core/inverter.cpp	Mon Mar 16 03:09:48 2015 +0000
@@ -20,21 +20,10 @@
     SetDtcB(0);
     SetDtcC(0);
     
-    TIM2->CR1 &= ~(TIM_CR1_CEN); //disable tim2
-    //TIM2->CR1 |= TIM_CR1_CMS;  //set bits 5 and 6 of the CR1 to 1.  (TIM_CR1_CMS == 96)
-    TIM2->CR1 |= (1 << 5);  //by only enabling bit 5, "Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) 
-                      //are set only when the counter is counting down"  (p.342)
-    //These lines do nothing so they are commented out.  They should do something..
-    /*
-    TIM2->CR1 &= ~(1 << 6);
-    //hmm, not sure what's going on there.  It's set to only trigger when counting down, however it triggers at both underflow and overflow
+    TIM2->CR1 &= ~(TIM_CR1_CEN);
+    TIM2->CR1 |= TIM_CR1_CMS;
+    TIM2->CR1 |= TIM_CR1_CEN;
     
-    TIM2->CR1 &= ~(1 << 1);  //Set bit 1 (update disable) to 0.  we want the timer overflow to trigger an interrupt
-    //TIM2->CR1 |= (1 << 2);  //Set bit 2 (update request source) to 1.  Only want under/overflow to trigger an interrupt.
-    */
-    
-    TIM2->DIER |= 1; // set bit 0 equal to 1.  this enables interrupts 
-    TIM2->CR1 |= TIM_CR1_CEN;  //enable tim2
     Enable();
 }