Bayley Wang / Mbed 2 deprecated eeprom_emulation_446

flash writing code for 446re

Dependencies:   mbed

FlashWriter/stm32f4xx_flash.c@3:16b0692f3ed3, 2017-02-28 (annotated)

Committer:
bwang
Date:
Tue Feb 28 22:31:12 2017 +0000
Revision:
3:16b0692f3ed3
Parent:
2:11238235cb62 
forgot an include

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bwang 0:2dfd987fe78d 1 /**
bwang 0:2dfd987fe78d 2 ******************************************************************************
bwang 0:2dfd987fe78d 3 * @file stm32f4xx_flash.c
bwang 0:2dfd987fe78d 4 * @author MCD Application Team
bwang 0:2dfd987fe78d 5 * @version V1.7.1
bwang 0:2dfd987fe78d 6 * @date 20-May-2016
bwang 0:2dfd987fe78d 7 * @brief This file provides firmware functions to manage the following
bwang 0:2dfd987fe78d 8 * functionalities of the FLASH peripheral:
bwang 0:2dfd987fe78d 9 * + FLASH Interface configuration
bwang 0:2dfd987fe78d 10 * + FLASH Memory Programming
bwang 0:2dfd987fe78d 11 * + Option Bytes Programming
bwang 0:2dfd987fe78d 12 * + Interrupts and flags management
bwang 0:2dfd987fe78d 13 *
bwang 0:2dfd987fe78d 14 @verbatim
bwang 0:2dfd987fe78d 15 ===============================================================================
bwang 0:2dfd987fe78d 16 ##### How to use this driver #####
bwang 0:2dfd987fe78d 17 ===============================================================================
bwang 0:2dfd987fe78d 18 [..]
bwang 0:2dfd987fe78d 19 This driver provides functions to configure and program the FLASH memory
bwang 0:2dfd987fe78d 20 of all STM32F4xx devices. These functions are split in 4 groups:
bwang 0:2dfd987fe78d 21
bwang 0:2dfd987fe78d 22 (#) FLASH Interface configuration functions: this group includes the
bwang 0:2dfd987fe78d 23 management of the following features:
bwang 0:2dfd987fe78d 24 (++) Set the latency
bwang 0:2dfd987fe78d 25 (++) Enable/Disable the prefetch buffer
bwang 0:2dfd987fe78d 26 (++) Enable/Disable the Instruction cache and the Data cache
bwang 0:2dfd987fe78d 27 (++) Reset the Instruction cache and the Data cache
bwang 0:2dfd987fe78d 28
bwang 0:2dfd987fe78d 29 (#) FLASH Memory Programming functions: this group includes all needed
bwang 0:2dfd987fe78d 30 functions to erase and program the main memory:
bwang 0:2dfd987fe78d 31 (++) Lock and Unlock the FLASH interface
bwang 0:2dfd987fe78d 32 (++) Erase function: Erase sector, erase all sectors
bwang 0:2dfd987fe78d 33 (++) Program functions: byte, half word, word and double word
bwang 0:2dfd987fe78d 34
bwang 0:2dfd987fe78d 35 (#) Option Bytes Programming functions: this group includes all needed
bwang 0:2dfd987fe78d 36 functions to manage the Option Bytes:
bwang 0:2dfd987fe78d 37 (++) Set/Reset the write protection
bwang 0:2dfd987fe78d 38 (++) Set the Read protection Level
bwang 0:2dfd987fe78d 39 (++) Set the BOR level
bwang 0:2dfd987fe78d 40 (++) Program the user Option Bytes
bwang 0:2dfd987fe78d 41 (++) Launch the Option Bytes loader
bwang 0:2dfd987fe78d 42
bwang 0:2dfd987fe78d 43 (#) Interrupts and flags management functions: this group
bwang 0:2dfd987fe78d 44 includes all needed functions to:
bwang 0:2dfd987fe78d 45 (++) Enable/Disable the FLASH interrupt sources
bwang 0:2dfd987fe78d 46 (++) Get flags status
bwang 0:2dfd987fe78d 47 (++) Clear flags
bwang 0:2dfd987fe78d 48 (++) Get FLASH operation status
bwang 0:2dfd987fe78d 49 (++) Wait for last FLASH operation
bwang 0:2dfd987fe78d 50 @endverbatim
bwang 0:2dfd987fe78d 51 ******************************************************************************
bwang 0:2dfd987fe78d 52 * @attention
bwang 0:2dfd987fe78d 53 *
bwang 0:2dfd987fe78d 54 * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
bwang 0:2dfd987fe78d 55 *
bwang 0:2dfd987fe78d 56 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
bwang 0:2dfd987fe78d 57 * You may not use this file except in compliance with the License.
bwang 0:2dfd987fe78d 58 * You may obtain a copy of the License at:
bwang 0:2dfd987fe78d 59 *
bwang 0:2dfd987fe78d 60 * http://www.st.com/software_license_agreement_liberty_v2
bwang 0:2dfd987fe78d 61 *
bwang 0:2dfd987fe78d 62 * Unless required by applicable law or agreed to in writing, software
bwang 0:2dfd987fe78d 63 * distributed under the License is distributed on an "AS IS" BASIS,
bwang 0:2dfd987fe78d 64 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bwang 0:2dfd987fe78d 65 * See the License for the specific language governing permissions and
bwang 0:2dfd987fe78d 66 * limitations under the License.
bwang 0:2dfd987fe78d 67 *
bwang 0:2dfd987fe78d 68 ******************************************************************************
bwang 0:2dfd987fe78d 69 */
bwang 0:2dfd987fe78d 70
bwang 0:2dfd987fe78d 71 /* Includes ------------------------------------------------------------------*/
bwang 0:2dfd987fe78d 72 #include "stm32f4xx_flash.h"
bwang 0:2dfd987fe78d 73
bwang 0:2dfd987fe78d 74 /** @addtogroup STM32F4xx_StdPeriph_Driver
bwang 0:2dfd987fe78d 75 * @{
bwang 0:2dfd987fe78d 76 */
bwang 0:2dfd987fe78d 77
bwang 0:2dfd987fe78d 78 /** @defgroup FLASH
bwang 0:2dfd987fe78d 79 * @brief FLASH driver modules
bwang 0:2dfd987fe78d 80 * @{
bwang 0:2dfd987fe78d 81 */
bwang 0:2dfd987fe78d 82
bwang 0:2dfd987fe78d 83 /* Private typedef -----------------------------------------------------------*/
bwang 0:2dfd987fe78d 84 /* Private define ------------------------------------------------------------*/
bwang 0:2dfd987fe78d 85 #define SECTOR_MASK ((uint32_t)0xFFFFFF07)
bwang 0:2dfd987fe78d 86
bwang 0:2dfd987fe78d 87 /* Private macro -------------------------------------------------------------*/
bwang 0:2dfd987fe78d 88 /* Private variables ---------------------------------------------------------*/
bwang 0:2dfd987fe78d 89 /* Private function prototypes -----------------------------------------------*/
bwang 0:2dfd987fe78d 90 /* Private functions ---------------------------------------------------------*/
bwang 0:2dfd987fe78d 91
bwang 0:2dfd987fe78d 92 /** @defgroup FLASH_Private_Functions
bwang 0:2dfd987fe78d 93 * @{
bwang 0:2dfd987fe78d 94 */
bwang 0:2dfd987fe78d 95
bwang 0:2dfd987fe78d 96 /** @defgroup FLASH_Group1 FLASH Interface configuration functions
bwang 0:2dfd987fe78d 97 * @brief FLASH Interface configuration functions
bwang 0:2dfd987fe78d 98 *
bwang 0:2dfd987fe78d 99
bwang 0:2dfd987fe78d 100 @verbatim
bwang 0:2dfd987fe78d 101 ===============================================================================
bwang 0:2dfd987fe78d 102 ##### FLASH Interface configuration functions #####
bwang 0:2dfd987fe78d 103 ===============================================================================
bwang 0:2dfd987fe78d 104 [..]
bwang 0:2dfd987fe78d 105 This group includes the following functions:
bwang 0:2dfd987fe78d 106 (+) void FLASH_SetLatency(uint32_t FLASH_Latency)
bwang 0:2dfd987fe78d 107 To correctly read data from FLASH memory, the number of wait states (LATENCY)
bwang 0:2dfd987fe78d 108 must be correctly programmed according to the frequency of the CPU clock
bwang 0:2dfd987fe78d 109 (HCLK) and the supply voltage of the device.
bwang 0:2dfd987fe78d 110 [..]
bwang 0:2dfd987fe78d 111 For STM32F405xx/07xx and STM32F415xx/17xx devices
bwang 0:2dfd987fe78d 112 +-------------------------------------------------------------------------------------+
bwang 0:2dfd987fe78d 113 | Latency | HCLK clock frequency (MHz) |
bwang 0:2dfd987fe78d 114 | |---------------------------------------------------------------------|
bwang 0:2dfd987fe78d 115 | | voltage range | voltage range | voltage range | voltage range |
bwang 0:2dfd987fe78d 116 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
bwang 0:2dfd987fe78d 117 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 118 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
bwang 0:2dfd987fe78d 119 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 120 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
bwang 0:2dfd987fe78d 121 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 122 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
bwang 0:2dfd987fe78d 123 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 124 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
bwang 0:2dfd987fe78d 125 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 126 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
bwang 0:2dfd987fe78d 127 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 128 |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
bwang 0:2dfd987fe78d 129 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 130 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
bwang 0:2dfd987fe78d 131 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 132 |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
bwang 0:2dfd987fe78d 133 +---------------|----------------|----------------|-----------------|-----------------+
bwang 0:2dfd987fe78d 134
bwang 0:2dfd987fe78d 135 [..]
bwang 0:2dfd987fe78d 136 For STM32F42xxx/43xxx devices
bwang 0:2dfd987fe78d 137 +-------------------------------------------------------------------------------------+
bwang 0:2dfd987fe78d 138 | Latency | HCLK clock frequency (MHz) |
bwang 0:2dfd987fe78d 139 | |---------------------------------------------------------------------|
bwang 0:2dfd987fe78d 140 | | voltage range | voltage range | voltage range | voltage range |
bwang 0:2dfd987fe78d 141 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
bwang 0:2dfd987fe78d 142 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 143 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
bwang 0:2dfd987fe78d 144 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 145 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
bwang 0:2dfd987fe78d 146 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 147 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
bwang 0:2dfd987fe78d 148 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 149 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
bwang 0:2dfd987fe78d 150 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 151 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
bwang 0:2dfd987fe78d 152 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 153 |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
bwang 0:2dfd987fe78d 154 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 155 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
bwang 0:2dfd987fe78d 156 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 157 |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
bwang 0:2dfd987fe78d 158 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 159 |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
bwang 0:2dfd987fe78d 160 +-------------------------------------------------------------------------------------+
bwang 0:2dfd987fe78d 161
bwang 0:2dfd987fe78d 162 [..]
bwang 0:2dfd987fe78d 163 For STM32F401x devices
bwang 0:2dfd987fe78d 164 +-------------------------------------------------------------------------------------+
bwang 0:2dfd987fe78d 165 | Latency | HCLK clock frequency (MHz) |
bwang 0:2dfd987fe78d 166 | |---------------------------------------------------------------------|
bwang 0:2dfd987fe78d 167 | | voltage range | voltage range | voltage range | voltage range |
bwang 0:2dfd987fe78d 168 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
bwang 0:2dfd987fe78d 169 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 170 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
bwang 0:2dfd987fe78d 171 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 172 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
bwang 0:2dfd987fe78d 173 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 174 |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
bwang 0:2dfd987fe78d 175 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 176 |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
bwang 0:2dfd987fe78d 177 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 178 |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
bwang 0:2dfd987fe78d 179 +-------------------------------------------------------------------------------------+
bwang 0:2dfd987fe78d 180
bwang 0:2dfd987fe78d 181 [..]
bwang 0:2dfd987fe78d 182 For STM32F410xx/STM32F411xE devices
bwang 0:2dfd987fe78d 183 +-------------------------------------------------------------------------------------+
bwang 0:2dfd987fe78d 184 | Latency | HCLK clock frequency (MHz) |
bwang 0:2dfd987fe78d 185 | |---------------------------------------------------------------------|
bwang 0:2dfd987fe78d 186 | | voltage range | voltage range | voltage range | voltage range |
bwang 0:2dfd987fe78d 187 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
bwang 0:2dfd987fe78d 188 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 189 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
bwang 0:2dfd987fe78d 190 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 191 |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
bwang 0:2dfd987fe78d 192 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 193 |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
bwang 0:2dfd987fe78d 194 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 195 |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
bwang 0:2dfd987fe78d 196 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 197 |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
bwang 0:2dfd987fe78d 198 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 199 |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
bwang 0:2dfd987fe78d 200 |---------------|----------------|----------------|-----------------|-----------------|
bwang 0:2dfd987fe78d 201 |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
bwang 0:2dfd987fe78d 202 +-------------------------------------------------------------------------------------+
bwang 0:2dfd987fe78d 203
bwang 0:2dfd987fe78d 204 [..]
bwang 0:2dfd987fe78d 205 +-------------------------------------------------------------------------------------------------------------------+
bwang 0:2dfd987fe78d 206 | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
bwang 0:2dfd987fe78d 207 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
bwang 0:2dfd987fe78d 208 |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
bwang 0:2dfd987fe78d 209 |Max Parallelism| x32 | x16 | x8 | x64 |
bwang 0:2dfd987fe78d 210 |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
bwang 0:2dfd987fe78d 211 |PSIZE[1:0] | 10 | 01 | 00 | 11 |
bwang 0:2dfd987fe78d 212 +-------------------------------------------------------------------------------------------------------------------+
bwang 0:2dfd987fe78d 213
bwang 0:2dfd987fe78d 214 -@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
bwang 0:2dfd987fe78d 215 (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz.
bwang 0:2dfd987fe78d 216 (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz.
bwang 0:2dfd987fe78d 217 [..]
bwang 0:2dfd987fe78d 218 On STM32F42xxx/43xxx devices:
bwang 0:2dfd987fe78d 219 (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
bwang 0:2dfd987fe78d 220 (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
bwang 0:2dfd987fe78d 221 (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON.
bwang 0:2dfd987fe78d 222 [..]
bwang 0:2dfd987fe78d 223 On STM32F401x devices:
bwang 0:2dfd987fe78d 224 (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
bwang 0:2dfd987fe78d 225 (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
bwang 0:2dfd987fe78d 226 [..]
bwang 0:2dfd987fe78d 227 On STM32F410xx/STM32F411xE devices:
bwang 0:2dfd987fe78d 228 (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
bwang 0:2dfd987fe78d 229 (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
bwang 0:2dfd987fe78d 230 (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
bwang 0:2dfd987fe78d 231
bwang 0:2dfd987fe78d 232 For more details please refer product DataSheet
bwang 0:2dfd987fe78d 233 You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
bwang 0:2dfd987fe78d 234
bwang 0:2dfd987fe78d 235 (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
bwang 0:2dfd987fe78d 236 (+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
bwang 0:2dfd987fe78d 237 (+) void FLASH_DataCacheCmd(FunctionalState NewState)
bwang 0:2dfd987fe78d 238 (+) void FLASH_InstructionCacheReset(void)
bwang 0:2dfd987fe78d 239 (+) void FLASH_DataCacheReset(void)
bwang 0:2dfd987fe78d 240
bwang 0:2dfd987fe78d 241 [..]
bwang 0:2dfd987fe78d 242 The unlock sequence is not needed for these functions.
bwang 0:2dfd987fe78d 243
bwang 0:2dfd987fe78d 244 @endverbatim
bwang 0:2dfd987fe78d 245 * @{
bwang 0:2dfd987fe78d 246 */
bwang 0:2dfd987fe78d 247
bwang 0:2dfd987fe78d 248 /**
bwang 0:2dfd987fe78d 249 * @brief Sets the code latency value.
bwang 0:2dfd987fe78d 250 * @param FLASH_Latency: specifies the FLASH Latency value.
bwang 0:2dfd987fe78d 251 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 252 * @arg FLASH_Latency_0: FLASH Zero Latency cycle
bwang 0:2dfd987fe78d 253 * @arg FLASH_Latency_1: FLASH One Latency cycle
bwang 0:2dfd987fe78d 254 * @arg FLASH_Latency_2: FLASH Two Latency cycles
bwang 0:2dfd987fe78d 255 * @arg FLASH_Latency_3: FLASH Three Latency cycles
bwang 0:2dfd987fe78d 256 * @arg FLASH_Latency_4: FLASH Four Latency cycles
bwang 0:2dfd987fe78d 257 * @arg FLASH_Latency_5: FLASH Five Latency cycles
bwang 0:2dfd987fe78d 258 * @arg FLASH_Latency_6: FLASH Six Latency cycles
bwang 0:2dfd987fe78d 259 * @arg FLASH_Latency_7: FLASH Seven Latency cycles
bwang 0:2dfd987fe78d 260 * @arg FLASH_Latency_8: FLASH Eight Latency cycles
bwang 0:2dfd987fe78d 261 * @arg FLASH_Latency_9: FLASH Nine Latency cycles
bwang 0:2dfd987fe78d 262 * @arg FLASH_Latency_10: FLASH Teen Latency cycles
bwang 0:2dfd987fe78d 263 * @arg FLASH_Latency_11: FLASH Eleven Latency cycles
bwang 0:2dfd987fe78d 264 * @arg FLASH_Latency_12: FLASH Twelve Latency cycles
bwang 0:2dfd987fe78d 265 * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles
bwang 0:2dfd987fe78d 266 * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
bwang 0:2dfd987fe78d 267 * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
bwang 0:2dfd987fe78d 268 *
bwang 0:2dfd987fe78d 269 * @note For STM32F405xx/407xx, STM32F415xx/417xx, STM32F401xx/411xE and STM32F412xG devices
bwang 0:2dfd987fe78d 270 * this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
bwang 0:2dfd987fe78d 271 *
bwang 0:2dfd987fe78d 272 * @note For STM32F42xxx/43xxx devices this parameter can be a value between
bwang 0:2dfd987fe78d 273 * FLASH_Latency_0 and FLASH_Latency_15.
bwang 0:2dfd987fe78d 274 *
bwang 0:2dfd987fe78d 275 * @retval None
bwang 0:2dfd987fe78d 276 */
bwang 0:2dfd987fe78d 277 void FLASH_SetLatency(uint32_t FLASH_Latency)
bwang 0:2dfd987fe78d 278 {
bwang 0:2dfd987fe78d 279 /* Check the parameters */
bwang 0:2dfd987fe78d 280 assert_param(IS_FLASH_LATENCY(FLASH_Latency));
bwang 0:2dfd987fe78d 281
bwang 0:2dfd987fe78d 282 /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
bwang 0:2dfd987fe78d 283 *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
bwang 0:2dfd987fe78d 284 }
bwang 0:2dfd987fe78d 285
bwang 0:2dfd987fe78d 286 /**
bwang 0:2dfd987fe78d 287 * @brief Enables or disables the Prefetch Buffer.
bwang 0:2dfd987fe78d 288 * @param NewState: new state of the Prefetch Buffer.
bwang 0:2dfd987fe78d 289 * This parameter can be: ENABLE or DISABLE.
bwang 0:2dfd987fe78d 290 * @retval None
bwang 0:2dfd987fe78d 291 */
bwang 0:2dfd987fe78d 292 void FLASH_PrefetchBufferCmd(FunctionalState NewState)
bwang 0:2dfd987fe78d 293 {
bwang 0:2dfd987fe78d 294 /* Check the parameters */
bwang 0:2dfd987fe78d 295 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 0:2dfd987fe78d 296
bwang 0:2dfd987fe78d 297 /* Enable or disable the Prefetch Buffer */
bwang 0:2dfd987fe78d 298 if(NewState != DISABLE)
bwang 0:2dfd987fe78d 299 {
bwang 0:2dfd987fe78d 300 FLASH->ACR |= FLASH_ACR_PRFTEN;
bwang 0:2dfd987fe78d 301 }
bwang 0:2dfd987fe78d 302 else
bwang 0:2dfd987fe78d 303 {
bwang 0:2dfd987fe78d 304 FLASH->ACR &= (~FLASH_ACR_PRFTEN);
bwang 0:2dfd987fe78d 305 }
bwang 0:2dfd987fe78d 306 }
bwang 0:2dfd987fe78d 307
bwang 0:2dfd987fe78d 308 /**
bwang 0:2dfd987fe78d 309 * @brief Enables or disables the Instruction Cache feature.
bwang 0:2dfd987fe78d 310 * @param NewState: new state of the Instruction Cache.
bwang 0:2dfd987fe78d 311 * This parameter can be: ENABLE or DISABLE.
bwang 0:2dfd987fe78d 312 * @retval None
bwang 0:2dfd987fe78d 313 */
bwang 0:2dfd987fe78d 314 void FLASH_InstructionCacheCmd(FunctionalState NewState)
bwang 0:2dfd987fe78d 315 {
bwang 0:2dfd987fe78d 316 /* Check the parameters */
bwang 0:2dfd987fe78d 317 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 0:2dfd987fe78d 318
bwang 0:2dfd987fe78d 319 if(NewState != DISABLE)
bwang 0:2dfd987fe78d 320 {
bwang 0:2dfd987fe78d 321 FLASH->ACR |= FLASH_ACR_ICEN;
bwang 0:2dfd987fe78d 322 }
bwang 0:2dfd987fe78d 323 else
bwang 0:2dfd987fe78d 324 {
bwang 0:2dfd987fe78d 325 FLASH->ACR &= (~FLASH_ACR_ICEN);
bwang 0:2dfd987fe78d 326 }
bwang 0:2dfd987fe78d 327 }
bwang 0:2dfd987fe78d 328
bwang 0:2dfd987fe78d 329 /**
bwang 0:2dfd987fe78d 330 * @brief Enables or disables the Data Cache feature.
bwang 0:2dfd987fe78d 331 * @param NewState: new state of the Data Cache.
bwang 0:2dfd987fe78d 332 * This parameter can be: ENABLE or DISABLE.
bwang 0:2dfd987fe78d 333 * @retval None
bwang 0:2dfd987fe78d 334 */
bwang 0:2dfd987fe78d 335 void FLASH_DataCacheCmd(FunctionalState NewState)
bwang 0:2dfd987fe78d 336 {
bwang 0:2dfd987fe78d 337 /* Check the parameters */
bwang 0:2dfd987fe78d 338 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 0:2dfd987fe78d 339
bwang 0:2dfd987fe78d 340 if(NewState != DISABLE)
bwang 0:2dfd987fe78d 341 {
bwang 0:2dfd987fe78d 342 FLASH->ACR |= FLASH_ACR_DCEN;
bwang 0:2dfd987fe78d 343 }
bwang 0:2dfd987fe78d 344 else
bwang 0:2dfd987fe78d 345 {
bwang 0:2dfd987fe78d 346 FLASH->ACR &= (~FLASH_ACR_DCEN);
bwang 0:2dfd987fe78d 347 }
bwang 0:2dfd987fe78d 348 }
bwang 0:2dfd987fe78d 349
bwang 0:2dfd987fe78d 350 /**
bwang 0:2dfd987fe78d 351 * @brief Resets the Instruction Cache.
bwang 0:2dfd987fe78d 352 * @note This function must be used only when the Instruction Cache is disabled.
bwang 0:2dfd987fe78d 353 * @param None
bwang 0:2dfd987fe78d 354 * @retval None
bwang 0:2dfd987fe78d 355 */
bwang 0:2dfd987fe78d 356 void FLASH_InstructionCacheReset(void)
bwang 0:2dfd987fe78d 357 {
bwang 0:2dfd987fe78d 358 FLASH->ACR |= FLASH_ACR_ICRST;
bwang 0:2dfd987fe78d 359 }
bwang 0:2dfd987fe78d 360
bwang 0:2dfd987fe78d 361 /**
bwang 0:2dfd987fe78d 362 * @brief Resets the Data Cache.
bwang 0:2dfd987fe78d 363 * @note This function must be used only when the Data Cache is disabled.
bwang 0:2dfd987fe78d 364 * @param None
bwang 0:2dfd987fe78d 365 * @retval None
bwang 0:2dfd987fe78d 366 */
bwang 0:2dfd987fe78d 367 void FLASH_DataCacheReset(void)
bwang 0:2dfd987fe78d 368 {
bwang 0:2dfd987fe78d 369 FLASH->ACR |= FLASH_ACR_DCRST;
bwang 0:2dfd987fe78d 370 }
bwang 0:2dfd987fe78d 371
bwang 0:2dfd987fe78d 372 /**
bwang 0:2dfd987fe78d 373 * @}
bwang 0:2dfd987fe78d 374 */
bwang 0:2dfd987fe78d 375
bwang 0:2dfd987fe78d 376 /** @defgroup FLASH_Group2 FLASH Memory Programming functions
bwang 0:2dfd987fe78d 377 * @brief FLASH Memory Programming functions
bwang 0:2dfd987fe78d 378 *
bwang 0:2dfd987fe78d 379 @verbatim
bwang 0:2dfd987fe78d 380 ===============================================================================
bwang 0:2dfd987fe78d 381 ##### FLASH Memory Programming functions #####
bwang 0:2dfd987fe78d 382 ===============================================================================
bwang 0:2dfd987fe78d 383 [..]
bwang 0:2dfd987fe78d 384 This group includes the following functions:
bwang 0:2dfd987fe78d 385 (+) void FLASH_Unlock(void)
bwang 0:2dfd987fe78d 386 (+) void FLASH_Lock(void)
bwang 0:2dfd987fe78d 387 (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
bwang 0:2dfd987fe78d 388 (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
bwang 0:2dfd987fe78d 389 (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
bwang 0:2dfd987fe78d 390 (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
bwang 0:2dfd987fe78d 391 (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
bwang 0:2dfd987fe78d 392 (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
bwang 0:2dfd987fe78d 393 The following functions can be used only for STM32F42xxx/43xxx devices.
bwang 0:2dfd987fe78d 394 (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
bwang 0:2dfd987fe78d 395 (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
bwang 0:2dfd987fe78d 396 [..]
bwang 0:2dfd987fe78d 397 Any operation of erase or program should follow these steps:
bwang 0:2dfd987fe78d 398 (#) Call the FLASH_Unlock() function to enable the FLASH control register access
bwang 0:2dfd987fe78d 399
bwang 0:2dfd987fe78d 400 (#) Call the desired function to erase sector(s) or program data
bwang 0:2dfd987fe78d 401
bwang 0:2dfd987fe78d 402 (#) Call the FLASH_Lock() function to disable the FLASH control register access
bwang 0:2dfd987fe78d 403 (recommended to protect the FLASH memory against possible unwanted operation)
bwang 0:2dfd987fe78d 404
bwang 0:2dfd987fe78d 405 @endverbatim
bwang 0:2dfd987fe78d 406 * @{
bwang 0:2dfd987fe78d 407 */
bwang 0:2dfd987fe78d 408
bwang 0:2dfd987fe78d 409 /**
bwang 0:2dfd987fe78d 410 * @brief Unlocks the FLASH control register access
bwang 0:2dfd987fe78d 411 * @param None
bwang 0:2dfd987fe78d 412 * @retval None
bwang 0:2dfd987fe78d 413 */
bwang 0:2dfd987fe78d 414 void FLASH_Unlock(void)
bwang 0:2dfd987fe78d 415 {
bwang 0:2dfd987fe78d 416 if((FLASH->CR & FLASH_CR_LOCK) != RESET)
bwang 0:2dfd987fe78d 417 {
bwang 0:2dfd987fe78d 418 /* Authorize the FLASH Registers access */
bwang 0:2dfd987fe78d 419 FLASH->KEYR = FLASH_KEY1;
bwang 0:2dfd987fe78d 420 FLASH->KEYR = FLASH_KEY2;
bwang 0:2dfd987fe78d 421 }
bwang 0:2dfd987fe78d 422 }
bwang 0:2dfd987fe78d 423
bwang 0:2dfd987fe78d 424 /**
bwang 0:2dfd987fe78d 425 * @brief Locks the FLASH control register access
bwang 0:2dfd987fe78d 426 * @param None
bwang 0:2dfd987fe78d 427 * @retval None
bwang 0:2dfd987fe78d 428 */
bwang 0:2dfd987fe78d 429 void FLASH_Lock(void)
bwang 0:2dfd987fe78d 430 {
bwang 0:2dfd987fe78d 431 /* Set the LOCK Bit to lock the FLASH Registers access */
bwang 0:2dfd987fe78d 432 FLASH->CR |= FLASH_CR_LOCK;
bwang 0:2dfd987fe78d 433 }
bwang 0:2dfd987fe78d 434
bwang 0:2dfd987fe78d 435 /**
bwang 0:2dfd987fe78d 436 * @brief Erases a specified FLASH Sector.
bwang 0:2dfd987fe78d 437 *
bwang 0:2dfd987fe78d 438 * @note If an erase and a program operations are requested simultaneously,
bwang 0:2dfd987fe78d 439 * the erase operation is performed before the program one.
bwang 0:2dfd987fe78d 440 *
bwang 0:2dfd987fe78d 441 * @param FLASH_Sector: The Sector number to be erased.
bwang 0:2dfd987fe78d 442 *
bwang 0:2dfd987fe78d 443 * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can
bwang 0:2dfd987fe78d 444 * be a value between FLASH_Sector_0 and FLASH_Sector_11.
bwang 0:2dfd987fe78d 445 *
bwang 0:2dfd987fe78d 446 * For STM32F42xxx/43xxx devices this parameter can be a value between
bwang 0:2dfd987fe78d 447 * FLASH_Sector_0 and FLASH_Sector_23.
bwang 0:2dfd987fe78d 448 *
bwang 0:2dfd987fe78d 449 * For STM32F401xx devices this parameter can be a value between
bwang 0:2dfd987fe78d 450 * FLASH_Sector_0 and FLASH_Sector_5.
bwang 0:2dfd987fe78d 451 *
bwang 0:2dfd987fe78d 452 * For STM32F411xE and STM32F412xG devices this parameter can be a value between
bwang 0:2dfd987fe78d 453 * FLASH_Sector_0 and FLASH_Sector_7.
bwang 0:2dfd987fe78d 454 *
bwang 0:2dfd987fe78d 455 * For STM32F410xx devices this parameter can be a value between
bwang 0:2dfd987fe78d 456 * FLASH_Sector_0 and FLASH_Sector_4.
bwang 0:2dfd987fe78d 457 *
bwang 0:2dfd987fe78d 458 * @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang 0:2dfd987fe78d 459 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 460 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang 0:2dfd987fe78d 461 * the operation will be done by byte (8-bit)
bwang 0:2dfd987fe78d 462 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang 0:2dfd987fe78d 463 * the operation will be done by half word (16-bit)
bwang 0:2dfd987fe78d 464 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang 0:2dfd987fe78d 465 * the operation will be done by word (32-bit)
bwang 0:2dfd987fe78d 466 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang 0:2dfd987fe78d 467 * the operation will be done by double word (64-bit)
bwang 0:2dfd987fe78d 468 *
bwang 0:2dfd987fe78d 469 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 470 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 471 */
bwang 0:2dfd987fe78d 472 FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
bwang 0:2dfd987fe78d 473 {
bwang 0:2dfd987fe78d 474 uint32_t tmp_psize = 0x0;
bwang 0:2dfd987fe78d 475 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 476
bwang 0:2dfd987fe78d 477 /* Check the parameters */
bwang 0:2dfd987fe78d 478 assert_param(IS_FLASH_SECTOR(FLASH_Sector));
bwang 0:2dfd987fe78d 479 assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang 0:2dfd987fe78d 480
bwang 0:2dfd987fe78d 481 if(VoltageRange == VoltageRange_1)
bwang 0:2dfd987fe78d 482 {
bwang 0:2dfd987fe78d 483 tmp_psize = FLASH_PSIZE_BYTE;
bwang 0:2dfd987fe78d 484 }
bwang 0:2dfd987fe78d 485 else if(VoltageRange == VoltageRange_2)
bwang 0:2dfd987fe78d 486 {
bwang 0:2dfd987fe78d 487 tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang 0:2dfd987fe78d 488 }
bwang 0:2dfd987fe78d 489 else if(VoltageRange == VoltageRange_3)
bwang 0:2dfd987fe78d 490 {
bwang 0:2dfd987fe78d 491 tmp_psize = FLASH_PSIZE_WORD;
bwang 0:2dfd987fe78d 492 }
bwang 0:2dfd987fe78d 493 else
bwang 0:2dfd987fe78d 494 {
bwang 0:2dfd987fe78d 495 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang 0:2dfd987fe78d 496 }
bwang 0:2dfd987fe78d 497 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 498 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 499
bwang 0:2dfd987fe78d 500 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 501 {
bwang 0:2dfd987fe78d 502 /* if the previous operation is completed, proceed to erase the sector */
bwang 0:2dfd987fe78d 503 FLASH->CR &= CR_PSIZE_MASK;
bwang 0:2dfd987fe78d 504 FLASH->CR |= tmp_psize;
bwang 0:2dfd987fe78d 505 FLASH->CR &= SECTOR_MASK;
bwang 0:2dfd987fe78d 506 FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
bwang 0:2dfd987fe78d 507 FLASH->CR |= FLASH_CR_STRT;
bwang 0:2dfd987fe78d 508
bwang 0:2dfd987fe78d 509 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 510 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 511
bwang 0:2dfd987fe78d 512 /* if the erase operation is completed, disable the SER Bit */
bwang 0:2dfd987fe78d 513 FLASH->CR &= (~FLASH_CR_SER);
bwang 0:2dfd987fe78d 514 FLASH->CR &= SECTOR_MASK;
bwang 0:2dfd987fe78d 515 }
bwang 0:2dfd987fe78d 516 /* Return the Erase Status */
bwang 0:2dfd987fe78d 517 return status;
bwang 0:2dfd987fe78d 518 }
bwang 0:2dfd987fe78d 519
bwang 0:2dfd987fe78d 520 /**
bwang 0:2dfd987fe78d 521 * @brief Erases all FLASH Sectors.
bwang 0:2dfd987fe78d 522 *
bwang 0:2dfd987fe78d 523 * @note If an erase and a program operations are requested simultaneously,
bwang 0:2dfd987fe78d 524 * the erase operation is performed before the program one.
bwang 0:2dfd987fe78d 525 *
bwang 0:2dfd987fe78d 526 * @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang 0:2dfd987fe78d 527 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 528 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang 0:2dfd987fe78d 529 * the operation will be done by byte (8-bit)
bwang 0:2dfd987fe78d 530 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang 0:2dfd987fe78d 531 * the operation will be done by half word (16-bit)
bwang 0:2dfd987fe78d 532 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang 0:2dfd987fe78d 533 * the operation will be done by word (32-bit)
bwang 0:2dfd987fe78d 534 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang 0:2dfd987fe78d 535 * the operation will be done by double word (64-bit)
bwang 0:2dfd987fe78d 536 *
bwang 0:2dfd987fe78d 537 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 538 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 539 */
bwang 0:2dfd987fe78d 540 FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
bwang 0:2dfd987fe78d 541 {
bwang 0:2dfd987fe78d 542 uint32_t tmp_psize = 0x0;
bwang 0:2dfd987fe78d 543 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 544
bwang 0:2dfd987fe78d 545 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 546 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 547 assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang 0:2dfd987fe78d 548
bwang 0:2dfd987fe78d 549 if(VoltageRange == VoltageRange_1)
bwang 0:2dfd987fe78d 550 {
bwang 0:2dfd987fe78d 551 tmp_psize = FLASH_PSIZE_BYTE;
bwang 0:2dfd987fe78d 552 }
bwang 0:2dfd987fe78d 553 else if(VoltageRange == VoltageRange_2)
bwang 0:2dfd987fe78d 554 {
bwang 0:2dfd987fe78d 555 tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang 0:2dfd987fe78d 556 }
bwang 0:2dfd987fe78d 557 else if(VoltageRange == VoltageRange_3)
bwang 0:2dfd987fe78d 558 {
bwang 0:2dfd987fe78d 559 tmp_psize = FLASH_PSIZE_WORD;
bwang 0:2dfd987fe78d 560 }
bwang 0:2dfd987fe78d 561 else
bwang 0:2dfd987fe78d 562 {
bwang 0:2dfd987fe78d 563 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang 0:2dfd987fe78d 564 }
bwang 0:2dfd987fe78d 565 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 566 {
bwang 0:2dfd987fe78d 567 /* if the previous operation is completed, proceed to erase all sectors */
bwang 0:2dfd987fe78d 568 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
bwang 0:2dfd987fe78d 569 FLASH->CR &= CR_PSIZE_MASK;
bwang 0:2dfd987fe78d 570 FLASH->CR |= tmp_psize;
bwang 0:2dfd987fe78d 571 FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
bwang 0:2dfd987fe78d 572 FLASH->CR |= FLASH_CR_STRT;
bwang 0:2dfd987fe78d 573
bwang 0:2dfd987fe78d 574 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 575 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 576
bwang 0:2dfd987fe78d 577 /* if the erase operation is completed, disable the MER Bit */
bwang 0:2dfd987fe78d 578 FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
bwang 0:2dfd987fe78d 579 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
bwang 0:2dfd987fe78d 580
bwang 0:2dfd987fe78d 581 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F446xx)
bwang 0:2dfd987fe78d 582 FLASH->CR &= CR_PSIZE_MASK;
bwang 0:2dfd987fe78d 583 FLASH->CR |= tmp_psize;
bwang 0:2dfd987fe78d 584 FLASH->CR |= FLASH_CR_MER;
bwang 0:2dfd987fe78d 585 FLASH->CR |= FLASH_CR_STRT;
bwang 0:2dfd987fe78d 586
bwang 0:2dfd987fe78d 587 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 588 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 589
bwang 0:2dfd987fe78d 590 /* if the erase operation is completed, disable the MER Bit */
bwang 0:2dfd987fe78d 591 FLASH->CR &= (~FLASH_CR_MER);
bwang 0:2dfd987fe78d 592 #endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F446xx */
bwang 0:2dfd987fe78d 593
bwang 0:2dfd987fe78d 594 }
bwang 0:2dfd987fe78d 595 /* Return the Erase Status */
bwang 0:2dfd987fe78d 596 return status;
bwang 0:2dfd987fe78d 597 }
bwang 0:2dfd987fe78d 598
bwang 0:2dfd987fe78d 599 /**
bwang 0:2dfd987fe78d 600 * @brief Erases all FLASH Sectors in Bank 1.
bwang 0:2dfd987fe78d 601 *
bwang 0:2dfd987fe78d 602 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 0:2dfd987fe78d 603 *
bwang 0:2dfd987fe78d 604 * @note If an erase and a program operations are requested simultaneously,
bwang 0:2dfd987fe78d 605 * the erase operation is performed before the program one.
bwang 0:2dfd987fe78d 606 *
bwang 0:2dfd987fe78d 607 * @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang 0:2dfd987fe78d 608 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 609 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang 0:2dfd987fe78d 610 * the operation will be done by byte (8-bit)
bwang 0:2dfd987fe78d 611 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang 0:2dfd987fe78d 612 * the operation will be done by half word (16-bit)
bwang 0:2dfd987fe78d 613 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang 0:2dfd987fe78d 614 * the operation will be done by word (32-bit)
bwang 0:2dfd987fe78d 615 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang 0:2dfd987fe78d 616 * the operation will be done by double word (64-bit)
bwang 0:2dfd987fe78d 617 *
bwang 0:2dfd987fe78d 618 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 619 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 620 */
bwang 0:2dfd987fe78d 621 FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
bwang 0:2dfd987fe78d 622 {
bwang 0:2dfd987fe78d 623 uint32_t tmp_psize = 0x0;
bwang 0:2dfd987fe78d 624 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 625
bwang 0:2dfd987fe78d 626 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 627 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 628 assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang 0:2dfd987fe78d 629
bwang 0:2dfd987fe78d 630 if(VoltageRange == VoltageRange_1)
bwang 0:2dfd987fe78d 631 {
bwang 0:2dfd987fe78d 632 tmp_psize = FLASH_PSIZE_BYTE;
bwang 0:2dfd987fe78d 633 }
bwang 0:2dfd987fe78d 634 else if(VoltageRange == VoltageRange_2)
bwang 0:2dfd987fe78d 635 {
bwang 0:2dfd987fe78d 636 tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang 0:2dfd987fe78d 637 }
bwang 0:2dfd987fe78d 638 else if(VoltageRange == VoltageRange_3)
bwang 0:2dfd987fe78d 639 {
bwang 0:2dfd987fe78d 640 tmp_psize = FLASH_PSIZE_WORD;
bwang 0:2dfd987fe78d 641 }
bwang 0:2dfd987fe78d 642 else
bwang 0:2dfd987fe78d 643 {
bwang 0:2dfd987fe78d 644 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang 0:2dfd987fe78d 645 }
bwang 0:2dfd987fe78d 646 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 647 {
bwang 0:2dfd987fe78d 648 /* if the previous operation is completed, proceed to erase all sectors */
bwang 0:2dfd987fe78d 649 FLASH->CR &= CR_PSIZE_MASK;
bwang 0:2dfd987fe78d 650 FLASH->CR |= tmp_psize;
bwang 0:2dfd987fe78d 651 FLASH->CR |= FLASH_CR_MER1;
bwang 0:2dfd987fe78d 652 FLASH->CR |= FLASH_CR_STRT;
bwang 0:2dfd987fe78d 653
bwang 0:2dfd987fe78d 654 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 655 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 656
bwang 0:2dfd987fe78d 657 /* if the erase operation is completed, disable the MER Bit */
bwang 0:2dfd987fe78d 658 FLASH->CR &= (~FLASH_CR_MER1);
bwang 0:2dfd987fe78d 659
bwang 0:2dfd987fe78d 660 }
bwang 0:2dfd987fe78d 661 /* Return the Erase Status */
bwang 0:2dfd987fe78d 662 return status;
bwang 0:2dfd987fe78d 663 }
bwang 0:2dfd987fe78d 664
bwang 0:2dfd987fe78d 665
bwang 0:2dfd987fe78d 666 /**
bwang 0:2dfd987fe78d 667 * @brief Erases all FLASH Sectors in Bank 2.
bwang 0:2dfd987fe78d 668 *
bwang 0:2dfd987fe78d 669 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 0:2dfd987fe78d 670 *
bwang 0:2dfd987fe78d 671 * @note If an erase and a program operations are requested simultaneously,
bwang 0:2dfd987fe78d 672 * the erase operation is performed before the program one.
bwang 0:2dfd987fe78d 673 *
bwang 0:2dfd987fe78d 674 * @param VoltageRange: The device voltage range which defines the erase parallelism.
bwang 0:2dfd987fe78d 675 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 676 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
bwang 0:2dfd987fe78d 677 * the operation will be done by byte (8-bit)
bwang 0:2dfd987fe78d 678 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
bwang 0:2dfd987fe78d 679 * the operation will be done by half word (16-bit)
bwang 0:2dfd987fe78d 680 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
bwang 0:2dfd987fe78d 681 * the operation will be done by word (32-bit)
bwang 0:2dfd987fe78d 682 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
bwang 0:2dfd987fe78d 683 * the operation will be done by double word (64-bit)
bwang 0:2dfd987fe78d 684 *
bwang 0:2dfd987fe78d 685 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 686 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 687 */
bwang 0:2dfd987fe78d 688 FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
bwang 0:2dfd987fe78d 689 {
bwang 0:2dfd987fe78d 690 uint32_t tmp_psize = 0x0;
bwang 0:2dfd987fe78d 691 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 692
bwang 0:2dfd987fe78d 693 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 694 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 695 assert_param(IS_VOLTAGERANGE(VoltageRange));
bwang 0:2dfd987fe78d 696
bwang 0:2dfd987fe78d 697 if(VoltageRange == VoltageRange_1)
bwang 0:2dfd987fe78d 698 {
bwang 0:2dfd987fe78d 699 tmp_psize = FLASH_PSIZE_BYTE;
bwang 0:2dfd987fe78d 700 }
bwang 0:2dfd987fe78d 701 else if(VoltageRange == VoltageRange_2)
bwang 0:2dfd987fe78d 702 {
bwang 0:2dfd987fe78d 703 tmp_psize = FLASH_PSIZE_HALF_WORD;
bwang 0:2dfd987fe78d 704 }
bwang 0:2dfd987fe78d 705 else if(VoltageRange == VoltageRange_3)
bwang 0:2dfd987fe78d 706 {
bwang 0:2dfd987fe78d 707 tmp_psize = FLASH_PSIZE_WORD;
bwang 0:2dfd987fe78d 708 }
bwang 0:2dfd987fe78d 709 else
bwang 0:2dfd987fe78d 710 {
bwang 0:2dfd987fe78d 711 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
bwang 0:2dfd987fe78d 712 }
bwang 0:2dfd987fe78d 713 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 714 {
bwang 0:2dfd987fe78d 715 /* if the previous operation is completed, proceed to erase all sectors */
bwang 0:2dfd987fe78d 716 FLASH->CR &= CR_PSIZE_MASK;
bwang 0:2dfd987fe78d 717 FLASH->CR |= tmp_psize;
bwang 0:2dfd987fe78d 718 FLASH->CR |= FLASH_CR_MER2;
bwang 0:2dfd987fe78d 719 FLASH->CR |= FLASH_CR_STRT;
bwang 0:2dfd987fe78d 720
bwang 0:2dfd987fe78d 721 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 722 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 723
bwang 0:2dfd987fe78d 724 /* if the erase operation is completed, disable the MER Bit */
bwang 0:2dfd987fe78d 725 FLASH->CR &= (~FLASH_CR_MER2);
bwang 0:2dfd987fe78d 726
bwang 0:2dfd987fe78d 727 }
bwang 0:2dfd987fe78d 728 /* Return the Erase Status */
bwang 0:2dfd987fe78d 729 return status;
bwang 0:2dfd987fe78d 730 }
bwang 0:2dfd987fe78d 731
bwang 0:2dfd987fe78d 732 /**
bwang 0:2dfd987fe78d 733 * @brief Programs a double word (64-bit) at a specified address.
bwang 0:2dfd987fe78d 734 * @note This function must be used when the device voltage range is from
bwang 0:2dfd987fe78d 735 * 2.7V to 3.6V and an External Vpp is present.
bwang 0:2dfd987fe78d 736 *
bwang 0:2dfd987fe78d 737 * @note If an erase and a program operations are requested simultaneously,
bwang 0:2dfd987fe78d 738 * the erase operation is performed before the program one.
bwang 0:2dfd987fe78d 739 *
bwang 0:2dfd987fe78d 740 * @param Address: specifies the address to be programmed.
bwang 0:2dfd987fe78d 741 * @param Data: specifies the data to be programmed.
bwang 0:2dfd987fe78d 742 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 743 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 744 */
bwang 0:2dfd987fe78d 745 FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
bwang 0:2dfd987fe78d 746 {
bwang 0:2dfd987fe78d 747 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 748
bwang 0:2dfd987fe78d 749 /* Check the parameters */
bwang 0:2dfd987fe78d 750 assert_param(IS_FLASH_ADDRESS(Address));
bwang 0:2dfd987fe78d 751
bwang 0:2dfd987fe78d 752 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 753 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 754
bwang 0:2dfd987fe78d 755 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 756 {
bwang 0:2dfd987fe78d 757 /* if the previous operation is completed, proceed to program the new data */
bwang 0:2dfd987fe78d 758 FLASH->CR &= CR_PSIZE_MASK;
bwang 0:2dfd987fe78d 759 FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
bwang 0:2dfd987fe78d 760 FLASH->CR |= FLASH_CR_PG;
bwang 0:2dfd987fe78d 761
bwang 0:2dfd987fe78d 762 *(__IO uint64_t*)Address = Data;
bwang 0:2dfd987fe78d 763
bwang 0:2dfd987fe78d 764 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 765 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 766
bwang 0:2dfd987fe78d 767 /* if the program operation is completed, disable the PG Bit */
bwang 0:2dfd987fe78d 768 FLASH->CR &= (~FLASH_CR_PG);
bwang 0:2dfd987fe78d 769 }
bwang 0:2dfd987fe78d 770 /* Return the Program Status */
bwang 0:2dfd987fe78d 771 return status;
bwang 0:2dfd987fe78d 772 }
bwang 0:2dfd987fe78d 773
bwang 0:2dfd987fe78d 774 /**
bwang 0:2dfd987fe78d 775 * @brief Programs a word (32-bit) at a specified address.
bwang 0:2dfd987fe78d 776 *
bwang 0:2dfd987fe78d 777 * @note This function must be used when the device voltage range is from 2.7V to 3.6V.
bwang 0:2dfd987fe78d 778 *
bwang 0:2dfd987fe78d 779 * @note If an erase and a program operations are requested simultaneously,
bwang 0:2dfd987fe78d 780 * the erase operation is performed before the program one.
bwang 0:2dfd987fe78d 781 *
bwang 0:2dfd987fe78d 782 * @param Address: specifies the address to be programmed.
bwang 0:2dfd987fe78d 783 * This parameter can be any address in Program memory zone or in OTP zone.
bwang 0:2dfd987fe78d 784 * @param Data: specifies the data to be programmed.
bwang 0:2dfd987fe78d 785 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 786 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 787 */
bwang 0:2dfd987fe78d 788 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
bwang 0:2dfd987fe78d 789 {
bwang 0:2dfd987fe78d 790 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 791
bwang 0:2dfd987fe78d 792 /* Check the parameters */
bwang 0:2dfd987fe78d 793 assert_param(IS_FLASH_ADDRESS(Address));
bwang 0:2dfd987fe78d 794
bwang 0:2dfd987fe78d 795 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 796 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 797
bwang 0:2dfd987fe78d 798 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 799 {
bwang 0:2dfd987fe78d 800 /* if the previous operation is completed, proceed to program the new data */
bwang 0:2dfd987fe78d 801 FLASH->CR &= CR_PSIZE_MASK;
bwang 0:2dfd987fe78d 802 FLASH->CR |= FLASH_PSIZE_WORD;
bwang 0:2dfd987fe78d 803 FLASH->CR |= FLASH_CR_PG;
bwang 0:2dfd987fe78d 804
bwang 0:2dfd987fe78d 805 *(__IO uint32_t*)Address = Data;
bwang 0:2dfd987fe78d 806
bwang 0:2dfd987fe78d 807 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 808 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 809
bwang 0:2dfd987fe78d 810 /* if the program operation is completed, disable the PG Bit */
bwang 0:2dfd987fe78d 811 FLASH->CR &= (~FLASH_CR_PG);
bwang 0:2dfd987fe78d 812 }
bwang 0:2dfd987fe78d 813 /* Return the Program Status */
bwang 0:2dfd987fe78d 814 return status;
bwang 0:2dfd987fe78d 815 }
bwang 0:2dfd987fe78d 816
bwang 0:2dfd987fe78d 817 /**
bwang 0:2dfd987fe78d 818 * @brief Programs a half word (16-bit) at a specified address.
bwang 0:2dfd987fe78d 819 * @note This function must be used when the device voltage range is from 2.1V to 3.6V.
bwang 0:2dfd987fe78d 820 *
bwang 0:2dfd987fe78d 821 * @note If an erase and a program operations are requested simultaneously,
bwang 0:2dfd987fe78d 822 * the erase operation is performed before the program one.
bwang 0:2dfd987fe78d 823 *
bwang 0:2dfd987fe78d 824 * @param Address: specifies the address to be programmed.
bwang 0:2dfd987fe78d 825 * This parameter can be any address in Program memory zone or in OTP zone.
bwang 0:2dfd987fe78d 826 * @param Data: specifies the data to be programmed.
bwang 0:2dfd987fe78d 827 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 828 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 829 */
bwang 0:2dfd987fe78d 830 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
bwang 0:2dfd987fe78d 831 {
bwang 0:2dfd987fe78d 832 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 833
bwang 0:2dfd987fe78d 834 /* Check the parameters */
bwang 0:2dfd987fe78d 835 assert_param(IS_FLASH_ADDRESS(Address));
bwang 0:2dfd987fe78d 836
bwang 0:2dfd987fe78d 837 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 838 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 839
bwang 0:2dfd987fe78d 840 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 841 {
bwang 0:2dfd987fe78d 842 /* if the previous operation is completed, proceed to program the new data */
bwang 0:2dfd987fe78d 843 FLASH->CR &= CR_PSIZE_MASK;
bwang 0:2dfd987fe78d 844 FLASH->CR |= FLASH_PSIZE_HALF_WORD;
bwang 0:2dfd987fe78d 845 FLASH->CR |= FLASH_CR_PG;
bwang 0:2dfd987fe78d 846
bwang 0:2dfd987fe78d 847 *(__IO uint16_t*)Address = Data;
bwang 0:2dfd987fe78d 848
bwang 0:2dfd987fe78d 849 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 850 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 851
bwang 0:2dfd987fe78d 852 /* if the program operation is completed, disable the PG Bit */
bwang 0:2dfd987fe78d 853 FLASH->CR &= (~FLASH_CR_PG);
bwang 0:2dfd987fe78d 854 }
bwang 0:2dfd987fe78d 855 /* Return the Program Status */
bwang 0:2dfd987fe78d 856 return status;
bwang 0:2dfd987fe78d 857 }
bwang 0:2dfd987fe78d 858
bwang 0:2dfd987fe78d 859 /**
bwang 0:2dfd987fe78d 860 * @brief Programs a byte (8-bit) at a specified address.
bwang 0:2dfd987fe78d 861 * @note This function can be used within all the device supply voltage ranges.
bwang 0:2dfd987fe78d 862 *
bwang 0:2dfd987fe78d 863 * @note If an erase and a program operations are requested simultaneously,
bwang 0:2dfd987fe78d 864 * the erase operation is performed before the program one.
bwang 0:2dfd987fe78d 865 *
bwang 0:2dfd987fe78d 866 * @param Address: specifies the address to be programmed.
bwang 0:2dfd987fe78d 867 * This parameter can be any address in Program memory zone or in OTP zone.
bwang 0:2dfd987fe78d 868 * @param Data: specifies the data to be programmed.
bwang 0:2dfd987fe78d 869 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 870 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 871 */
bwang 0:2dfd987fe78d 872 FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
bwang 0:2dfd987fe78d 873 {
bwang 0:2dfd987fe78d 874 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 875
bwang 0:2dfd987fe78d 876 /* Check the parameters */
bwang 0:2dfd987fe78d 877 assert_param(IS_FLASH_ADDRESS(Address));
bwang 0:2dfd987fe78d 878
bwang 0:2dfd987fe78d 879 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 880 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 881
bwang 0:2dfd987fe78d 882 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 883 {
bwang 0:2dfd987fe78d 884 /* if the previous operation is completed, proceed to program the new data */
bwang 0:2dfd987fe78d 885 FLASH->CR &= CR_PSIZE_MASK;
bwang 0:2dfd987fe78d 886 FLASH->CR |= FLASH_PSIZE_BYTE;
bwang 0:2dfd987fe78d 887 FLASH->CR |= FLASH_CR_PG;
bwang 0:2dfd987fe78d 888
bwang 0:2dfd987fe78d 889 *(__IO uint8_t*)Address = Data;
bwang 0:2dfd987fe78d 890
bwang 0:2dfd987fe78d 891 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 892 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 893
bwang 0:2dfd987fe78d 894 /* if the program operation is completed, disable the PG Bit */
bwang 0:2dfd987fe78d 895 FLASH->CR &= (~FLASH_CR_PG);
bwang 0:2dfd987fe78d 896 }
bwang 0:2dfd987fe78d 897
bwang 0:2dfd987fe78d 898 /* Return the Program Status */
bwang 0:2dfd987fe78d 899 return status;
bwang 0:2dfd987fe78d 900 }
bwang 0:2dfd987fe78d 901
bwang 0:2dfd987fe78d 902 /**
bwang 0:2dfd987fe78d 903 * @}
bwang 0:2dfd987fe78d 904 */
bwang 0:2dfd987fe78d 905
bwang 0:2dfd987fe78d 906 /** @defgroup FLASH_Group3 Option Bytes Programming functions
bwang 0:2dfd987fe78d 907 * @brief Option Bytes Programming functions
bwang 0:2dfd987fe78d 908 *
bwang 0:2dfd987fe78d 909 @verbatim
bwang 0:2dfd987fe78d 910 ===============================================================================
bwang 0:2dfd987fe78d 911 ##### Option Bytes Programming functions #####
bwang 0:2dfd987fe78d 912 ===============================================================================
bwang 0:2dfd987fe78d 913 [..]
bwang 0:2dfd987fe78d 914 This group includes the following functions:
bwang 0:2dfd987fe78d 915 (+) void FLASH_OB_Unlock(void)
bwang 0:2dfd987fe78d 916 (+) void FLASH_OB_Lock(void)
bwang 0:2dfd987fe78d 917 (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
bwang 0:2dfd987fe78d 918 (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
bwang 0:2dfd987fe78d 919 (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
bwang 0:2dfd987fe78d 920 (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
bwang 0:2dfd987fe78d 921 (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
bwang 0:2dfd987fe78d 922 (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
bwang 0:2dfd987fe78d 923 (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
bwang 0:2dfd987fe78d 924 (+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
bwang 0:2dfd987fe78d 925 (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
bwang 0:2dfd987fe78d 926 (+) FLASH_Status FLASH_OB_Launch(void)
bwang 0:2dfd987fe78d 927 (+) uint32_t FLASH_OB_GetUser(void)
bwang 0:2dfd987fe78d 928 (+) uint8_t FLASH_OB_GetWRP(void)
bwang 0:2dfd987fe78d 929 (+) uint8_t FLASH_OB_GetWRP1(void)
bwang 0:2dfd987fe78d 930 (+) uint8_t FLASH_OB_GetPCROP(void)
bwang 0:2dfd987fe78d 931 (+) uint8_t FLASH_OB_GetPCROP1(void)
bwang 0:2dfd987fe78d 932 (+) uint8_t FLASH_OB_GetRDP(void)
bwang 0:2dfd987fe78d 933 (+) uint8_t FLASH_OB_GetBOR(void)
bwang 0:2dfd987fe78d 934 [..]
bwang 0:2dfd987fe78d 935 The following function can be used only for STM32F42xxx/43xxx devices.
bwang 0:2dfd987fe78d 936 (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
bwang 0:2dfd987fe78d 937 [..]
bwang 0:2dfd987fe78d 938 Any operation of erase or program should follow these steps:
bwang 0:2dfd987fe78d 939 (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
bwang 0:2dfd987fe78d 940 register access
bwang 0:2dfd987fe78d 941
bwang 0:2dfd987fe78d 942 (#) Call one or several functions to program the desired Option Bytes:
bwang 0:2dfd987fe78d 943 (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
bwang 0:2dfd987fe78d 944 => to Enable/Disable the desired sector write protection
bwang 0:2dfd987fe78d 945 (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read
bwang 0:2dfd987fe78d 946 Protection Level
bwang 0:2dfd987fe78d 947 (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
bwang 0:2dfd987fe78d 948 => to configure the user Option Bytes.
bwang 0:2dfd987fe78d 949 (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level
bwang 0:2dfd987fe78d 950
bwang 0:2dfd987fe78d 951 (#) Once all needed Option Bytes to be programmed are correctly written,
bwang 0:2dfd987fe78d 952 call the FLASH_OB_Launch() function to launch the Option Bytes
bwang 0:2dfd987fe78d 953 programming process.
bwang 0:2dfd987fe78d 954
bwang 0:2dfd987fe78d 955 -@- When changing the IWDG mode from HW to SW or from SW to HW, a system
bwang 0:2dfd987fe78d 956 reset is needed to make the change effective.
bwang 0:2dfd987fe78d 957
bwang 0:2dfd987fe78d 958 (#) Call the FLASH_OB_Lock() function to disable the FLASH option control
bwang 0:2dfd987fe78d 959 register access (recommended to protect the Option Bytes against
bwang 0:2dfd987fe78d 960 possible unwanted operations)
bwang 0:2dfd987fe78d 961
bwang 0:2dfd987fe78d 962 @endverbatim
bwang 0:2dfd987fe78d 963 * @{
bwang 0:2dfd987fe78d 964 */
bwang 0:2dfd987fe78d 965
bwang 0:2dfd987fe78d 966 /**
bwang 0:2dfd987fe78d 967 * @brief Unlocks the FLASH Option Control Registers access.
bwang 0:2dfd987fe78d 968 * @param None
bwang 0:2dfd987fe78d 969 * @retval None
bwang 0:2dfd987fe78d 970 */
bwang 0:2dfd987fe78d 971 void FLASH_OB_Unlock(void)
bwang 0:2dfd987fe78d 972 {
bwang 0:2dfd987fe78d 973 if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
bwang 0:2dfd987fe78d 974 {
bwang 0:2dfd987fe78d 975 /* Authorizes the Option Byte register programming */
bwang 0:2dfd987fe78d 976 FLASH->OPTKEYR = FLASH_OPT_KEY1;
bwang 0:2dfd987fe78d 977 FLASH->OPTKEYR = FLASH_OPT_KEY2;
bwang 0:2dfd987fe78d 978 }
bwang 0:2dfd987fe78d 979 }
bwang 0:2dfd987fe78d 980
bwang 0:2dfd987fe78d 981 /**
bwang 0:2dfd987fe78d 982 * @brief Locks the FLASH Option Control Registers access.
bwang 0:2dfd987fe78d 983 * @param None
bwang 0:2dfd987fe78d 984 * @retval None
bwang 0:2dfd987fe78d 985 */
bwang 0:2dfd987fe78d 986 void FLASH_OB_Lock(void)
bwang 0:2dfd987fe78d 987 {
bwang 0:2dfd987fe78d 988 /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
bwang 0:2dfd987fe78d 989 FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
bwang 0:2dfd987fe78d 990 }
bwang 0:2dfd987fe78d 991
bwang 0:2dfd987fe78d 992 /**
bwang 0:2dfd987fe78d 993 * @brief Enables or disables the write protection of the desired sectors, for the first
bwang 0:2dfd987fe78d 994 * 1 Mb of the Flash
bwang 0:2dfd987fe78d 995 *
bwang 0:2dfd987fe78d 996 * @note When the memory read protection level is selected (RDP level = 1),
bwang 0:2dfd987fe78d 997 * it is not possible to program or erase the flash sector i if CortexM4
bwang 0:2dfd987fe78d 998 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
bwang 0:2dfd987fe78d 999 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
bwang 0:2dfd987fe78d 1000 *
bwang 0:2dfd987fe78d 1001 * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
bwang 0:2dfd987fe78d 1002 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1003 * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
bwang 0:2dfd987fe78d 1004 * @arg OB_WRP_Sector_All
bwang 0:2dfd987fe78d 1005 * @param Newstate: new state of the Write Protection.
bwang 0:2dfd987fe78d 1006 * This parameter can be: ENABLE or DISABLE.
bwang 0:2dfd987fe78d 1007 * @retval None
bwang 0:2dfd987fe78d 1008 */
bwang 0:2dfd987fe78d 1009 void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
bwang 0:2dfd987fe78d 1010 {
bwang 0:2dfd987fe78d 1011 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1012
bwang 0:2dfd987fe78d 1013 /* Check the parameters */
bwang 0:2dfd987fe78d 1014 assert_param(IS_OB_WRP(OB_WRP));
bwang 0:2dfd987fe78d 1015 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 0:2dfd987fe78d 1016
bwang 0:2dfd987fe78d 1017 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 1018
bwang 0:2dfd987fe78d 1019 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 1020 {
bwang 0:2dfd987fe78d 1021 if(NewState != DISABLE)
bwang 0:2dfd987fe78d 1022 {
bwang 0:2dfd987fe78d 1023 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
bwang 0:2dfd987fe78d 1024 }
bwang 0:2dfd987fe78d 1025 else
bwang 0:2dfd987fe78d 1026 {
bwang 0:2dfd987fe78d 1027 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
bwang 0:2dfd987fe78d 1028 }
bwang 0:2dfd987fe78d 1029 }
bwang 0:2dfd987fe78d 1030 }
bwang 0:2dfd987fe78d 1031
bwang 0:2dfd987fe78d 1032 /**
bwang 0:2dfd987fe78d 1033 * @brief Enables or disables the write protection of the desired sectors, for the second
bwang 0:2dfd987fe78d 1034 * 1 Mb of the Flash
bwang 0:2dfd987fe78d 1035 *
bwang 0:2dfd987fe78d 1036 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 0:2dfd987fe78d 1037 *
bwang 0:2dfd987fe78d 1038 * @note When the memory read out protection is selected (RDP level = 1),
bwang 0:2dfd987fe78d 1039 * it is not possible to program or erase the flash sector i if CortexM4
bwang 0:2dfd987fe78d 1040 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
bwang 0:2dfd987fe78d 1041 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
bwang 0:2dfd987fe78d 1042 *
bwang 0:2dfd987fe78d 1043 * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
bwang 0:2dfd987fe78d 1044 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1045 * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
bwang 0:2dfd987fe78d 1046 * @arg OB_WRP_Sector_All
bwang 0:2dfd987fe78d 1047 * @param Newstate: new state of the Write Protection.
bwang 0:2dfd987fe78d 1048 * This parameter can be: ENABLE or DISABLE.
bwang 0:2dfd987fe78d 1049 * @retval None
bwang 0:2dfd987fe78d 1050 */
bwang 0:2dfd987fe78d 1051 void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
bwang 0:2dfd987fe78d 1052 {
bwang 0:2dfd987fe78d 1053 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1054
bwang 0:2dfd987fe78d 1055 /* Check the parameters */
bwang 0:2dfd987fe78d 1056 assert_param(IS_OB_WRP(OB_WRP));
bwang 0:2dfd987fe78d 1057 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 0:2dfd987fe78d 1058
bwang 0:2dfd987fe78d 1059 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 1060
bwang 0:2dfd987fe78d 1061 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 1062 {
bwang 0:2dfd987fe78d 1063 if(NewState != DISABLE)
bwang 0:2dfd987fe78d 1064 {
bwang 0:2dfd987fe78d 1065 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
bwang 0:2dfd987fe78d 1066 }
bwang 0:2dfd987fe78d 1067 else
bwang 0:2dfd987fe78d 1068 {
bwang 0:2dfd987fe78d 1069 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
bwang 0:2dfd987fe78d 1070 }
bwang 0:2dfd987fe78d 1071 }
bwang 0:2dfd987fe78d 1072 }
bwang 0:2dfd987fe78d 1073
bwang 0:2dfd987fe78d 1074 /**
bwang 0:2dfd987fe78d 1075 * @brief Select the Protection Mode (SPRMOD).
bwang 0:2dfd987fe78d 1076 *
bwang 0:2dfd987fe78d 1077 * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
bwang 0:2dfd987fe78d 1078 *
bwang 0:2dfd987fe78d 1079 * @note After PCROP activation, Option Byte modification is not possible.
bwang 0:2dfd987fe78d 1080 * Exception made for the global Read Out Protection modification level (level1 to level0)
bwang 0:2dfd987fe78d 1081 * @note Once SPRMOD bit is active unprotection of a protected sector is not possible
bwang 0:2dfd987fe78d 1082 *
bwang 0:2dfd987fe78d 1083 * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
bwang 0:2dfd987fe78d 1084 *
bwang 0:2dfd987fe78d 1085 * @note Some Precautions should be taken when activating the PCROP feature :
bwang 0:2dfd987fe78d 1086 * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1
bwang 0:2dfd987fe78d 1087 * and WRPi = 1 (default value), then the user sector i is read/write protected.
bwang 0:2dfd987fe78d 1088 * In order to avoid activation of PCROP Mode for undesired sectors, please follow the
bwang 0:2dfd987fe78d 1089 * below safety sequence :
bwang 0:2dfd987fe78d 1090 * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function
bwang 0:2dfd987fe78d 1091 * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
bwang 0:2dfd987fe78d 1092 * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
bwang 0:2dfd987fe78d 1093 * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
bwang 0:2dfd987fe78d 1094 *
bwang 0:2dfd987fe78d 1095 * @param OB_PCROP: Select the Protection Mode of nWPRi bits
bwang 0:2dfd987fe78d 1096 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1097 * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
bwang 0:2dfd987fe78d 1098 * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
bwang 0:2dfd987fe78d 1099 * @retval None
bwang 0:2dfd987fe78d 1100 */
bwang 0:2dfd987fe78d 1101 void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
bwang 0:2dfd987fe78d 1102 {
bwang 0:2dfd987fe78d 1103 uint8_t optiontmp = 0xFF;
bwang 0:2dfd987fe78d 1104
bwang 0:2dfd987fe78d 1105 /* Check the parameters */
bwang 0:2dfd987fe78d 1106 assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
bwang 0:2dfd987fe78d 1107
bwang 0:2dfd987fe78d 1108 /* Mask SPRMOD bit */
bwang 0:2dfd987fe78d 1109 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
bwang 0:2dfd987fe78d 1110 /* Update Option Byte */
bwang 0:2dfd987fe78d 1111 *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp);
bwang 0:2dfd987fe78d 1112
bwang 0:2dfd987fe78d 1113 }
bwang 0:2dfd987fe78d 1114
bwang 0:2dfd987fe78d 1115 /**
bwang 0:2dfd987fe78d 1116 * @brief Enables or disables the read/write protection (PCROP) of the desired
bwang 0:2dfd987fe78d 1117 * sectors, for the first 1 MB of the Flash.
bwang 0:2dfd987fe78d 1118 *
bwang 0:2dfd987fe78d 1119 * @note This function can be used only for STM32F42xxx/43xxx , STM32F401xx/411xE
bwang 0:2dfd987fe78d 1120 * and STM32F412xG devices.
bwang 0:2dfd987fe78d 1121 *
bwang 0:2dfd987fe78d 1122 * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
bwang 0:2dfd987fe78d 1123 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1124 * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for
bwang 0:2dfd987fe78d 1125 * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and
bwang 0:2dfd987fe78d 1126 * OB_PCROP_Sector5 for STM32F401xx/411xE devices.
bwang 0:2dfd987fe78d 1127 * @arg OB_PCROP_Sector_All
bwang 0:2dfd987fe78d 1128 * @param Newstate: new state of the Write Protection.
bwang 0:2dfd987fe78d 1129 * This parameter can be: ENABLE or DISABLE.
bwang 0:2dfd987fe78d 1130 * @retval None
bwang 0:2dfd987fe78d 1131 */
bwang 0:2dfd987fe78d 1132 void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
bwang 0:2dfd987fe78d 1133 {
bwang 0:2dfd987fe78d 1134 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1135
bwang 0:2dfd987fe78d 1136 /* Check the parameters */
bwang 0:2dfd987fe78d 1137 assert_param(IS_OB_PCROP(OB_PCROP));
bwang 0:2dfd987fe78d 1138 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 0:2dfd987fe78d 1139
bwang 0:2dfd987fe78d 1140 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 1141
bwang 0:2dfd987fe78d 1142 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 1143 {
bwang 0:2dfd987fe78d 1144 if(NewState != DISABLE)
bwang 0:2dfd987fe78d 1145 {
bwang 0:2dfd987fe78d 1146 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
bwang 0:2dfd987fe78d 1147 }
bwang 0:2dfd987fe78d 1148 else
bwang 0:2dfd987fe78d 1149 {
bwang 0:2dfd987fe78d 1150 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
bwang 0:2dfd987fe78d 1151 }
bwang 0:2dfd987fe78d 1152 }
bwang 0:2dfd987fe78d 1153 }
bwang 0:2dfd987fe78d 1154
bwang 0:2dfd987fe78d 1155 /**
bwang 0:2dfd987fe78d 1156 * @brief Enables or disables the read/write protection (PCROP) of the desired
bwang 0:2dfd987fe78d 1157 * sectors
bwang 0:2dfd987fe78d 1158 *
bwang 0:2dfd987fe78d 1159 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 0:2dfd987fe78d 1160 *
bwang 0:2dfd987fe78d 1161 * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
bwang 0:2dfd987fe78d 1162 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1163 * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
bwang 0:2dfd987fe78d 1164 * @arg OB_PCROP_Sector_All
bwang 0:2dfd987fe78d 1165 * @param Newstate: new state of the Write Protection.
bwang 0:2dfd987fe78d 1166 * This parameter can be: ENABLE or DISABLE.
bwang 0:2dfd987fe78d 1167 * @retval None
bwang 0:2dfd987fe78d 1168 */
bwang 0:2dfd987fe78d 1169 void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
bwang 0:2dfd987fe78d 1170 {
bwang 0:2dfd987fe78d 1171 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1172
bwang 0:2dfd987fe78d 1173 /* Check the parameters */
bwang 0:2dfd987fe78d 1174 assert_param(IS_OB_PCROP(OB_PCROP));
bwang 0:2dfd987fe78d 1175 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 0:2dfd987fe78d 1176
bwang 0:2dfd987fe78d 1177 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 1178
bwang 0:2dfd987fe78d 1179 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 1180 {
bwang 0:2dfd987fe78d 1181 if(NewState != DISABLE)
bwang 0:2dfd987fe78d 1182 {
bwang 0:2dfd987fe78d 1183 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
bwang 0:2dfd987fe78d 1184 }
bwang 0:2dfd987fe78d 1185 else
bwang 0:2dfd987fe78d 1186 {
bwang 0:2dfd987fe78d 1187 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
bwang 0:2dfd987fe78d 1188 }
bwang 0:2dfd987fe78d 1189 }
bwang 0:2dfd987fe78d 1190 }
bwang 0:2dfd987fe78d 1191
bwang 0:2dfd987fe78d 1192
bwang 0:2dfd987fe78d 1193 /**
bwang 0:2dfd987fe78d 1194 * @brief Sets the read protection level.
bwang 0:2dfd987fe78d 1195 * @param OB_RDP: specifies the read protection level.
bwang 0:2dfd987fe78d 1196 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1197 * @arg OB_RDP_Level_0: No protection
bwang 0:2dfd987fe78d 1198 * @arg OB_RDP_Level_1: Read protection of the memory
bwang 0:2dfd987fe78d 1199 * @arg OB_RDP_Level_2: Full chip protection
bwang 0:2dfd987fe78d 1200 *
bwang 0:2dfd987fe78d 1201 * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
bwang 0:2dfd987fe78d 1202 *
bwang 0:2dfd987fe78d 1203 * @retval None
bwang 0:2dfd987fe78d 1204 */
bwang 0:2dfd987fe78d 1205 void FLASH_OB_RDPConfig(uint8_t OB_RDP)
bwang 0:2dfd987fe78d 1206 {
bwang 0:2dfd987fe78d 1207 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1208
bwang 0:2dfd987fe78d 1209 /* Check the parameters */
bwang 0:2dfd987fe78d 1210 assert_param(IS_OB_RDP(OB_RDP));
bwang 0:2dfd987fe78d 1211
bwang 0:2dfd987fe78d 1212 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 1213
bwang 0:2dfd987fe78d 1214 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 1215 {
bwang 0:2dfd987fe78d 1216 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
bwang 0:2dfd987fe78d 1217
bwang 0:2dfd987fe78d 1218 }
bwang 0:2dfd987fe78d 1219 }
bwang 0:2dfd987fe78d 1220
bwang 0:2dfd987fe78d 1221 /**
bwang 0:2dfd987fe78d 1222 * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
bwang 0:2dfd987fe78d 1223 * @param OB_IWDG: Selects the IWDG mode
bwang 0:2dfd987fe78d 1224 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1225 * @arg OB_IWDG_SW: Software IWDG selected
bwang 0:2dfd987fe78d 1226 * @arg OB_IWDG_HW: Hardware IWDG selected
bwang 0:2dfd987fe78d 1227 * @param OB_STOP: Reset event when entering STOP mode.
bwang 0:2dfd987fe78d 1228 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1229 * @arg OB_STOP_NoRST: No reset generated when entering in STOP
bwang 0:2dfd987fe78d 1230 * @arg OB_STOP_RST: Reset generated when entering in STOP
bwang 0:2dfd987fe78d 1231 * @param OB_STDBY: Reset event when entering Standby mode.
bwang 0:2dfd987fe78d 1232 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1233 * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
bwang 0:2dfd987fe78d 1234 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
bwang 0:2dfd987fe78d 1235 * @retval None
bwang 0:2dfd987fe78d 1236 */
bwang 0:2dfd987fe78d 1237 void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
bwang 0:2dfd987fe78d 1238 {
bwang 0:2dfd987fe78d 1239 uint8_t optiontmp = 0xFF;
bwang 0:2dfd987fe78d 1240 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1241
bwang 0:2dfd987fe78d 1242 /* Check the parameters */
bwang 0:2dfd987fe78d 1243 assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
bwang 0:2dfd987fe78d 1244 assert_param(IS_OB_STOP_SOURCE(OB_STOP));
bwang 0:2dfd987fe78d 1245 assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
bwang 0:2dfd987fe78d 1246
bwang 0:2dfd987fe78d 1247 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 1248 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 1249
bwang 0:2dfd987fe78d 1250 if(status == FLASH_COMPLETE2)
bwang 0:2dfd987fe78d 1251 {
bwang 0:2dfd987fe78d 1252 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
bwang 0:2dfd987fe78d 1253 /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
bwang 0:2dfd987fe78d 1254 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
bwang 0:2dfd987fe78d 1255 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
bwang 0:2dfd987fe78d 1256
bwang 0:2dfd987fe78d 1257 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F446xx)
bwang 0:2dfd987fe78d 1258 /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
bwang 0:2dfd987fe78d 1259 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
bwang 0:2dfd987fe78d 1260 #endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
bwang 0:2dfd987fe78d 1261
bwang 0:2dfd987fe78d 1262 /* Update User Option Byte */
bwang 0:2dfd987fe78d 1263 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
bwang 0:2dfd987fe78d 1264 }
bwang 0:2dfd987fe78d 1265 }
bwang 0:2dfd987fe78d 1266
bwang 0:2dfd987fe78d 1267 /**
bwang 0:2dfd987fe78d 1268 * @brief Configure the Dual Bank Boot.
bwang 0:2dfd987fe78d 1269 *
bwang 0:2dfd987fe78d 1270 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 0:2dfd987fe78d 1271 *
bwang 0:2dfd987fe78d 1272 * @param OB_BOOT: specifies the Dual Bank Boot Option byte.
bwang 0:2dfd987fe78d 1273 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1274 * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
bwang 0:2dfd987fe78d 1275 * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
bwang 0:2dfd987fe78d 1276 * @retval None
bwang 0:2dfd987fe78d 1277 */
bwang 0:2dfd987fe78d 1278 void FLASH_OB_BootConfig(uint8_t OB_BOOT)
bwang 0:2dfd987fe78d 1279 {
bwang 0:2dfd987fe78d 1280 /* Check the parameters */
bwang 0:2dfd987fe78d 1281 assert_param(IS_OB_BOOT(OB_BOOT));
bwang 0:2dfd987fe78d 1282
bwang 0:2dfd987fe78d 1283 /* Set Dual Bank Boot */
bwang 0:2dfd987fe78d 1284 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
bwang 0:2dfd987fe78d 1285 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT;
bwang 0:2dfd987fe78d 1286
bwang 0:2dfd987fe78d 1287 }
bwang 0:2dfd987fe78d 1288
bwang 0:2dfd987fe78d 1289 /**
bwang 0:2dfd987fe78d 1290 * @brief Sets the BOR Level.
bwang 0:2dfd987fe78d 1291 * @param OB_BOR: specifies the Option Bytes BOR Reset Level.
bwang 0:2dfd987fe78d 1292 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1293 * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
bwang 0:2dfd987fe78d 1294 * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
bwang 0:2dfd987fe78d 1295 * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
bwang 0:2dfd987fe78d 1296 * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
bwang 0:2dfd987fe78d 1297 * @retval None
bwang 0:2dfd987fe78d 1298 */
bwang 0:2dfd987fe78d 1299 void FLASH_OB_BORConfig(uint8_t OB_BOR)
bwang 0:2dfd987fe78d 1300 {
bwang 0:2dfd987fe78d 1301 /* Check the parameters */
bwang 0:2dfd987fe78d 1302 assert_param(IS_OB_BOR(OB_BOR));
bwang 0:2dfd987fe78d 1303
bwang 0:2dfd987fe78d 1304 /* Set the BOR Level */
bwang 0:2dfd987fe78d 1305 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
bwang 0:2dfd987fe78d 1306 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
bwang 0:2dfd987fe78d 1307
bwang 0:2dfd987fe78d 1308 }
bwang 0:2dfd987fe78d 1309
bwang 0:2dfd987fe78d 1310 /**
bwang 0:2dfd987fe78d 1311 * @brief Launch the option byte loading.
bwang 0:2dfd987fe78d 1312 * @param None
bwang 0:2dfd987fe78d 1313 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 1314 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 1315 */
bwang 0:2dfd987fe78d 1316 FLASH_Status FLASH_OB_Launch(void)
bwang 0:2dfd987fe78d 1317 {
bwang 0:2dfd987fe78d 1318 FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1319
bwang 0:2dfd987fe78d 1320 /* Set the OPTSTRT bit in OPTCR register */
bwang 0:2dfd987fe78d 1321 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
bwang 0:2dfd987fe78d 1322
bwang 0:2dfd987fe78d 1323 /* Wait for last operation to be completed */
bwang 0:2dfd987fe78d 1324 status = FLASH_WaitForLastOperation2();
bwang 0:2dfd987fe78d 1325
bwang 0:2dfd987fe78d 1326 return status;
bwang 0:2dfd987fe78d 1327 }
bwang 0:2dfd987fe78d 1328
bwang 0:2dfd987fe78d 1329 /**
bwang 0:2dfd987fe78d 1330 * @brief Returns the FLASH User Option Bytes values.
bwang 0:2dfd987fe78d 1331 * @param None
bwang 0:2dfd987fe78d 1332 * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
bwang 0:2dfd987fe78d 1333 * and RST_STDBY(Bit2).
bwang 0:2dfd987fe78d 1334 */
bwang 0:2dfd987fe78d 1335 uint8_t FLASH_OB_GetUser(void)
bwang 0:2dfd987fe78d 1336 {
bwang 0:2dfd987fe78d 1337 /* Return the User Option Byte */
bwang 0:2dfd987fe78d 1338 return (uint8_t)(FLASH->OPTCR >> 5);
bwang 0:2dfd987fe78d 1339 }
bwang 0:2dfd987fe78d 1340
bwang 0:2dfd987fe78d 1341 /**
bwang 0:2dfd987fe78d 1342 * @brief Returns the FLASH Write Protection Option Bytes value.
bwang 0:2dfd987fe78d 1343 * @param None
bwang 0:2dfd987fe78d 1344 * @retval The FLASH Write Protection Option Bytes value
bwang 0:2dfd987fe78d 1345 */
bwang 0:2dfd987fe78d 1346 uint16_t FLASH_OB_GetWRP(void)
bwang 0:2dfd987fe78d 1347 {
bwang 0:2dfd987fe78d 1348 /* Return the FLASH write protection Register value */
bwang 0:2dfd987fe78d 1349 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
bwang 0:2dfd987fe78d 1350 }
bwang 0:2dfd987fe78d 1351
bwang 0:2dfd987fe78d 1352 /**
bwang 0:2dfd987fe78d 1353 * @brief Returns the FLASH Write Protection Option Bytes value.
bwang 0:2dfd987fe78d 1354 *
bwang 0:2dfd987fe78d 1355 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 0:2dfd987fe78d 1356 *
bwang 0:2dfd987fe78d 1357 * @param None
bwang 0:2dfd987fe78d 1358 * @retval The FLASH Write Protection Option Bytes value
bwang 0:2dfd987fe78d 1359 */
bwang 0:2dfd987fe78d 1360 uint16_t FLASH_OB_GetWRP1(void)
bwang 0:2dfd987fe78d 1361 {
bwang 0:2dfd987fe78d 1362 /* Return the FLASH write protection Register value */
bwang 0:2dfd987fe78d 1363 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
bwang 0:2dfd987fe78d 1364 }
bwang 0:2dfd987fe78d 1365
bwang 0:2dfd987fe78d 1366 /**
bwang 0:2dfd987fe78d 1367 * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
bwang 0:2dfd987fe78d 1368 *
bwang 0:2dfd987fe78d 1369 * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices.
bwang 0:2dfd987fe78d 1370 *
bwang 0:2dfd987fe78d 1371 * @param None
bwang 0:2dfd987fe78d 1372 * @retval The FLASH PC Read/Write Protection Option Bytes value
bwang 0:2dfd987fe78d 1373 */
bwang 0:2dfd987fe78d 1374 uint16_t FLASH_OB_GetPCROP(void)
bwang 0:2dfd987fe78d 1375 {
bwang 0:2dfd987fe78d 1376 /* Return the FLASH PC Read/write protection Register value */
bwang 0:2dfd987fe78d 1377 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
bwang 0:2dfd987fe78d 1378 }
bwang 0:2dfd987fe78d 1379
bwang 0:2dfd987fe78d 1380 /**
bwang 0:2dfd987fe78d 1381 * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
bwang 0:2dfd987fe78d 1382 *
bwang 0:2dfd987fe78d 1383 * @note This function can be used only for STM32F42xxx/43xxx devices.
bwang 0:2dfd987fe78d 1384 *
bwang 0:2dfd987fe78d 1385 * @param None
bwang 0:2dfd987fe78d 1386 * @retval The FLASH PC Read/Write Protection Option Bytes value
bwang 0:2dfd987fe78d 1387 */
bwang 0:2dfd987fe78d 1388 uint16_t FLASH_OB_GetPCROP1(void)
bwang 0:2dfd987fe78d 1389 {
bwang 0:2dfd987fe78d 1390 /* Return the FLASH write protection Register value */
bwang 0:2dfd987fe78d 1391 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
bwang 0:2dfd987fe78d 1392 }
bwang 0:2dfd987fe78d 1393
bwang 0:2dfd987fe78d 1394 /**
bwang 0:2dfd987fe78d 1395 * @brief Returns the FLASH Read Protection level.
bwang 0:2dfd987fe78d 1396 * @param None
bwang 0:2dfd987fe78d 1397 * @retval FLASH ReadOut Protection Status:
bwang 0:2dfd987fe78d 1398 * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
bwang 0:2dfd987fe78d 1399 * - RESET, when OB_RDP_Level_0 is set
bwang 0:2dfd987fe78d 1400 */
bwang 0:2dfd987fe78d 1401 FlagStatus FLASH_OB_GetRDP(void)
bwang 0:2dfd987fe78d 1402 {
bwang 0:2dfd987fe78d 1403 FlagStatus readstatus = RESET;
bwang 0:2dfd987fe78d 1404
bwang 0:2dfd987fe78d 1405 if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
bwang 0:2dfd987fe78d 1406 {
bwang 0:2dfd987fe78d 1407 readstatus = SET;
bwang 0:2dfd987fe78d 1408 }
bwang 0:2dfd987fe78d 1409 else
bwang 0:2dfd987fe78d 1410 {
bwang 0:2dfd987fe78d 1411 readstatus = RESET;
bwang 0:2dfd987fe78d 1412 }
bwang 0:2dfd987fe78d 1413 return readstatus;
bwang 0:2dfd987fe78d 1414 }
bwang 0:2dfd987fe78d 1415
bwang 0:2dfd987fe78d 1416 /**
bwang 0:2dfd987fe78d 1417 * @brief Returns the FLASH BOR level.
bwang 0:2dfd987fe78d 1418 * @param None
bwang 0:2dfd987fe78d 1419 * @retval The FLASH BOR level:
bwang 0:2dfd987fe78d 1420 * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
bwang 0:2dfd987fe78d 1421 * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
bwang 0:2dfd987fe78d 1422 * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
bwang 0:2dfd987fe78d 1423 * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
bwang 0:2dfd987fe78d 1424 */
bwang 0:2dfd987fe78d 1425 uint8_t FLASH_OB_GetBOR(void)
bwang 0:2dfd987fe78d 1426 {
bwang 0:2dfd987fe78d 1427 /* Return the FLASH BOR level */
bwang 0:2dfd987fe78d 1428 return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
bwang 0:2dfd987fe78d 1429 }
bwang 0:2dfd987fe78d 1430
bwang 0:2dfd987fe78d 1431 /**
bwang 0:2dfd987fe78d 1432 * @}
bwang 0:2dfd987fe78d 1433 */
bwang 0:2dfd987fe78d 1434
bwang 0:2dfd987fe78d 1435 /** @defgroup FLASH_Group4 Interrupts and flags management functions
bwang 0:2dfd987fe78d 1436 * @brief Interrupts and flags management functions
bwang 0:2dfd987fe78d 1437 *
bwang 0:2dfd987fe78d 1438 @verbatim
bwang 0:2dfd987fe78d 1439 ===============================================================================
bwang 0:2dfd987fe78d 1440 ##### Interrupts and flags management functions #####
bwang 0:2dfd987fe78d 1441 ===============================================================================
bwang 0:2dfd987fe78d 1442 @endverbatim
bwang 0:2dfd987fe78d 1443 * @{
bwang 0:2dfd987fe78d 1444 */
bwang 0:2dfd987fe78d 1445
bwang 0:2dfd987fe78d 1446 /**
bwang 0:2dfd987fe78d 1447 * @brief Enables or disables the specified FLASH interrupts.
bwang 0:2dfd987fe78d 1448 * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
bwang 0:2dfd987fe78d 1449 * This parameter can be any combination of the following values:
bwang 0:2dfd987fe78d 1450 * @arg FLASH_IT_ERR: FLASH Error Interrupt
bwang 0:2dfd987fe78d 1451 * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
bwang 0:2dfd987fe78d 1452 * @retval None
bwang 0:2dfd987fe78d 1453 */
bwang 0:2dfd987fe78d 1454 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
bwang 0:2dfd987fe78d 1455 {
bwang 0:2dfd987fe78d 1456 /* Check the parameters */
bwang 0:2dfd987fe78d 1457 assert_param(IS_FLASH_IT(FLASH_IT));
bwang 0:2dfd987fe78d 1458 assert_param(IS_FUNCTIONAL_STATE(NewState));
bwang 0:2dfd987fe78d 1459
bwang 0:2dfd987fe78d 1460 if(NewState != DISABLE)
bwang 0:2dfd987fe78d 1461 {
bwang 0:2dfd987fe78d 1462 /* Enable the interrupt sources */
bwang 0:2dfd987fe78d 1463 FLASH->CR |= FLASH_IT;
bwang 0:2dfd987fe78d 1464 }
bwang 0:2dfd987fe78d 1465 else
bwang 0:2dfd987fe78d 1466 {
bwang 0:2dfd987fe78d 1467 /* Disable the interrupt sources */
bwang 0:2dfd987fe78d 1468 FLASH->CR &= ~(uint32_t)FLASH_IT;
bwang 0:2dfd987fe78d 1469 }
bwang 0:2dfd987fe78d 1470 }
bwang 0:2dfd987fe78d 1471
bwang 0:2dfd987fe78d 1472 /**
bwang 0:2dfd987fe78d 1473 * @brief Checks whether the specified FLASH flag is set or not.
bwang 0:2dfd987fe78d 1474 * @param FLASH_FLAG: specifies the FLASH flag to check.
bwang 0:2dfd987fe78d 1475 * This parameter can be one of the following values:
bwang 0:2dfd987fe78d 1476 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
bwang 0:2dfd987fe78d 1477 * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
bwang 0:2dfd987fe78d 1478 * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
bwang 0:2dfd987fe78d 1479 * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
bwang 0:2dfd987fe78d 1480 * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
bwang 0:2dfd987fe78d 1481 * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
bwang 0:2dfd987fe78d 1482 * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
bwang 0:2dfd987fe78d 1483 * @arg FLASH_FLAG_BSY: FLASH Busy flag
bwang 0:2dfd987fe78d 1484 * @retval The new state of FLASH_FLAG (SET or RESET).
bwang 0:2dfd987fe78d 1485 */
bwang 0:2dfd987fe78d 1486 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
bwang 0:2dfd987fe78d 1487 {
bwang 0:2dfd987fe78d 1488 FlagStatus bitstatus = RESET;
bwang 0:2dfd987fe78d 1489 /* Check the parameters */
bwang 0:2dfd987fe78d 1490 assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
bwang 0:2dfd987fe78d 1491
bwang 0:2dfd987fe78d 1492 if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
bwang 0:2dfd987fe78d 1493 {
bwang 0:2dfd987fe78d 1494 bitstatus = SET;
bwang 0:2dfd987fe78d 1495 }
bwang 0:2dfd987fe78d 1496 else
bwang 0:2dfd987fe78d 1497 {
bwang 0:2dfd987fe78d 1498 bitstatus = RESET;
bwang 0:2dfd987fe78d 1499 }
bwang 0:2dfd987fe78d 1500 /* Return the new state of FLASH_FLAG (SET or RESET) */
bwang 0:2dfd987fe78d 1501 return bitstatus;
bwang 0:2dfd987fe78d 1502 }
bwang 0:2dfd987fe78d 1503
bwang 0:2dfd987fe78d 1504 /**
bwang 0:2dfd987fe78d 1505 * @brief Clears the FLASH's pending flags.
bwang 0:2dfd987fe78d 1506 * @param FLASH_FLAG: specifies the FLASH flags to clear.
bwang 0:2dfd987fe78d 1507 * This parameter can be any combination of the following values:
bwang 0:2dfd987fe78d 1508 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
bwang 0:2dfd987fe78d 1509 * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
bwang 0:2dfd987fe78d 1510 * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
bwang 0:2dfd987fe78d 1511 * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
bwang 0:2dfd987fe78d 1512 * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
bwang 0:2dfd987fe78d 1513 * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
bwang 0:2dfd987fe78d 1514 * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
bwang 0:2dfd987fe78d 1515 * @retval None
bwang 0:2dfd987fe78d 1516 */
bwang 0:2dfd987fe78d 1517 void FLASH_ClearFlag(uint32_t FLASH_FLAG)
bwang 0:2dfd987fe78d 1518 {
bwang 0:2dfd987fe78d 1519 /* Check the parameters */
bwang 0:2dfd987fe78d 1520 assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
bwang 0:2dfd987fe78d 1521
bwang 0:2dfd987fe78d 1522 /* Clear the flags */
bwang 0:2dfd987fe78d 1523 FLASH->SR = FLASH_FLAG;
bwang 0:2dfd987fe78d 1524 }
bwang 0:2dfd987fe78d 1525
bwang 0:2dfd987fe78d 1526 /**
bwang 0:2dfd987fe78d 1527 * @brief Returns the FLASH Status.
bwang 0:2dfd987fe78d 1528 * @param None
bwang 0:2dfd987fe78d 1529 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 1530 * FLASH_ERROR_WRP2, FLASH_ERROR_RD2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 1531 */
bwang 0:2dfd987fe78d 1532 FLASH_Status FLASH_GetStatus(void)
bwang 0:2dfd987fe78d 1533 {
bwang 0:2dfd987fe78d 1534 FLASH_Status flashstatus = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1535
bwang 0:2dfd987fe78d 1536 if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
bwang 0:2dfd987fe78d 1537 {
bwang 0:2dfd987fe78d 1538 flashstatus = FLASH_BUSY2;
bwang 0:2dfd987fe78d 1539 }
bwang 0:2dfd987fe78d 1540 else
bwang 0:2dfd987fe78d 1541 {
bwang 0:2dfd987fe78d 1542 if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
bwang 0:2dfd987fe78d 1543 {
bwang 0:2dfd987fe78d 1544 flashstatus = FLASH_ERROR_WRP2;
bwang 0:2dfd987fe78d 1545 }
bwang 0:2dfd987fe78d 1546 else
bwang 0:2dfd987fe78d 1547 {
bwang 0:2dfd987fe78d 1548 if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
bwang 0:2dfd987fe78d 1549 {
bwang 0:2dfd987fe78d 1550 flashstatus = FLASH_ERROR_RD2;
bwang 0:2dfd987fe78d 1551 }
bwang 0:2dfd987fe78d 1552 else
bwang 0:2dfd987fe78d 1553 {
bwang 0:2dfd987fe78d 1554 if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00)
bwang 0:2dfd987fe78d 1555 {
bwang 0:2dfd987fe78d 1556 flashstatus = FLASH_ERROR_PROGRAM2;
bwang 0:2dfd987fe78d 1557 }
bwang 0:2dfd987fe78d 1558 else
bwang 0:2dfd987fe78d 1559 {
bwang 0:2dfd987fe78d 1560 if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
bwang 0:2dfd987fe78d 1561 {
bwang 0:2dfd987fe78d 1562 flashstatus = FLASH_ERROR_OPERATION2;
bwang 0:2dfd987fe78d 1563 }
bwang 0:2dfd987fe78d 1564 else
bwang 0:2dfd987fe78d 1565 {
bwang 0:2dfd987fe78d 1566 flashstatus = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1567 }
bwang 0:2dfd987fe78d 1568 }
bwang 0:2dfd987fe78d 1569 }
bwang 0:2dfd987fe78d 1570 }
bwang 0:2dfd987fe78d 1571 }
bwang 0:2dfd987fe78d 1572 /* Return the FLASH Status */
bwang 0:2dfd987fe78d 1573 return flashstatus;
bwang 0:2dfd987fe78d 1574 }
bwang 0:2dfd987fe78d 1575
bwang 0:2dfd987fe78d 1576 /**
bwang 0:2dfd987fe78d 1577 * @brief Waits for a FLASH operation to complete.
bwang 0:2dfd987fe78d 1578 * @param None
bwang 0:2dfd987fe78d 1579 * @retval FLASH Status: The returned value can be: FLASH_BUSY2, FLASH_ERROR_PROGRAM2,
bwang 0:2dfd987fe78d 1580 * FLASH_ERROR_WRP2, FLASH_ERROR_OPERATION2 or FLASH_COMPLETE2.
bwang 0:2dfd987fe78d 1581 */
bwang 0:2dfd987fe78d 1582 FLASH_Status FLASH_WaitForLastOperation2(void)
bwang 0:2dfd987fe78d 1583 {
bwang 0:2dfd987fe78d 1584 __IO FLASH_Status status = FLASH_COMPLETE2;
bwang 0:2dfd987fe78d 1585
bwang 0:2dfd987fe78d 1586 /* Check for the FLASH Status */
bwang 0:2dfd987fe78d 1587 status = FLASH_GetStatus();
bwang 0:2dfd987fe78d 1588
bwang 0:2dfd987fe78d 1589 /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
bwang 0:2dfd987fe78d 1590 Even if the FLASH operation fails, the BUSY flag will be reset and an error
bwang 0:2dfd987fe78d 1591 flag will be set */
bwang 0:2dfd987fe78d 1592 while(status == FLASH_BUSY2)
bwang 0:2dfd987fe78d 1593 {
bwang 0:2dfd987fe78d 1594 status = FLASH_GetStatus();
bwang 0:2dfd987fe78d 1595 }
bwang 0:2dfd987fe78d 1596 /* Return the operation status */
bwang 0:2dfd987fe78d 1597 return status;
bwang 0:2dfd987fe78d 1598 }
bwang 0:2dfd987fe78d 1599
bwang 0:2dfd987fe78d 1600 /**
bwang 0:2dfd987fe78d 1601 * @}
bwang 0:2dfd987fe78d 1602 */
bwang 0:2dfd987fe78d 1603
bwang 0:2dfd987fe78d 1604 /**
bwang 0:2dfd987fe78d 1605 * @}
bwang 0:2dfd987fe78d 1606 */
bwang 0:2dfd987fe78d 1607
bwang 0:2dfd987fe78d 1608 /**
bwang 0:2dfd987fe78d 1609 * @}
bwang 0:2dfd987fe78d 1610 */
bwang 0:2dfd987fe78d 1611
bwang 0:2dfd987fe78d 1612 /**
bwang 0:2dfd987fe78d 1613 * @}
bwang 0:2dfd987fe78d 1614 */
bwang 0:2dfd987fe78d 1615
bwang 0:2dfd987fe78d 1616 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/