Gérard Sontag / ENORA-Forth

A forth for LPC8xxx

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lpc8xx.s@2:2f8532130cca, 2016-05-12 (annotated)

Committer:
Recifarium
Date:
Thu May 12 15:59:55 2016 +0000
Revision:
2:2f8532130cca
Parent:
1:1224cf3799a5 
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UserRevisionLine numberNew contents of line
Recifarium 1:1224cf3799a5 1 ; MSEl=6, PSEL=1, DIV=3 ==> 28MHz
Recifarium 1:1224cf3799a5 2
Recifarium 0:df922596d756 3
Recifarium 0:df922596d756 4 RAMForIAP EQU 128
Recifarium 0:df922596d756 5 RomSize EQU 0x4000
Recifarium 0:df922596d756 6
Recifarium 0:df922596d756 7 ;-----------------------------------
Recifarium 0:df922596d756 8 ; This is the specific file for
Recifarium 0:df922596d756 9 ; LPC8xx chip
Recifarium 0:df922596d756 10 ; to be used with forth main program
Recifarium 0:df922596d756 11 ;-----------------------------------
Recifarium 0:df922596d756 12 APB EQU 0x40000000
Recifarium 0:df922596d756 13 PINASSIGN0 EQU 0x4000C000
Recifarium 0:df922596d756 14 SYSAHBCLKCTRL EQU 0x40048080
Recifarium 0:df922596d756 15 UARTCLKDIV EQU 0x40048094
Recifarium 0:df922596d756 16 USART0 EQU 0x40064000
Recifarium 0:df922596d756 17 CFG EQU 0x000
Recifarium 0:df922596d756 18 CTL EQU 0x004
Recifarium 0:df922596d756 19 STAT EQU 0x008
Recifarium 0:df922596d756 20 INTENSET EQU 0x00C
Recifarium 0:df922596d756 21 INTENCLR EQU 0x010
Recifarium 0:df922596d756 22 RXDAT EQU 0x014
Recifarium 0:df922596d756 23 TXDAT EQU 0x01C
Recifarium 0:df922596d756 24 BRG EQU 0x020
Recifarium 0:df922596d756 25 INTSTAT EQU 0x024
Recifarium 0:df922596d756 26 PIO0_1 EQU 1
Recifarium 0:df922596d756 27 PIO0_6 EQU 6
Recifarium 0:df922596d756 28 RX EQU PIO0_1
Recifarium 0:df922596d756 29 TX EQU PIO0_6
Recifarium 0:df922596d756 30
Recifarium 0:df922596d756 31 ;/*****************************************************************************
Recifarium 0:df922596d756 32 ; * @file: startup_LPC8xx.s
Recifarium 0:df922596d756 33 ; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
Recifarium 0:df922596d756 34 ; * for the NXP LPC8xx Device Series
Recifarium 0:df922596d756 35 ; * @version: V1.0
Recifarium 0:df922596d756 36 ; * @date: 16. Aug. 2012
Recifarium 0:df922596d756 37 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
Recifarium 0:df922596d756 38 ; *
Recifarium 0:df922596d756 39 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
Recifarium 0:df922596d756 40 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
Recifarium 0:df922596d756 41 ; * processor based microcontrollers. This file can be freely distributed
Recifarium 0:df922596d756 42 ; * within development tools that are supporting such ARM based processors.
Recifarium 0:df922596d756 43 ; *
Recifarium 0:df922596d756 44 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Recifarium 0:df922596d756 45 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Recifarium 0:df922596d756 46 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Recifarium 0:df922596d756 47 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Recifarium 0:df922596d756 48 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Recifarium 0:df922596d756 49 ; *
Recifarium 0:df922596d756 50 ; *****************************************************************************/
Recifarium 0:df922596d756 51 ; Vector Table Mapped to Address 0 at Reset
Recifarium 0:df922596d756 52 THUMB
Recifarium 0:df922596d756 53 AREA RESET, DATA , READONLY
Recifarium 0:df922596d756 54 EXPORT __Vectors
Recifarium 0:df922596d756 55
Recifarium 0:df922596d756 56 __Vectors DCD __initial_sp ; Top of Stack
Recifarium 0:df922596d756 57 DCD Reset_Handler ; Reset Handler
Recifarium 0:df922596d756 58 DCD NMI_Handler ; NMI Handler
Recifarium 0:df922596d756 59 DCD HardFault_Handler ; Hard Fault Handler
Recifarium 0:df922596d756 60 DCD 0 ; Reserved
Recifarium 0:df922596d756 61 DCD 0 ; Reserved
Recifarium 0:df922596d756 62 DCD 0 ; Reserved
Recifarium 0:df922596d756 63 DCD 0 ; Reserved
Recifarium 0:df922596d756 64 DCD 0 ; Reserved
Recifarium 0:df922596d756 65 DCD 0 ; Reserved
Recifarium 0:df922596d756 66 DCD 0 ; Reserved
Recifarium 0:df922596d756 67 DCD SVC_Handler ; SVCall Handler
Recifarium 0:df922596d756 68 DCD 0 ; Reserved
Recifarium 0:df922596d756 69 DCD 0 ; Reserved
Recifarium 0:df922596d756 70 DCD PendSV_Handler ; PendSV Handler
Recifarium 0:df922596d756 71 DCD SysTick_Handler ; SysTick Handler
Recifarium 0:df922596d756 72
Recifarium 0:df922596d756 73 ; External Interrupts
Recifarium 0:df922596d756 74 DCD SPI0_IRQHandler ; SPI0 controller
Recifarium 0:df922596d756 75 DCD SPI1_IRQHandler ; SPI1 controller
Recifarium 0:df922596d756 76 DCD 0 ; Reserved
Recifarium 0:df922596d756 77 DCD UART0_IRQHandler ; UART0
Recifarium 0:df922596d756 78 DCD UART1_IRQHandler ; UART1
Recifarium 0:df922596d756 79 DCD UART2_IRQHandler ; UART2
Recifarium 0:df922596d756 80 DCD 0 ; Reserved
Recifarium 0:df922596d756 81 DCD 0 ; Reserved
Recifarium 0:df922596d756 82 DCD I2C_IRQHandler ; I2C controller
Recifarium 0:df922596d756 83 DCD SCT_IRQHandler ; Smart Counter Timer
Recifarium 0:df922596d756 84 DCD MRT_IRQHandler ; Multi-Rate Timer
Recifarium 0:df922596d756 85 DCD CMP_IRQHandler ; Comparator
Recifarium 0:df922596d756 86 DCD WDT_IRQHandler ; PIO1 (0:11)
Recifarium 0:df922596d756 87 DCD BOD_IRQHandler ; Brown Out Detect
Recifarium 0:df922596d756 88 DCD 0 ; Reserved
Recifarium 0:df922596d756 89 DCD WKT_IRQHandler ; Wakeup timer
Recifarium 0:df922596d756 90 DCD 0 ; Reserved
Recifarium 0:df922596d756 91 DCD 0 ; Reserved
Recifarium 0:df922596d756 92 DCD 0 ; Reserved
Recifarium 0:df922596d756 93 DCD 0 ; Reserved
Recifarium 0:df922596d756 94 DCD 0 ; Reserved
Recifarium 0:df922596d756 95 DCD 0 ; Reserved
Recifarium 0:df922596d756 96 DCD 0 ; Reserved
Recifarium 0:df922596d756 97 DCD 0 ; Reserved
Recifarium 0:df922596d756 98 DCD PININT0_IRQHandler ; PIO INT0
Recifarium 0:df922596d756 99 DCD PININT1_IRQHandler ; PIO INT1
Recifarium 0:df922596d756 100 DCD PININT2_IRQHandler ; PIO INT2
Recifarium 0:df922596d756 101 DCD PININT3_IRQHandler ; PIO INT3
Recifarium 0:df922596d756 102 DCD PININT4_IRQHandler ; PIO INT4
Recifarium 0:df922596d756 103 DCD PININT5_IRQHandler ; PIO INT5
Recifarium 0:df922596d756 104 DCD PININT6_IRQHandler ; PIO INT6
Recifarium 0:df922596d756 105 DCD PININT7_IRQHandler ; PIO INT7
Recifarium 0:df922596d756 106
Recifarium 0:df922596d756 107 IF :LNOT::DEF:NO_CRP
Recifarium 0:df922596d756 108 AREA |.ARM.__at_0x02FC|, CODE
Recifarium 0:df922596d756 109 ; , READONLY
Recifarium 0:df922596d756 110 CRP_Key DCD 0xFFFFFFFF
Recifarium 0:df922596d756 111 ENDIF
Recifarium 0:df922596d756 112
Recifarium 0:df922596d756 113 AREA |.text|, CODE
Recifarium 0:df922596d756 114 HardFault_Handler\
Recifarium 0:df922596d756 115 PROC
Recifarium 0:df922596d756 116 EXPORT HardFault_Handler [WEAK]
Recifarium 0:df922596d756 117 B .
Recifarium 0:df922596d756 118 ENDP
Recifarium 0:df922596d756 119 SVC_Handler PROC
Recifarium 0:df922596d756 120 EXPORT SVC_Handler [WEAK]
Recifarium 0:df922596d756 121 B .
Recifarium 0:df922596d756 122 ENDP
Recifarium 0:df922596d756 123 PendSV_Handler PROC
Recifarium 0:df922596d756 124 EXPORT PendSV_Handler [WEAK]
Recifarium 0:df922596d756 125 B .
Recifarium 0:df922596d756 126 ENDP
Recifarium 0:df922596d756 127 SysTick_Handler PROC
Recifarium 0:df922596d756 128 EXPORT SysTick_Handler [WEAK]
Recifarium 0:df922596d756 129 B .
Recifarium 0:df922596d756 130 ENDP
Recifarium 0:df922596d756 131
Recifarium 0:df922596d756 132 Default_Handler PROC
Recifarium 0:df922596d756 133
Recifarium 0:df922596d756 134 EXPORT NMI_Handler [WEAK]
Recifarium 0:df922596d756 135 EXPORT SPI0_IRQHandler [WEAK]
Recifarium 0:df922596d756 136 EXPORT SPI1_IRQHandler [WEAK]
Recifarium 0:df922596d756 137 EXPORT UART0_IRQHandler [WEAK]
Recifarium 0:df922596d756 138 EXPORT UART1_IRQHandler [WEAK]
Recifarium 0:df922596d756 139 EXPORT UART2_IRQHandler [WEAK]
Recifarium 0:df922596d756 140 EXPORT I2C_IRQHandler [WEAK]
Recifarium 0:df922596d756 141 EXPORT SCT_IRQHandler [WEAK]
Recifarium 0:df922596d756 142 EXPORT MRT_IRQHandler [WEAK]
Recifarium 0:df922596d756 143 EXPORT CMP_IRQHandler [WEAK]
Recifarium 0:df922596d756 144 EXPORT WDT_IRQHandler [WEAK]
Recifarium 0:df922596d756 145 EXPORT BOD_IRQHandler [WEAK]
Recifarium 0:df922596d756 146 EXPORT WKT_IRQHandler [WEAK]
Recifarium 0:df922596d756 147 EXPORT PININT0_IRQHandler [WEAK]
Recifarium 0:df922596d756 148 EXPORT PININT1_IRQHandler [WEAK]
Recifarium 0:df922596d756 149 EXPORT PININT2_IRQHandler [WEAK]
Recifarium 0:df922596d756 150 EXPORT PININT3_IRQHandler [WEAK]
Recifarium 0:df922596d756 151 EXPORT PININT4_IRQHandler [WEAK]
Recifarium 0:df922596d756 152 EXPORT PININT5_IRQHandler [WEAK]
Recifarium 0:df922596d756 153 EXPORT PININT6_IRQHandler [WEAK]
Recifarium 0:df922596d756 154 EXPORT PININT7_IRQHandler [WEAK]
Recifarium 0:df922596d756 155
Recifarium 0:df922596d756 156 NMI_Handler
Recifarium 0:df922596d756 157 SPI0_IRQHandler
Recifarium 0:df922596d756 158 SPI1_IRQHandler
Recifarium 0:df922596d756 159 UART0_IRQHandler
Recifarium 0:df922596d756 160 UART1_IRQHandler
Recifarium 0:df922596d756 161 UART2_IRQHandler
Recifarium 0:df922596d756 162 I2C_IRQHandler
Recifarium 0:df922596d756 163 SCT_IRQHandler
Recifarium 0:df922596d756 164 MRT_IRQHandler
Recifarium 0:df922596d756 165 CMP_IRQHandler
Recifarium 0:df922596d756 166 WDT_IRQHandler
Recifarium 0:df922596d756 167 BOD_IRQHandler
Recifarium 0:df922596d756 168 WKT_IRQHandler
Recifarium 0:df922596d756 169 PININT0_IRQHandler
Recifarium 0:df922596d756 170 PININT1_IRQHandler
Recifarium 0:df922596d756 171 PININT2_IRQHandler
Recifarium 0:df922596d756 172 PININT3_IRQHandler
Recifarium 0:df922596d756 173 PININT4_IRQHandler
Recifarium 0:df922596d756 174 PININT5_IRQHandler
Recifarium 0:df922596d756 175 PININT6_IRQHandler
Recifarium 0:df922596d756 176 PININT7_IRQHandler
Recifarium 0:df922596d756 177
Recifarium 0:df922596d756 178 B .
Recifarium 0:df922596d756 179
Recifarium 0:df922596d756 180 ENDP
Recifarium 0:df922596d756 181 ALIGN
Recifarium 0:df922596d756 182 ; Configure USART 0/1/2 for receiving and transmitting data:
Recifarium 0:df922596d756 183 ; In the SYSAHBCLKCTRL register, set bit 14 to 16 (Table 18) to enable the clock to the register interface.
Recifarium 0:df922596d756 184
Recifarium 1:1224cf3799a5 185
Recifarium 1:1224cf3799a5 186 ; FLASHCFG et FLASHTIM >> à seter to 0 !!!!!!!!!
Recifarium 1:1224cf3799a5 187
Recifarium 0:df922596d756 188 UartConfig
Recifarium 0:df922596d756 189 MOVS r2, #1
Recifarium 0:df922596d756 190 LSLS r2, #14 ; USART0 (bit 14)
Recifarium 0:df922596d756 191 LDR r1, =SYSAHBCLKCTRL
Recifarium 0:df922596d756 192 LDR r0, [r1]
Recifarium 0:df922596d756 193 ORRS r0, r0, r2
Recifarium 0:df922596d756 194 STR r0, [r1]
Recifarium 0:df922596d756 195 ;Configure the USART0 pin functions through the switch matrix. See Section 15.4.
Recifarium 0:df922596d756 196 Value EQU TX+256*(RX+(256*(255+256*255)))
Recifarium 0:df922596d756 197 LDR r0,=Value
Recifarium 0:df922596d756 198 LDR r1,=PINASSIGN0
Recifarium 0:df922596d756 199 STR r0,[r1]
Recifarium 0:df922596d756 200 ;Configure the UART clock div
Recifarium 1:1224cf3799a5 201 MOVS r0,#3 ; UART clock 4MHz/16
Recifarium 0:df922596d756 202 LDR r1,=UARTCLKDIV
Recifarium 0:df922596d756 203 STR r0,[r1]
Recifarium 0:df922596d756 204 LDR r1,=(USART0)
Recifarium 0:df922596d756 205 ;Configure data
Recifarium 0:df922596d756 206 MOVS r0,#0x05 ; 8 bits, no Parity, 1 Stop bit */
Recifarium 0:df922596d756 207 STR r0, [r1,#CFG]
Recifarium 0:df922596d756 208 ;Configure BRG
Recifarium 1:1224cf3799a5 209 MOVS r0,#12 ; 19200bps
Recifarium 1:1224cf3799a5 210 ; MOVS r0,#3 ; 57600bps
Recifarium 0:df922596d756 211 STR r0,[r1,#BRG]
Recifarium 0:df922596d756 212 BX lr
Recifarium 0:df922596d756 213 LTORG
Recifarium 0:df922596d756 214 ;-----------------------------------
Recifarium 0:df922596d756 215 ; DONT Change the 3 lines below
Recifarium 0:df922596d756 216 ; and leave the xEmit label on
Recifarium 0:df922596d756 217 ; the same line as instruction
Recifarium 0:df922596d756 218 ;-----------------------------------
Recifarium 1:1224cf3799a5 219 LTx LINK LDup
Recifarium 0:df922596d756 220 DCB 4
Recifarium 0:df922596d756 221 DCB "EMIT"
Recifarium 0:df922596d756 222
Recifarium 0:df922596d756 223 ;-----------------------------------
Recifarium 0:df922596d756 224 ; Place here your code for the Emit
Recifarium 0:df922596d756 225 ; routine
Recifarium 0:df922596d756 226 ; If it is a high level put a doCol
Recifarium 1:1224cf3799a5 227 ; at the beginning and an Exit at the end
Recifarium 0:df922596d756 228 ;-----------------------------------
Recifarium 1:1224cf3799a5 229 Emit DCD xEmit
Recifarium 0:df922596d756 230 xEmit LDR r1,=(USART0)
Recifarium 0:df922596d756 231 Emit1 LDR r2,[r1,#STAT]
Recifarium 0:df922596d756 232 LSRS r2,#3
Recifarium 0:df922596d756 233 BCC Emit1 ; ? ready to Xmit
Recifarium 0:df922596d756 234 STR TOS,[r1,#TXDAT] ; Xmit
Recifarium 0:df922596d756 235 POP {TOS} ; Discard & Update TOS
Recifarium 1:1224cf3799a5 236 Next
Recifarium 0:df922596d756 237
Recifarium 0:df922596d756 238 ;-----------------------------------
Recifarium 0:df922596d756 239 ; DONT Change the 4 lines below
Recifarium 0:df922596d756 240 ; and leave the xRecv label on
Recifarium 0:df922596d756 241 ; the same line as instruction
Recifarium 0:df922596d756 242 ;-----------------------------------
Recifarium 0:df922596d756 243 LRecv LINK LTx
Recifarium 0:df922596d756 244 DCB 4
Recifarium 0:df922596d756 245 DCB "KEY?"
Recifarium 1:1224cf3799a5 246 KeyQ DCD Recv0
Recifarium 0:df922596d756 247 ;-----------------------------------
Recifarium 0:df922596d756 248 ; Place here your code for the Key?
Recifarium 0:df922596d756 249 ; routine
Recifarium 0:df922596d756 250 ; If it is a high level put a doCol
Recifarium 0:df922596d756 251 ; at the beginning and an Exit at the end
Recifarium 0:df922596d756 252 ;-----------------------------------
Recifarium 1:1224cf3799a5 253
Recifarium 1:1224cf3799a5 254 Recv0 PUSH {TOS}
Recifarium 0:df922596d756 255 LDR r1,=(USART0)
Recifarium 0:df922596d756 256 LDR r2,[r1,#STAT]
Recifarium 0:df922596d756 257 LSRS r2,#1
Recifarium 0:df922596d756 258 BCC Recv1
Recifarium 0:df922596d756 259 LDR TOS,=0xffffffff ; True flag
Recifarium 0:df922596d756 260 B Recv2
Recifarium 0:df922596d756 261 Recv1 SUBS TOS,TOS ; Clear TOS (false falg)
Recifarium 1:1224cf3799a5 262 Recv2 Next
Recifarium 0:df922596d756 263
Recifarium 0:df922596d756 264 ;-----------------------------------
Recifarium 0:df922596d756 265 ; DONT Change the 4 lines below
Recifarium 0:df922596d756 266 ;-----------------------------------
Recifarium 0:df922596d756 267 LKey LINK LRecv
Recifarium 0:df922596d756 268 DCB 3
Recifarium 0:df922596d756 269 DCB "KEY"
Recifarium 1:1224cf3799a5 270 Key DCD xKey
Recifarium 0:df922596d756 271 ;-----------------------------------
Recifarium 0:df922596d756 272 ; Place here your code for the Key
Recifarium 0:df922596d756 273 ; routine
Recifarium 0:df922596d756 274 ; If it is a high level put a doCol
Recifarium 0:df922596d756 275 ; at the begenning and an Exit at the end
Recifarium 0:df922596d756 276 ;-----------------------------------
Recifarium 0:df922596d756 277 xKey PUSH {TOS}
Recifarium 0:df922596d756 278 LDR r1,=(USART0)
Recifarium 0:df922596d756 279 Key1 LDR r2,[r1,#STAT]
Recifarium 0:df922596d756 280 LSRS r2,#1
Recifarium 0:df922596d756 281 BCC Key1
Recifarium 0:df922596d756 282 LDR TOS,[r1,#RXDAT]
Recifarium 1:1224cf3799a5 283 Next
Recifarium 0:df922596d756 284 END