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TARGET_NUCLEO_F411RE/stm32f411xe.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
88:9327015d4013 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f411xe.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V2.1.0
bogdanm 86:04dd9b1680ae 6 * @date 19-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
bogdanm 86:04dd9b1680ae 8 *
bogdanm 86:04dd9b1680ae 9 * This file contains:
bogdanm 86:04dd9b1680ae 10 * - Data structures and the address mapping for all peripherals
bogdanm 86:04dd9b1680ae 11 * - Peripheral's registers declarations and bits definition
bogdanm 88:9327015d4013 12 * - Macros to access peripheral’s registers hardware
bogdanm 86:04dd9b1680ae 13 *
bogdanm 86:04dd9b1680ae 14 ******************************************************************************
bogdanm 86:04dd9b1680ae 15 * @attention
bogdanm 86:04dd9b1680ae 16 *
bogdanm 86:04dd9b1680ae 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 18 *
bogdanm 86:04dd9b1680ae 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 20 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 22 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 25 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 27 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 28 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 29 *
bogdanm 86:04dd9b1680ae 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 40 *
bogdanm 86:04dd9b1680ae 41 ******************************************************************************
bogdanm 86:04dd9b1680ae 42 */
bogdanm 86:04dd9b1680ae 43
bogdanm 86:04dd9b1680ae 44 /** @addtogroup CMSIS
bogdanm 86:04dd9b1680ae 45 * @{
bogdanm 86:04dd9b1680ae 46 */
bogdanm 86:04dd9b1680ae 47
bogdanm 88:9327015d4013 48 /** @addtogroup stm32f411xe
bogdanm 86:04dd9b1680ae 49 * @{
bogdanm 86:04dd9b1680ae 50 */
bogdanm 86:04dd9b1680ae 51
bogdanm 88:9327015d4013 52 #ifndef __STM32F411xE_H
bogdanm 88:9327015d4013 53 #define __STM32F411xE_H
bogdanm 86:04dd9b1680ae 54
bogdanm 86:04dd9b1680ae 55 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 56 extern "C" {
bogdanm 86:04dd9b1680ae 57 #endif /* __cplusplus */
bogdanm 86:04dd9b1680ae 58
bogdanm 86:04dd9b1680ae 59
bogdanm 86:04dd9b1680ae 60 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 86:04dd9b1680ae 61 * @{
bogdanm 86:04dd9b1680ae 62 */
bogdanm 86:04dd9b1680ae 63
bogdanm 86:04dd9b1680ae 64 /**
bogdanm 86:04dd9b1680ae 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
bogdanm 86:04dd9b1680ae 66 */
bogdanm 86:04dd9b1680ae 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
bogdanm 86:04dd9b1680ae 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
bogdanm 86:04dd9b1680ae 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
bogdanm 86:04dd9b1680ae 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 86:04dd9b1680ae 71 #define __FPU_PRESENT 1 /*!< FPU present */
bogdanm 86:04dd9b1680ae 72
bogdanm 86:04dd9b1680ae 73 /**
bogdanm 86:04dd9b1680ae 74 * @}
bogdanm 86:04dd9b1680ae 75 */
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 /** @addtogroup Peripheral_interrupt_number_definition
bogdanm 86:04dd9b1680ae 78 * @{
bogdanm 86:04dd9b1680ae 79 */
bogdanm 86:04dd9b1680ae 80
bogdanm 86:04dd9b1680ae 81 /**
bogdanm 86:04dd9b1680ae 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
bogdanm 86:04dd9b1680ae 83 * in @ref Library_configuration_section
bogdanm 86:04dd9b1680ae 84 */
bogdanm 86:04dd9b1680ae 85 typedef enum
bogdanm 86:04dd9b1680ae 86 {
bogdanm 86:04dd9b1680ae 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
bogdanm 86:04dd9b1680ae 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 86:04dd9b1680ae 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
bogdanm 86:04dd9b1680ae 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
bogdanm 86:04dd9b1680ae 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
bogdanm 86:04dd9b1680ae 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
bogdanm 86:04dd9b1680ae 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
bogdanm 86:04dd9b1680ae 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
bogdanm 86:04dd9b1680ae 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
bogdanm 86:04dd9b1680ae 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
bogdanm 86:04dd9b1680ae 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 86:04dd9b1680ae 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
bogdanm 86:04dd9b1680ae 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
bogdanm 86:04dd9b1680ae 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
bogdanm 86:04dd9b1680ae 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
bogdanm 86:04dd9b1680ae 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
bogdanm 86:04dd9b1680ae 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
bogdanm 86:04dd9b1680ae 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
bogdanm 86:04dd9b1680ae 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
bogdanm 86:04dd9b1680ae 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
bogdanm 86:04dd9b1680ae 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
bogdanm 86:04dd9b1680ae 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
bogdanm 86:04dd9b1680ae 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
bogdanm 86:04dd9b1680ae 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
bogdanm 86:04dd9b1680ae 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
bogdanm 86:04dd9b1680ae 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
bogdanm 86:04dd9b1680ae 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
bogdanm 86:04dd9b1680ae 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
bogdanm 86:04dd9b1680ae 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
bogdanm 86:04dd9b1680ae 116 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
bogdanm 86:04dd9b1680ae 117 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
bogdanm 86:04dd9b1680ae 118 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
bogdanm 86:04dd9b1680ae 119 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
bogdanm 86:04dd9b1680ae 120 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
bogdanm 86:04dd9b1680ae 121 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
bogdanm 86:04dd9b1680ae 122 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
bogdanm 86:04dd9b1680ae 123 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
bogdanm 86:04dd9b1680ae 124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
bogdanm 86:04dd9b1680ae 125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
bogdanm 86:04dd9b1680ae 126 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
bogdanm 86:04dd9b1680ae 127 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
bogdanm 86:04dd9b1680ae 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
bogdanm 86:04dd9b1680ae 129 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
bogdanm 86:04dd9b1680ae 130 USART1_IRQn = 37, /*!< USART1 global Interrupt */
bogdanm 86:04dd9b1680ae 131 USART2_IRQn = 38, /*!< USART2 global Interrupt */
bogdanm 86:04dd9b1680ae 132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
bogdanm 86:04dd9b1680ae 133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
bogdanm 86:04dd9b1680ae 134 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
bogdanm 86:04dd9b1680ae 135 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
bogdanm 86:04dd9b1680ae 136 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
bogdanm 86:04dd9b1680ae 137 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
bogdanm 86:04dd9b1680ae 138 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
bogdanm 86:04dd9b1680ae 139 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
bogdanm 86:04dd9b1680ae 140 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
bogdanm 86:04dd9b1680ae 141 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
bogdanm 86:04dd9b1680ae 142 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
bogdanm 86:04dd9b1680ae 143 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
bogdanm 86:04dd9b1680ae 144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
bogdanm 86:04dd9b1680ae 145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
bogdanm 86:04dd9b1680ae 146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
bogdanm 86:04dd9b1680ae 147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
bogdanm 86:04dd9b1680ae 148 USART6_IRQn = 71, /*!< USART6 global interrupt */
bogdanm 86:04dd9b1680ae 149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
bogdanm 86:04dd9b1680ae 150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
bogdanm 86:04dd9b1680ae 151 FPU_IRQn = 81, /*!< FPU global interrupt */
bogdanm 86:04dd9b1680ae 152 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
bogdanm 86:04dd9b1680ae 153 SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
bogdanm 86:04dd9b1680ae 154 } IRQn_Type;
bogdanm 86:04dd9b1680ae 155
bogdanm 86:04dd9b1680ae 156 /**
bogdanm 86:04dd9b1680ae 157 * @}
bogdanm 86:04dd9b1680ae 158 */
bogdanm 86:04dd9b1680ae 159
bogdanm 86:04dd9b1680ae 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm 86:04dd9b1680ae 161 #include "system_stm32f4xx.h"
bogdanm 86:04dd9b1680ae 162 #include <stdint.h>
bogdanm 86:04dd9b1680ae 163
bogdanm 86:04dd9b1680ae 164 /** @addtogroup Peripheral_registers_structures
bogdanm 86:04dd9b1680ae 165 * @{
bogdanm 86:04dd9b1680ae 166 */
bogdanm 86:04dd9b1680ae 167
bogdanm 86:04dd9b1680ae 168 /**
bogdanm 86:04dd9b1680ae 169 * @brief Analog to Digital Converter
bogdanm 86:04dd9b1680ae 170 */
bogdanm 86:04dd9b1680ae 171
bogdanm 86:04dd9b1680ae 172 typedef struct
bogdanm 86:04dd9b1680ae 173 {
bogdanm 86:04dd9b1680ae 174 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 175 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 176 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 177 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 178 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 188 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
bogdanm 86:04dd9b1680ae 189 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
bogdanm 86:04dd9b1680ae 190 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
bogdanm 86:04dd9b1680ae 191 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
bogdanm 86:04dd9b1680ae 192 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
bogdanm 86:04dd9b1680ae 193 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
bogdanm 86:04dd9b1680ae 194 } ADC_TypeDef;
bogdanm 86:04dd9b1680ae 195
bogdanm 86:04dd9b1680ae 196 typedef struct
bogdanm 86:04dd9b1680ae 197 {
bogdanm 86:04dd9b1680ae 198 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
bogdanm 86:04dd9b1680ae 199 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
bogdanm 86:04dd9b1680ae 200 __IO uint32_t CDR; /*!< ADC common regular data register for dual
bogdanm 86:04dd9b1680ae 201 AND triple modes, Address offset: ADC1 base address + 0x308 */
bogdanm 86:04dd9b1680ae 202 } ADC_Common_TypeDef;
bogdanm 86:04dd9b1680ae 203
bogdanm 86:04dd9b1680ae 204 /**
bogdanm 86:04dd9b1680ae 205 * @brief CRC calculation unit
bogdanm 86:04dd9b1680ae 206 */
bogdanm 86:04dd9b1680ae 207
bogdanm 86:04dd9b1680ae 208 typedef struct
bogdanm 86:04dd9b1680ae 209 {
bogdanm 86:04dd9b1680ae 210 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 211 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 212 uint8_t RESERVED0; /*!< Reserved, 0x05 */
bogdanm 86:04dd9b1680ae 213 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 86:04dd9b1680ae 214 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 215 } CRC_TypeDef;
bogdanm 86:04dd9b1680ae 216
bogdanm 86:04dd9b1680ae 217 /**
bogdanm 86:04dd9b1680ae 218 * @brief Debug MCU
bogdanm 86:04dd9b1680ae 219 */
bogdanm 86:04dd9b1680ae 220
bogdanm 86:04dd9b1680ae 221 typedef struct
bogdanm 86:04dd9b1680ae 222 {
bogdanm 86:04dd9b1680ae 223 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 224 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 225 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 226 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 227 }DBGMCU_TypeDef;
bogdanm 86:04dd9b1680ae 228
bogdanm 86:04dd9b1680ae 229
bogdanm 86:04dd9b1680ae 230 /**
bogdanm 86:04dd9b1680ae 231 * @brief DMA Controller
bogdanm 86:04dd9b1680ae 232 */
bogdanm 86:04dd9b1680ae 233
bogdanm 86:04dd9b1680ae 234 typedef struct
bogdanm 86:04dd9b1680ae 235 {
bogdanm 86:04dd9b1680ae 236 __IO uint32_t CR; /*!< DMA stream x configuration register */
bogdanm 86:04dd9b1680ae 237 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
bogdanm 86:04dd9b1680ae 238 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
bogdanm 86:04dd9b1680ae 239 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
bogdanm 86:04dd9b1680ae 240 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
bogdanm 86:04dd9b1680ae 241 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
bogdanm 86:04dd9b1680ae 242 } DMA_Stream_TypeDef;
bogdanm 86:04dd9b1680ae 243
bogdanm 86:04dd9b1680ae 244 typedef struct
bogdanm 86:04dd9b1680ae 245 {
bogdanm 86:04dd9b1680ae 246 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 247 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 248 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 249 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 250 } DMA_TypeDef;
bogdanm 86:04dd9b1680ae 251
bogdanm 86:04dd9b1680ae 252
bogdanm 86:04dd9b1680ae 253 /**
bogdanm 86:04dd9b1680ae 254 * @brief External Interrupt/Event Controller
bogdanm 86:04dd9b1680ae 255 */
bogdanm 86:04dd9b1680ae 256
bogdanm 86:04dd9b1680ae 257 typedef struct
bogdanm 86:04dd9b1680ae 258 {
bogdanm 86:04dd9b1680ae 259 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 260 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 261 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 262 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 263 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 264 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 265 } EXTI_TypeDef;
bogdanm 86:04dd9b1680ae 266
bogdanm 86:04dd9b1680ae 267 /**
bogdanm 86:04dd9b1680ae 268 * @brief FLASH Registers
bogdanm 86:04dd9b1680ae 269 */
bogdanm 86:04dd9b1680ae 270
bogdanm 86:04dd9b1680ae 271 typedef struct
bogdanm 86:04dd9b1680ae 272 {
bogdanm 86:04dd9b1680ae 273 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 274 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 275 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 276 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 277 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 278 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 279 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 280 } FLASH_TypeDef;
bogdanm 86:04dd9b1680ae 281
bogdanm 86:04dd9b1680ae 282 /**
bogdanm 86:04dd9b1680ae 283 * @brief General Purpose I/O
bogdanm 86:04dd9b1680ae 284 */
bogdanm 86:04dd9b1680ae 285
bogdanm 86:04dd9b1680ae 286 typedef struct
bogdanm 86:04dd9b1680ae 287 {
bogdanm 86:04dd9b1680ae 288 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 289 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 290 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 291 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 292 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 293 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 294 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 295 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
bogdanm 86:04dd9b1680ae 296 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 297 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
bogdanm 86:04dd9b1680ae 298 } GPIO_TypeDef;
bogdanm 86:04dd9b1680ae 299
bogdanm 86:04dd9b1680ae 300 /**
bogdanm 86:04dd9b1680ae 301 * @brief System configuration controller
bogdanm 86:04dd9b1680ae 302 */
bogdanm 86:04dd9b1680ae 303
bogdanm 86:04dd9b1680ae 304 typedef struct
bogdanm 86:04dd9b1680ae 305 {
bogdanm 86:04dd9b1680ae 306 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 307 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 308 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
bogdanm 86:04dd9b1680ae 309 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
bogdanm 86:04dd9b1680ae 310 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 311 } SYSCFG_TypeDef;
bogdanm 86:04dd9b1680ae 312
bogdanm 86:04dd9b1680ae 313 /**
bogdanm 86:04dd9b1680ae 314 * @brief Inter-integrated Circuit Interface
bogdanm 86:04dd9b1680ae 315 */
bogdanm 86:04dd9b1680ae 316
bogdanm 86:04dd9b1680ae 317 typedef struct
bogdanm 86:04dd9b1680ae 318 {
bogdanm 86:04dd9b1680ae 319 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 320 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 321 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 322 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 323 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 324 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 325 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 326 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 327 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 328 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 329 } I2C_TypeDef;
bogdanm 86:04dd9b1680ae 330
bogdanm 86:04dd9b1680ae 331 /**
bogdanm 86:04dd9b1680ae 332 * @brief Independent WATCHDOG
bogdanm 86:04dd9b1680ae 333 */
bogdanm 86:04dd9b1680ae 334
bogdanm 86:04dd9b1680ae 335 typedef struct
bogdanm 86:04dd9b1680ae 336 {
bogdanm 86:04dd9b1680ae 337 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 338 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 339 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 340 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 341 } IWDG_TypeDef;
bogdanm 86:04dd9b1680ae 342
bogdanm 86:04dd9b1680ae 343 /**
bogdanm 86:04dd9b1680ae 344 * @brief Power Control
bogdanm 86:04dd9b1680ae 345 */
bogdanm 86:04dd9b1680ae 346
bogdanm 86:04dd9b1680ae 347 typedef struct
bogdanm 86:04dd9b1680ae 348 {
bogdanm 86:04dd9b1680ae 349 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 350 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 351 } PWR_TypeDef;
bogdanm 86:04dd9b1680ae 352
bogdanm 86:04dd9b1680ae 353 /**
bogdanm 86:04dd9b1680ae 354 * @brief Reset and Clock Control
bogdanm 86:04dd9b1680ae 355 */
bogdanm 86:04dd9b1680ae 356
bogdanm 86:04dd9b1680ae 357 typedef struct
bogdanm 86:04dd9b1680ae 358 {
bogdanm 86:04dd9b1680ae 359 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 360 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 361 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 362 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 363 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 364 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 365 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 366 uint32_t RESERVED0; /*!< Reserved, 0x1C */
bogdanm 86:04dd9b1680ae 367 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 368 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 369 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
bogdanm 86:04dd9b1680ae 370 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 371 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 372 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
bogdanm 86:04dd9b1680ae 373 uint32_t RESERVED2; /*!< Reserved, 0x3C */
bogdanm 86:04dd9b1680ae 374 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
bogdanm 86:04dd9b1680ae 375 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
bogdanm 86:04dd9b1680ae 376 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
bogdanm 86:04dd9b1680ae 377 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
bogdanm 86:04dd9b1680ae 378 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
bogdanm 86:04dd9b1680ae 379 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
bogdanm 86:04dd9b1680ae 380 uint32_t RESERVED4; /*!< Reserved, 0x5C */
bogdanm 86:04dd9b1680ae 381 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
bogdanm 86:04dd9b1680ae 382 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
bogdanm 86:04dd9b1680ae 383 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
bogdanm 86:04dd9b1680ae 384 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
bogdanm 86:04dd9b1680ae 385 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
bogdanm 86:04dd9b1680ae 386 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
bogdanm 86:04dd9b1680ae 387 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
bogdanm 86:04dd9b1680ae 388 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
bogdanm 86:04dd9b1680ae 389
bogdanm 86:04dd9b1680ae 390 } RCC_TypeDef;
bogdanm 86:04dd9b1680ae 391
bogdanm 86:04dd9b1680ae 392 /**
bogdanm 86:04dd9b1680ae 393 * @brief Real-Time Clock
bogdanm 86:04dd9b1680ae 394 */
bogdanm 86:04dd9b1680ae 395
bogdanm 86:04dd9b1680ae 396 typedef struct
bogdanm 86:04dd9b1680ae 397 {
bogdanm 86:04dd9b1680ae 398 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 399 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 400 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 401 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 402 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 403 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 404 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 405 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 406 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 407 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 408 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 409 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 410 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 411 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 412 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 86:04dd9b1680ae 413 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 86:04dd9b1680ae 414 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
bogdanm 86:04dd9b1680ae 415 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 86:04dd9b1680ae 416 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
bogdanm 86:04dd9b1680ae 417 uint32_t RESERVED7; /*!< Reserved, 0x4C */
bogdanm 86:04dd9b1680ae 418 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
bogdanm 86:04dd9b1680ae 419 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 86:04dd9b1680ae 420 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 86:04dd9b1680ae 421 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 86:04dd9b1680ae 422 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 86:04dd9b1680ae 423 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
bogdanm 86:04dd9b1680ae 424 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
bogdanm 86:04dd9b1680ae 425 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
bogdanm 86:04dd9b1680ae 426 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
bogdanm 86:04dd9b1680ae 427 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
bogdanm 86:04dd9b1680ae 428 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
bogdanm 86:04dd9b1680ae 429 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
bogdanm 86:04dd9b1680ae 430 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
bogdanm 86:04dd9b1680ae 431 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
bogdanm 86:04dd9b1680ae 432 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
bogdanm 86:04dd9b1680ae 433 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
bogdanm 86:04dd9b1680ae 434 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
bogdanm 86:04dd9b1680ae 435 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
bogdanm 86:04dd9b1680ae 436 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
bogdanm 86:04dd9b1680ae 437 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
bogdanm 86:04dd9b1680ae 438 } RTC_TypeDef;
bogdanm 86:04dd9b1680ae 439
bogdanm 86:04dd9b1680ae 440
bogdanm 86:04dd9b1680ae 441 /**
bogdanm 86:04dd9b1680ae 442 * @brief SD host Interface
bogdanm 86:04dd9b1680ae 443 */
bogdanm 86:04dd9b1680ae 444
bogdanm 86:04dd9b1680ae 445 typedef struct
bogdanm 86:04dd9b1680ae 446 {
bogdanm 86:04dd9b1680ae 447 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 448 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 449 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 450 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 451 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 452 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 453 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 454 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 455 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 456 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 457 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 458 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 459 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 460 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 461 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
bogdanm 86:04dd9b1680ae 462 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
bogdanm 86:04dd9b1680ae 463 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
bogdanm 86:04dd9b1680ae 464 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
bogdanm 86:04dd9b1680ae 465 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
bogdanm 86:04dd9b1680ae 466 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
bogdanm 86:04dd9b1680ae 467 } SDIO_TypeDef;
bogdanm 86:04dd9b1680ae 468
bogdanm 86:04dd9b1680ae 469 /**
bogdanm 86:04dd9b1680ae 470 * @brief Serial Peripheral Interface
bogdanm 86:04dd9b1680ae 471 */
bogdanm 86:04dd9b1680ae 472
bogdanm 86:04dd9b1680ae 473 typedef struct
bogdanm 86:04dd9b1680ae 474 {
bogdanm 86:04dd9b1680ae 475 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 476 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 477 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 478 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 479 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 480 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 481 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 482 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 483 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 484 } SPI_TypeDef;
bogdanm 86:04dd9b1680ae 485
bogdanm 86:04dd9b1680ae 486 /**
bogdanm 86:04dd9b1680ae 487 * @brief TIM
bogdanm 86:04dd9b1680ae 488 */
bogdanm 86:04dd9b1680ae 489
bogdanm 86:04dd9b1680ae 490 typedef struct
bogdanm 86:04dd9b1680ae 491 {
bogdanm 86:04dd9b1680ae 492 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 493 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 494 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 495 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 496 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 497 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 498 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 499 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 86:04dd9b1680ae 500 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 86:04dd9b1680ae 501 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 86:04dd9b1680ae 502 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
bogdanm 86:04dd9b1680ae 503 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 86:04dd9b1680ae 504 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 86:04dd9b1680ae 505 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 86:04dd9b1680ae 506 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 86:04dd9b1680ae 507 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 86:04dd9b1680ae 508 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 86:04dd9b1680ae 509 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 86:04dd9b1680ae 510 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 86:04dd9b1680ae 511 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
bogdanm 86:04dd9b1680ae 512 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 86:04dd9b1680ae 513 } TIM_TypeDef;
bogdanm 86:04dd9b1680ae 514
bogdanm 86:04dd9b1680ae 515 /**
bogdanm 86:04dd9b1680ae 516 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 86:04dd9b1680ae 517 */
bogdanm 86:04dd9b1680ae 518
bogdanm 86:04dd9b1680ae 519 typedef struct
bogdanm 86:04dd9b1680ae 520 {
bogdanm 86:04dd9b1680ae 521 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 522 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 523 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 524 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
bogdanm 86:04dd9b1680ae 525 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
bogdanm 86:04dd9b1680ae 526 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
bogdanm 86:04dd9b1680ae 527 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
bogdanm 86:04dd9b1680ae 528 } USART_TypeDef;
bogdanm 86:04dd9b1680ae 529
bogdanm 86:04dd9b1680ae 530 /**
bogdanm 86:04dd9b1680ae 531 * @brief Window WATCHDOG
bogdanm 86:04dd9b1680ae 532 */
bogdanm 86:04dd9b1680ae 533
bogdanm 86:04dd9b1680ae 534 typedef struct
bogdanm 86:04dd9b1680ae 535 {
bogdanm 86:04dd9b1680ae 536 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 86:04dd9b1680ae 537 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 86:04dd9b1680ae 538 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 86:04dd9b1680ae 539 } WWDG_TypeDef;
bogdanm 86:04dd9b1680ae 540
bogdanm 86:04dd9b1680ae 541
bogdanm 86:04dd9b1680ae 542 /**
bogdanm 86:04dd9b1680ae 543 * @brief __USB_OTG_Core_register
bogdanm 86:04dd9b1680ae 544 */
bogdanm 86:04dd9b1680ae 545 typedef struct
bogdanm 86:04dd9b1680ae 546 {
bogdanm 86:04dd9b1680ae 547 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
bogdanm 86:04dd9b1680ae 548 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
bogdanm 86:04dd9b1680ae 549 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
bogdanm 86:04dd9b1680ae 550 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
bogdanm 86:04dd9b1680ae 551 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
bogdanm 86:04dd9b1680ae 552 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
bogdanm 86:04dd9b1680ae 553 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
bogdanm 86:04dd9b1680ae 554 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
bogdanm 86:04dd9b1680ae 555 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
bogdanm 86:04dd9b1680ae 556 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
bogdanm 86:04dd9b1680ae 557 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
bogdanm 86:04dd9b1680ae 558 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
bogdanm 86:04dd9b1680ae 559 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
bogdanm 86:04dd9b1680ae 560 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
bogdanm 86:04dd9b1680ae 561 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
bogdanm 86:04dd9b1680ae 562 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
bogdanm 86:04dd9b1680ae 563 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
bogdanm 86:04dd9b1680ae 564 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
bogdanm 86:04dd9b1680ae 565 }
bogdanm 86:04dd9b1680ae 566 USB_OTG_GlobalTypeDef;
bogdanm 86:04dd9b1680ae 567
bogdanm 86:04dd9b1680ae 568
bogdanm 86:04dd9b1680ae 569
bogdanm 86:04dd9b1680ae 570 /**
bogdanm 86:04dd9b1680ae 571 * @brief __device_Registers
bogdanm 86:04dd9b1680ae 572 */
bogdanm 86:04dd9b1680ae 573 typedef struct
bogdanm 86:04dd9b1680ae 574 {
bogdanm 86:04dd9b1680ae 575 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
bogdanm 86:04dd9b1680ae 576 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
bogdanm 86:04dd9b1680ae 577 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
bogdanm 86:04dd9b1680ae 578 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
bogdanm 86:04dd9b1680ae 579 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
bogdanm 86:04dd9b1680ae 580 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
bogdanm 86:04dd9b1680ae 581 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
bogdanm 86:04dd9b1680ae 582 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
bogdanm 86:04dd9b1680ae 583 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
bogdanm 86:04dd9b1680ae 584 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
bogdanm 86:04dd9b1680ae 585 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
bogdanm 86:04dd9b1680ae 586 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
bogdanm 86:04dd9b1680ae 587 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
bogdanm 86:04dd9b1680ae 588 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
bogdanm 86:04dd9b1680ae 589 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
bogdanm 86:04dd9b1680ae 590 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
bogdanm 86:04dd9b1680ae 591 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
bogdanm 86:04dd9b1680ae 592 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
bogdanm 86:04dd9b1680ae 593 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
bogdanm 86:04dd9b1680ae 594 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
bogdanm 86:04dd9b1680ae 595 }
bogdanm 86:04dd9b1680ae 596 USB_OTG_DeviceTypeDef;
bogdanm 86:04dd9b1680ae 597
bogdanm 86:04dd9b1680ae 598
bogdanm 86:04dd9b1680ae 599 /**
bogdanm 86:04dd9b1680ae 600 * @brief __IN_Endpoint-Specific_Register
bogdanm 86:04dd9b1680ae 601 */
bogdanm 86:04dd9b1680ae 602 typedef struct
bogdanm 86:04dd9b1680ae 603 {
bogdanm 86:04dd9b1680ae 604 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
bogdanm 86:04dd9b1680ae 605 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
bogdanm 86:04dd9b1680ae 606 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
bogdanm 86:04dd9b1680ae 607 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
bogdanm 86:04dd9b1680ae 608 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
bogdanm 86:04dd9b1680ae 609 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
bogdanm 86:04dd9b1680ae 610 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
bogdanm 86:04dd9b1680ae 611 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
bogdanm 86:04dd9b1680ae 612 }
bogdanm 86:04dd9b1680ae 613 USB_OTG_INEndpointTypeDef;
bogdanm 86:04dd9b1680ae 614
bogdanm 86:04dd9b1680ae 615
bogdanm 86:04dd9b1680ae 616 /**
bogdanm 86:04dd9b1680ae 617 * @brief __OUT_Endpoint-Specific_Registers
bogdanm 86:04dd9b1680ae 618 */
bogdanm 86:04dd9b1680ae 619 typedef struct
bogdanm 86:04dd9b1680ae 620 {
bogdanm 86:04dd9b1680ae 621 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
bogdanm 86:04dd9b1680ae 622 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
bogdanm 86:04dd9b1680ae 623 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
bogdanm 86:04dd9b1680ae 624 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
bogdanm 86:04dd9b1680ae 625 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
bogdanm 86:04dd9b1680ae 626 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
bogdanm 86:04dd9b1680ae 627 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
bogdanm 86:04dd9b1680ae 628 }
bogdanm 86:04dd9b1680ae 629 USB_OTG_OUTEndpointTypeDef;
bogdanm 86:04dd9b1680ae 630
bogdanm 86:04dd9b1680ae 631
bogdanm 86:04dd9b1680ae 632 /**
bogdanm 86:04dd9b1680ae 633 * @brief __Host_Mode_Register_Structures
bogdanm 86:04dd9b1680ae 634 */
bogdanm 86:04dd9b1680ae 635 typedef struct
bogdanm 86:04dd9b1680ae 636 {
bogdanm 86:04dd9b1680ae 637 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
bogdanm 86:04dd9b1680ae 638 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
bogdanm 86:04dd9b1680ae 639 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
bogdanm 86:04dd9b1680ae 640 uint32_t Reserved40C; /* Reserved 40Ch*/
bogdanm 86:04dd9b1680ae 641 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
bogdanm 86:04dd9b1680ae 642 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
bogdanm 86:04dd9b1680ae 643 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
bogdanm 86:04dd9b1680ae 644 }
bogdanm 86:04dd9b1680ae 645 USB_OTG_HostTypeDef;
bogdanm 86:04dd9b1680ae 646
bogdanm 86:04dd9b1680ae 647
bogdanm 86:04dd9b1680ae 648 /**
bogdanm 86:04dd9b1680ae 649 * @brief __Host_Channel_Specific_Registers
bogdanm 86:04dd9b1680ae 650 */
bogdanm 86:04dd9b1680ae 651 typedef struct
bogdanm 86:04dd9b1680ae 652 {
bogdanm 86:04dd9b1680ae 653 __IO uint32_t HCCHAR;
bogdanm 86:04dd9b1680ae 654 __IO uint32_t HCSPLT;
bogdanm 86:04dd9b1680ae 655 __IO uint32_t HCINT;
bogdanm 86:04dd9b1680ae 656 __IO uint32_t HCINTMSK;
bogdanm 86:04dd9b1680ae 657 __IO uint32_t HCTSIZ;
bogdanm 86:04dd9b1680ae 658 __IO uint32_t HCDMA;
bogdanm 86:04dd9b1680ae 659 uint32_t Reserved[2];
bogdanm 86:04dd9b1680ae 660 }
bogdanm 86:04dd9b1680ae 661 USB_OTG_HostChannelTypeDef;
bogdanm 86:04dd9b1680ae 662
bogdanm 86:04dd9b1680ae 663
bogdanm 86:04dd9b1680ae 664 /**
bogdanm 86:04dd9b1680ae 665 * @brief Peripheral_memory_map
bogdanm 86:04dd9b1680ae 666 */
bogdanm 86:04dd9b1680ae 667 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
bogdanm 86:04dd9b1680ae 668 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
bogdanm 86:04dd9b1680ae 669 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
bogdanm 86:04dd9b1680ae 670 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
bogdanm 86:04dd9b1680ae 671 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
bogdanm 86:04dd9b1680ae 672 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
bogdanm 86:04dd9b1680ae 673 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
bogdanm 86:04dd9b1680ae 674 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
bogdanm 86:04dd9b1680ae 675 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
bogdanm 86:04dd9b1680ae 676 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
bogdanm 86:04dd9b1680ae 677 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
bogdanm 86:04dd9b1680ae 678 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
bogdanm 86:04dd9b1680ae 679 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
bogdanm 86:04dd9b1680ae 680 #define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
bogdanm 86:04dd9b1680ae 681
bogdanm 86:04dd9b1680ae 682 /* Legacy defines */
bogdanm 86:04dd9b1680ae 683 #define SRAM_BASE SRAM1_BASE
bogdanm 86:04dd9b1680ae 684 #define SRAM_BB_BASE SRAM1_BB_BASE
bogdanm 86:04dd9b1680ae 685
bogdanm 86:04dd9b1680ae 686
bogdanm 86:04dd9b1680ae 687 /*!< Peripheral memory map */
bogdanm 86:04dd9b1680ae 688 #define APB1PERIPH_BASE PERIPH_BASE
bogdanm 86:04dd9b1680ae 689 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
bogdanm 86:04dd9b1680ae 690 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm 86:04dd9b1680ae 691 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
bogdanm 86:04dd9b1680ae 692
bogdanm 86:04dd9b1680ae 693 /*!< APB1 peripherals */
bogdanm 86:04dd9b1680ae 694 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
bogdanm 86:04dd9b1680ae 695 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
bogdanm 86:04dd9b1680ae 696 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
bogdanm 86:04dd9b1680ae 697 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
bogdanm 86:04dd9b1680ae 698 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
bogdanm 86:04dd9b1680ae 699 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
bogdanm 86:04dd9b1680ae 700 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
bogdanm 86:04dd9b1680ae 701 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
bogdanm 86:04dd9b1680ae 702 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
bogdanm 86:04dd9b1680ae 703 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
bogdanm 86:04dd9b1680ae 704 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
bogdanm 86:04dd9b1680ae 705 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
bogdanm 86:04dd9b1680ae 706 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
bogdanm 86:04dd9b1680ae 707 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
bogdanm 86:04dd9b1680ae 708 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
bogdanm 86:04dd9b1680ae 709 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
bogdanm 86:04dd9b1680ae 710
bogdanm 86:04dd9b1680ae 711 /*!< APB2 peripherals */
bogdanm 86:04dd9b1680ae 712 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
bogdanm 86:04dd9b1680ae 713 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
bogdanm 86:04dd9b1680ae 714 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
bogdanm 86:04dd9b1680ae 715 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
bogdanm 86:04dd9b1680ae 716 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
bogdanm 86:04dd9b1680ae 717 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
bogdanm 86:04dd9b1680ae 718 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
bogdanm 86:04dd9b1680ae 719 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
bogdanm 86:04dd9b1680ae 720 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
bogdanm 86:04dd9b1680ae 721 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
bogdanm 86:04dd9b1680ae 722 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
bogdanm 86:04dd9b1680ae 723 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
bogdanm 86:04dd9b1680ae 724 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
bogdanm 86:04dd9b1680ae 725 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
bogdanm 86:04dd9b1680ae 726
bogdanm 86:04dd9b1680ae 727 /*!< AHB1 peripherals */
bogdanm 86:04dd9b1680ae 728 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
bogdanm 86:04dd9b1680ae 729 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
bogdanm 86:04dd9b1680ae 730 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
bogdanm 86:04dd9b1680ae 731 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
bogdanm 86:04dd9b1680ae 732 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
bogdanm 86:04dd9b1680ae 733 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
bogdanm 86:04dd9b1680ae 734 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
bogdanm 86:04dd9b1680ae 735 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
bogdanm 86:04dd9b1680ae 736 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
bogdanm 86:04dd9b1680ae 737 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
bogdanm 86:04dd9b1680ae 738 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
bogdanm 86:04dd9b1680ae 739 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
bogdanm 86:04dd9b1680ae 740 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
bogdanm 86:04dd9b1680ae 741 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
bogdanm 86:04dd9b1680ae 742 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
bogdanm 86:04dd9b1680ae 743 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
bogdanm 86:04dd9b1680ae 744 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
bogdanm 86:04dd9b1680ae 745 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
bogdanm 86:04dd9b1680ae 746 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
bogdanm 86:04dd9b1680ae 747 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
bogdanm 86:04dd9b1680ae 748 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
bogdanm 86:04dd9b1680ae 749 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
bogdanm 86:04dd9b1680ae 750 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
bogdanm 86:04dd9b1680ae 751 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
bogdanm 86:04dd9b1680ae 752 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
bogdanm 86:04dd9b1680ae 753 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
bogdanm 86:04dd9b1680ae 754 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
bogdanm 86:04dd9b1680ae 755
bogdanm 86:04dd9b1680ae 756 /* Debug MCU registers base address */
bogdanm 86:04dd9b1680ae 757 #define DBGMCU_BASE ((uint32_t )0xE0042000)
bogdanm 86:04dd9b1680ae 758
bogdanm 86:04dd9b1680ae 759 /*!< USB registers base address */
bogdanm 86:04dd9b1680ae 760 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
bogdanm 86:04dd9b1680ae 761
bogdanm 86:04dd9b1680ae 762 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
bogdanm 86:04dd9b1680ae 763 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
bogdanm 86:04dd9b1680ae 764 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
bogdanm 86:04dd9b1680ae 765 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
bogdanm 86:04dd9b1680ae 766 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
bogdanm 86:04dd9b1680ae 767 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
bogdanm 86:04dd9b1680ae 768 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
bogdanm 86:04dd9b1680ae 769 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
bogdanm 86:04dd9b1680ae 770 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
bogdanm 86:04dd9b1680ae 771 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
bogdanm 86:04dd9b1680ae 772 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
bogdanm 86:04dd9b1680ae 773 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
bogdanm 86:04dd9b1680ae 774
bogdanm 86:04dd9b1680ae 775 /**
bogdanm 86:04dd9b1680ae 776 * @}
bogdanm 86:04dd9b1680ae 777 */
bogdanm 86:04dd9b1680ae 778
bogdanm 86:04dd9b1680ae 779 /** @addtogroup Peripheral_declaration
bogdanm 86:04dd9b1680ae 780 * @{
bogdanm 86:04dd9b1680ae 781 */
bogdanm 86:04dd9b1680ae 782 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 86:04dd9b1680ae 783 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 86:04dd9b1680ae 784 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
bogdanm 86:04dd9b1680ae 785 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
bogdanm 86:04dd9b1680ae 786 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 86:04dd9b1680ae 787 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 86:04dd9b1680ae 788 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 86:04dd9b1680ae 789 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
bogdanm 86:04dd9b1680ae 790 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 86:04dd9b1680ae 791 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
bogdanm 86:04dd9b1680ae 792 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
bogdanm 86:04dd9b1680ae 793 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 86:04dd9b1680ae 794 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 86:04dd9b1680ae 795 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 86:04dd9b1680ae 796 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
bogdanm 86:04dd9b1680ae 797 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 86:04dd9b1680ae 798 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 86:04dd9b1680ae 799 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 86:04dd9b1680ae 800 #define USART6 ((USART_TypeDef *) USART6_BASE)
bogdanm 86:04dd9b1680ae 801 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm 86:04dd9b1680ae 802 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 86:04dd9b1680ae 803 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
bogdanm 86:04dd9b1680ae 804 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 86:04dd9b1680ae 805 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
bogdanm 86:04dd9b1680ae 806 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 86:04dd9b1680ae 807 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 86:04dd9b1680ae 808 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
bogdanm 86:04dd9b1680ae 809 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
bogdanm 86:04dd9b1680ae 810 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
bogdanm 86:04dd9b1680ae 811 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
bogdanm 86:04dd9b1680ae 812 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 86:04dd9b1680ae 813 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 86:04dd9b1680ae 814 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 86:04dd9b1680ae 815 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 86:04dd9b1680ae 816 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm 86:04dd9b1680ae 817 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
bogdanm 86:04dd9b1680ae 818 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 86:04dd9b1680ae 819 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 86:04dd9b1680ae 820 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 86:04dd9b1680ae 821 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 86:04dd9b1680ae 822 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
bogdanm 86:04dd9b1680ae 823 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
bogdanm 86:04dd9b1680ae 824 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
bogdanm 86:04dd9b1680ae 825 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
bogdanm 86:04dd9b1680ae 826 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
bogdanm 86:04dd9b1680ae 827 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
bogdanm 86:04dd9b1680ae 828 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
bogdanm 86:04dd9b1680ae 829 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
bogdanm 86:04dd9b1680ae 830 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
bogdanm 86:04dd9b1680ae 831 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
bogdanm 86:04dd9b1680ae 832 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
bogdanm 86:04dd9b1680ae 833 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
bogdanm 86:04dd9b1680ae 834 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
bogdanm 86:04dd9b1680ae 835 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
bogdanm 86:04dd9b1680ae 836 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
bogdanm 86:04dd9b1680ae 837 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
bogdanm 86:04dd9b1680ae 838 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
bogdanm 86:04dd9b1680ae 839
bogdanm 86:04dd9b1680ae 840 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 86:04dd9b1680ae 841
bogdanm 86:04dd9b1680ae 842 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
bogdanm 86:04dd9b1680ae 843
bogdanm 86:04dd9b1680ae 844 /**
bogdanm 86:04dd9b1680ae 845 * @}
bogdanm 86:04dd9b1680ae 846 */
bogdanm 86:04dd9b1680ae 847
bogdanm 86:04dd9b1680ae 848 /** @addtogroup Exported_constants
bogdanm 86:04dd9b1680ae 849 * @{
bogdanm 86:04dd9b1680ae 850 */
bogdanm 86:04dd9b1680ae 851
bogdanm 86:04dd9b1680ae 852 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 86:04dd9b1680ae 853 * @{
bogdanm 86:04dd9b1680ae 854 */
bogdanm 86:04dd9b1680ae 855
bogdanm 86:04dd9b1680ae 856 /******************************************************************************/
bogdanm 86:04dd9b1680ae 857 /* Peripheral Registers_Bits_Definition */
bogdanm 86:04dd9b1680ae 858 /******************************************************************************/
bogdanm 86:04dd9b1680ae 859
bogdanm 86:04dd9b1680ae 860 /******************************************************************************/
bogdanm 86:04dd9b1680ae 861 /* */
bogdanm 86:04dd9b1680ae 862 /* Analog to Digital Converter */
bogdanm 86:04dd9b1680ae 863 /* */
bogdanm 86:04dd9b1680ae 864 /******************************************************************************/
bogdanm 86:04dd9b1680ae 865 /******************** Bit definition for ADC_SR register ********************/
bogdanm 86:04dd9b1680ae 866 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
bogdanm 86:04dd9b1680ae 867 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
bogdanm 86:04dd9b1680ae 868 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
bogdanm 86:04dd9b1680ae 869 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
bogdanm 86:04dd9b1680ae 870 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
bogdanm 86:04dd9b1680ae 871 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
bogdanm 86:04dd9b1680ae 872
bogdanm 86:04dd9b1680ae 873 /******************* Bit definition for ADC_CR1 register ********************/
bogdanm 86:04dd9b1680ae 874 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
bogdanm 86:04dd9b1680ae 875 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 876 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 877 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 878 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 879 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 880 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
bogdanm 86:04dd9b1680ae 881 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
bogdanm 86:04dd9b1680ae 882 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
bogdanm 86:04dd9b1680ae 883 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
bogdanm 86:04dd9b1680ae 884 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
bogdanm 86:04dd9b1680ae 885 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
bogdanm 86:04dd9b1680ae 886 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
bogdanm 86:04dd9b1680ae 887 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
bogdanm 86:04dd9b1680ae 888 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
bogdanm 86:04dd9b1680ae 889 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 890 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 891 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 892 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
bogdanm 86:04dd9b1680ae 893 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
bogdanm 86:04dd9b1680ae 894 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
bogdanm 86:04dd9b1680ae 895 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 896 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 897 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
bogdanm 86:04dd9b1680ae 898
bogdanm 86:04dd9b1680ae 899 /******************* Bit definition for ADC_CR2 register ********************/
bogdanm 86:04dd9b1680ae 900 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
bogdanm 86:04dd9b1680ae 901 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
bogdanm 86:04dd9b1680ae 902 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
bogdanm 86:04dd9b1680ae 903 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
bogdanm 86:04dd9b1680ae 904 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
bogdanm 86:04dd9b1680ae 905 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
bogdanm 86:04dd9b1680ae 906 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
bogdanm 86:04dd9b1680ae 907 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 908 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 909 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 910 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 911 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
bogdanm 86:04dd9b1680ae 912 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 913 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 914 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
bogdanm 86:04dd9b1680ae 915 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
bogdanm 86:04dd9b1680ae 916 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 917 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 918 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 919 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 920 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
bogdanm 86:04dd9b1680ae 921 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 922 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 923 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
bogdanm 86:04dd9b1680ae 924
bogdanm 86:04dd9b1680ae 925 /****************** Bit definition for ADC_SMPR1 register *******************/
bogdanm 86:04dd9b1680ae 926 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
bogdanm 86:04dd9b1680ae 927 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 928 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 929 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 930 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
bogdanm 86:04dd9b1680ae 931 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 932 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 933 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 934 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
bogdanm 86:04dd9b1680ae 935 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 936 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 937 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 938 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
bogdanm 86:04dd9b1680ae 939 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 940 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 941 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 942 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
bogdanm 86:04dd9b1680ae 943 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 944 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 945 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 946 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
bogdanm 86:04dd9b1680ae 947 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 948 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 949 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 950 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
bogdanm 86:04dd9b1680ae 951 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 952 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 953 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 954 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
bogdanm 86:04dd9b1680ae 955 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 956 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 957 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 958 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
bogdanm 86:04dd9b1680ae 959 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 960 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 961 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 962
bogdanm 86:04dd9b1680ae 963 /****************** Bit definition for ADC_SMPR2 register *******************/
bogdanm 86:04dd9b1680ae 964 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
bogdanm 86:04dd9b1680ae 965 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 966 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 967 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 968 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
bogdanm 86:04dd9b1680ae 969 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 970 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 971 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 972 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
bogdanm 86:04dd9b1680ae 973 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 974 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 975 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 976 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
bogdanm 86:04dd9b1680ae 977 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 978 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 979 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 980 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
bogdanm 86:04dd9b1680ae 981 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 982 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 983 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 984 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
bogdanm 86:04dd9b1680ae 985 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 986 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 987 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 988 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
bogdanm 86:04dd9b1680ae 989 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 990 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 991 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 992 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
bogdanm 86:04dd9b1680ae 993 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 994 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 995 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 996 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
bogdanm 86:04dd9b1680ae 997 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 998 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 999 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1000 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
bogdanm 86:04dd9b1680ae 1001 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1002 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1003 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1004
bogdanm 86:04dd9b1680ae 1005 /****************** Bit definition for ADC_JOFR1 register *******************/
bogdanm 86:04dd9b1680ae 1006 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
bogdanm 86:04dd9b1680ae 1007
bogdanm 86:04dd9b1680ae 1008 /****************** Bit definition for ADC_JOFR2 register *******************/
bogdanm 86:04dd9b1680ae 1009 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
bogdanm 86:04dd9b1680ae 1010
bogdanm 86:04dd9b1680ae 1011 /****************** Bit definition for ADC_JOFR3 register *******************/
bogdanm 86:04dd9b1680ae 1012 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
bogdanm 86:04dd9b1680ae 1013
bogdanm 86:04dd9b1680ae 1014 /****************** Bit definition for ADC_JOFR4 register *******************/
bogdanm 86:04dd9b1680ae 1015 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
bogdanm 86:04dd9b1680ae 1016
bogdanm 86:04dd9b1680ae 1017 /******************* Bit definition for ADC_HTR register ********************/
bogdanm 86:04dd9b1680ae 1018 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
bogdanm 86:04dd9b1680ae 1019
bogdanm 86:04dd9b1680ae 1020 /******************* Bit definition for ADC_LTR register ********************/
bogdanm 86:04dd9b1680ae 1021 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
bogdanm 86:04dd9b1680ae 1022
bogdanm 86:04dd9b1680ae 1023 /******************* Bit definition for ADC_SQR1 register *******************/
bogdanm 86:04dd9b1680ae 1024 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1025 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1026 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1027 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1028 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1029 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1030 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1031 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1032 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1033 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1034 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1035 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1036 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1037 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1038 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1039 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1040 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1041 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1042 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1043 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1044 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1045 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1046 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1047 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1048 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
bogdanm 86:04dd9b1680ae 1049 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1050 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1051 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1052 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1053
bogdanm 86:04dd9b1680ae 1054 /******************* Bit definition for ADC_SQR2 register *******************/
bogdanm 86:04dd9b1680ae 1055 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1056 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1057 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1058 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1059 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1060 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1061 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1062 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1063 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1064 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1065 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1066 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1067 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1068 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1069 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1070 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1071 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1072 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1073 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1074 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1075 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1076 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1077 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1078 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1079 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1080 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1081 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1082 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1083 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1084 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1085 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1086 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1087 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1088 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1089 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1090 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1091
bogdanm 86:04dd9b1680ae 1092 /******************* Bit definition for ADC_SQR3 register *******************/
bogdanm 86:04dd9b1680ae 1093 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1094 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1095 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1096 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1097 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1098 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1099 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1100 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1101 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1102 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1103 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1104 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1105 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1106 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1107 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1108 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1109 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1110 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1111 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1112 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1113 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1114 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1115 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1116 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1117 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1118 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1119 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1120 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1121 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1122 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1123 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
bogdanm 86:04dd9b1680ae 1124 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1125 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1126 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1127 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1128 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1129
bogdanm 86:04dd9b1680ae 1130 /******************* Bit definition for ADC_JSQR register *******************/
bogdanm 86:04dd9b1680ae 1131 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
bogdanm 86:04dd9b1680ae 1132 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1133 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1134 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1135 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1136 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1137 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
bogdanm 86:04dd9b1680ae 1138 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1139 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1140 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1141 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1142 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1143 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
bogdanm 86:04dd9b1680ae 1144 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1145 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1146 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1147 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1148 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1149 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
bogdanm 86:04dd9b1680ae 1150 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1151 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1152 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1153 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1154 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1155 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
bogdanm 86:04dd9b1680ae 1156 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1157 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1158
bogdanm 86:04dd9b1680ae 1159 /******************* Bit definition for ADC_JDR1 register *******************/
bogdanm 86:04dd9b1680ae 1160 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 86:04dd9b1680ae 1161
bogdanm 86:04dd9b1680ae 1162 /******************* Bit definition for ADC_JDR2 register *******************/
bogdanm 86:04dd9b1680ae 1163 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 86:04dd9b1680ae 1164
bogdanm 86:04dd9b1680ae 1165 /******************* Bit definition for ADC_JDR3 register *******************/
bogdanm 86:04dd9b1680ae 1166 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 86:04dd9b1680ae 1167
bogdanm 86:04dd9b1680ae 1168 /******************* Bit definition for ADC_JDR4 register *******************/
bogdanm 86:04dd9b1680ae 1169 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
bogdanm 86:04dd9b1680ae 1170
bogdanm 86:04dd9b1680ae 1171 /******************** Bit definition for ADC_DR register ********************/
bogdanm 86:04dd9b1680ae 1172 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
bogdanm 86:04dd9b1680ae 1173 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
bogdanm 86:04dd9b1680ae 1174
bogdanm 86:04dd9b1680ae 1175 /******************* Bit definition for ADC_CSR register ********************/
bogdanm 86:04dd9b1680ae 1176 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
bogdanm 86:04dd9b1680ae 1177 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
bogdanm 86:04dd9b1680ae 1178 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
bogdanm 86:04dd9b1680ae 1179 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
bogdanm 86:04dd9b1680ae 1180 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
bogdanm 86:04dd9b1680ae 1181 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
bogdanm 86:04dd9b1680ae 1182 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
bogdanm 86:04dd9b1680ae 1183 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
bogdanm 86:04dd9b1680ae 1184 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
bogdanm 86:04dd9b1680ae 1185 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
bogdanm 86:04dd9b1680ae 1186 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
bogdanm 86:04dd9b1680ae 1187 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
bogdanm 86:04dd9b1680ae 1188 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
bogdanm 86:04dd9b1680ae 1189 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
bogdanm 86:04dd9b1680ae 1190 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
bogdanm 86:04dd9b1680ae 1191 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
bogdanm 86:04dd9b1680ae 1192 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
bogdanm 86:04dd9b1680ae 1193 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
bogdanm 86:04dd9b1680ae 1194
bogdanm 86:04dd9b1680ae 1195 /******************* Bit definition for ADC_CCR register ********************/
bogdanm 86:04dd9b1680ae 1196 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
bogdanm 86:04dd9b1680ae 1197 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1198 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1199 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1200 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1201 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 1202 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
bogdanm 86:04dd9b1680ae 1203 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1204 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1205 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 1206 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 1207 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
bogdanm 86:04dd9b1680ae 1208 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
bogdanm 86:04dd9b1680ae 1209 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1210 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1211 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
bogdanm 86:04dd9b1680ae 1212 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 1213 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 1214 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
bogdanm 86:04dd9b1680ae 1215 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
bogdanm 86:04dd9b1680ae 1216
bogdanm 86:04dd9b1680ae 1217 /******************* Bit definition for ADC_CDR register ********************/
bogdanm 86:04dd9b1680ae 1218 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
bogdanm 86:04dd9b1680ae 1219 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
bogdanm 86:04dd9b1680ae 1220
bogdanm 86:04dd9b1680ae 1221 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1222 /* */
bogdanm 86:04dd9b1680ae 1223 /* CRC calculation unit */
bogdanm 86:04dd9b1680ae 1224 /* */
bogdanm 86:04dd9b1680ae 1225 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1226 /******************* Bit definition for CRC_DR register *********************/
bogdanm 86:04dd9b1680ae 1227 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
bogdanm 86:04dd9b1680ae 1228
bogdanm 86:04dd9b1680ae 1229
bogdanm 86:04dd9b1680ae 1230 /******************* Bit definition for CRC_IDR register ********************/
bogdanm 86:04dd9b1680ae 1231 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
bogdanm 86:04dd9b1680ae 1232
bogdanm 86:04dd9b1680ae 1233
bogdanm 86:04dd9b1680ae 1234 /******************** Bit definition for CRC_CR register ********************/
bogdanm 86:04dd9b1680ae 1235 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
bogdanm 86:04dd9b1680ae 1236
bogdanm 86:04dd9b1680ae 1237 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1238 /* */
bogdanm 86:04dd9b1680ae 1239 /* Debug MCU */
bogdanm 86:04dd9b1680ae 1240 /* */
bogdanm 86:04dd9b1680ae 1241 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1242
bogdanm 86:04dd9b1680ae 1243 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1244 /* */
bogdanm 86:04dd9b1680ae 1245 /* DMA Controller */
bogdanm 86:04dd9b1680ae 1246 /* */
bogdanm 86:04dd9b1680ae 1247 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1248 /******************** Bits definition for DMA_SxCR register *****************/
bogdanm 86:04dd9b1680ae 1249 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
bogdanm 86:04dd9b1680ae 1250 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1251 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1252 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1253 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
bogdanm 86:04dd9b1680ae 1254 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 1255 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1256 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
bogdanm 86:04dd9b1680ae 1257 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1258 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1259 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1260 #define DMA_SxCR_CT ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1261 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1262 #define DMA_SxCR_PL ((uint32_t)0x00030000)
bogdanm 86:04dd9b1680ae 1263 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1264 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1265 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1266 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
bogdanm 86:04dd9b1680ae 1267 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1268 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1269 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
bogdanm 86:04dd9b1680ae 1270 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1271 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1272 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1273 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1274 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1275 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
bogdanm 86:04dd9b1680ae 1276 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1277 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1278 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1279 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1280 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1281 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1282 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1283 #define DMA_SxCR_EN ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1284
bogdanm 86:04dd9b1680ae 1285 /******************** Bits definition for DMA_SxCNDTR register **************/
bogdanm 86:04dd9b1680ae 1286 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
bogdanm 86:04dd9b1680ae 1287 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1288 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1289 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1290 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1291 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1292 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1293 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1294 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1295 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1296 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1297 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1298 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1299 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1300 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1301 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1302 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1303
bogdanm 86:04dd9b1680ae 1304 /******************** Bits definition for DMA_SxFCR register ****************/
bogdanm 86:04dd9b1680ae 1305 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1306 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
bogdanm 86:04dd9b1680ae 1307 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1308 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1309 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1310 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1311 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
bogdanm 86:04dd9b1680ae 1312 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1313 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1314
bogdanm 86:04dd9b1680ae 1315 /******************** Bits definition for DMA_LISR register *****************/
bogdanm 86:04dd9b1680ae 1316 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1317 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1318 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1319 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1320 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1321 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1322 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1323 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1324 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1325 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1326 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1327 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1328 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1329 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1330 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1331 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1332 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1333 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1334 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1335 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1336
bogdanm 86:04dd9b1680ae 1337 /******************** Bits definition for DMA_HISR register *****************/
bogdanm 86:04dd9b1680ae 1338 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1339 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1340 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1341 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1342 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1343 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1344 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1345 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1346 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1347 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1348 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1349 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1350 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1351 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1352 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1353 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1354 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1355 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1356 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1357 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1358
bogdanm 86:04dd9b1680ae 1359 /******************** Bits definition for DMA_LIFCR register ****************/
bogdanm 86:04dd9b1680ae 1360 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1361 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1362 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1363 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1364 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1365 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1366 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1367 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1368 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1369 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1370 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1371 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1372 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1373 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1374 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1375 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1376 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1377 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1378 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1379 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1380
bogdanm 86:04dd9b1680ae 1381 /******************** Bits definition for DMA_HIFCR register ****************/
bogdanm 86:04dd9b1680ae 1382 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1383 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1384 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1385 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1386 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1387 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1388 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1389 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1390 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1391 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1392 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1393 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1394 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1395 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1396 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1397 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1398 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1399 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1400 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1401 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1402
bogdanm 86:04dd9b1680ae 1403
bogdanm 86:04dd9b1680ae 1404 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1405 /* */
bogdanm 86:04dd9b1680ae 1406 /* External Interrupt/Event Controller */
bogdanm 86:04dd9b1680ae 1407 /* */
bogdanm 86:04dd9b1680ae 1408 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1409 /******************* Bit definition for EXTI_IMR register *******************/
bogdanm 86:04dd9b1680ae 1410 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
bogdanm 86:04dd9b1680ae 1411 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
bogdanm 86:04dd9b1680ae 1412 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
bogdanm 86:04dd9b1680ae 1413 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
bogdanm 86:04dd9b1680ae 1414 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
bogdanm 86:04dd9b1680ae 1415 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
bogdanm 86:04dd9b1680ae 1416 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
bogdanm 86:04dd9b1680ae 1417 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
bogdanm 86:04dd9b1680ae 1418 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
bogdanm 86:04dd9b1680ae 1419 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
bogdanm 86:04dd9b1680ae 1420 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
bogdanm 86:04dd9b1680ae 1421 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
bogdanm 86:04dd9b1680ae 1422 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
bogdanm 86:04dd9b1680ae 1423 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
bogdanm 86:04dd9b1680ae 1424 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
bogdanm 86:04dd9b1680ae 1425 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
bogdanm 86:04dd9b1680ae 1426 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
bogdanm 86:04dd9b1680ae 1427 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
bogdanm 86:04dd9b1680ae 1428 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
bogdanm 86:04dd9b1680ae 1429 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
bogdanm 86:04dd9b1680ae 1430
bogdanm 86:04dd9b1680ae 1431 /******************* Bit definition for EXTI_EMR register *******************/
bogdanm 86:04dd9b1680ae 1432 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
bogdanm 86:04dd9b1680ae 1433 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
bogdanm 86:04dd9b1680ae 1434 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
bogdanm 86:04dd9b1680ae 1435 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
bogdanm 86:04dd9b1680ae 1436 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
bogdanm 86:04dd9b1680ae 1437 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
bogdanm 86:04dd9b1680ae 1438 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
bogdanm 86:04dd9b1680ae 1439 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
bogdanm 86:04dd9b1680ae 1440 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
bogdanm 86:04dd9b1680ae 1441 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
bogdanm 86:04dd9b1680ae 1442 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
bogdanm 86:04dd9b1680ae 1443 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
bogdanm 86:04dd9b1680ae 1444 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
bogdanm 86:04dd9b1680ae 1445 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
bogdanm 86:04dd9b1680ae 1446 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
bogdanm 86:04dd9b1680ae 1447 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
bogdanm 86:04dd9b1680ae 1448 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
bogdanm 86:04dd9b1680ae 1449 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
bogdanm 86:04dd9b1680ae 1450 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
bogdanm 86:04dd9b1680ae 1451 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
bogdanm 86:04dd9b1680ae 1452
bogdanm 86:04dd9b1680ae 1453 /****************** Bit definition for EXTI_RTSR register *******************/
bogdanm 86:04dd9b1680ae 1454 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
bogdanm 86:04dd9b1680ae 1455 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
bogdanm 86:04dd9b1680ae 1456 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
bogdanm 86:04dd9b1680ae 1457 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
bogdanm 86:04dd9b1680ae 1458 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
bogdanm 86:04dd9b1680ae 1459 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
bogdanm 86:04dd9b1680ae 1460 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
bogdanm 86:04dd9b1680ae 1461 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
bogdanm 86:04dd9b1680ae 1462 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
bogdanm 86:04dd9b1680ae 1463 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
bogdanm 86:04dd9b1680ae 1464 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
bogdanm 86:04dd9b1680ae 1465 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
bogdanm 86:04dd9b1680ae 1466 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
bogdanm 86:04dd9b1680ae 1467 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
bogdanm 86:04dd9b1680ae 1468 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
bogdanm 86:04dd9b1680ae 1469 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
bogdanm 86:04dd9b1680ae 1470 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
bogdanm 86:04dd9b1680ae 1471 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
bogdanm 86:04dd9b1680ae 1472 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
bogdanm 86:04dd9b1680ae 1473 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
bogdanm 86:04dd9b1680ae 1474
bogdanm 86:04dd9b1680ae 1475 /****************** Bit definition for EXTI_FTSR register *******************/
bogdanm 86:04dd9b1680ae 1476 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
bogdanm 86:04dd9b1680ae 1477 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
bogdanm 86:04dd9b1680ae 1478 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
bogdanm 86:04dd9b1680ae 1479 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
bogdanm 86:04dd9b1680ae 1480 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
bogdanm 86:04dd9b1680ae 1481 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
bogdanm 86:04dd9b1680ae 1482 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
bogdanm 86:04dd9b1680ae 1483 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
bogdanm 86:04dd9b1680ae 1484 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
bogdanm 86:04dd9b1680ae 1485 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
bogdanm 86:04dd9b1680ae 1486 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
bogdanm 86:04dd9b1680ae 1487 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
bogdanm 86:04dd9b1680ae 1488 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
bogdanm 86:04dd9b1680ae 1489 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
bogdanm 86:04dd9b1680ae 1490 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
bogdanm 86:04dd9b1680ae 1491 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
bogdanm 86:04dd9b1680ae 1492 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
bogdanm 86:04dd9b1680ae 1493 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
bogdanm 86:04dd9b1680ae 1494 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
bogdanm 86:04dd9b1680ae 1495 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
bogdanm 86:04dd9b1680ae 1496
bogdanm 86:04dd9b1680ae 1497 /****************** Bit definition for EXTI_SWIER register ******************/
bogdanm 86:04dd9b1680ae 1498 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
bogdanm 86:04dd9b1680ae 1499 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
bogdanm 86:04dd9b1680ae 1500 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
bogdanm 86:04dd9b1680ae 1501 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
bogdanm 86:04dd9b1680ae 1502 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
bogdanm 86:04dd9b1680ae 1503 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
bogdanm 86:04dd9b1680ae 1504 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
bogdanm 86:04dd9b1680ae 1505 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
bogdanm 86:04dd9b1680ae 1506 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
bogdanm 86:04dd9b1680ae 1507 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
bogdanm 86:04dd9b1680ae 1508 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
bogdanm 86:04dd9b1680ae 1509 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
bogdanm 86:04dd9b1680ae 1510 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
bogdanm 86:04dd9b1680ae 1511 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
bogdanm 86:04dd9b1680ae 1512 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
bogdanm 86:04dd9b1680ae 1513 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
bogdanm 86:04dd9b1680ae 1514 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
bogdanm 86:04dd9b1680ae 1515 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
bogdanm 86:04dd9b1680ae 1516 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
bogdanm 86:04dd9b1680ae 1517 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
bogdanm 86:04dd9b1680ae 1518
bogdanm 86:04dd9b1680ae 1519 /******************* Bit definition for EXTI_PR register ********************/
bogdanm 86:04dd9b1680ae 1520 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
bogdanm 86:04dd9b1680ae 1521 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
bogdanm 86:04dd9b1680ae 1522 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
bogdanm 86:04dd9b1680ae 1523 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
bogdanm 86:04dd9b1680ae 1524 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
bogdanm 86:04dd9b1680ae 1525 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
bogdanm 86:04dd9b1680ae 1526 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
bogdanm 86:04dd9b1680ae 1527 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
bogdanm 86:04dd9b1680ae 1528 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
bogdanm 86:04dd9b1680ae 1529 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
bogdanm 86:04dd9b1680ae 1530 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
bogdanm 86:04dd9b1680ae 1531 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
bogdanm 86:04dd9b1680ae 1532 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
bogdanm 86:04dd9b1680ae 1533 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
bogdanm 86:04dd9b1680ae 1534 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
bogdanm 86:04dd9b1680ae 1535 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
bogdanm 86:04dd9b1680ae 1536 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
bogdanm 86:04dd9b1680ae 1537 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
bogdanm 86:04dd9b1680ae 1538 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
bogdanm 86:04dd9b1680ae 1539 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
bogdanm 86:04dd9b1680ae 1540
bogdanm 86:04dd9b1680ae 1541 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1542 /* */
bogdanm 86:04dd9b1680ae 1543 /* FLASH */
bogdanm 86:04dd9b1680ae 1544 /* */
bogdanm 86:04dd9b1680ae 1545 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1546 /******************* Bits definition for FLASH_ACR register *****************/
bogdanm 86:04dd9b1680ae 1547 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
bogdanm 86:04dd9b1680ae 1548 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 1549 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1550 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1551 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
bogdanm 86:04dd9b1680ae 1552 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1553 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
bogdanm 86:04dd9b1680ae 1554 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
bogdanm 86:04dd9b1680ae 1555 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
bogdanm 86:04dd9b1680ae 1556
bogdanm 86:04dd9b1680ae 1557 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1558 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1559 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1560 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1561 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1562 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
bogdanm 86:04dd9b1680ae 1563 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
bogdanm 86:04dd9b1680ae 1564
bogdanm 86:04dd9b1680ae 1565 /******************* Bits definition for FLASH_SR register ******************/
bogdanm 86:04dd9b1680ae 1566 #define FLASH_SR_EOP ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1567 #define FLASH_SR_SOP ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1568 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1569 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1570 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1571 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1572 #define FLASH_SR_BSY ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1573
bogdanm 86:04dd9b1680ae 1574 /******************* Bits definition for FLASH_CR register ******************/
bogdanm 86:04dd9b1680ae 1575 #define FLASH_CR_PG ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1576 #define FLASH_CR_SER ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1577 #define FLASH_CR_MER ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1578 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
bogdanm 86:04dd9b1680ae 1579 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1580 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1581 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1582 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1583 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1584 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
bogdanm 86:04dd9b1680ae 1585 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1586 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1587 #define FLASH_CR_STRT ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1588 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1589 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 1590
bogdanm 86:04dd9b1680ae 1591 /******************* Bits definition for FLASH_OPTCR register ***************/
bogdanm 86:04dd9b1680ae 1592 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1593 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1594 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1595 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1596 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
bogdanm 86:04dd9b1680ae 1597
bogdanm 86:04dd9b1680ae 1598 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1599 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1600 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1601 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
bogdanm 86:04dd9b1680ae 1602 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1603 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1604 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1605 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1606 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1607 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1608 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1609 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1610 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
bogdanm 86:04dd9b1680ae 1611 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1612 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1613 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1614 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1615 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1616 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1617 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1618 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 1619 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1620 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1621 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1622 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1623
bogdanm 86:04dd9b1680ae 1624 /****************** Bits definition for FLASH_OPTCR1 register ***************/
bogdanm 86:04dd9b1680ae 1625 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
bogdanm 86:04dd9b1680ae 1626 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1627 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1628 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1629 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1630 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1631 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1632 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1633 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 1634 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1635 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1636 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1637 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1638
bogdanm 86:04dd9b1680ae 1639 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1640 /* */
bogdanm 86:04dd9b1680ae 1641 /* General Purpose I/O */
bogdanm 86:04dd9b1680ae 1642 /* */
bogdanm 86:04dd9b1680ae 1643 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1644 /****************** Bits definition for GPIO_MODER register *****************/
bogdanm 86:04dd9b1680ae 1645 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm 86:04dd9b1680ae 1646 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1647 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1648
bogdanm 86:04dd9b1680ae 1649 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm 86:04dd9b1680ae 1650 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1651 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1652
bogdanm 86:04dd9b1680ae 1653 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm 86:04dd9b1680ae 1654 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1655 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1656
bogdanm 86:04dd9b1680ae 1657 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm 86:04dd9b1680ae 1658 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1659 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1660
bogdanm 86:04dd9b1680ae 1661 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm 86:04dd9b1680ae 1662 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1663 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1664
bogdanm 86:04dd9b1680ae 1665 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm 86:04dd9b1680ae 1666 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1667 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1668
bogdanm 86:04dd9b1680ae 1669 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm 86:04dd9b1680ae 1670 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1671 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1672
bogdanm 86:04dd9b1680ae 1673 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm 86:04dd9b1680ae 1674 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1675 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1676
bogdanm 86:04dd9b1680ae 1677 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm 86:04dd9b1680ae 1678 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1679 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1680
bogdanm 86:04dd9b1680ae 1681 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm 86:04dd9b1680ae 1682 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1683 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1684
bogdanm 86:04dd9b1680ae 1685 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm 86:04dd9b1680ae 1686 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1687 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1688
bogdanm 86:04dd9b1680ae 1689 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm 86:04dd9b1680ae 1690 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1691 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 1692
bogdanm 86:04dd9b1680ae 1693 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm 86:04dd9b1680ae 1694 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1695 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1696
bogdanm 86:04dd9b1680ae 1697 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm 86:04dd9b1680ae 1698 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1699 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1700
bogdanm 86:04dd9b1680ae 1701 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm 86:04dd9b1680ae 1702 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 1703 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 1704
bogdanm 86:04dd9b1680ae 1705 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm 86:04dd9b1680ae 1706 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 1707 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 1708
bogdanm 86:04dd9b1680ae 1709 /****************** Bits definition for GPIO_OTYPER register ****************/
bogdanm 86:04dd9b1680ae 1710 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1711 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1712 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1713 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1714 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1715 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1716 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1717 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1718 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1719 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1720 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1721 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1722 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1723 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1724 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1725 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1726
bogdanm 86:04dd9b1680ae 1727 /****************** Bits definition for GPIO_OSPEEDR register ***************/
bogdanm 86:04dd9b1680ae 1728 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm 86:04dd9b1680ae 1729 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1730 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1731
bogdanm 86:04dd9b1680ae 1732 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm 86:04dd9b1680ae 1733 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1734 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1735
bogdanm 86:04dd9b1680ae 1736 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm 86:04dd9b1680ae 1737 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1738 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1739
bogdanm 86:04dd9b1680ae 1740 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm 86:04dd9b1680ae 1741 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1742 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1743
bogdanm 86:04dd9b1680ae 1744 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm 86:04dd9b1680ae 1745 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1746 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1747
bogdanm 86:04dd9b1680ae 1748 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm 86:04dd9b1680ae 1749 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1750 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1751
bogdanm 86:04dd9b1680ae 1752 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm 86:04dd9b1680ae 1753 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1754 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1755
bogdanm 86:04dd9b1680ae 1756 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm 86:04dd9b1680ae 1757 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1758 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1759
bogdanm 86:04dd9b1680ae 1760 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm 86:04dd9b1680ae 1761 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1762 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1763
bogdanm 86:04dd9b1680ae 1764 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm 86:04dd9b1680ae 1765 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1766 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1767
bogdanm 86:04dd9b1680ae 1768 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm 86:04dd9b1680ae 1769 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1770 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1771
bogdanm 86:04dd9b1680ae 1772 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm 86:04dd9b1680ae 1773 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1774 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 1775
bogdanm 86:04dd9b1680ae 1776 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm 86:04dd9b1680ae 1777 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1778 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1779
bogdanm 86:04dd9b1680ae 1780 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm 86:04dd9b1680ae 1781 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1782 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1783
bogdanm 86:04dd9b1680ae 1784 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm 86:04dd9b1680ae 1785 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 1786 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 1787
bogdanm 86:04dd9b1680ae 1788 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm 86:04dd9b1680ae 1789 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 1790 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 1791
bogdanm 86:04dd9b1680ae 1792 /****************** Bits definition for GPIO_PUPDR register *****************/
bogdanm 86:04dd9b1680ae 1793 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm 86:04dd9b1680ae 1794 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1795 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1796
bogdanm 86:04dd9b1680ae 1797 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm 86:04dd9b1680ae 1798 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1799 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1800
bogdanm 86:04dd9b1680ae 1801 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm 86:04dd9b1680ae 1802 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1803 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1804
bogdanm 86:04dd9b1680ae 1805 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm 86:04dd9b1680ae 1806 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1807 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1808
bogdanm 86:04dd9b1680ae 1809 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm 86:04dd9b1680ae 1810 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1811 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1812
bogdanm 86:04dd9b1680ae 1813 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm 86:04dd9b1680ae 1814 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1815 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1816
bogdanm 86:04dd9b1680ae 1817 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm 86:04dd9b1680ae 1818 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1819 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1820
bogdanm 86:04dd9b1680ae 1821 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm 86:04dd9b1680ae 1822 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1823 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1824
bogdanm 86:04dd9b1680ae 1825 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm 86:04dd9b1680ae 1826 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1827 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1828
bogdanm 86:04dd9b1680ae 1829 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm 86:04dd9b1680ae 1830 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1831 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1832
bogdanm 86:04dd9b1680ae 1833 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm 86:04dd9b1680ae 1834 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1835 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1836
bogdanm 86:04dd9b1680ae 1837 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm 86:04dd9b1680ae 1838 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1839 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 1840
bogdanm 86:04dd9b1680ae 1841 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm 86:04dd9b1680ae 1842 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1843 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1844
bogdanm 86:04dd9b1680ae 1845 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm 86:04dd9b1680ae 1846 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1847 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1848
bogdanm 86:04dd9b1680ae 1849 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm 86:04dd9b1680ae 1850 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 1851 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 1852
bogdanm 86:04dd9b1680ae 1853 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm 86:04dd9b1680ae 1854 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 1855 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 1856
bogdanm 86:04dd9b1680ae 1857 /****************** Bits definition for GPIO_IDR register *******************/
bogdanm 86:04dd9b1680ae 1858 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1859 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1860 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1861 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1862 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1863 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1864 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1865 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1866 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1867 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1868 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1869 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1870 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1871 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1872 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1873 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1874 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
bogdanm 86:04dd9b1680ae 1875 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
bogdanm 86:04dd9b1680ae 1876 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
bogdanm 86:04dd9b1680ae 1877 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
bogdanm 86:04dd9b1680ae 1878 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
bogdanm 86:04dd9b1680ae 1879 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
bogdanm 86:04dd9b1680ae 1880 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
bogdanm 86:04dd9b1680ae 1881 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
bogdanm 86:04dd9b1680ae 1882 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
bogdanm 86:04dd9b1680ae 1883 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
bogdanm 86:04dd9b1680ae 1884 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
bogdanm 86:04dd9b1680ae 1885 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
bogdanm 86:04dd9b1680ae 1886 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
bogdanm 86:04dd9b1680ae 1887 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
bogdanm 86:04dd9b1680ae 1888 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
bogdanm 86:04dd9b1680ae 1889 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
bogdanm 86:04dd9b1680ae 1890 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
bogdanm 86:04dd9b1680ae 1891
bogdanm 86:04dd9b1680ae 1892 /****************** Bits definition for GPIO_ODR register *******************/
bogdanm 86:04dd9b1680ae 1893 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1894 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1895 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1896 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1897 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1898 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1899 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1900 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1901 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1902 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1903 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1904 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1905 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1906 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1907 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1908 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1909 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
bogdanm 86:04dd9b1680ae 1910 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
bogdanm 86:04dd9b1680ae 1911 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
bogdanm 86:04dd9b1680ae 1912 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
bogdanm 86:04dd9b1680ae 1913 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
bogdanm 86:04dd9b1680ae 1914 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
bogdanm 86:04dd9b1680ae 1915 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
bogdanm 86:04dd9b1680ae 1916 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
bogdanm 86:04dd9b1680ae 1917 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
bogdanm 86:04dd9b1680ae 1918 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
bogdanm 86:04dd9b1680ae 1919 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
bogdanm 86:04dd9b1680ae 1920 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
bogdanm 86:04dd9b1680ae 1921 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
bogdanm 86:04dd9b1680ae 1922 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
bogdanm 86:04dd9b1680ae 1923 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
bogdanm 86:04dd9b1680ae 1924 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
bogdanm 86:04dd9b1680ae 1925 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
bogdanm 86:04dd9b1680ae 1926
bogdanm 86:04dd9b1680ae 1927 /****************** Bits definition for GPIO_BSRR register ******************/
bogdanm 86:04dd9b1680ae 1928 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1929 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1930 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1931 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1932 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1933 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1934 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1935 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1936 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1937 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1938 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1939 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1940 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1941 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1942 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1943 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1944 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1945 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1946 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1947 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1948 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1949 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 1950 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 1951 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 1952 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 1953 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 1954 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 1955 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 1956 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 1957 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 1958 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 1959 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 1960
bogdanm 86:04dd9b1680ae 1961 /****************** Bit definition for GPIO_LCKR register *********************/
bogdanm 86:04dd9b1680ae 1962 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1963 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1964 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1965 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1966 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1967 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1968 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1969 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1970 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1971 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1972 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1973 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1974 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1975 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1976 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1977 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1978 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1979
bogdanm 86:04dd9b1680ae 1980 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1981 /* */
bogdanm 86:04dd9b1680ae 1982 /* Inter-integrated Circuit Interface */
bogdanm 86:04dd9b1680ae 1983 /* */
bogdanm 86:04dd9b1680ae 1984 /******************************************************************************/
bogdanm 86:04dd9b1680ae 1985 /******************* Bit definition for I2C_CR1 register ********************/
bogdanm 86:04dd9b1680ae 1986 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
bogdanm 86:04dd9b1680ae 1987 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
bogdanm 86:04dd9b1680ae 1988 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
bogdanm 86:04dd9b1680ae 1989 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
bogdanm 86:04dd9b1680ae 1990 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
bogdanm 86:04dd9b1680ae 1991 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
bogdanm 86:04dd9b1680ae 1992 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
bogdanm 86:04dd9b1680ae 1993 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
bogdanm 86:04dd9b1680ae 1994 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
bogdanm 86:04dd9b1680ae 1995 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
bogdanm 86:04dd9b1680ae 1996 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
bogdanm 86:04dd9b1680ae 1997 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
bogdanm 86:04dd9b1680ae 1998 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
bogdanm 86:04dd9b1680ae 1999 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
bogdanm 86:04dd9b1680ae 2000
bogdanm 86:04dd9b1680ae 2001 /******************* Bit definition for I2C_CR2 register ********************/
bogdanm 86:04dd9b1680ae 2002 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
bogdanm 86:04dd9b1680ae 2003 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 2004 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 2005 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 2006 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 2007 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 2008 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 2009
bogdanm 86:04dd9b1680ae 2010 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
bogdanm 86:04dd9b1680ae 2011 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
bogdanm 86:04dd9b1680ae 2012 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
bogdanm 86:04dd9b1680ae 2013 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
bogdanm 86:04dd9b1680ae 2014 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
bogdanm 86:04dd9b1680ae 2015
bogdanm 86:04dd9b1680ae 2016 /******************* Bit definition for I2C_OAR1 register *******************/
bogdanm 86:04dd9b1680ae 2017 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
bogdanm 86:04dd9b1680ae 2018 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
bogdanm 86:04dd9b1680ae 2019
bogdanm 86:04dd9b1680ae 2020 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 2021 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 2022 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 2023 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 2024 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 2025 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 2026 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 2027 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 86:04dd9b1680ae 2028 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
bogdanm 86:04dd9b1680ae 2029 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
bogdanm 86:04dd9b1680ae 2030
bogdanm 86:04dd9b1680ae 2031 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
bogdanm 86:04dd9b1680ae 2032
bogdanm 86:04dd9b1680ae 2033 /******************* Bit definition for I2C_OAR2 register *******************/
bogdanm 86:04dd9b1680ae 2034 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
bogdanm 86:04dd9b1680ae 2035 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
bogdanm 86:04dd9b1680ae 2036
bogdanm 86:04dd9b1680ae 2037 /******************** Bit definition for I2C_DR register ********************/
bogdanm 86:04dd9b1680ae 2038 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
bogdanm 86:04dd9b1680ae 2039
bogdanm 86:04dd9b1680ae 2040 /******************* Bit definition for I2C_SR1 register ********************/
bogdanm 86:04dd9b1680ae 2041 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
bogdanm 86:04dd9b1680ae 2042 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
bogdanm 86:04dd9b1680ae 2043 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
bogdanm 86:04dd9b1680ae 2044 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
bogdanm 86:04dd9b1680ae 2045 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
bogdanm 86:04dd9b1680ae 2046 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
bogdanm 86:04dd9b1680ae 2047 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
bogdanm 86:04dd9b1680ae 2048 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
bogdanm 86:04dd9b1680ae 2049 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
bogdanm 86:04dd9b1680ae 2050 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
bogdanm 86:04dd9b1680ae 2051 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
bogdanm 86:04dd9b1680ae 2052 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
bogdanm 86:04dd9b1680ae 2053 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
bogdanm 86:04dd9b1680ae 2054 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
bogdanm 86:04dd9b1680ae 2055
bogdanm 86:04dd9b1680ae 2056 /******************* Bit definition for I2C_SR2 register ********************/
bogdanm 86:04dd9b1680ae 2057 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
bogdanm 86:04dd9b1680ae 2058 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
bogdanm 86:04dd9b1680ae 2059 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
bogdanm 86:04dd9b1680ae 2060 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
bogdanm 86:04dd9b1680ae 2061 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
bogdanm 86:04dd9b1680ae 2062 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
bogdanm 86:04dd9b1680ae 2063 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
bogdanm 86:04dd9b1680ae 2064 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
bogdanm 86:04dd9b1680ae 2065
bogdanm 86:04dd9b1680ae 2066 /******************* Bit definition for I2C_CCR register ********************/
bogdanm 86:04dd9b1680ae 2067 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
bogdanm 86:04dd9b1680ae 2068 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
bogdanm 86:04dd9b1680ae 2069 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
bogdanm 86:04dd9b1680ae 2070
bogdanm 86:04dd9b1680ae 2071 /****************** Bit definition for I2C_TRISE register *******************/
bogdanm 86:04dd9b1680ae 2072 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
bogdanm 86:04dd9b1680ae 2073
bogdanm 86:04dd9b1680ae 2074 /****************** Bit definition for I2C_FLTR register *******************/
bogdanm 86:04dd9b1680ae 2075 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
bogdanm 86:04dd9b1680ae 2076 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
bogdanm 86:04dd9b1680ae 2077
bogdanm 86:04dd9b1680ae 2078 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2079 /* */
bogdanm 86:04dd9b1680ae 2080 /* Independent WATCHDOG */
bogdanm 86:04dd9b1680ae 2081 /* */
bogdanm 86:04dd9b1680ae 2082 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2083 /******************* Bit definition for IWDG_KR register ********************/
bogdanm 86:04dd9b1680ae 2084 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
bogdanm 86:04dd9b1680ae 2085
bogdanm 86:04dd9b1680ae 2086 /******************* Bit definition for IWDG_PR register ********************/
bogdanm 86:04dd9b1680ae 2087 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
bogdanm 86:04dd9b1680ae 2088 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 2089 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 2090 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 2091
bogdanm 86:04dd9b1680ae 2092 /******************* Bit definition for IWDG_RLR register *******************/
bogdanm 86:04dd9b1680ae 2093 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
bogdanm 86:04dd9b1680ae 2094
bogdanm 86:04dd9b1680ae 2095 /******************* Bit definition for IWDG_SR register ********************/
bogdanm 86:04dd9b1680ae 2096 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
bogdanm 86:04dd9b1680ae 2097 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
bogdanm 86:04dd9b1680ae 2098
bogdanm 86:04dd9b1680ae 2099
bogdanm 86:04dd9b1680ae 2100 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2101 /* */
bogdanm 86:04dd9b1680ae 2102 /* Power Control */
bogdanm 86:04dd9b1680ae 2103 /* */
bogdanm 86:04dd9b1680ae 2104 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2105 /******************** Bit definition for PWR_CR register ********************/
bogdanm 86:04dd9b1680ae 2106 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
bogdanm 86:04dd9b1680ae 2107 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
bogdanm 86:04dd9b1680ae 2108 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
bogdanm 86:04dd9b1680ae 2109 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
bogdanm 86:04dd9b1680ae 2110 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
bogdanm 86:04dd9b1680ae 2111
bogdanm 86:04dd9b1680ae 2112 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
bogdanm 86:04dd9b1680ae 2113 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 86:04dd9b1680ae 2114 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 86:04dd9b1680ae 2115 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 86:04dd9b1680ae 2116
bogdanm 86:04dd9b1680ae 2117 /*!< PVD level configuration */
bogdanm 86:04dd9b1680ae 2118 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
bogdanm 86:04dd9b1680ae 2119 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
bogdanm 86:04dd9b1680ae 2120 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
bogdanm 86:04dd9b1680ae 2121 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
bogdanm 86:04dd9b1680ae 2122 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
bogdanm 86:04dd9b1680ae 2123 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
bogdanm 86:04dd9b1680ae 2124 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
bogdanm 86:04dd9b1680ae 2125 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
bogdanm 86:04dd9b1680ae 2126
bogdanm 86:04dd9b1680ae 2127 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
bogdanm 86:04dd9b1680ae 2128 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
bogdanm 86:04dd9b1680ae 2129 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
bogdanm 86:04dd9b1680ae 2130 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
bogdanm 86:04dd9b1680ae 2131 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
bogdanm 86:04dd9b1680ae 2132
bogdanm 86:04dd9b1680ae 2133 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
bogdanm 86:04dd9b1680ae 2134 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
bogdanm 86:04dd9b1680ae 2135 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
bogdanm 86:04dd9b1680ae 2136
bogdanm 86:04dd9b1680ae 2137 #define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
bogdanm 86:04dd9b1680ae 2138 #define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
bogdanm 86:04dd9b1680ae 2139 /* Legacy define */
bogdanm 86:04dd9b1680ae 2140 #define PWR_CR_PMODE PWR_CR_VOS
bogdanm 86:04dd9b1680ae 2141
bogdanm 86:04dd9b1680ae 2142 /******************* Bit definition for PWR_CSR register ********************/
bogdanm 86:04dd9b1680ae 2143 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
bogdanm 86:04dd9b1680ae 2144 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
bogdanm 86:04dd9b1680ae 2145 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
bogdanm 86:04dd9b1680ae 2146 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
bogdanm 86:04dd9b1680ae 2147 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
bogdanm 86:04dd9b1680ae 2148 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
bogdanm 86:04dd9b1680ae 2149 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
bogdanm 86:04dd9b1680ae 2150
bogdanm 86:04dd9b1680ae 2151 /* Legacy define */
bogdanm 86:04dd9b1680ae 2152 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
bogdanm 86:04dd9b1680ae 2153
bogdanm 86:04dd9b1680ae 2154 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2155 /* */
bogdanm 86:04dd9b1680ae 2156 /* Reset and Clock Control */
bogdanm 86:04dd9b1680ae 2157 /* */
bogdanm 86:04dd9b1680ae 2158 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2159 /******************** Bit definition for RCC_CR register ********************/
bogdanm 86:04dd9b1680ae 2160 #define RCC_CR_HSION ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2161 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2162
bogdanm 86:04dd9b1680ae 2163 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
bogdanm 86:04dd9b1680ae 2164 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
bogdanm 86:04dd9b1680ae 2165 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
bogdanm 86:04dd9b1680ae 2166 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
bogdanm 86:04dd9b1680ae 2167 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
bogdanm 86:04dd9b1680ae 2168 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
bogdanm 86:04dd9b1680ae 2169
bogdanm 86:04dd9b1680ae 2170 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
bogdanm 86:04dd9b1680ae 2171 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
bogdanm 86:04dd9b1680ae 2172 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
bogdanm 86:04dd9b1680ae 2173 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
bogdanm 86:04dd9b1680ae 2174 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
bogdanm 86:04dd9b1680ae 2175 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
bogdanm 86:04dd9b1680ae 2176 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
bogdanm 86:04dd9b1680ae 2177 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
bogdanm 86:04dd9b1680ae 2178 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
bogdanm 86:04dd9b1680ae 2179
bogdanm 86:04dd9b1680ae 2180 #define RCC_CR_HSEON ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2181 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2182 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2183 #define RCC_CR_CSSON ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2184 #define RCC_CR_PLLON ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 2185 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 2186 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 2187 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 2188
bogdanm 86:04dd9b1680ae 2189 /******************** Bit definition for RCC_PLLCFGR register ***************/
bogdanm 86:04dd9b1680ae 2190 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
bogdanm 86:04dd9b1680ae 2191 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2192 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2193 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2194 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2195 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2196 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2197
bogdanm 86:04dd9b1680ae 2198 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
bogdanm 86:04dd9b1680ae 2199 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 2200 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2201 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2202 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2203 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2204 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2205 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2206 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2207 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2208
bogdanm 86:04dd9b1680ae 2209 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
bogdanm 86:04dd9b1680ae 2210 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2211 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2212
bogdanm 86:04dd9b1680ae 2213 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2214 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2215 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
bogdanm 86:04dd9b1680ae 2216
bogdanm 86:04dd9b1680ae 2217 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
bogdanm 86:04dd9b1680ae 2218 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 2219 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 2220 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 2221 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 2222
bogdanm 86:04dd9b1680ae 2223 /******************** Bit definition for RCC_CFGR register ******************/
bogdanm 86:04dd9b1680ae 2224 /*!< SW configuration */
bogdanm 86:04dd9b1680ae 2225 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
bogdanm 86:04dd9b1680ae 2226 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 86:04dd9b1680ae 2227 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 86:04dd9b1680ae 2228
bogdanm 86:04dd9b1680ae 2229 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
bogdanm 86:04dd9b1680ae 2230 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
bogdanm 86:04dd9b1680ae 2231 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
bogdanm 86:04dd9b1680ae 2232
bogdanm 86:04dd9b1680ae 2233 /*!< SWS configuration */
bogdanm 86:04dd9b1680ae 2234 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
bogdanm 86:04dd9b1680ae 2235 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 86:04dd9b1680ae 2236 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 86:04dd9b1680ae 2237
bogdanm 86:04dd9b1680ae 2238 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
bogdanm 86:04dd9b1680ae 2239 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
bogdanm 86:04dd9b1680ae 2240 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
bogdanm 86:04dd9b1680ae 2241
bogdanm 86:04dd9b1680ae 2242 /*!< HPRE configuration */
bogdanm 86:04dd9b1680ae 2243 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
bogdanm 86:04dd9b1680ae 2244 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 86:04dd9b1680ae 2245 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 86:04dd9b1680ae 2246 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 86:04dd9b1680ae 2247 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 86:04dd9b1680ae 2248
bogdanm 86:04dd9b1680ae 2249 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
bogdanm 86:04dd9b1680ae 2250 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
bogdanm 86:04dd9b1680ae 2251 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
bogdanm 86:04dd9b1680ae 2252 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
bogdanm 86:04dd9b1680ae 2253 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
bogdanm 86:04dd9b1680ae 2254 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
bogdanm 86:04dd9b1680ae 2255 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
bogdanm 86:04dd9b1680ae 2256 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
bogdanm 86:04dd9b1680ae 2257 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
bogdanm 86:04dd9b1680ae 2258
bogdanm 86:04dd9b1680ae 2259 /*!< PPRE1 configuration */
bogdanm 86:04dd9b1680ae 2260 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
bogdanm 86:04dd9b1680ae 2261 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 86:04dd9b1680ae 2262 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 86:04dd9b1680ae 2263 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
bogdanm 86:04dd9b1680ae 2264
bogdanm 86:04dd9b1680ae 2265 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 86:04dd9b1680ae 2266 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
bogdanm 86:04dd9b1680ae 2267 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
bogdanm 86:04dd9b1680ae 2268 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
bogdanm 86:04dd9b1680ae 2269 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
bogdanm 86:04dd9b1680ae 2270
bogdanm 86:04dd9b1680ae 2271 /*!< PPRE2 configuration */
bogdanm 86:04dd9b1680ae 2272 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
bogdanm 86:04dd9b1680ae 2273 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
bogdanm 86:04dd9b1680ae 2274 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
bogdanm 86:04dd9b1680ae 2275 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
bogdanm 86:04dd9b1680ae 2276
bogdanm 86:04dd9b1680ae 2277 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 86:04dd9b1680ae 2278 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
bogdanm 86:04dd9b1680ae 2279 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
bogdanm 86:04dd9b1680ae 2280 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
bogdanm 86:04dd9b1680ae 2281 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
bogdanm 86:04dd9b1680ae 2282
bogdanm 86:04dd9b1680ae 2283 /*!< RTCPRE configuration */
bogdanm 86:04dd9b1680ae 2284 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
bogdanm 86:04dd9b1680ae 2285 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2286 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2287 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2288 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2289 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2290
bogdanm 86:04dd9b1680ae 2291 /*!< MCO1 configuration */
bogdanm 86:04dd9b1680ae 2292 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
bogdanm 86:04dd9b1680ae 2293 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2294 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2295
bogdanm 86:04dd9b1680ae 2296 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 2297
bogdanm 86:04dd9b1680ae 2298 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
bogdanm 86:04dd9b1680ae 2299 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 2300 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 2301 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 2302
bogdanm 86:04dd9b1680ae 2303 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
bogdanm 86:04dd9b1680ae 2304 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 2305 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 2306 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 2307
bogdanm 86:04dd9b1680ae 2308 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
bogdanm 86:04dd9b1680ae 2309 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 2310 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 2311
bogdanm 86:04dd9b1680ae 2312 /******************** Bit definition for RCC_CIR register *******************/
bogdanm 86:04dd9b1680ae 2313 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2314 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2315 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2316 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2317 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2318 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2319
bogdanm 86:04dd9b1680ae 2320 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2321 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2322 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2323 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2324 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2325 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2326 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2327
bogdanm 86:04dd9b1680ae 2328 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2329 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2330 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2331 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2332 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2333 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2334
bogdanm 86:04dd9b1680ae 2335 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 2336
bogdanm 86:04dd9b1680ae 2337 /******************** Bit definition for RCC_AHB1RSTR register **************/
bogdanm 86:04dd9b1680ae 2338 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2339 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2340 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2341 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2342 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2343 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2344 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2345 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2346 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2347
bogdanm 86:04dd9b1680ae 2348 /******************** Bit definition for RCC_AHB2RSTR register **************/
bogdanm 86:04dd9b1680ae 2349 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2350
bogdanm 86:04dd9b1680ae 2351 /******************** Bit definition for RCC_AHB3RSTR register **************/
bogdanm 86:04dd9b1680ae 2352
bogdanm 86:04dd9b1680ae 2353 /******************** Bit definition for RCC_APB1RSTR register **************/
bogdanm 86:04dd9b1680ae 2354 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2355 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2356 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2357 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2358 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2359 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2360 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2361 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2362 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2363 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2364 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 2365 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 2366
bogdanm 86:04dd9b1680ae 2367 /******************** Bit definition for RCC_APB2RSTR register **************/
bogdanm 86:04dd9b1680ae 2368 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2369 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2370 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2371 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2372 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2373 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2374 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2375 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2376 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2377 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2378 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2379 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2380
bogdanm 86:04dd9b1680ae 2381 /* Old SPI1RST bit definition, maintained for legacy purpose */
bogdanm 86:04dd9b1680ae 2382 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
bogdanm 86:04dd9b1680ae 2383
bogdanm 86:04dd9b1680ae 2384 /******************** Bit definition for RCC_AHB1ENR register ***************/
bogdanm 86:04dd9b1680ae 2385 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2386 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2387 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2388 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2389 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2390 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2391 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2392 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2393 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2394 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2395 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2396
bogdanm 86:04dd9b1680ae 2397 /******************** Bit definition for RCC_AHB2ENR register ***************/
bogdanm 86:04dd9b1680ae 2398 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2399
bogdanm 86:04dd9b1680ae 2400 /******************** Bit definition for RCC_AHB3ENR register ***************/
bogdanm 86:04dd9b1680ae 2401
bogdanm 86:04dd9b1680ae 2402 /******************** Bit definition for RCC_APB1ENR register ***************/
bogdanm 86:04dd9b1680ae 2403 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2404 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2405 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2406 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2407 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2408 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2409 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2410 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2411 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2412 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2413 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 2414 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 2415
bogdanm 86:04dd9b1680ae 2416 /******************** Bit definition for RCC_APB2ENR register ***************/
bogdanm 86:04dd9b1680ae 2417 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2418 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2419 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2420 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2421 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2422 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2423 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2424 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2425 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2426 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2427 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2428 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2429
bogdanm 86:04dd9b1680ae 2430 /******************** Bit definition for RCC_AHB1LPENR register *************/
bogdanm 86:04dd9b1680ae 2431 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2432 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2433 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2434 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2435 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2436 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2437 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2438 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2439 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2440 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2441 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2442 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2443 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2444 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2445
bogdanm 86:04dd9b1680ae 2446 /******************** Bit definition for RCC_AHB2LPENR register *************/
bogdanm 86:04dd9b1680ae 2447 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2448
bogdanm 86:04dd9b1680ae 2449 /******************** Bit definition for RCC_AHB3LPENR register *************/
bogdanm 86:04dd9b1680ae 2450
bogdanm 86:04dd9b1680ae 2451 /******************** Bit definition for RCC_APB1LPENR register *************/
bogdanm 86:04dd9b1680ae 2452 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2453 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2454 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2455 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2456 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2457 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2458 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2459 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2460 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2461 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2462 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 2463 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 2464 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 2465
bogdanm 86:04dd9b1680ae 2466 /******************** Bit definition for RCC_APB2LPENR register *************/
bogdanm 86:04dd9b1680ae 2467 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2468 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2469 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2470 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2471 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2472 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2473 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2474 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2475 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2476 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2477 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2478 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2479
bogdanm 86:04dd9b1680ae 2480 /******************** Bit definition for RCC_BDCR register ******************/
bogdanm 86:04dd9b1680ae 2481 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2482 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2483 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2484 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2485
bogdanm 86:04dd9b1680ae 2486 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
bogdanm 86:04dd9b1680ae 2487 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2488 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2489
bogdanm 86:04dd9b1680ae 2490 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2491 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2492
bogdanm 86:04dd9b1680ae 2493 /******************** Bit definition for RCC_CSR register *******************/
bogdanm 86:04dd9b1680ae 2494 #define RCC_CSR_LSION ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2495 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2496 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 2497 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 2498 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 2499 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 2500 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 2501 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 2502 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 2503 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 2504
bogdanm 86:04dd9b1680ae 2505 /******************** Bit definition for RCC_SSCGR register *****************/
bogdanm 86:04dd9b1680ae 2506 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
bogdanm 86:04dd9b1680ae 2507 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
bogdanm 86:04dd9b1680ae 2508 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 2509 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 2510
bogdanm 86:04dd9b1680ae 2511 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
bogdanm 86:04dd9b1680ae 2512 #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
bogdanm 86:04dd9b1680ae 2513 #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2514 #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2515 #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2516 #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2517 #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2518 #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2519
bogdanm 86:04dd9b1680ae 2520 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
bogdanm 86:04dd9b1680ae 2521 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 2522 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2523 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2524 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2525 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2526 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2527 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2528 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2529 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2530
bogdanm 86:04dd9b1680ae 2531 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
bogdanm 86:04dd9b1680ae 2532 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 2533 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 2534 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 2535
bogdanm 86:04dd9b1680ae 2536
bogdanm 86:04dd9b1680ae 2537 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2538 /* */
bogdanm 86:04dd9b1680ae 2539 /* Real-Time Clock (RTC) */
bogdanm 86:04dd9b1680ae 2540 /* */
bogdanm 86:04dd9b1680ae 2541 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2542 /******************** Bits definition for RTC_TR register *******************/
bogdanm 86:04dd9b1680ae 2543 #define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2544 #define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm 86:04dd9b1680ae 2545 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2546 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2547 #define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm 86:04dd9b1680ae 2548 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2549 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2550 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2551 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2552 #define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm 86:04dd9b1680ae 2553 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2554 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2555 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2556 #define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm 86:04dd9b1680ae 2557 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2558 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2559 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2560 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2561 #define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm 86:04dd9b1680ae 2562 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2563 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2564 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 2565 #define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm 86:04dd9b1680ae 2566 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2567 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2568 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2569 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2570
bogdanm 86:04dd9b1680ae 2571 /******************** Bits definition for RTC_DR register *******************/
bogdanm 86:04dd9b1680ae 2572 #define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm 86:04dd9b1680ae 2573 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2574 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2575 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2576 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 2577 #define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm 86:04dd9b1680ae 2578 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2579 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2580 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2581 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2582 #define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm 86:04dd9b1680ae 2583 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2584 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2585 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2586 #define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2587 #define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm 86:04dd9b1680ae 2588 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2589 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2590 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2591 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2592 #define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm 86:04dd9b1680ae 2593 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2594 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2595 #define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm 86:04dd9b1680ae 2596 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2597 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2598 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2599 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2600
bogdanm 86:04dd9b1680ae 2601 /******************** Bits definition for RTC_CR register *******************/
bogdanm 86:04dd9b1680ae 2602 #define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 2603 #define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm 86:04dd9b1680ae 2604 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2605 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2606 #define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2607 #define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2608 #define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2609 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2610 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2611 #define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2612 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2613 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2614 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2615 #define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2616 #define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2617 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2618 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2619 #define RTC_CR_DCE ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2620 #define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 2621 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2622 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2623 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2624 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm 86:04dd9b1680ae 2625 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2626 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2627 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2628
bogdanm 86:04dd9b1680ae 2629 /******************** Bits definition for RTC_ISR register ******************/
bogdanm 86:04dd9b1680ae 2630 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2631 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2632 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2633 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2634 #define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2635 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2636 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2637 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2638 #define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2639 #define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 2640 #define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2641 #define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2642 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2643 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2644 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2645 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2646
bogdanm 86:04dd9b1680ae 2647 /******************** Bits definition for RTC_PRER register *****************/
bogdanm 86:04dd9b1680ae 2648 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm 86:04dd9b1680ae 2649 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
bogdanm 86:04dd9b1680ae 2650
bogdanm 86:04dd9b1680ae 2651 /******************** Bits definition for RTC_WUTR register *****************/
bogdanm 86:04dd9b1680ae 2652 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm 86:04dd9b1680ae 2653
bogdanm 86:04dd9b1680ae 2654 /******************** Bits definition for RTC_CALIBR register ***************/
bogdanm 86:04dd9b1680ae 2655 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2656 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
bogdanm 86:04dd9b1680ae 2657
bogdanm 86:04dd9b1680ae 2658 /******************** Bits definition for RTC_ALRMAR register ***************/
bogdanm 86:04dd9b1680ae 2659 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 2660 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 2661 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm 86:04dd9b1680ae 2662 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 2663 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 2664 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm 86:04dd9b1680ae 2665 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 2666 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 2667 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 2668 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 2669 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 2670 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2671 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm 86:04dd9b1680ae 2672 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2673 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2674 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm 86:04dd9b1680ae 2675 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2676 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2677 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2678 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2679 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2680 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm 86:04dd9b1680ae 2681 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2682 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2683 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2684 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm 86:04dd9b1680ae 2685 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2686 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2687 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2688 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2689 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2690 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm 86:04dd9b1680ae 2691 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2692 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2693 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 2694 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm 86:04dd9b1680ae 2695 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2696 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2697 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2698 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2699
bogdanm 86:04dd9b1680ae 2700 /******************** Bits definition for RTC_ALRMBR register ***************/
bogdanm 86:04dd9b1680ae 2701 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 2702 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
bogdanm 86:04dd9b1680ae 2703 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
bogdanm 86:04dd9b1680ae 2704 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
bogdanm 86:04dd9b1680ae 2705 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
bogdanm 86:04dd9b1680ae 2706 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
bogdanm 86:04dd9b1680ae 2707 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 2708 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 2709 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 2710 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 2711 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 2712 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2713 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
bogdanm 86:04dd9b1680ae 2714 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2715 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2716 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
bogdanm 86:04dd9b1680ae 2717 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2718 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2719 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2720 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2721 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2722 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
bogdanm 86:04dd9b1680ae 2723 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2724 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2725 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2726 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
bogdanm 86:04dd9b1680ae 2727 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2728 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2729 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2730 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2731 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2732 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
bogdanm 86:04dd9b1680ae 2733 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2734 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2735 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 2736 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
bogdanm 86:04dd9b1680ae 2737 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2738 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2739 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2740 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2741
bogdanm 86:04dd9b1680ae 2742 /******************** Bits definition for RTC_WPR register ******************/
bogdanm 86:04dd9b1680ae 2743 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm 86:04dd9b1680ae 2744
bogdanm 86:04dd9b1680ae 2745 /******************** Bits definition for RTC_SSR register ******************/
bogdanm 86:04dd9b1680ae 2746 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm 86:04dd9b1680ae 2747
bogdanm 86:04dd9b1680ae 2748 /******************** Bits definition for RTC_SHIFTR register ***************/
bogdanm 86:04dd9b1680ae 2749 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm 86:04dd9b1680ae 2750 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm 86:04dd9b1680ae 2751
bogdanm 86:04dd9b1680ae 2752 /******************** Bits definition for RTC_TSTR register *****************/
bogdanm 86:04dd9b1680ae 2753 #define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 2754 #define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm 86:04dd9b1680ae 2755 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 2756 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 2757 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm 86:04dd9b1680ae 2758 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2759 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2760 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2761 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 2762 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm 86:04dd9b1680ae 2763 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2764 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2765 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2766 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm 86:04dd9b1680ae 2767 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2768 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2769 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2770 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2771 #define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm 86:04dd9b1680ae 2772 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2773 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2774 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 2775 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm 86:04dd9b1680ae 2776 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2777 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2778 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2779 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2780
bogdanm 86:04dd9b1680ae 2781 /******************** Bits definition for RTC_TSDR register *****************/
bogdanm 86:04dd9b1680ae 2782 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm 86:04dd9b1680ae 2783 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2784 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2785 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2786 #define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2787 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm 86:04dd9b1680ae 2788 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2789 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2790 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2791 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2792 #define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm 86:04dd9b1680ae 2793 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2794 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2795 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm 86:04dd9b1680ae 2796 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2797 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2798 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2799 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2800
bogdanm 86:04dd9b1680ae 2801 /******************** Bits definition for RTC_TSSSR register ****************/
bogdanm 86:04dd9b1680ae 2802 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm 86:04dd9b1680ae 2803
bogdanm 86:04dd9b1680ae 2804 /******************** Bits definition for RTC_CAL register *****************/
bogdanm 86:04dd9b1680ae 2805 #define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2806 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2807 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2808 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm 86:04dd9b1680ae 2809 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2810 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2811 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2812 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2813 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2814 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 2815 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 2816 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2817 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2818
bogdanm 86:04dd9b1680ae 2819 /******************** Bits definition for RTC_TAFCR register ****************/
bogdanm 86:04dd9b1680ae 2820 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 2821 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 2822 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 2823 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 2824 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm 86:04dd9b1680ae 2825 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 2826 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 2827 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm 86:04dd9b1680ae 2828 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 2829 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 2830 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm 86:04dd9b1680ae 2831 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 2832 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 2833 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 2834 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 2835 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 2836 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 2837 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 2838 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 2839 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 2840
bogdanm 86:04dd9b1680ae 2841 /******************** Bits definition for RTC_ALRMASSR register *************/
bogdanm 86:04dd9b1680ae 2842 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 86:04dd9b1680ae 2843 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 2844 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 2845 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 2846 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 2847 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm 86:04dd9b1680ae 2848
bogdanm 86:04dd9b1680ae 2849 /******************** Bits definition for RTC_ALRMBSSR register *************/
bogdanm 86:04dd9b1680ae 2850 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 86:04dd9b1680ae 2851 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 2852 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 2853 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 2854 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 2855 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
bogdanm 86:04dd9b1680ae 2856
bogdanm 86:04dd9b1680ae 2857 /******************** Bits definition for RTC_BKP0R register ****************/
bogdanm 86:04dd9b1680ae 2858 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2859
bogdanm 86:04dd9b1680ae 2860 /******************** Bits definition for RTC_BKP1R register ****************/
bogdanm 86:04dd9b1680ae 2861 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2862
bogdanm 86:04dd9b1680ae 2863 /******************** Bits definition for RTC_BKP2R register ****************/
bogdanm 86:04dd9b1680ae 2864 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2865
bogdanm 86:04dd9b1680ae 2866 /******************** Bits definition for RTC_BKP3R register ****************/
bogdanm 86:04dd9b1680ae 2867 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2868
bogdanm 86:04dd9b1680ae 2869 /******************** Bits definition for RTC_BKP4R register ****************/
bogdanm 86:04dd9b1680ae 2870 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2871
bogdanm 86:04dd9b1680ae 2872 /******************** Bits definition for RTC_BKP5R register ****************/
bogdanm 86:04dd9b1680ae 2873 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2874
bogdanm 86:04dd9b1680ae 2875 /******************** Bits definition for RTC_BKP6R register ****************/
bogdanm 86:04dd9b1680ae 2876 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2877
bogdanm 86:04dd9b1680ae 2878 /******************** Bits definition for RTC_BKP7R register ****************/
bogdanm 86:04dd9b1680ae 2879 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2880
bogdanm 86:04dd9b1680ae 2881 /******************** Bits definition for RTC_BKP8R register ****************/
bogdanm 86:04dd9b1680ae 2882 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2883
bogdanm 86:04dd9b1680ae 2884 /******************** Bits definition for RTC_BKP9R register ****************/
bogdanm 86:04dd9b1680ae 2885 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2886
bogdanm 86:04dd9b1680ae 2887 /******************** Bits definition for RTC_BKP10R register ***************/
bogdanm 86:04dd9b1680ae 2888 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2889
bogdanm 86:04dd9b1680ae 2890 /******************** Bits definition for RTC_BKP11R register ***************/
bogdanm 86:04dd9b1680ae 2891 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2892
bogdanm 86:04dd9b1680ae 2893 /******************** Bits definition for RTC_BKP12R register ***************/
bogdanm 86:04dd9b1680ae 2894 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2895
bogdanm 86:04dd9b1680ae 2896 /******************** Bits definition for RTC_BKP13R register ***************/
bogdanm 86:04dd9b1680ae 2897 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2898
bogdanm 86:04dd9b1680ae 2899 /******************** Bits definition for RTC_BKP14R register ***************/
bogdanm 86:04dd9b1680ae 2900 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2901
bogdanm 86:04dd9b1680ae 2902 /******************** Bits definition for RTC_BKP15R register ***************/
bogdanm 86:04dd9b1680ae 2903 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2904
bogdanm 86:04dd9b1680ae 2905 /******************** Bits definition for RTC_BKP16R register ***************/
bogdanm 86:04dd9b1680ae 2906 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2907
bogdanm 86:04dd9b1680ae 2908 /******************** Bits definition for RTC_BKP17R register ***************/
bogdanm 86:04dd9b1680ae 2909 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2910
bogdanm 86:04dd9b1680ae 2911 /******************** Bits definition for RTC_BKP18R register ***************/
bogdanm 86:04dd9b1680ae 2912 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2913
bogdanm 86:04dd9b1680ae 2914 /******************** Bits definition for RTC_BKP19R register ***************/
bogdanm 86:04dd9b1680ae 2915 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
bogdanm 86:04dd9b1680ae 2916
bogdanm 86:04dd9b1680ae 2917
bogdanm 86:04dd9b1680ae 2918
bogdanm 86:04dd9b1680ae 2919 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2920 /* */
bogdanm 86:04dd9b1680ae 2921 /* SD host Interface */
bogdanm 86:04dd9b1680ae 2922 /* */
bogdanm 86:04dd9b1680ae 2923 /******************************************************************************/
bogdanm 86:04dd9b1680ae 2924 /****************** Bit definition for SDIO_POWER register ******************/
bogdanm 86:04dd9b1680ae 2925 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
bogdanm 86:04dd9b1680ae 2926 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 2927 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 2928
bogdanm 86:04dd9b1680ae 2929 /****************** Bit definition for SDIO_CLKCR register ******************/
bogdanm 86:04dd9b1680ae 2930 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
bogdanm 86:04dd9b1680ae 2931 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
bogdanm 86:04dd9b1680ae 2932 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
bogdanm 86:04dd9b1680ae 2933 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
bogdanm 86:04dd9b1680ae 2934
bogdanm 86:04dd9b1680ae 2935 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
bogdanm 86:04dd9b1680ae 2936 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 2937 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 2938
bogdanm 86:04dd9b1680ae 2939 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
bogdanm 86:04dd9b1680ae 2940 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
bogdanm 86:04dd9b1680ae 2941
bogdanm 86:04dd9b1680ae 2942 /******************* Bit definition for SDIO_ARG register *******************/
bogdanm 86:04dd9b1680ae 2943 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
bogdanm 86:04dd9b1680ae 2944
bogdanm 86:04dd9b1680ae 2945 /******************* Bit definition for SDIO_CMD register *******************/
bogdanm 86:04dd9b1680ae 2946 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
bogdanm 86:04dd9b1680ae 2947
bogdanm 86:04dd9b1680ae 2948 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
bogdanm 86:04dd9b1680ae 2949 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
bogdanm 86:04dd9b1680ae 2950 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
bogdanm 86:04dd9b1680ae 2951
bogdanm 86:04dd9b1680ae 2952 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
bogdanm 86:04dd9b1680ae 2953 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
bogdanm 86:04dd9b1680ae 2954 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
bogdanm 86:04dd9b1680ae 2955 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
bogdanm 86:04dd9b1680ae 2956 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
bogdanm 86:04dd9b1680ae 2957 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
bogdanm 86:04dd9b1680ae 2958 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
bogdanm 86:04dd9b1680ae 2959
bogdanm 86:04dd9b1680ae 2960 /***************** Bit definition for SDIO_RESPCMD register *****************/
bogdanm 86:04dd9b1680ae 2961 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
bogdanm 86:04dd9b1680ae 2962
bogdanm 86:04dd9b1680ae 2963 /****************** Bit definition for SDIO_RESP0 register ******************/
bogdanm 86:04dd9b1680ae 2964 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 86:04dd9b1680ae 2965
bogdanm 86:04dd9b1680ae 2966 /****************** Bit definition for SDIO_RESP1 register ******************/
bogdanm 86:04dd9b1680ae 2967 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 86:04dd9b1680ae 2968
bogdanm 86:04dd9b1680ae 2969 /****************** Bit definition for SDIO_RESP2 register ******************/
bogdanm 86:04dd9b1680ae 2970 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 86:04dd9b1680ae 2971
bogdanm 86:04dd9b1680ae 2972 /****************** Bit definition for SDIO_RESP3 register ******************/
bogdanm 86:04dd9b1680ae 2973 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 86:04dd9b1680ae 2974
bogdanm 86:04dd9b1680ae 2975 /****************** Bit definition for SDIO_RESP4 register ******************/
bogdanm 86:04dd9b1680ae 2976 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
bogdanm 86:04dd9b1680ae 2977
bogdanm 86:04dd9b1680ae 2978 /****************** Bit definition for SDIO_DTIMER register *****************/
bogdanm 86:04dd9b1680ae 2979 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
bogdanm 86:04dd9b1680ae 2980
bogdanm 86:04dd9b1680ae 2981 /****************** Bit definition for SDIO_DLEN register *******************/
bogdanm 86:04dd9b1680ae 2982 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
bogdanm 86:04dd9b1680ae 2983
bogdanm 86:04dd9b1680ae 2984 /****************** Bit definition for SDIO_DCTRL register ******************/
bogdanm 86:04dd9b1680ae 2985 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
bogdanm 86:04dd9b1680ae 2986 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
bogdanm 86:04dd9b1680ae 2987 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
bogdanm 86:04dd9b1680ae 2988 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
bogdanm 86:04dd9b1680ae 2989
bogdanm 86:04dd9b1680ae 2990 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
bogdanm 86:04dd9b1680ae 2991 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 2992 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 2993 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 2994 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 2995
bogdanm 86:04dd9b1680ae 2996 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
bogdanm 86:04dd9b1680ae 2997 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
bogdanm 86:04dd9b1680ae 2998 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
bogdanm 86:04dd9b1680ae 2999 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
bogdanm 86:04dd9b1680ae 3000
bogdanm 86:04dd9b1680ae 3001 /****************** Bit definition for SDIO_DCOUNT register *****************/
bogdanm 86:04dd9b1680ae 3002 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
bogdanm 86:04dd9b1680ae 3003
bogdanm 86:04dd9b1680ae 3004 /****************** Bit definition for SDIO_STA register ********************/
bogdanm 86:04dd9b1680ae 3005 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
bogdanm 86:04dd9b1680ae 3006 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
bogdanm 86:04dd9b1680ae 3007 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
bogdanm 86:04dd9b1680ae 3008 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
bogdanm 86:04dd9b1680ae 3009 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
bogdanm 86:04dd9b1680ae 3010 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
bogdanm 86:04dd9b1680ae 3011 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
bogdanm 86:04dd9b1680ae 3012 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
bogdanm 86:04dd9b1680ae 3013 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
bogdanm 86:04dd9b1680ae 3014 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
bogdanm 86:04dd9b1680ae 3015 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
bogdanm 86:04dd9b1680ae 3016 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
bogdanm 86:04dd9b1680ae 3017 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
bogdanm 86:04dd9b1680ae 3018 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
bogdanm 86:04dd9b1680ae 3019 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
bogdanm 86:04dd9b1680ae 3020 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
bogdanm 86:04dd9b1680ae 3021 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
bogdanm 86:04dd9b1680ae 3022 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
bogdanm 86:04dd9b1680ae 3023 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
bogdanm 86:04dd9b1680ae 3024 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
bogdanm 86:04dd9b1680ae 3025 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
bogdanm 86:04dd9b1680ae 3026 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
bogdanm 86:04dd9b1680ae 3027 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
bogdanm 86:04dd9b1680ae 3028 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
bogdanm 86:04dd9b1680ae 3029
bogdanm 86:04dd9b1680ae 3030 /******************* Bit definition for SDIO_ICR register *******************/
bogdanm 86:04dd9b1680ae 3031 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
bogdanm 86:04dd9b1680ae 3032 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
bogdanm 86:04dd9b1680ae 3033 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
bogdanm 86:04dd9b1680ae 3034 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
bogdanm 86:04dd9b1680ae 3035 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
bogdanm 86:04dd9b1680ae 3036 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
bogdanm 86:04dd9b1680ae 3037 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
bogdanm 86:04dd9b1680ae 3038 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
bogdanm 86:04dd9b1680ae 3039 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
bogdanm 86:04dd9b1680ae 3040 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
bogdanm 86:04dd9b1680ae 3041 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
bogdanm 86:04dd9b1680ae 3042 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
bogdanm 86:04dd9b1680ae 3043 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
bogdanm 86:04dd9b1680ae 3044
bogdanm 86:04dd9b1680ae 3045 /****************** Bit definition for SDIO_MASK register *******************/
bogdanm 86:04dd9b1680ae 3046 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
bogdanm 86:04dd9b1680ae 3047 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
bogdanm 86:04dd9b1680ae 3048 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
bogdanm 86:04dd9b1680ae 3049 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
bogdanm 86:04dd9b1680ae 3050 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
bogdanm 86:04dd9b1680ae 3051 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
bogdanm 86:04dd9b1680ae 3052 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
bogdanm 86:04dd9b1680ae 3053 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
bogdanm 86:04dd9b1680ae 3054 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
bogdanm 86:04dd9b1680ae 3055 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
bogdanm 86:04dd9b1680ae 3056 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
bogdanm 86:04dd9b1680ae 3057 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
bogdanm 86:04dd9b1680ae 3058 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
bogdanm 86:04dd9b1680ae 3059 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
bogdanm 86:04dd9b1680ae 3060 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
bogdanm 86:04dd9b1680ae 3061 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
bogdanm 86:04dd9b1680ae 3062 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
bogdanm 86:04dd9b1680ae 3063 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
bogdanm 86:04dd9b1680ae 3064 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
bogdanm 86:04dd9b1680ae 3065 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
bogdanm 86:04dd9b1680ae 3066 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
bogdanm 86:04dd9b1680ae 3067 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
bogdanm 86:04dd9b1680ae 3068 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
bogdanm 86:04dd9b1680ae 3069 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
bogdanm 86:04dd9b1680ae 3070
bogdanm 86:04dd9b1680ae 3071 /***************** Bit definition for SDIO_FIFOCNT register *****************/
bogdanm 86:04dd9b1680ae 3072 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
bogdanm 86:04dd9b1680ae 3073
bogdanm 86:04dd9b1680ae 3074 /****************** Bit definition for SDIO_FIFO register *******************/
bogdanm 86:04dd9b1680ae 3075 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
bogdanm 86:04dd9b1680ae 3076
bogdanm 86:04dd9b1680ae 3077 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3078 /* */
bogdanm 86:04dd9b1680ae 3079 /* Serial Peripheral Interface */
bogdanm 86:04dd9b1680ae 3080 /* */
bogdanm 86:04dd9b1680ae 3081 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3082 /******************* Bit definition for SPI_CR1 register ********************/
bogdanm 86:04dd9b1680ae 3083 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
bogdanm 86:04dd9b1680ae 3084 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
bogdanm 86:04dd9b1680ae 3085 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
bogdanm 86:04dd9b1680ae 3086
bogdanm 86:04dd9b1680ae 3087 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
bogdanm 86:04dd9b1680ae 3088 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3089 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3090 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3091
bogdanm 86:04dd9b1680ae 3092 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
bogdanm 86:04dd9b1680ae 3093 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
bogdanm 86:04dd9b1680ae 3094 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
bogdanm 86:04dd9b1680ae 3095 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
bogdanm 86:04dd9b1680ae 3096 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
bogdanm 86:04dd9b1680ae 3097 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
bogdanm 86:04dd9b1680ae 3098 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
bogdanm 86:04dd9b1680ae 3099 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
bogdanm 86:04dd9b1680ae 3100 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
bogdanm 86:04dd9b1680ae 3101 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
bogdanm 86:04dd9b1680ae 3102
bogdanm 86:04dd9b1680ae 3103 /******************* Bit definition for SPI_CR2 register ********************/
bogdanm 86:04dd9b1680ae 3104 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
bogdanm 86:04dd9b1680ae 3105 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
bogdanm 86:04dd9b1680ae 3106 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
bogdanm 86:04dd9b1680ae 3107 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
bogdanm 86:04dd9b1680ae 3108 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
bogdanm 86:04dd9b1680ae 3109 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
bogdanm 86:04dd9b1680ae 3110 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
bogdanm 86:04dd9b1680ae 3111
bogdanm 86:04dd9b1680ae 3112 /******************** Bit definition for SPI_SR register ********************/
bogdanm 86:04dd9b1680ae 3113 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
bogdanm 86:04dd9b1680ae 3114 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
bogdanm 86:04dd9b1680ae 3115 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
bogdanm 86:04dd9b1680ae 3116 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
bogdanm 86:04dd9b1680ae 3117 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
bogdanm 86:04dd9b1680ae 3118 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
bogdanm 86:04dd9b1680ae 3119 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
bogdanm 86:04dd9b1680ae 3120 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
bogdanm 86:04dd9b1680ae 3121 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
bogdanm 86:04dd9b1680ae 3122
bogdanm 86:04dd9b1680ae 3123 /******************** Bit definition for SPI_DR register ********************/
bogdanm 86:04dd9b1680ae 3124 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
bogdanm 86:04dd9b1680ae 3125
bogdanm 86:04dd9b1680ae 3126 /******************* Bit definition for SPI_CRCPR register ******************/
bogdanm 86:04dd9b1680ae 3127 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
bogdanm 86:04dd9b1680ae 3128
bogdanm 86:04dd9b1680ae 3129 /****************** Bit definition for SPI_RXCRCR register ******************/
bogdanm 86:04dd9b1680ae 3130 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
bogdanm 86:04dd9b1680ae 3131
bogdanm 86:04dd9b1680ae 3132 /****************** Bit definition for SPI_TXCRCR register ******************/
bogdanm 86:04dd9b1680ae 3133 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
bogdanm 86:04dd9b1680ae 3134
bogdanm 86:04dd9b1680ae 3135 /****************** Bit definition for SPI_I2SCFGR register *****************/
bogdanm 86:04dd9b1680ae 3136 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
bogdanm 86:04dd9b1680ae 3137
bogdanm 86:04dd9b1680ae 3138 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
bogdanm 86:04dd9b1680ae 3139 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3140 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3141
bogdanm 86:04dd9b1680ae 3142 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
bogdanm 86:04dd9b1680ae 3143
bogdanm 86:04dd9b1680ae 3144 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
bogdanm 86:04dd9b1680ae 3145 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3146 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3147
bogdanm 86:04dd9b1680ae 3148 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
bogdanm 86:04dd9b1680ae 3149
bogdanm 86:04dd9b1680ae 3150 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
bogdanm 86:04dd9b1680ae 3151 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3152 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3153
bogdanm 86:04dd9b1680ae 3154 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
bogdanm 86:04dd9b1680ae 3155 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
bogdanm 86:04dd9b1680ae 3156
bogdanm 86:04dd9b1680ae 3157 /****************** Bit definition for SPI_I2SPR register *******************/
bogdanm 86:04dd9b1680ae 3158 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
bogdanm 86:04dd9b1680ae 3159 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
bogdanm 86:04dd9b1680ae 3160 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
bogdanm 86:04dd9b1680ae 3161
bogdanm 86:04dd9b1680ae 3162 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3163 /* */
bogdanm 86:04dd9b1680ae 3164 /* SYSCFG */
bogdanm 86:04dd9b1680ae 3165 /* */
bogdanm 86:04dd9b1680ae 3166 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3167 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
bogdanm 86:04dd9b1680ae 3168 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
bogdanm 86:04dd9b1680ae 3169 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 3170 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 3171 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 3172
bogdanm 86:04dd9b1680ae 3173 /****************** Bit definition for SYSCFG_PMC register ******************/
bogdanm 86:04dd9b1680ae 3174 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
bogdanm 86:04dd9b1680ae 3175
bogdanm 86:04dd9b1680ae 3176 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
bogdanm 86:04dd9b1680ae 3177 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
bogdanm 86:04dd9b1680ae 3178 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
bogdanm 86:04dd9b1680ae 3179 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
bogdanm 86:04dd9b1680ae 3180 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
bogdanm 86:04dd9b1680ae 3181 /**
bogdanm 86:04dd9b1680ae 3182 * @brief EXTI0 configuration
bogdanm 86:04dd9b1680ae 3183 */
bogdanm 86:04dd9b1680ae 3184 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
bogdanm 86:04dd9b1680ae 3185 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
bogdanm 86:04dd9b1680ae 3186 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
bogdanm 86:04dd9b1680ae 3187 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
bogdanm 86:04dd9b1680ae 3188 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
bogdanm 86:04dd9b1680ae 3189 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
bogdanm 86:04dd9b1680ae 3190
bogdanm 86:04dd9b1680ae 3191 /**
bogdanm 86:04dd9b1680ae 3192 * @brief EXTI1 configuration
bogdanm 86:04dd9b1680ae 3193 */
bogdanm 86:04dd9b1680ae 3194 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
bogdanm 86:04dd9b1680ae 3195 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
bogdanm 86:04dd9b1680ae 3196 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
bogdanm 86:04dd9b1680ae 3197 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
bogdanm 86:04dd9b1680ae 3198 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
bogdanm 86:04dd9b1680ae 3199 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
bogdanm 86:04dd9b1680ae 3200
bogdanm 86:04dd9b1680ae 3201 /**
bogdanm 86:04dd9b1680ae 3202 * @brief EXTI2 configuration
bogdanm 86:04dd9b1680ae 3203 */
bogdanm 86:04dd9b1680ae 3204 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
bogdanm 86:04dd9b1680ae 3205 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
bogdanm 86:04dd9b1680ae 3206 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
bogdanm 86:04dd9b1680ae 3207 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
bogdanm 86:04dd9b1680ae 3208 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
bogdanm 86:04dd9b1680ae 3209 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
bogdanm 86:04dd9b1680ae 3210
bogdanm 86:04dd9b1680ae 3211 /**
bogdanm 86:04dd9b1680ae 3212 * @brief EXTI3 configuration
bogdanm 86:04dd9b1680ae 3213 */
bogdanm 86:04dd9b1680ae 3214 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
bogdanm 86:04dd9b1680ae 3215 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
bogdanm 86:04dd9b1680ae 3216 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
bogdanm 86:04dd9b1680ae 3217 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
bogdanm 86:04dd9b1680ae 3218 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
bogdanm 86:04dd9b1680ae 3219 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
bogdanm 86:04dd9b1680ae 3220
bogdanm 86:04dd9b1680ae 3221 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
bogdanm 86:04dd9b1680ae 3222 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
bogdanm 86:04dd9b1680ae 3223 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
bogdanm 86:04dd9b1680ae 3224 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
bogdanm 86:04dd9b1680ae 3225 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
bogdanm 86:04dd9b1680ae 3226 /**
bogdanm 86:04dd9b1680ae 3227 * @brief EXTI4 configuration
bogdanm 86:04dd9b1680ae 3228 */
bogdanm 86:04dd9b1680ae 3229 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
bogdanm 86:04dd9b1680ae 3230 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
bogdanm 86:04dd9b1680ae 3231 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
bogdanm 86:04dd9b1680ae 3232 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
bogdanm 86:04dd9b1680ae 3233 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
bogdanm 86:04dd9b1680ae 3234 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
bogdanm 86:04dd9b1680ae 3235
bogdanm 86:04dd9b1680ae 3236 /**
bogdanm 86:04dd9b1680ae 3237 * @brief EXTI5 configuration
bogdanm 86:04dd9b1680ae 3238 */
bogdanm 86:04dd9b1680ae 3239 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
bogdanm 86:04dd9b1680ae 3240 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
bogdanm 86:04dd9b1680ae 3241 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
bogdanm 86:04dd9b1680ae 3242 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
bogdanm 86:04dd9b1680ae 3243 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
bogdanm 86:04dd9b1680ae 3244 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
bogdanm 86:04dd9b1680ae 3245
bogdanm 86:04dd9b1680ae 3246 /**
bogdanm 86:04dd9b1680ae 3247 * @brief EXTI6 configuration
bogdanm 86:04dd9b1680ae 3248 */
bogdanm 86:04dd9b1680ae 3249 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
bogdanm 86:04dd9b1680ae 3250 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
bogdanm 86:04dd9b1680ae 3251 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
bogdanm 86:04dd9b1680ae 3252 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
bogdanm 86:04dd9b1680ae 3253 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
bogdanm 86:04dd9b1680ae 3254 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
bogdanm 86:04dd9b1680ae 3255
bogdanm 86:04dd9b1680ae 3256 /**
bogdanm 86:04dd9b1680ae 3257 * @brief EXTI7 configuration
bogdanm 86:04dd9b1680ae 3258 */
bogdanm 86:04dd9b1680ae 3259 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
bogdanm 86:04dd9b1680ae 3260 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
bogdanm 86:04dd9b1680ae 3261 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
bogdanm 86:04dd9b1680ae 3262 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
bogdanm 86:04dd9b1680ae 3263 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
bogdanm 86:04dd9b1680ae 3264 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
bogdanm 86:04dd9b1680ae 3265
bogdanm 86:04dd9b1680ae 3266
bogdanm 86:04dd9b1680ae 3267 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
bogdanm 86:04dd9b1680ae 3268 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
bogdanm 86:04dd9b1680ae 3269 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
bogdanm 86:04dd9b1680ae 3270 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
bogdanm 86:04dd9b1680ae 3271 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
bogdanm 86:04dd9b1680ae 3272
bogdanm 86:04dd9b1680ae 3273 /**
bogdanm 86:04dd9b1680ae 3274 * @brief EXTI8 configuration
bogdanm 86:04dd9b1680ae 3275 */
bogdanm 86:04dd9b1680ae 3276 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
bogdanm 86:04dd9b1680ae 3277 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
bogdanm 86:04dd9b1680ae 3278 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
bogdanm 86:04dd9b1680ae 3279 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
bogdanm 86:04dd9b1680ae 3280 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
bogdanm 86:04dd9b1680ae 3281 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
bogdanm 86:04dd9b1680ae 3282
bogdanm 86:04dd9b1680ae 3283 /**
bogdanm 86:04dd9b1680ae 3284 * @brief EXTI9 configuration
bogdanm 86:04dd9b1680ae 3285 */
bogdanm 86:04dd9b1680ae 3286 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
bogdanm 86:04dd9b1680ae 3287 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
bogdanm 86:04dd9b1680ae 3288 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
bogdanm 86:04dd9b1680ae 3289 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
bogdanm 86:04dd9b1680ae 3290 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
bogdanm 86:04dd9b1680ae 3291 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
bogdanm 86:04dd9b1680ae 3292
bogdanm 86:04dd9b1680ae 3293 /**
bogdanm 86:04dd9b1680ae 3294 * @brief EXTI10 configuration
bogdanm 86:04dd9b1680ae 3295 */
bogdanm 86:04dd9b1680ae 3296 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
bogdanm 86:04dd9b1680ae 3297 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
bogdanm 86:04dd9b1680ae 3298 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
bogdanm 86:04dd9b1680ae 3299 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
bogdanm 86:04dd9b1680ae 3300 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
bogdanm 86:04dd9b1680ae 3301 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
bogdanm 86:04dd9b1680ae 3302
bogdanm 86:04dd9b1680ae 3303 /**
bogdanm 86:04dd9b1680ae 3304 * @brief EXTI11 configuration
bogdanm 86:04dd9b1680ae 3305 */
bogdanm 86:04dd9b1680ae 3306 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
bogdanm 86:04dd9b1680ae 3307 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
bogdanm 86:04dd9b1680ae 3308 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
bogdanm 86:04dd9b1680ae 3309 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
bogdanm 86:04dd9b1680ae 3310 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
bogdanm 86:04dd9b1680ae 3311 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
bogdanm 86:04dd9b1680ae 3312
bogdanm 86:04dd9b1680ae 3313 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
bogdanm 86:04dd9b1680ae 3314 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
bogdanm 86:04dd9b1680ae 3315 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
bogdanm 86:04dd9b1680ae 3316 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
bogdanm 86:04dd9b1680ae 3317 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
bogdanm 86:04dd9b1680ae 3318 /**
bogdanm 86:04dd9b1680ae 3319 * @brief EXTI12 configuration
bogdanm 86:04dd9b1680ae 3320 */
bogdanm 86:04dd9b1680ae 3321 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
bogdanm 86:04dd9b1680ae 3322 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
bogdanm 86:04dd9b1680ae 3323 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
bogdanm 86:04dd9b1680ae 3324 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
bogdanm 86:04dd9b1680ae 3325 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
bogdanm 86:04dd9b1680ae 3326 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
bogdanm 86:04dd9b1680ae 3327
bogdanm 86:04dd9b1680ae 3328 /**
bogdanm 86:04dd9b1680ae 3329 * @brief EXTI13 configuration
bogdanm 86:04dd9b1680ae 3330 */
bogdanm 86:04dd9b1680ae 3331 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
bogdanm 86:04dd9b1680ae 3332 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
bogdanm 86:04dd9b1680ae 3333 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
bogdanm 86:04dd9b1680ae 3334 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
bogdanm 86:04dd9b1680ae 3335 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
bogdanm 86:04dd9b1680ae 3336 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
bogdanm 86:04dd9b1680ae 3337
bogdanm 86:04dd9b1680ae 3338 /**
bogdanm 86:04dd9b1680ae 3339 * @brief EXTI14 configuration
bogdanm 86:04dd9b1680ae 3340 */
bogdanm 86:04dd9b1680ae 3341 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
bogdanm 86:04dd9b1680ae 3342 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
bogdanm 86:04dd9b1680ae 3343 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
bogdanm 86:04dd9b1680ae 3344 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
bogdanm 86:04dd9b1680ae 3345 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
bogdanm 86:04dd9b1680ae 3346 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
bogdanm 86:04dd9b1680ae 3347
bogdanm 86:04dd9b1680ae 3348 /**
bogdanm 86:04dd9b1680ae 3349 * @brief EXTI15 configuration
bogdanm 86:04dd9b1680ae 3350 */
bogdanm 86:04dd9b1680ae 3351 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
bogdanm 86:04dd9b1680ae 3352 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
bogdanm 86:04dd9b1680ae 3353 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
bogdanm 86:04dd9b1680ae 3354 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
bogdanm 86:04dd9b1680ae 3355 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
bogdanm 86:04dd9b1680ae 3356 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
bogdanm 86:04dd9b1680ae 3357
bogdanm 86:04dd9b1680ae 3358 /****************** Bit definition for SYSCFG_CMPCR register ****************/
bogdanm 86:04dd9b1680ae 3359 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
bogdanm 86:04dd9b1680ae 3360 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
bogdanm 86:04dd9b1680ae 3361
bogdanm 86:04dd9b1680ae 3362 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3363 /* */
bogdanm 86:04dd9b1680ae 3364 /* TIM */
bogdanm 86:04dd9b1680ae 3365 /* */
bogdanm 86:04dd9b1680ae 3366 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3367 /******************* Bit definition for TIM_CR1 register ********************/
bogdanm 86:04dd9b1680ae 3368 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
bogdanm 86:04dd9b1680ae 3369 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
bogdanm 86:04dd9b1680ae 3370 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
bogdanm 86:04dd9b1680ae 3371 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
bogdanm 86:04dd9b1680ae 3372 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
bogdanm 86:04dd9b1680ae 3373
bogdanm 86:04dd9b1680ae 3374 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
bogdanm 86:04dd9b1680ae 3375 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3376 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3377
bogdanm 86:04dd9b1680ae 3378 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
bogdanm 86:04dd9b1680ae 3379
bogdanm 86:04dd9b1680ae 3380 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
bogdanm 86:04dd9b1680ae 3381 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3382 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3383
bogdanm 86:04dd9b1680ae 3384 /******************* Bit definition for TIM_CR2 register ********************/
bogdanm 86:04dd9b1680ae 3385 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
bogdanm 86:04dd9b1680ae 3386 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
bogdanm 86:04dd9b1680ae 3387 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
bogdanm 86:04dd9b1680ae 3388
bogdanm 86:04dd9b1680ae 3389 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 86:04dd9b1680ae 3390 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3391 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3392 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3393
bogdanm 86:04dd9b1680ae 3394 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
bogdanm 86:04dd9b1680ae 3395 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
bogdanm 86:04dd9b1680ae 3396 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
bogdanm 86:04dd9b1680ae 3397 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
bogdanm 86:04dd9b1680ae 3398 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
bogdanm 86:04dd9b1680ae 3399 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
bogdanm 86:04dd9b1680ae 3400 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
bogdanm 86:04dd9b1680ae 3401 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 86:04dd9b1680ae 3402
bogdanm 86:04dd9b1680ae 3403 /******************* Bit definition for TIM_SMCR register *******************/
bogdanm 86:04dd9b1680ae 3404 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
bogdanm 86:04dd9b1680ae 3405 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3406 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3407 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3408
bogdanm 86:04dd9b1680ae 3409 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
bogdanm 86:04dd9b1680ae 3410 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3411 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3412 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3413
bogdanm 86:04dd9b1680ae 3414 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
bogdanm 86:04dd9b1680ae 3415
bogdanm 86:04dd9b1680ae 3416 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
bogdanm 86:04dd9b1680ae 3417 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3418 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3419 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3420 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3421
bogdanm 86:04dd9b1680ae 3422 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
bogdanm 86:04dd9b1680ae 3423 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3424 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3425
bogdanm 86:04dd9b1680ae 3426 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
bogdanm 86:04dd9b1680ae 3427 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
bogdanm 86:04dd9b1680ae 3428
bogdanm 86:04dd9b1680ae 3429 /******************* Bit definition for TIM_DIER register *******************/
bogdanm 86:04dd9b1680ae 3430 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
bogdanm 86:04dd9b1680ae 3431 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
bogdanm 86:04dd9b1680ae 3432 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
bogdanm 86:04dd9b1680ae 3433 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
bogdanm 86:04dd9b1680ae 3434 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
bogdanm 86:04dd9b1680ae 3435 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
bogdanm 86:04dd9b1680ae 3436 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
bogdanm 86:04dd9b1680ae 3437 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
bogdanm 86:04dd9b1680ae 3438 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
bogdanm 86:04dd9b1680ae 3439 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
bogdanm 86:04dd9b1680ae 3440 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
bogdanm 86:04dd9b1680ae 3441 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
bogdanm 86:04dd9b1680ae 3442 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
bogdanm 86:04dd9b1680ae 3443 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
bogdanm 86:04dd9b1680ae 3444 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
bogdanm 86:04dd9b1680ae 3445
bogdanm 86:04dd9b1680ae 3446 /******************** Bit definition for TIM_SR register ********************/
bogdanm 86:04dd9b1680ae 3447 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
bogdanm 86:04dd9b1680ae 3448 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
bogdanm 86:04dd9b1680ae 3449 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
bogdanm 86:04dd9b1680ae 3450 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
bogdanm 86:04dd9b1680ae 3451 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
bogdanm 86:04dd9b1680ae 3452 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
bogdanm 86:04dd9b1680ae 3453 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
bogdanm 86:04dd9b1680ae 3454 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
bogdanm 86:04dd9b1680ae 3455 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
bogdanm 86:04dd9b1680ae 3456 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
bogdanm 86:04dd9b1680ae 3457 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
bogdanm 86:04dd9b1680ae 3458 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
bogdanm 86:04dd9b1680ae 3459
bogdanm 86:04dd9b1680ae 3460 /******************* Bit definition for TIM_EGR register ********************/
bogdanm 86:04dd9b1680ae 3461 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
bogdanm 86:04dd9b1680ae 3462 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
bogdanm 86:04dd9b1680ae 3463 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
bogdanm 86:04dd9b1680ae 3464 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
bogdanm 86:04dd9b1680ae 3465 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
bogdanm 86:04dd9b1680ae 3466 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
bogdanm 86:04dd9b1680ae 3467 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
bogdanm 86:04dd9b1680ae 3468 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
bogdanm 86:04dd9b1680ae 3469
bogdanm 86:04dd9b1680ae 3470 /****************** Bit definition for TIM_CCMR1 register *******************/
bogdanm 86:04dd9b1680ae 3471 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
bogdanm 86:04dd9b1680ae 3472 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3473 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3474
bogdanm 86:04dd9b1680ae 3475 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
bogdanm 86:04dd9b1680ae 3476 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
bogdanm 86:04dd9b1680ae 3477
bogdanm 86:04dd9b1680ae 3478 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
bogdanm 86:04dd9b1680ae 3479 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3480 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3481 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3482
bogdanm 86:04dd9b1680ae 3483 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
bogdanm 86:04dd9b1680ae 3484
bogdanm 86:04dd9b1680ae 3485 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
bogdanm 86:04dd9b1680ae 3486 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3487 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3488
bogdanm 86:04dd9b1680ae 3489 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
bogdanm 86:04dd9b1680ae 3490 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
bogdanm 86:04dd9b1680ae 3491
bogdanm 86:04dd9b1680ae 3492 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
bogdanm 86:04dd9b1680ae 3493 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3494 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3495 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3496
bogdanm 86:04dd9b1680ae 3497 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
bogdanm 86:04dd9b1680ae 3498
bogdanm 86:04dd9b1680ae 3499 /*----------------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 3500
bogdanm 86:04dd9b1680ae 3501 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
bogdanm 86:04dd9b1680ae 3502 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3503 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3504
bogdanm 86:04dd9b1680ae 3505 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
bogdanm 86:04dd9b1680ae 3506 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3507 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3508 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3509 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3510
bogdanm 86:04dd9b1680ae 3511 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
bogdanm 86:04dd9b1680ae 3512 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3513 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3514
bogdanm 86:04dd9b1680ae 3515 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
bogdanm 86:04dd9b1680ae 3516 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3517 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3518 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3519 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3520
bogdanm 86:04dd9b1680ae 3521 /****************** Bit definition for TIM_CCMR2 register *******************/
bogdanm 86:04dd9b1680ae 3522 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
bogdanm 86:04dd9b1680ae 3523 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3524 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3525
bogdanm 86:04dd9b1680ae 3526 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
bogdanm 86:04dd9b1680ae 3527 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
bogdanm 86:04dd9b1680ae 3528
bogdanm 86:04dd9b1680ae 3529 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
bogdanm 86:04dd9b1680ae 3530 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3531 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3532 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3533
bogdanm 86:04dd9b1680ae 3534 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
bogdanm 86:04dd9b1680ae 3535
bogdanm 86:04dd9b1680ae 3536 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
bogdanm 86:04dd9b1680ae 3537 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3538 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3539
bogdanm 86:04dd9b1680ae 3540 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
bogdanm 86:04dd9b1680ae 3541 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
bogdanm 86:04dd9b1680ae 3542
bogdanm 86:04dd9b1680ae 3543 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 86:04dd9b1680ae 3544 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3545 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3546 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3547
bogdanm 86:04dd9b1680ae 3548 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
bogdanm 86:04dd9b1680ae 3549
bogdanm 86:04dd9b1680ae 3550 /*----------------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 3551
bogdanm 86:04dd9b1680ae 3552 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
bogdanm 86:04dd9b1680ae 3553 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3554 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3555
bogdanm 86:04dd9b1680ae 3556 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
bogdanm 86:04dd9b1680ae 3557 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3558 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3559 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3560 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3561
bogdanm 86:04dd9b1680ae 3562 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
bogdanm 86:04dd9b1680ae 3563 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3564 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3565
bogdanm 86:04dd9b1680ae 3566 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
bogdanm 86:04dd9b1680ae 3567 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3568 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3569 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3570 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3571
bogdanm 86:04dd9b1680ae 3572 /******************* Bit definition for TIM_CCER register *******************/
bogdanm 86:04dd9b1680ae 3573 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
bogdanm 86:04dd9b1680ae 3574 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
bogdanm 86:04dd9b1680ae 3575 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
bogdanm 86:04dd9b1680ae 3576 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
bogdanm 86:04dd9b1680ae 3577 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
bogdanm 86:04dd9b1680ae 3578 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
bogdanm 86:04dd9b1680ae 3579 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
bogdanm 86:04dd9b1680ae 3580 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
bogdanm 86:04dd9b1680ae 3581 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
bogdanm 86:04dd9b1680ae 3582 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
bogdanm 86:04dd9b1680ae 3583 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
bogdanm 86:04dd9b1680ae 3584 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
bogdanm 86:04dd9b1680ae 3585 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
bogdanm 86:04dd9b1680ae 3586 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
bogdanm 86:04dd9b1680ae 3587 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 86:04dd9b1680ae 3588
bogdanm 86:04dd9b1680ae 3589 /******************* Bit definition for TIM_CNT register ********************/
bogdanm 86:04dd9b1680ae 3590 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
bogdanm 86:04dd9b1680ae 3591
bogdanm 86:04dd9b1680ae 3592 /******************* Bit definition for TIM_PSC register ********************/
bogdanm 86:04dd9b1680ae 3593 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
bogdanm 86:04dd9b1680ae 3594
bogdanm 86:04dd9b1680ae 3595 /******************* Bit definition for TIM_ARR register ********************/
bogdanm 86:04dd9b1680ae 3596 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
bogdanm 86:04dd9b1680ae 3597
bogdanm 86:04dd9b1680ae 3598 /******************* Bit definition for TIM_RCR register ********************/
bogdanm 86:04dd9b1680ae 3599 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
bogdanm 86:04dd9b1680ae 3600
bogdanm 86:04dd9b1680ae 3601 /******************* Bit definition for TIM_CCR1 register *******************/
bogdanm 86:04dd9b1680ae 3602 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
bogdanm 86:04dd9b1680ae 3603
bogdanm 86:04dd9b1680ae 3604 /******************* Bit definition for TIM_CCR2 register *******************/
bogdanm 86:04dd9b1680ae 3605 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
bogdanm 86:04dd9b1680ae 3606
bogdanm 86:04dd9b1680ae 3607 /******************* Bit definition for TIM_CCR3 register *******************/
bogdanm 86:04dd9b1680ae 3608 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
bogdanm 86:04dd9b1680ae 3609
bogdanm 86:04dd9b1680ae 3610 /******************* Bit definition for TIM_CCR4 register *******************/
bogdanm 86:04dd9b1680ae 3611 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
bogdanm 86:04dd9b1680ae 3612
bogdanm 86:04dd9b1680ae 3613 /******************* Bit definition for TIM_BDTR register *******************/
bogdanm 86:04dd9b1680ae 3614 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
bogdanm 86:04dd9b1680ae 3615 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3616 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3617 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3618 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3619 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 3620 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 3621 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 3622 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
bogdanm 86:04dd9b1680ae 3623
bogdanm 86:04dd9b1680ae 3624 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
bogdanm 86:04dd9b1680ae 3625 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3626 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3627
bogdanm 86:04dd9b1680ae 3628 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
bogdanm 86:04dd9b1680ae 3629 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
bogdanm 86:04dd9b1680ae 3630 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
bogdanm 86:04dd9b1680ae 3631 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
bogdanm 86:04dd9b1680ae 3632 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
bogdanm 86:04dd9b1680ae 3633 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
bogdanm 86:04dd9b1680ae 3634
bogdanm 86:04dd9b1680ae 3635 /******************* Bit definition for TIM_DCR register ********************/
bogdanm 86:04dd9b1680ae 3636 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
bogdanm 86:04dd9b1680ae 3637 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3638 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3639 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3640 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3641 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 3642
bogdanm 86:04dd9b1680ae 3643 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
bogdanm 86:04dd9b1680ae 3644 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3645 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3646 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3647 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3648 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 3649
bogdanm 86:04dd9b1680ae 3650 /******************* Bit definition for TIM_DMAR register *******************/
bogdanm 86:04dd9b1680ae 3651 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
bogdanm 86:04dd9b1680ae 3652
bogdanm 86:04dd9b1680ae 3653 /******************* Bit definition for TIM_OR register *********************/
bogdanm 86:04dd9b1680ae 3654 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
bogdanm 86:04dd9b1680ae 3655 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3656 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3657 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
bogdanm 86:04dd9b1680ae 3658 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3659 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3660
bogdanm 86:04dd9b1680ae 3661
bogdanm 86:04dd9b1680ae 3662 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3663 /* */
bogdanm 86:04dd9b1680ae 3664 /* Universal Synchronous Asynchronous Receiver Transmitter */
bogdanm 86:04dd9b1680ae 3665 /* */
bogdanm 86:04dd9b1680ae 3666 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3667 /******************* Bit definition for USART_SR register *******************/
bogdanm 86:04dd9b1680ae 3668 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
bogdanm 86:04dd9b1680ae 3669 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
bogdanm 86:04dd9b1680ae 3670 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
bogdanm 86:04dd9b1680ae 3671 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
bogdanm 86:04dd9b1680ae 3672 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
bogdanm 86:04dd9b1680ae 3673 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
bogdanm 86:04dd9b1680ae 3674 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
bogdanm 86:04dd9b1680ae 3675 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
bogdanm 86:04dd9b1680ae 3676 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
bogdanm 86:04dd9b1680ae 3677 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
bogdanm 86:04dd9b1680ae 3678
bogdanm 86:04dd9b1680ae 3679 /******************* Bit definition for USART_DR register *******************/
bogdanm 86:04dd9b1680ae 3680 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
bogdanm 86:04dd9b1680ae 3681
bogdanm 86:04dd9b1680ae 3682 /****************** Bit definition for USART_BRR register *******************/
bogdanm 86:04dd9b1680ae 3683 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
bogdanm 86:04dd9b1680ae 3684 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
bogdanm 86:04dd9b1680ae 3685
bogdanm 86:04dd9b1680ae 3686 /****************** Bit definition for USART_CR1 register *******************/
bogdanm 86:04dd9b1680ae 3687 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
bogdanm 86:04dd9b1680ae 3688 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
bogdanm 86:04dd9b1680ae 3689 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
bogdanm 86:04dd9b1680ae 3690 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
bogdanm 86:04dd9b1680ae 3691 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
bogdanm 86:04dd9b1680ae 3692 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
bogdanm 86:04dd9b1680ae 3693 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
bogdanm 86:04dd9b1680ae 3694 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
bogdanm 86:04dd9b1680ae 3695 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
bogdanm 86:04dd9b1680ae 3696 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
bogdanm 86:04dd9b1680ae 3697 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
bogdanm 86:04dd9b1680ae 3698 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
bogdanm 86:04dd9b1680ae 3699 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
bogdanm 86:04dd9b1680ae 3700 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
bogdanm 86:04dd9b1680ae 3701 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
bogdanm 86:04dd9b1680ae 3702
bogdanm 86:04dd9b1680ae 3703 /****************** Bit definition for USART_CR2 register *******************/
bogdanm 86:04dd9b1680ae 3704 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
bogdanm 86:04dd9b1680ae 3705 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
bogdanm 86:04dd9b1680ae 3706 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
bogdanm 86:04dd9b1680ae 3707 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
bogdanm 86:04dd9b1680ae 3708 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
bogdanm 86:04dd9b1680ae 3709 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
bogdanm 86:04dd9b1680ae 3710 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
bogdanm 86:04dd9b1680ae 3711
bogdanm 86:04dd9b1680ae 3712 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
bogdanm 86:04dd9b1680ae 3713 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3714 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3715
bogdanm 86:04dd9b1680ae 3716 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
bogdanm 86:04dd9b1680ae 3717
bogdanm 86:04dd9b1680ae 3718 /****************** Bit definition for USART_CR3 register *******************/
bogdanm 86:04dd9b1680ae 3719 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
bogdanm 86:04dd9b1680ae 3720 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
bogdanm 86:04dd9b1680ae 3721 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
bogdanm 86:04dd9b1680ae 3722 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
bogdanm 86:04dd9b1680ae 3723 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
bogdanm 86:04dd9b1680ae 3724 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
bogdanm 86:04dd9b1680ae 3725 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
bogdanm 86:04dd9b1680ae 3726 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
bogdanm 86:04dd9b1680ae 3727 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
bogdanm 86:04dd9b1680ae 3728 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
bogdanm 86:04dd9b1680ae 3729 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
bogdanm 86:04dd9b1680ae 3730 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
bogdanm 86:04dd9b1680ae 3731
bogdanm 86:04dd9b1680ae 3732 /****************** Bit definition for USART_GTPR register ******************/
bogdanm 86:04dd9b1680ae 3733 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
bogdanm 86:04dd9b1680ae 3734 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3735 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3736 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3737 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3738 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 3739 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 3740 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 3741 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
bogdanm 86:04dd9b1680ae 3742
bogdanm 86:04dd9b1680ae 3743 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
bogdanm 86:04dd9b1680ae 3744
bogdanm 86:04dd9b1680ae 3745 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3746 /* */
bogdanm 86:04dd9b1680ae 3747 /* Window WATCHDOG */
bogdanm 86:04dd9b1680ae 3748 /* */
bogdanm 86:04dd9b1680ae 3749 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3750 /******************* Bit definition for WWDG_CR register ********************/
bogdanm 86:04dd9b1680ae 3751 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
bogdanm 86:04dd9b1680ae 3752 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3753 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3754 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3755 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3756 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 3757 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 3758 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 3759
bogdanm 86:04dd9b1680ae 3760 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
bogdanm 86:04dd9b1680ae 3761
bogdanm 86:04dd9b1680ae 3762 /******************* Bit definition for WWDG_CFR register *******************/
bogdanm 86:04dd9b1680ae 3763 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
bogdanm 86:04dd9b1680ae 3764 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3765 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3766 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3767 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3768 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 3769 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 3770 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 3771
bogdanm 86:04dd9b1680ae 3772 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
bogdanm 86:04dd9b1680ae 3773 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3774 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3775
bogdanm 86:04dd9b1680ae 3776 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
bogdanm 86:04dd9b1680ae 3777
bogdanm 86:04dd9b1680ae 3778 /******************* Bit definition for WWDG_SR register ********************/
bogdanm 86:04dd9b1680ae 3779 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
bogdanm 86:04dd9b1680ae 3780
bogdanm 86:04dd9b1680ae 3781
bogdanm 86:04dd9b1680ae 3782 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3783 /* */
bogdanm 86:04dd9b1680ae 3784 /* DBG */
bogdanm 86:04dd9b1680ae 3785 /* */
bogdanm 86:04dd9b1680ae 3786 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3787 /******************** Bit definition for DBGMCU_IDCODE register *************/
bogdanm 86:04dd9b1680ae 3788 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
bogdanm 86:04dd9b1680ae 3789 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
bogdanm 86:04dd9b1680ae 3790
bogdanm 86:04dd9b1680ae 3791 /******************** Bit definition for DBGMCU_CR register *****************/
bogdanm 86:04dd9b1680ae 3792 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 3793 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 3794 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 3795 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 3796
bogdanm 86:04dd9b1680ae 3797 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
bogdanm 86:04dd9b1680ae 3798 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3799 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3800
bogdanm 86:04dd9b1680ae 3801 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
bogdanm 86:04dd9b1680ae 3802 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 3803 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 3804 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 3805 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 3806 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 3807 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 3808 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 3809 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 3810 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 3811 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 3812 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 3813 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 3814 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 3815 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 3816 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 3817 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 3818 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 3819 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
bogdanm 86:04dd9b1680ae 3820 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
bogdanm 86:04dd9b1680ae 3821
bogdanm 86:04dd9b1680ae 3822 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
bogdanm 86:04dd9b1680ae 3823 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 3824 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 3825 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 3826 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 3827 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 3828
bogdanm 86:04dd9b1680ae 3829 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3830 /* */
bogdanm 86:04dd9b1680ae 3831 /* USB_OTG */
bogdanm 86:04dd9b1680ae 3832 /* */
bogdanm 86:04dd9b1680ae 3833 /******************************************************************************/
bogdanm 86:04dd9b1680ae 3834 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
bogdanm 86:04dd9b1680ae 3835 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
bogdanm 86:04dd9b1680ae 3836 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
bogdanm 86:04dd9b1680ae 3837 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
bogdanm 86:04dd9b1680ae 3838 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
bogdanm 86:04dd9b1680ae 3839 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
bogdanm 86:04dd9b1680ae 3840 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
bogdanm 86:04dd9b1680ae 3841 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
bogdanm 86:04dd9b1680ae 3842 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
bogdanm 86:04dd9b1680ae 3843 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
bogdanm 86:04dd9b1680ae 3844 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
bogdanm 86:04dd9b1680ae 3845
bogdanm 86:04dd9b1680ae 3846 /******************** Bit definition forUSB_OTG_HCFG register ********************/
bogdanm 86:04dd9b1680ae 3847
bogdanm 86:04dd9b1680ae 3848 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
bogdanm 86:04dd9b1680ae 3849 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3850 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3851 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
bogdanm 86:04dd9b1680ae 3852
bogdanm 86:04dd9b1680ae 3853 /******************** Bit definition forUSB_OTG_DCFG register ********************/
bogdanm 86:04dd9b1680ae 3854
bogdanm 86:04dd9b1680ae 3855 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
bogdanm 86:04dd9b1680ae 3856 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3857 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3858 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
bogdanm 86:04dd9b1680ae 3859
bogdanm 86:04dd9b1680ae 3860 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
bogdanm 86:04dd9b1680ae 3861 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3862 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3863 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3864 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3865 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 3866 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 3867 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 3868
bogdanm 86:04dd9b1680ae 3869 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
bogdanm 86:04dd9b1680ae 3870 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3871 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3872
bogdanm 86:04dd9b1680ae 3873 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
bogdanm 86:04dd9b1680ae 3874 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3875 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3876
bogdanm 86:04dd9b1680ae 3877 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
bogdanm 86:04dd9b1680ae 3878 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
bogdanm 86:04dd9b1680ae 3879 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
bogdanm 86:04dd9b1680ae 3880 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
bogdanm 86:04dd9b1680ae 3881
bogdanm 86:04dd9b1680ae 3882 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
bogdanm 86:04dd9b1680ae 3883 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
bogdanm 86:04dd9b1680ae 3884 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
bogdanm 86:04dd9b1680ae 3885 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
bogdanm 86:04dd9b1680ae 3886 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
bogdanm 86:04dd9b1680ae 3887 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
bogdanm 86:04dd9b1680ae 3888 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
bogdanm 86:04dd9b1680ae 3889
bogdanm 86:04dd9b1680ae 3890 /******************** Bit definition forUSB_OTG_DCTL register ********************/
bogdanm 86:04dd9b1680ae 3891 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
bogdanm 86:04dd9b1680ae 3892 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
bogdanm 86:04dd9b1680ae 3893 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
bogdanm 86:04dd9b1680ae 3894 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
bogdanm 86:04dd9b1680ae 3895
bogdanm 86:04dd9b1680ae 3896 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
bogdanm 86:04dd9b1680ae 3897 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3898 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3899 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3900 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
bogdanm 86:04dd9b1680ae 3901 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
bogdanm 86:04dd9b1680ae 3902 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
bogdanm 86:04dd9b1680ae 3903 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
bogdanm 86:04dd9b1680ae 3904 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
bogdanm 86:04dd9b1680ae 3905
bogdanm 86:04dd9b1680ae 3906 /******************** Bit definition forUSB_OTG_HFIR register ********************/
bogdanm 86:04dd9b1680ae 3907 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
bogdanm 86:04dd9b1680ae 3908
bogdanm 86:04dd9b1680ae 3909 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
bogdanm 86:04dd9b1680ae 3910 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
bogdanm 86:04dd9b1680ae 3911 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
bogdanm 86:04dd9b1680ae 3912
bogdanm 86:04dd9b1680ae 3913 /******************** Bit definition forUSB_OTG_DSTS register ********************/
bogdanm 86:04dd9b1680ae 3914 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
bogdanm 86:04dd9b1680ae 3915
bogdanm 86:04dd9b1680ae 3916 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
bogdanm 86:04dd9b1680ae 3917 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3918 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3919 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
bogdanm 86:04dd9b1680ae 3920 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
bogdanm 86:04dd9b1680ae 3921
bogdanm 86:04dd9b1680ae 3922 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
bogdanm 86:04dd9b1680ae 3923 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
bogdanm 86:04dd9b1680ae 3924
bogdanm 86:04dd9b1680ae 3925 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
bogdanm 86:04dd9b1680ae 3926 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3927 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3928 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3929 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3930 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
bogdanm 86:04dd9b1680ae 3931 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
bogdanm 86:04dd9b1680ae 3932 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
bogdanm 86:04dd9b1680ae 3933
bogdanm 86:04dd9b1680ae 3934 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
bogdanm 86:04dd9b1680ae 3935
bogdanm 86:04dd9b1680ae 3936 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
bogdanm 86:04dd9b1680ae 3937 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3938 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3939 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3940 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
bogdanm 86:04dd9b1680ae 3941 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
bogdanm 86:04dd9b1680ae 3942 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
bogdanm 86:04dd9b1680ae 3943
bogdanm 86:04dd9b1680ae 3944 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
bogdanm 86:04dd9b1680ae 3945 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3946 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3947 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3948 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3949 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
bogdanm 86:04dd9b1680ae 3950 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
bogdanm 86:04dd9b1680ae 3951 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
bogdanm 86:04dd9b1680ae 3952 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
bogdanm 86:04dd9b1680ae 3953 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
bogdanm 86:04dd9b1680ae 3954 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
bogdanm 86:04dd9b1680ae 3955 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
bogdanm 86:04dd9b1680ae 3956 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
bogdanm 86:04dd9b1680ae 3957 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
bogdanm 86:04dd9b1680ae 3958 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
bogdanm 86:04dd9b1680ae 3959 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
bogdanm 86:04dd9b1680ae 3960 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
bogdanm 86:04dd9b1680ae 3961 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
bogdanm 86:04dd9b1680ae 3962
bogdanm 86:04dd9b1680ae 3963 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
bogdanm 86:04dd9b1680ae 3964 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
bogdanm 86:04dd9b1680ae 3965 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
bogdanm 86:04dd9b1680ae 3966 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
bogdanm 86:04dd9b1680ae 3967 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
bogdanm 86:04dd9b1680ae 3968 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
bogdanm 86:04dd9b1680ae 3969
bogdanm 86:04dd9b1680ae 3970 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
bogdanm 86:04dd9b1680ae 3971 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3972 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3973 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3974 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3975 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 3976 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
bogdanm 86:04dd9b1680ae 3977 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
bogdanm 86:04dd9b1680ae 3978
bogdanm 86:04dd9b1680ae 3979 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
bogdanm 86:04dd9b1680ae 3980 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 86:04dd9b1680ae 3981 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 86:04dd9b1680ae 3982 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
bogdanm 86:04dd9b1680ae 3983 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
bogdanm 86:04dd9b1680ae 3984 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
bogdanm 86:04dd9b1680ae 3985 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
bogdanm 86:04dd9b1680ae 3986 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
bogdanm 86:04dd9b1680ae 3987 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 86:04dd9b1680ae 3988
bogdanm 86:04dd9b1680ae 3989 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
bogdanm 86:04dd9b1680ae 3990 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
bogdanm 86:04dd9b1680ae 3991
bogdanm 86:04dd9b1680ae 3992 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
bogdanm 86:04dd9b1680ae 3993 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 3994 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 3995 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 3996 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 3997 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 3998 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 3999 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 4000 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 86:04dd9b1680ae 4001
bogdanm 86:04dd9b1680ae 4002 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
bogdanm 86:04dd9b1680ae 4003 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4004 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4005 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4006 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4007 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 4008 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 4009 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 4010 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
bogdanm 86:04dd9b1680ae 4011
bogdanm 86:04dd9b1680ae 4012 /******************** Bit definition forUSB_OTG_HAINT register ********************/
bogdanm 86:04dd9b1680ae 4013 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
bogdanm 86:04dd9b1680ae 4014
bogdanm 86:04dd9b1680ae 4015 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
bogdanm 86:04dd9b1680ae 4016 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 86:04dd9b1680ae 4017 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 86:04dd9b1680ae 4018 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
bogdanm 86:04dd9b1680ae 4019 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
bogdanm 86:04dd9b1680ae 4020 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
bogdanm 86:04dd9b1680ae 4021 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
bogdanm 86:04dd9b1680ae 4022 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 86:04dd9b1680ae 4023
bogdanm 86:04dd9b1680ae 4024 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
bogdanm 86:04dd9b1680ae 4025 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
bogdanm 86:04dd9b1680ae 4026 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
bogdanm 86:04dd9b1680ae 4027 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
bogdanm 86:04dd9b1680ae 4028 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
bogdanm 86:04dd9b1680ae 4029 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
bogdanm 86:04dd9b1680ae 4030 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
bogdanm 86:04dd9b1680ae 4031 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
bogdanm 86:04dd9b1680ae 4032 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
bogdanm 86:04dd9b1680ae 4033 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
bogdanm 86:04dd9b1680ae 4034 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
bogdanm 86:04dd9b1680ae 4035 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
bogdanm 86:04dd9b1680ae 4036 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
bogdanm 86:04dd9b1680ae 4037 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
bogdanm 86:04dd9b1680ae 4038 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
bogdanm 86:04dd9b1680ae 4039 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
bogdanm 86:04dd9b1680ae 4040 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
bogdanm 86:04dd9b1680ae 4041 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
bogdanm 86:04dd9b1680ae 4042 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
bogdanm 86:04dd9b1680ae 4043 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
bogdanm 86:04dd9b1680ae 4044 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
bogdanm 86:04dd9b1680ae 4045 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
bogdanm 86:04dd9b1680ae 4046 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
bogdanm 86:04dd9b1680ae 4047 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
bogdanm 86:04dd9b1680ae 4048 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
bogdanm 86:04dd9b1680ae 4049 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
bogdanm 86:04dd9b1680ae 4050 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
bogdanm 86:04dd9b1680ae 4051
bogdanm 86:04dd9b1680ae 4052 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
bogdanm 86:04dd9b1680ae 4053 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
bogdanm 86:04dd9b1680ae 4054 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
bogdanm 86:04dd9b1680ae 4055 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
bogdanm 86:04dd9b1680ae 4056 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
bogdanm 86:04dd9b1680ae 4057 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
bogdanm 86:04dd9b1680ae 4058 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
bogdanm 86:04dd9b1680ae 4059 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
bogdanm 86:04dd9b1680ae 4060 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
bogdanm 86:04dd9b1680ae 4061 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
bogdanm 86:04dd9b1680ae 4062 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
bogdanm 86:04dd9b1680ae 4063 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
bogdanm 86:04dd9b1680ae 4064 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
bogdanm 86:04dd9b1680ae 4065 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
bogdanm 86:04dd9b1680ae 4066 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
bogdanm 86:04dd9b1680ae 4067 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
bogdanm 86:04dd9b1680ae 4068 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
bogdanm 86:04dd9b1680ae 4069 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
bogdanm 86:04dd9b1680ae 4070 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
bogdanm 86:04dd9b1680ae 4071 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
bogdanm 86:04dd9b1680ae 4072 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
bogdanm 86:04dd9b1680ae 4073 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
bogdanm 86:04dd9b1680ae 4074 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
bogdanm 86:04dd9b1680ae 4075 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
bogdanm 86:04dd9b1680ae 4076 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
bogdanm 86:04dd9b1680ae 4077 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
bogdanm 86:04dd9b1680ae 4078 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
bogdanm 86:04dd9b1680ae 4079
bogdanm 86:04dd9b1680ae 4080 /******************** Bit definition forUSB_OTG_DAINT register ********************/
bogdanm 86:04dd9b1680ae 4081 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
bogdanm 86:04dd9b1680ae 4082 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
bogdanm 86:04dd9b1680ae 4083
bogdanm 86:04dd9b1680ae 4084 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
bogdanm 86:04dd9b1680ae 4085 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
bogdanm 86:04dd9b1680ae 4086
bogdanm 86:04dd9b1680ae 4087 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
bogdanm 86:04dd9b1680ae 4088 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
bogdanm 86:04dd9b1680ae 4089 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
bogdanm 86:04dd9b1680ae 4090 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
bogdanm 86:04dd9b1680ae 4091 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
bogdanm 86:04dd9b1680ae 4092
bogdanm 86:04dd9b1680ae 4093 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
bogdanm 86:04dd9b1680ae 4094 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
bogdanm 86:04dd9b1680ae 4095 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
bogdanm 86:04dd9b1680ae 4096
bogdanm 86:04dd9b1680ae 4097 /******************** Bit definition for OTG register ********************/
bogdanm 86:04dd9b1680ae 4098
bogdanm 86:04dd9b1680ae 4099 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
bogdanm 86:04dd9b1680ae 4100 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4101 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4102 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4103 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4104 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
bogdanm 86:04dd9b1680ae 4105
bogdanm 86:04dd9b1680ae 4106 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
bogdanm 86:04dd9b1680ae 4107 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4108 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4109
bogdanm 86:04dd9b1680ae 4110 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
bogdanm 86:04dd9b1680ae 4111 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4112 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4113 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4114 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4115
bogdanm 86:04dd9b1680ae 4116 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
bogdanm 86:04dd9b1680ae 4117 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4118 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4119 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4120 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4121
bogdanm 86:04dd9b1680ae 4122 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
bogdanm 86:04dd9b1680ae 4123 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4124 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4125 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4126 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4127
bogdanm 86:04dd9b1680ae 4128 /******************** Bit definition for OTG register ********************/
bogdanm 86:04dd9b1680ae 4129
bogdanm 86:04dd9b1680ae 4130 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
bogdanm 86:04dd9b1680ae 4131 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4132 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4133 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4134 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4135 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
bogdanm 86:04dd9b1680ae 4136
bogdanm 86:04dd9b1680ae 4137 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
bogdanm 86:04dd9b1680ae 4138 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4139 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4140
bogdanm 86:04dd9b1680ae 4141 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
bogdanm 86:04dd9b1680ae 4142 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4143 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4144 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4145 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4146
bogdanm 86:04dd9b1680ae 4147 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
bogdanm 86:04dd9b1680ae 4148 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4149 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4150 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4151 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4152
bogdanm 86:04dd9b1680ae 4153 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
bogdanm 86:04dd9b1680ae 4154 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4155 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4156 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4157 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4158
bogdanm 86:04dd9b1680ae 4159 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
bogdanm 86:04dd9b1680ae 4160 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
bogdanm 86:04dd9b1680ae 4161
bogdanm 86:04dd9b1680ae 4162 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
bogdanm 86:04dd9b1680ae 4163 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
bogdanm 86:04dd9b1680ae 4164
bogdanm 86:04dd9b1680ae 4165 /******************** Bit definition for OTG register ********************/
bogdanm 86:04dd9b1680ae 4166 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
bogdanm 86:04dd9b1680ae 4167 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
bogdanm 86:04dd9b1680ae 4168 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
bogdanm 86:04dd9b1680ae 4169 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
bogdanm 86:04dd9b1680ae 4170
bogdanm 86:04dd9b1680ae 4171 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
bogdanm 86:04dd9b1680ae 4172 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
bogdanm 86:04dd9b1680ae 4173
bogdanm 86:04dd9b1680ae 4174 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
bogdanm 86:04dd9b1680ae 4175 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
bogdanm 86:04dd9b1680ae 4176
bogdanm 86:04dd9b1680ae 4177 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
bogdanm 86:04dd9b1680ae 4178 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4179 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4180 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4181 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4182 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 4183 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 4184 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 4185 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
bogdanm 86:04dd9b1680ae 4186
bogdanm 86:04dd9b1680ae 4187 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
bogdanm 86:04dd9b1680ae 4188 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4189 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4190 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4191 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4192 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 4193 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 4194 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 4195
bogdanm 86:04dd9b1680ae 4196 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
bogdanm 86:04dd9b1680ae 4197 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
bogdanm 86:04dd9b1680ae 4198 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
bogdanm 86:04dd9b1680ae 4199
bogdanm 86:04dd9b1680ae 4200 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
bogdanm 86:04dd9b1680ae 4201 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4202 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4203 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4204 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4205 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 4206 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 4207 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 4208 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
bogdanm 86:04dd9b1680ae 4209 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
bogdanm 86:04dd9b1680ae 4210 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
bogdanm 86:04dd9b1680ae 4211
bogdanm 86:04dd9b1680ae 4212 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
bogdanm 86:04dd9b1680ae 4213 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4214 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4215 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4216 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4217 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 4218 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 4219 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 4220 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
bogdanm 86:04dd9b1680ae 4221 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
bogdanm 86:04dd9b1680ae 4222 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
bogdanm 86:04dd9b1680ae 4223
bogdanm 86:04dd9b1680ae 4224 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
bogdanm 86:04dd9b1680ae 4225 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
bogdanm 86:04dd9b1680ae 4226
bogdanm 86:04dd9b1680ae 4227 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
bogdanm 86:04dd9b1680ae 4228 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
bogdanm 86:04dd9b1680ae 4229 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
bogdanm 86:04dd9b1680ae 4230
bogdanm 86:04dd9b1680ae 4231 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
bogdanm 86:04dd9b1680ae 4232 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
bogdanm 86:04dd9b1680ae 4233 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
bogdanm 86:04dd9b1680ae 4234 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
bogdanm 86:04dd9b1680ae 4235 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
bogdanm 86:04dd9b1680ae 4236 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
bogdanm 86:04dd9b1680ae 4237 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
bogdanm 86:04dd9b1680ae 4238
bogdanm 86:04dd9b1680ae 4239 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
bogdanm 86:04dd9b1680ae 4240 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
bogdanm 86:04dd9b1680ae 4241 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
bogdanm 86:04dd9b1680ae 4242
bogdanm 86:04dd9b1680ae 4243 /******************** Bit definition forUSB_OTG_CID register ********************/
bogdanm 86:04dd9b1680ae 4244 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
bogdanm 86:04dd9b1680ae 4245
bogdanm 86:04dd9b1680ae 4246 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
bogdanm 86:04dd9b1680ae 4247 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 86:04dd9b1680ae 4248 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 86:04dd9b1680ae 4249 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
bogdanm 86:04dd9b1680ae 4250 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
bogdanm 86:04dd9b1680ae 4251 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
bogdanm 86:04dd9b1680ae 4252 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
bogdanm 86:04dd9b1680ae 4253 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
bogdanm 86:04dd9b1680ae 4254 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 86:04dd9b1680ae 4255 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
bogdanm 86:04dd9b1680ae 4256
bogdanm 86:04dd9b1680ae 4257 /******************** Bit definition forUSB_OTG_HPRT register ********************/
bogdanm 86:04dd9b1680ae 4258 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
bogdanm 86:04dd9b1680ae 4259 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
bogdanm 86:04dd9b1680ae 4260 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
bogdanm 86:04dd9b1680ae 4261 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
bogdanm 86:04dd9b1680ae 4262 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
bogdanm 86:04dd9b1680ae 4263 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
bogdanm 86:04dd9b1680ae 4264 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
bogdanm 86:04dd9b1680ae 4265 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
bogdanm 86:04dd9b1680ae 4266 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
bogdanm 86:04dd9b1680ae 4267
bogdanm 86:04dd9b1680ae 4268 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
bogdanm 86:04dd9b1680ae 4269 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4270 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4271 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
bogdanm 86:04dd9b1680ae 4272
bogdanm 86:04dd9b1680ae 4273 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
bogdanm 86:04dd9b1680ae 4274 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4275 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4276 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4277 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4278
bogdanm 86:04dd9b1680ae 4279 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
bogdanm 86:04dd9b1680ae 4280 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4281 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4282
bogdanm 86:04dd9b1680ae 4283 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
bogdanm 86:04dd9b1680ae 4284 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
bogdanm 86:04dd9b1680ae 4285 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
bogdanm 86:04dd9b1680ae 4286 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
bogdanm 86:04dd9b1680ae 4287 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
bogdanm 86:04dd9b1680ae 4288 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
bogdanm 86:04dd9b1680ae 4289 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
bogdanm 86:04dd9b1680ae 4290 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
bogdanm 86:04dd9b1680ae 4291 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
bogdanm 86:04dd9b1680ae 4292 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
bogdanm 86:04dd9b1680ae 4293 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
bogdanm 86:04dd9b1680ae 4294 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
bogdanm 86:04dd9b1680ae 4295
bogdanm 86:04dd9b1680ae 4296 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
bogdanm 86:04dd9b1680ae 4297 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
bogdanm 86:04dd9b1680ae 4298 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
bogdanm 86:04dd9b1680ae 4299
bogdanm 86:04dd9b1680ae 4300 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
bogdanm 86:04dd9b1680ae 4301 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
bogdanm 86:04dd9b1680ae 4302 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
bogdanm 86:04dd9b1680ae 4303 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
bogdanm 86:04dd9b1680ae 4304 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
bogdanm 86:04dd9b1680ae 4305
bogdanm 86:04dd9b1680ae 4306 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
bogdanm 86:04dd9b1680ae 4307 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4308 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4309 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
bogdanm 86:04dd9b1680ae 4310
bogdanm 86:04dd9b1680ae 4311 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
bogdanm 86:04dd9b1680ae 4312 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4313 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4314 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4315 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4316 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
bogdanm 86:04dd9b1680ae 4317 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
bogdanm 86:04dd9b1680ae 4318 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
bogdanm 86:04dd9b1680ae 4319 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
bogdanm 86:04dd9b1680ae 4320 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
bogdanm 86:04dd9b1680ae 4321 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
bogdanm 86:04dd9b1680ae 4322
bogdanm 86:04dd9b1680ae 4323 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
bogdanm 86:04dd9b1680ae 4324 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
bogdanm 86:04dd9b1680ae 4325
bogdanm 86:04dd9b1680ae 4326 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
bogdanm 86:04dd9b1680ae 4327 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4328 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4329 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4330 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4331 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
bogdanm 86:04dd9b1680ae 4332 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
bogdanm 86:04dd9b1680ae 4333
bogdanm 86:04dd9b1680ae 4334 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
bogdanm 86:04dd9b1680ae 4335 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4336 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4337
bogdanm 86:04dd9b1680ae 4338 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
bogdanm 86:04dd9b1680ae 4339 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4340 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4341
bogdanm 86:04dd9b1680ae 4342 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
bogdanm 86:04dd9b1680ae 4343 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4344 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4345 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4346 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4347 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 4348 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 4349 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 4350 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
bogdanm 86:04dd9b1680ae 4351 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
bogdanm 86:04dd9b1680ae 4352 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
bogdanm 86:04dd9b1680ae 4353
bogdanm 86:04dd9b1680ae 4354 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
bogdanm 86:04dd9b1680ae 4355
bogdanm 86:04dd9b1680ae 4356 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
bogdanm 86:04dd9b1680ae 4357 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4358 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4359 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4360 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4361 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 4362 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 4363 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 4364
bogdanm 86:04dd9b1680ae 4365 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
bogdanm 86:04dd9b1680ae 4366 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4367 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4368 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
bogdanm 86:04dd9b1680ae 4369 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
bogdanm 86:04dd9b1680ae 4370 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
bogdanm 86:04dd9b1680ae 4371 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
bogdanm 86:04dd9b1680ae 4372 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
bogdanm 86:04dd9b1680ae 4373
bogdanm 86:04dd9b1680ae 4374 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
bogdanm 86:04dd9b1680ae 4375 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4376 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4377 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
bogdanm 86:04dd9b1680ae 4378 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
bogdanm 86:04dd9b1680ae 4379
bogdanm 86:04dd9b1680ae 4380 /******************** Bit definition forUSB_OTG_HCINT register ********************/
bogdanm 86:04dd9b1680ae 4381 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
bogdanm 86:04dd9b1680ae 4382 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
bogdanm 86:04dd9b1680ae 4383 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
bogdanm 86:04dd9b1680ae 4384 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
bogdanm 86:04dd9b1680ae 4385 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
bogdanm 86:04dd9b1680ae 4386 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
bogdanm 86:04dd9b1680ae 4387 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
bogdanm 86:04dd9b1680ae 4388 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
bogdanm 86:04dd9b1680ae 4389 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
bogdanm 86:04dd9b1680ae 4390 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
bogdanm 86:04dd9b1680ae 4391 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
bogdanm 86:04dd9b1680ae 4392
bogdanm 86:04dd9b1680ae 4393 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
bogdanm 86:04dd9b1680ae 4394 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
bogdanm 86:04dd9b1680ae 4395 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
bogdanm 86:04dd9b1680ae 4396 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
bogdanm 86:04dd9b1680ae 4397 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
bogdanm 86:04dd9b1680ae 4398 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
bogdanm 86:04dd9b1680ae 4399 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
bogdanm 86:04dd9b1680ae 4400 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
bogdanm 86:04dd9b1680ae 4401 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
bogdanm 86:04dd9b1680ae 4402 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
bogdanm 86:04dd9b1680ae 4403 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
bogdanm 86:04dd9b1680ae 4404 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
bogdanm 86:04dd9b1680ae 4405
bogdanm 86:04dd9b1680ae 4406 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
bogdanm 86:04dd9b1680ae 4407 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
bogdanm 86:04dd9b1680ae 4408 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
bogdanm 86:04dd9b1680ae 4409 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
bogdanm 86:04dd9b1680ae 4410 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
bogdanm 86:04dd9b1680ae 4411 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
bogdanm 86:04dd9b1680ae 4412 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
bogdanm 86:04dd9b1680ae 4413 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
bogdanm 86:04dd9b1680ae 4414 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
bogdanm 86:04dd9b1680ae 4415 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
bogdanm 86:04dd9b1680ae 4416 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
bogdanm 86:04dd9b1680ae 4417 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
bogdanm 86:04dd9b1680ae 4418
bogdanm 86:04dd9b1680ae 4419 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
bogdanm 86:04dd9b1680ae 4420
bogdanm 86:04dd9b1680ae 4421 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
bogdanm 86:04dd9b1680ae 4422 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
bogdanm 86:04dd9b1680ae 4423 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
bogdanm 86:04dd9b1680ae 4424 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
bogdanm 86:04dd9b1680ae 4425 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
bogdanm 86:04dd9b1680ae 4426 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
bogdanm 86:04dd9b1680ae 4427 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
bogdanm 86:04dd9b1680ae 4428 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
bogdanm 86:04dd9b1680ae 4429 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4430 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4431
bogdanm 86:04dd9b1680ae 4432 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
bogdanm 86:04dd9b1680ae 4433 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
bogdanm 86:04dd9b1680ae 4434
bogdanm 86:04dd9b1680ae 4435 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
bogdanm 86:04dd9b1680ae 4436 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
bogdanm 86:04dd9b1680ae 4437
bogdanm 86:04dd9b1680ae 4438 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
bogdanm 86:04dd9b1680ae 4439 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
bogdanm 86:04dd9b1680ae 4440
bogdanm 86:04dd9b1680ae 4441 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
bogdanm 86:04dd9b1680ae 4442 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
bogdanm 86:04dd9b1680ae 4443 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
bogdanm 86:04dd9b1680ae 4444
bogdanm 86:04dd9b1680ae 4445 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
bogdanm 86:04dd9b1680ae 4446
bogdanm 86:04dd9b1680ae 4447 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4448 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
bogdanm 86:04dd9b1680ae 4449 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
bogdanm 86:04dd9b1680ae 4450 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
bogdanm 86:04dd9b1680ae 4451 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
bogdanm 86:04dd9b1680ae 4452 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
bogdanm 86:04dd9b1680ae 4453 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4454 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4455 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
bogdanm 86:04dd9b1680ae 4456 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
bogdanm 86:04dd9b1680ae 4457 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
bogdanm 86:04dd9b1680ae 4458 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
bogdanm 86:04dd9b1680ae 4459 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
bogdanm 86:04dd9b1680ae 4460 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
bogdanm 86:04dd9b1680ae 4461
bogdanm 86:04dd9b1680ae 4462 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
bogdanm 86:04dd9b1680ae 4463 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
bogdanm 86:04dd9b1680ae 4464 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
bogdanm 86:04dd9b1680ae 4465 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
bogdanm 86:04dd9b1680ae 4466 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
bogdanm 86:04dd9b1680ae 4467 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
bogdanm 86:04dd9b1680ae 4468 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
bogdanm 86:04dd9b1680ae 4469
bogdanm 86:04dd9b1680ae 4470 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
bogdanm 86:04dd9b1680ae 4471
bogdanm 86:04dd9b1680ae 4472 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
bogdanm 86:04dd9b1680ae 4473 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
bogdanm 86:04dd9b1680ae 4474
bogdanm 86:04dd9b1680ae 4475 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
bogdanm 86:04dd9b1680ae 4476 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4477 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4478
bogdanm 86:04dd9b1680ae 4479 /******************** Bit definition for PCGCCTL register ********************/
bogdanm 86:04dd9b1680ae 4480 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
bogdanm 86:04dd9b1680ae 4481 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 86:04dd9b1680ae 4482 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 86:04dd9b1680ae 4483
bogdanm 86:04dd9b1680ae 4484 /**
bogdanm 86:04dd9b1680ae 4485 * @}
bogdanm 86:04dd9b1680ae 4486 */
bogdanm 86:04dd9b1680ae 4487
bogdanm 86:04dd9b1680ae 4488 /**
bogdanm 86:04dd9b1680ae 4489 * @}
bogdanm 86:04dd9b1680ae 4490 */
bogdanm 86:04dd9b1680ae 4491
bogdanm 86:04dd9b1680ae 4492 /** @addtogroup Exported_macros
bogdanm 86:04dd9b1680ae 4493 * @{
bogdanm 86:04dd9b1680ae 4494 */
bogdanm 86:04dd9b1680ae 4495
bogdanm 86:04dd9b1680ae 4496 /******************************* ADC Instances ********************************/
bogdanm 86:04dd9b1680ae 4497 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
bogdanm 86:04dd9b1680ae 4498
bogdanm 86:04dd9b1680ae 4499 /******************************* CRC Instances ********************************/
bogdanm 86:04dd9b1680ae 4500 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm 86:04dd9b1680ae 4501
bogdanm 86:04dd9b1680ae 4502 /******************************** DMA Instances *******************************/
bogdanm 86:04dd9b1680ae 4503 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
bogdanm 86:04dd9b1680ae 4504 ((INSTANCE) == DMA1_Stream1) || \
bogdanm 86:04dd9b1680ae 4505 ((INSTANCE) == DMA1_Stream2) || \
bogdanm 86:04dd9b1680ae 4506 ((INSTANCE) == DMA1_Stream3) || \
bogdanm 86:04dd9b1680ae 4507 ((INSTANCE) == DMA1_Stream4) || \
bogdanm 86:04dd9b1680ae 4508 ((INSTANCE) == DMA1_Stream5) || \
bogdanm 86:04dd9b1680ae 4509 ((INSTANCE) == DMA1_Stream6) || \
bogdanm 86:04dd9b1680ae 4510 ((INSTANCE) == DMA1_Stream7) || \
bogdanm 86:04dd9b1680ae 4511 ((INSTANCE) == DMA2_Stream0) || \
bogdanm 86:04dd9b1680ae 4512 ((INSTANCE) == DMA2_Stream1) || \
bogdanm 86:04dd9b1680ae 4513 ((INSTANCE) == DMA2_Stream2) || \
bogdanm 86:04dd9b1680ae 4514 ((INSTANCE) == DMA2_Stream3) || \
bogdanm 86:04dd9b1680ae 4515 ((INSTANCE) == DMA2_Stream4) || \
bogdanm 86:04dd9b1680ae 4516 ((INSTANCE) == DMA2_Stream5) || \
bogdanm 86:04dd9b1680ae 4517 ((INSTANCE) == DMA2_Stream6) || \
bogdanm 86:04dd9b1680ae 4518 ((INSTANCE) == DMA2_Stream7))
bogdanm 86:04dd9b1680ae 4519
bogdanm 86:04dd9b1680ae 4520 /******************************* GPIO Instances *******************************/
bogdanm 86:04dd9b1680ae 4521 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 86:04dd9b1680ae 4522 ((INSTANCE) == GPIOB) || \
bogdanm 86:04dd9b1680ae 4523 ((INSTANCE) == GPIOC) || \
bogdanm 86:04dd9b1680ae 4524 ((INSTANCE) == GPIOD) || \
bogdanm 86:04dd9b1680ae 4525 ((INSTANCE) == GPIOE) || \
bogdanm 86:04dd9b1680ae 4526 ((INSTANCE) == GPIOH))
bogdanm 86:04dd9b1680ae 4527
bogdanm 86:04dd9b1680ae 4528 /******************************** I2C Instances *******************************/
bogdanm 86:04dd9b1680ae 4529 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
bogdanm 86:04dd9b1680ae 4530 ((INSTANCE) == I2C2) || \
bogdanm 86:04dd9b1680ae 4531 ((INSTANCE) == I2C3))
bogdanm 86:04dd9b1680ae 4532
bogdanm 86:04dd9b1680ae 4533 /******************************** I2S Instances *******************************/
bogdanm 86:04dd9b1680ae 4534 #define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 86:04dd9b1680ae 4535 ((INSTANCE) == SPI2) || \
bogdanm 86:04dd9b1680ae 4536 ((INSTANCE) == SPI3) || \
bogdanm 86:04dd9b1680ae 4537 ((INSTANCE) == SPI4) || \
bogdanm 86:04dd9b1680ae 4538 ((INSTANCE) == SPI5))
bogdanm 86:04dd9b1680ae 4539
bogdanm 86:04dd9b1680ae 4540 /*************************** I2S Extended Instances ***************************/
bogdanm 86:04dd9b1680ae 4541 #define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
bogdanm 86:04dd9b1680ae 4542 ((INSTANCE) == SPI3) || \
bogdanm 86:04dd9b1680ae 4543 ((INSTANCE) == I2S2ext) || \
bogdanm 86:04dd9b1680ae 4544 ((INSTANCE) == I2S3ext))
bogdanm 86:04dd9b1680ae 4545
bogdanm 86:04dd9b1680ae 4546
bogdanm 86:04dd9b1680ae 4547 /****************************** RTC Instances *********************************/
bogdanm 86:04dd9b1680ae 4548 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm 86:04dd9b1680ae 4549
bogdanm 86:04dd9b1680ae 4550 /******************************** SPI Instances *******************************/
bogdanm 86:04dd9b1680ae 4551 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 86:04dd9b1680ae 4552 ((INSTANCE) == SPI2) || \
bogdanm 86:04dd9b1680ae 4553 ((INSTANCE) == SPI3) || \
bogdanm 86:04dd9b1680ae 4554 ((INSTANCE) == SPI4) || \
bogdanm 86:04dd9b1680ae 4555 ((INSTANCE) == SPI5))
bogdanm 86:04dd9b1680ae 4556 /*************************** SPI Extended Instances ***************************/
bogdanm 86:04dd9b1680ae 4557 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 86:04dd9b1680ae 4558 ((INSTANCE) == SPI2) || \
bogdanm 86:04dd9b1680ae 4559 ((INSTANCE) == SPI3) || \
bogdanm 86:04dd9b1680ae 4560 ((INSTANCE) == SPI4) || \
bogdanm 86:04dd9b1680ae 4561 ((INSTANCE) == SPI5) || \
bogdanm 86:04dd9b1680ae 4562 ((INSTANCE) == I2S2ext) || \
bogdanm 86:04dd9b1680ae 4563 ((INSTANCE) == I2S3ext))
bogdanm 86:04dd9b1680ae 4564
bogdanm 86:04dd9b1680ae 4565 /****************** TIM Instances : All supported instances *******************/
bogdanm 86:04dd9b1680ae 4566 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4567 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4568 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4569 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4570 ((INSTANCE) == TIM5) || \
bogdanm 86:04dd9b1680ae 4571 ((INSTANCE) == TIM9) || \
bogdanm 86:04dd9b1680ae 4572 ((INSTANCE) == TIM10) || \
bogdanm 86:04dd9b1680ae 4573 ((INSTANCE) == TIM11))
bogdanm 86:04dd9b1680ae 4574
bogdanm 86:04dd9b1680ae 4575 /************* TIM Instances : at least 1 capture/compare channel *************/
bogdanm 86:04dd9b1680ae 4576 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4577 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4578 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4579 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4580 ((INSTANCE) == TIM5) || \
bogdanm 86:04dd9b1680ae 4581 ((INSTANCE) == TIM9) || \
bogdanm 86:04dd9b1680ae 4582 ((INSTANCE) == TIM10) || \
bogdanm 86:04dd9b1680ae 4583 ((INSTANCE) == TIM11))
bogdanm 86:04dd9b1680ae 4584
bogdanm 86:04dd9b1680ae 4585 /************ TIM Instances : at least 2 capture/compare channels *************/
bogdanm 86:04dd9b1680ae 4586 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4587 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4588 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4589 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4590 ((INSTANCE) == TIM5) || \
bogdanm 86:04dd9b1680ae 4591 ((INSTANCE) == TIM9))
bogdanm 86:04dd9b1680ae 4592
bogdanm 86:04dd9b1680ae 4593 /************ TIM Instances : at least 3 capture/compare channels *************/
bogdanm 86:04dd9b1680ae 4594 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4595 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4596 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4597 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4598 ((INSTANCE) == TIM5))
bogdanm 86:04dd9b1680ae 4599
bogdanm 86:04dd9b1680ae 4600 /************ TIM Instances : at least 4 capture/compare channels *************/
bogdanm 86:04dd9b1680ae 4601 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4602 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4603 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4604 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4605 ((INSTANCE) == TIM5))
bogdanm 86:04dd9b1680ae 4606
bogdanm 86:04dd9b1680ae 4607 /******************** TIM Instances : Advanced-control timers *****************/
bogdanm 86:04dd9b1680ae 4608 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
bogdanm 86:04dd9b1680ae 4609
bogdanm 86:04dd9b1680ae 4610 /******************* TIM Instances : Timer input XOR function *****************/
bogdanm 86:04dd9b1680ae 4611 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4612 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4613 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4614 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4615 ((INSTANCE) == TIM5))
bogdanm 86:04dd9b1680ae 4616
bogdanm 86:04dd9b1680ae 4617 /****************** TIM Instances : DMA requests generation (UDE) *************/
bogdanm 86:04dd9b1680ae 4618 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4619 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4620 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4621 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4622 ((INSTANCE) == TIM5))
bogdanm 86:04dd9b1680ae 4623
bogdanm 86:04dd9b1680ae 4624 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
bogdanm 86:04dd9b1680ae 4625 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4626 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4627 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4628 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4629 ((INSTANCE) == TIM5))
bogdanm 86:04dd9b1680ae 4630
bogdanm 86:04dd9b1680ae 4631 /************ TIM Instances : DMA requests generation (COMDE) *****************/
bogdanm 86:04dd9b1680ae 4632 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4633 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4634 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4635 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4636 ((INSTANCE) == TIM5))
bogdanm 86:04dd9b1680ae 4637
bogdanm 86:04dd9b1680ae 4638 /******************** TIM Instances : DMA burst feature ***********************/
bogdanm 86:04dd9b1680ae 4639 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4640 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4641 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4642 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4643 ((INSTANCE) == TIM5))
bogdanm 86:04dd9b1680ae 4644
bogdanm 86:04dd9b1680ae 4645 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
bogdanm 86:04dd9b1680ae 4646 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4647 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4648 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4649 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4650 ((INSTANCE) == TIM5) || \
bogdanm 86:04dd9b1680ae 4651 ((INSTANCE) == TIM9))
bogdanm 86:04dd9b1680ae 4652
bogdanm 86:04dd9b1680ae 4653 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
bogdanm 86:04dd9b1680ae 4654 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4655 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4656 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4657 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4658 ((INSTANCE) == TIM5) || \
bogdanm 86:04dd9b1680ae 4659 ((INSTANCE) == TIM9))
bogdanm 86:04dd9b1680ae 4660
bogdanm 86:04dd9b1680ae 4661 /********************** TIM Instances : 32 bit Counter ************************/
bogdanm 86:04dd9b1680ae 4662 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4663 ((INSTANCE) == TIM5))
bogdanm 86:04dd9b1680ae 4664
bogdanm 86:04dd9b1680ae 4665 /***************** TIM Instances : external trigger input availabe ************/
bogdanm 86:04dd9b1680ae 4666 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
bogdanm 86:04dd9b1680ae 4667 ((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4668 ((INSTANCE) == TIM3) || \
bogdanm 86:04dd9b1680ae 4669 ((INSTANCE) == TIM4) || \
bogdanm 86:04dd9b1680ae 4670 ((INSTANCE) == TIM5))
bogdanm 86:04dd9b1680ae 4671
bogdanm 86:04dd9b1680ae 4672 /****************** TIM Instances : remapping capability **********************/
bogdanm 86:04dd9b1680ae 4673 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
bogdanm 86:04dd9b1680ae 4674 ((INSTANCE) == TIM5) || \
bogdanm 86:04dd9b1680ae 4675 ((INSTANCE) == TIM11))
bogdanm 86:04dd9b1680ae 4676
bogdanm 86:04dd9b1680ae 4677 /******************* TIM Instances : output(s) available **********************/
bogdanm 86:04dd9b1680ae 4678 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 86:04dd9b1680ae 4679 ((((INSTANCE) == TIM1) && \
bogdanm 86:04dd9b1680ae 4680 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 4681 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 4682 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 4683 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 86:04dd9b1680ae 4684 || \
bogdanm 86:04dd9b1680ae 4685 (((INSTANCE) == TIM2) && \
bogdanm 86:04dd9b1680ae 4686 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 4687 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 4688 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 4689 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 86:04dd9b1680ae 4690 || \
bogdanm 86:04dd9b1680ae 4691 (((INSTANCE) == TIM3) && \
bogdanm 86:04dd9b1680ae 4692 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 4693 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 4694 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 4695 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 86:04dd9b1680ae 4696 || \
bogdanm 86:04dd9b1680ae 4697 (((INSTANCE) == TIM4) && \
bogdanm 86:04dd9b1680ae 4698 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 4699 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 4700 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 4701 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 86:04dd9b1680ae 4702 || \
bogdanm 86:04dd9b1680ae 4703 (((INSTANCE) == TIM5) && \
bogdanm 86:04dd9b1680ae 4704 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 4705 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 4706 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 4707 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 86:04dd9b1680ae 4708 || \
bogdanm 86:04dd9b1680ae 4709 (((INSTANCE) == TIM9) && \
bogdanm 86:04dd9b1680ae 4710 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 4711 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 86:04dd9b1680ae 4712 || \
bogdanm 86:04dd9b1680ae 4713 (((INSTANCE) == TIM10) && \
bogdanm 86:04dd9b1680ae 4714 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 86:04dd9b1680ae 4715 || \
bogdanm 86:04dd9b1680ae 4716 (((INSTANCE) == TIM11) && \
bogdanm 86:04dd9b1680ae 4717 (((CHANNEL) == TIM_CHANNEL_1))))
bogdanm 86:04dd9b1680ae 4718
bogdanm 86:04dd9b1680ae 4719 /************ TIM Instances : complementary output(s) available ***************/
bogdanm 86:04dd9b1680ae 4720 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 86:04dd9b1680ae 4721 ((((INSTANCE) == TIM1) && \
bogdanm 86:04dd9b1680ae 4722 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 4723 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 4724 ((CHANNEL) == TIM_CHANNEL_3))))
bogdanm 86:04dd9b1680ae 4725
bogdanm 86:04dd9b1680ae 4726 /******************** USART Instances : Synchronous mode **********************/
bogdanm 86:04dd9b1680ae 4727 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 4728 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 4729 ((INSTANCE) == USART6))
bogdanm 86:04dd9b1680ae 4730
bogdanm 86:04dd9b1680ae 4731 /******************** UART Instances : Asynchronous mode **********************/
bogdanm 86:04dd9b1680ae 4732 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 4733 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 4734 ((INSTANCE) == USART6))
bogdanm 86:04dd9b1680ae 4735
bogdanm 86:04dd9b1680ae 4736 /****************** UART Instances : Hardware Flow control ********************/
bogdanm 86:04dd9b1680ae 4737 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 4738 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 4739 ((INSTANCE) == USART6))
bogdanm 86:04dd9b1680ae 4740
bogdanm 86:04dd9b1680ae 4741 /********************* UART Instances : Smard card mode ***********************/
bogdanm 86:04dd9b1680ae 4742 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 4743 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 4744 ((INSTANCE) == USART6))
bogdanm 86:04dd9b1680ae 4745
bogdanm 86:04dd9b1680ae 4746 /*********************** UART Instances : IRDA mode ***************************/
bogdanm 86:04dd9b1680ae 4747 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 86:04dd9b1680ae 4748 ((INSTANCE) == USART2) || \
bogdanm 86:04dd9b1680ae 4749 ((INSTANCE) == USART6))
bogdanm 86:04dd9b1680ae 4750
bogdanm 86:04dd9b1680ae 4751 /****************************** IWDG Instances ********************************/
bogdanm 86:04dd9b1680ae 4752 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm 86:04dd9b1680ae 4753
bogdanm 86:04dd9b1680ae 4754 /****************************** WWDG Instances ********************************/
bogdanm 86:04dd9b1680ae 4755 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm 86:04dd9b1680ae 4756
bogdanm 86:04dd9b1680ae 4757
bogdanm 86:04dd9b1680ae 4758 /**
bogdanm 86:04dd9b1680ae 4759 * @}
bogdanm 86:04dd9b1680ae 4760 */
bogdanm 86:04dd9b1680ae 4761
bogdanm 86:04dd9b1680ae 4762 /**
bogdanm 86:04dd9b1680ae 4763 * @}
bogdanm 86:04dd9b1680ae 4764 */
bogdanm 86:04dd9b1680ae 4765
bogdanm 86:04dd9b1680ae 4766 /**
bogdanm 86:04dd9b1680ae 4767 * @}
bogdanm 86:04dd9b1680ae 4768 */
bogdanm 86:04dd9b1680ae 4769
bogdanm 86:04dd9b1680ae 4770 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 4771 }
bogdanm 86:04dd9b1680ae 4772 #endif /* __cplusplus */
bogdanm 86:04dd9b1680ae 4773
bogdanm 86:04dd9b1680ae 4774 #endif /* __STM32F411xE_H */
bogdanm 86:04dd9b1680ae 4775
bogdanm 86:04dd9b1680ae 4776
bogdanm 86:04dd9b1680ae 4777
bogdanm 86:04dd9b1680ae 4778 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/