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TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_rcc_ex.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
93:e188a91d3eaa 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 93:e188a91d3eaa 1 /**
Kojto 93:e188a91d3eaa 2 ******************************************************************************
Kojto 93:e188a91d3eaa 3 * @file stm32f4xx_hal_rcc_ex.h
Kojto 93:e188a91d3eaa 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V1.1.0
Kojto 93:e188a91d3eaa 6 * @date 19-June-2014
Kojto 93:e188a91d3eaa 7 * @brief Header file of RCC HAL Extension module.
Kojto 93:e188a91d3eaa 8 ******************************************************************************
Kojto 93:e188a91d3eaa 9 * @attention
Kojto 93:e188a91d3eaa 10 *
Kojto 93:e188a91d3eaa 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 93:e188a91d3eaa 12 *
Kojto 93:e188a91d3eaa 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 93:e188a91d3eaa 14 * are permitted provided that the following conditions are met:
Kojto 93:e188a91d3eaa 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 93:e188a91d3eaa 16 * this list of conditions and the following disclaimer.
Kojto 93:e188a91d3eaa 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 93:e188a91d3eaa 18 * this list of conditions and the following disclaimer in the documentation
Kojto 93:e188a91d3eaa 19 * and/or other materials provided with the distribution.
Kojto 93:e188a91d3eaa 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 93:e188a91d3eaa 21 * may be used to endorse or promote products derived from this software
Kojto 93:e188a91d3eaa 22 * without specific prior written permission.
Kojto 93:e188a91d3eaa 23 *
Kojto 93:e188a91d3eaa 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 93:e188a91d3eaa 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 93:e188a91d3eaa 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 93:e188a91d3eaa 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 93:e188a91d3eaa 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 93:e188a91d3eaa 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 93:e188a91d3eaa 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 93:e188a91d3eaa 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 93:e188a91d3eaa 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 93:e188a91d3eaa 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 93:e188a91d3eaa 34 *
Kojto 93:e188a91d3eaa 35 ******************************************************************************
Kojto 93:e188a91d3eaa 36 */
Kojto 93:e188a91d3eaa 37
Kojto 93:e188a91d3eaa 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 93:e188a91d3eaa 39 #ifndef __STM32F4xx_HAL_RCC_EX_H
Kojto 93:e188a91d3eaa 40 #define __STM32F4xx_HAL_RCC_EX_H
Kojto 93:e188a91d3eaa 41
Kojto 93:e188a91d3eaa 42 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 43 extern "C" {
Kojto 93:e188a91d3eaa 44 #endif
Kojto 93:e188a91d3eaa 45
Kojto 93:e188a91d3eaa 46 /* Includes ------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 47 #include "stm32f4xx_hal_def.h"
Kojto 93:e188a91d3eaa 48
Kojto 93:e188a91d3eaa 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 93:e188a91d3eaa 50 * @{
Kojto 93:e188a91d3eaa 51 */
Kojto 93:e188a91d3eaa 52
Kojto 93:e188a91d3eaa 53 /** @addtogroup RCCEx
Kojto 93:e188a91d3eaa 54 * @{
Kojto 93:e188a91d3eaa 55 */
Kojto 93:e188a91d3eaa 56
Kojto 93:e188a91d3eaa 57 /* Exported types ------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 58 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 59 /**
Kojto 93:e188a91d3eaa 60 * @brief PLLI2S Clock structure definition
Kojto 93:e188a91d3eaa 61 */
Kojto 93:e188a91d3eaa 62 typedef struct
Kojto 93:e188a91d3eaa 63 {
Kojto 93:e188a91d3eaa 64 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 93:e188a91d3eaa 65 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 93:e188a91d3eaa 66 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 93:e188a91d3eaa 67
Kojto 93:e188a91d3eaa 68 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto 93:e188a91d3eaa 69 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 93:e188a91d3eaa 70 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 93:e188a91d3eaa 71
Kojto 93:e188a91d3eaa 72 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
Kojto 93:e188a91d3eaa 73 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 93:e188a91d3eaa 74 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 93:e188a91d3eaa 75 }RCC_PLLI2SInitTypeDef;
Kojto 93:e188a91d3eaa 76
Kojto 93:e188a91d3eaa 77 /**
Kojto 93:e188a91d3eaa 78 * @brief PLLSAI Clock structure definition
Kojto 93:e188a91d3eaa 79 */
Kojto 93:e188a91d3eaa 80 typedef struct
Kojto 93:e188a91d3eaa 81 {
Kojto 93:e188a91d3eaa 82 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 93:e188a91d3eaa 83 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 93:e188a91d3eaa 84 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto 93:e188a91d3eaa 85
Kojto 93:e188a91d3eaa 86 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
Kojto 93:e188a91d3eaa 87 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 93:e188a91d3eaa 88 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto 93:e188a91d3eaa 89
Kojto 93:e188a91d3eaa 90 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
Kojto 93:e188a91d3eaa 91 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 93:e188a91d3eaa 92 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
Kojto 93:e188a91d3eaa 93
Kojto 93:e188a91d3eaa 94 }RCC_PLLSAIInitTypeDef;
Kojto 93:e188a91d3eaa 95 /**
Kojto 93:e188a91d3eaa 96 * @brief RCC extended clocks structure definition
Kojto 93:e188a91d3eaa 97 */
Kojto 93:e188a91d3eaa 98 typedef struct
Kojto 93:e188a91d3eaa 99 {
Kojto 93:e188a91d3eaa 100 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 101 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 102
Kojto 93:e188a91d3eaa 103 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto 93:e188a91d3eaa 104 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 93:e188a91d3eaa 105
Kojto 93:e188a91d3eaa 106 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto 93:e188a91d3eaa 107 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto 93:e188a91d3eaa 108
Kojto 93:e188a91d3eaa 109 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 93:e188a91d3eaa 110 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 93:e188a91d3eaa 111 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 93:e188a91d3eaa 112
Kojto 93:e188a91d3eaa 113 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 93:e188a91d3eaa 114 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 93:e188a91d3eaa 115 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto 93:e188a91d3eaa 116
Kojto 93:e188a91d3eaa 117 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
Kojto 93:e188a91d3eaa 118 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
Kojto 93:e188a91d3eaa 119
Kojto 93:e188a91d3eaa 120 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto 93:e188a91d3eaa 121 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 122
Kojto 93:e188a91d3eaa 123 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
Kojto 93:e188a91d3eaa 124 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto 93:e188a91d3eaa 125
Kojto 93:e188a91d3eaa 126 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 127 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 93:e188a91d3eaa 128
Kojto 93:e188a91d3eaa 129 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
Kojto 93:e188a91d3eaa 130 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
Kojto 93:e188a91d3eaa 131 /**
Kojto 93:e188a91d3eaa 132 * @brief PLLI2S Clock structure definition
Kojto 93:e188a91d3eaa 133 */
Kojto 93:e188a91d3eaa 134 typedef struct
Kojto 93:e188a91d3eaa 135 {
Kojto 93:e188a91d3eaa 136 #if defined(STM32F411xE)
Kojto 93:e188a91d3eaa 137 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
Kojto 93:e188a91d3eaa 138 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
Kojto 93:e188a91d3eaa 139 #endif /* STM32F411xE */
Kojto 93:e188a91d3eaa 140
Kojto 93:e188a91d3eaa 141 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 93:e188a91d3eaa 142 This parameter must be a number between Min_Data = 192 and Max_Data = 432
Kojto 93:e188a91d3eaa 143 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 93:e188a91d3eaa 144
Kojto 93:e188a91d3eaa 145 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto 93:e188a91d3eaa 146 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 93:e188a91d3eaa 147 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 93:e188a91d3eaa 148
Kojto 93:e188a91d3eaa 149 }RCC_PLLI2SInitTypeDef;
Kojto 93:e188a91d3eaa 150
Kojto 93:e188a91d3eaa 151
Kojto 93:e188a91d3eaa 152 /**
Kojto 93:e188a91d3eaa 153 * @brief RCC extended clocks structure definition
Kojto 93:e188a91d3eaa 154 */
Kojto 93:e188a91d3eaa 155 typedef struct
Kojto 93:e188a91d3eaa 156 {
Kojto 93:e188a91d3eaa 157 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 158 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 159
Kojto 93:e188a91d3eaa 160 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto 93:e188a91d3eaa 161 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 93:e188a91d3eaa 162
Kojto 93:e188a91d3eaa 163 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto 93:e188a91d3eaa 164 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 165
Kojto 93:e188a91d3eaa 166 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 167 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
Kojto 93:e188a91d3eaa 168 /* Exported constants --------------------------------------------------------*/
Kojto 93:e188a91d3eaa 169 /** @defgroup RCCEx_Exported_Constants
Kojto 93:e188a91d3eaa 170 * @{
Kojto 93:e188a91d3eaa 171 */
Kojto 93:e188a91d3eaa 172
Kojto 93:e188a91d3eaa 173 /** @defgroup RCCEx_Periph_Clock_Selection
Kojto 93:e188a91d3eaa 174 * @{
Kojto 93:e188a91d3eaa 175 */
Kojto 93:e188a91d3eaa 176 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 177 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 178 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 179 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 180 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 181 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 182 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 183 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
Kojto 93:e188a91d3eaa 184 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 93:e188a91d3eaa 185
Kojto 93:e188a91d3eaa 186 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
Kojto 93:e188a91d3eaa 187 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
Kojto 93:e188a91d3eaa 188 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 189 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 190 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
Kojto 93:e188a91d3eaa 191 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
Kojto 93:e188a91d3eaa 192
Kojto 93:e188a91d3eaa 193 /**
Kojto 93:e188a91d3eaa 194 * @}
Kojto 93:e188a91d3eaa 195 */
Kojto 93:e188a91d3eaa 196
Kojto 93:e188a91d3eaa 197 /** @defgroup RCCEx_BitAddress_AliasRegion
Kojto 93:e188a91d3eaa 198 * @brief RCC registers bit address in the alias region
Kojto 93:e188a91d3eaa 199 * @{
Kojto 93:e188a91d3eaa 200 */
Kojto 93:e188a91d3eaa 201 /* --- CR Register ---*/
Kojto 93:e188a91d3eaa 202 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 203 /* Alias word address of PLLSAION bit */
Kojto 93:e188a91d3eaa 204 #define PLLSAION_BitNumber 0x1C
Kojto 93:e188a91d3eaa 205 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
Kojto 93:e188a91d3eaa 206
Kojto 93:e188a91d3eaa 207 /* --- DCKCFGR Register ---*/
Kojto 93:e188a91d3eaa 208 /* Alias word address of TIMPRE bit */
Kojto 93:e188a91d3eaa 209 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
Kojto 93:e188a91d3eaa 210 #define TIMPRE_BitNumber 0x18
Kojto 93:e188a91d3eaa 211 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
Kojto 93:e188a91d3eaa 212 /**
Kojto 93:e188a91d3eaa 213 * @}
Kojto 93:e188a91d3eaa 214 */
Kojto 93:e188a91d3eaa 215
Kojto 93:e188a91d3eaa 216 /** @defgroup RCCEx_PLLI2S_Clock_Source
Kojto 93:e188a91d3eaa 217 * @{
Kojto 93:e188a91d3eaa 218 */
Kojto 93:e188a91d3eaa 219 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto 93:e188a91d3eaa 220 /**
Kojto 93:e188a91d3eaa 221 * @}
Kojto 93:e188a91d3eaa 222 */
Kojto 93:e188a91d3eaa 223
Kojto 93:e188a91d3eaa 224 /** @defgroup RCCEx_PLLSAI_Clock_Source
Kojto 93:e188a91d3eaa 225 * @{
Kojto 93:e188a91d3eaa 226 */
Kojto 93:e188a91d3eaa 227 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto 93:e188a91d3eaa 228 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto 93:e188a91d3eaa 229 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 93:e188a91d3eaa 230 /**
Kojto 93:e188a91d3eaa 231 * @}
Kojto 93:e188a91d3eaa 232 */
Kojto 93:e188a91d3eaa 233
Kojto 93:e188a91d3eaa 234 /** @defgroup RCCEx_PLLSAI_DIVQ
Kojto 93:e188a91d3eaa 235 * @{
Kojto 93:e188a91d3eaa 236 */
Kojto 93:e188a91d3eaa 237 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto 93:e188a91d3eaa 238 /**
Kojto 93:e188a91d3eaa 239 * @}
Kojto 93:e188a91d3eaa 240 */
Kojto 93:e188a91d3eaa 241
Kojto 93:e188a91d3eaa 242 /** @defgroup RCCEx_PLLI2S_DIVQ
Kojto 93:e188a91d3eaa 243 * @{
Kojto 93:e188a91d3eaa 244 */
Kojto 93:e188a91d3eaa 245 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto 93:e188a91d3eaa 246
Kojto 93:e188a91d3eaa 247 /**
Kojto 93:e188a91d3eaa 248 * @}
Kojto 93:e188a91d3eaa 249 */
Kojto 93:e188a91d3eaa 250
Kojto 93:e188a91d3eaa 251 /** @defgroup RCCEx_PLLSAI_DIVR
Kojto 93:e188a91d3eaa 252 * @{
Kojto 93:e188a91d3eaa 253 */
Kojto 93:e188a91d3eaa 254 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 255 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 256 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 257 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
Kojto 93:e188a91d3eaa 258 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
Kojto 93:e188a91d3eaa 259 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
Kojto 93:e188a91d3eaa 260 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
Kojto 93:e188a91d3eaa 261 ((VALUE) == RCC_PLLSAIDIVR_16))
Kojto 93:e188a91d3eaa 262
Kojto 93:e188a91d3eaa 263 /**
Kojto 93:e188a91d3eaa 264 * @}
Kojto 93:e188a91d3eaa 265 */
Kojto 93:e188a91d3eaa 266
Kojto 93:e188a91d3eaa 267 /** @defgroup RCCEx_SAI_BlockA_Clock_Source
Kojto 93:e188a91d3eaa 268 * @{
Kojto 93:e188a91d3eaa 269 */
Kojto 93:e188a91d3eaa 270 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 271 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 272 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
Kojto 93:e188a91d3eaa 273 /**
Kojto 93:e188a91d3eaa 274 * @}
Kojto 93:e188a91d3eaa 275 */
Kojto 93:e188a91d3eaa 276
Kojto 93:e188a91d3eaa 277 /** @defgroup RCCEx_SAI_BlockB_Clock_Source
Kojto 93:e188a91d3eaa 278 * @{
Kojto 93:e188a91d3eaa 279 */
Kojto 93:e188a91d3eaa 280 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 281 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
Kojto 93:e188a91d3eaa 282 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
Kojto 93:e188a91d3eaa 283 /**
Kojto 93:e188a91d3eaa 284 * @}
Kojto 93:e188a91d3eaa 285 */
Kojto 93:e188a91d3eaa 286
Kojto 93:e188a91d3eaa 287 /** @defgroup RCCEx_TIM_PRescaler_Selection
Kojto 93:e188a91d3eaa 288 * @{
Kojto 93:e188a91d3eaa 289 */
Kojto 93:e188a91d3eaa 290 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 291 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 292 /**
Kojto 93:e188a91d3eaa 293 * @}
Kojto 93:e188a91d3eaa 294 */
Kojto 93:e188a91d3eaa 295 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 93:e188a91d3eaa 296
Kojto 93:e188a91d3eaa 297 #if defined(STM32F411xE)
Kojto 93:e188a91d3eaa 298 /** @defgroup RCCEx_PLLI2S_PLLI2SM
Kojto 93:e188a91d3eaa 299 * @{
Kojto 93:e188a91d3eaa 300 */
Kojto 93:e188a91d3eaa 301 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
Kojto 93:e188a91d3eaa 302 /**
Kojto 93:e188a91d3eaa 303 * @}
Kojto 93:e188a91d3eaa 304 */
Kojto 93:e188a91d3eaa 305
Kojto 93:e188a91d3eaa 306 /** @defgroup RCCEx_LSE_Dual_Mode_Selection
Kojto 93:e188a91d3eaa 307 * @{
Kojto 93:e188a91d3eaa 308 */
Kojto 93:e188a91d3eaa 309 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 310 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 311 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
Kojto 93:e188a91d3eaa 312 ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto 93:e188a91d3eaa 313 /**
Kojto 93:e188a91d3eaa 314 * @}
Kojto 93:e188a91d3eaa 315 */
Kojto 93:e188a91d3eaa 316
Kojto 93:e188a91d3eaa 317 #endif /* STM32F411xE */
Kojto 93:e188a91d3eaa 318 /**
Kojto 93:e188a91d3eaa 319 * @}
Kojto 93:e188a91d3eaa 320 */
Kojto 93:e188a91d3eaa 321
Kojto 93:e188a91d3eaa 322 /* Exported macro ------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 323
Kojto 93:e188a91d3eaa 324 /*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/
Kojto 93:e188a91d3eaa 325 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 326 /** @brief Enables or disables the AHB1 peripheral clock.
Kojto 93:e188a91d3eaa 327 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 328 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 329 * using it.
Kojto 93:e188a91d3eaa 330 */
Kojto 93:e188a91d3eaa 331 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
Kojto 93:e188a91d3eaa 332 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
Kojto 93:e188a91d3eaa 333 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
Kojto 93:e188a91d3eaa 334 #define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
Kojto 93:e188a91d3eaa 335 #define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
Kojto 93:e188a91d3eaa 336 #define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
Kojto 93:e188a91d3eaa 337 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
Kojto 93:e188a91d3eaa 338 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
Kojto 93:e188a91d3eaa 339 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
Kojto 93:e188a91d3eaa 340 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
Kojto 93:e188a91d3eaa 341 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
Kojto 93:e188a91d3eaa 342 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
Kojto 93:e188a91d3eaa 343
Kojto 93:e188a91d3eaa 344 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 93:e188a91d3eaa 345 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 93:e188a91d3eaa 346 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto 93:e188a91d3eaa 347 #define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto 93:e188a91d3eaa 348 #define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto 93:e188a91d3eaa 349 #define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto 93:e188a91d3eaa 350 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto 93:e188a91d3eaa 351 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto 93:e188a91d3eaa 352 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto 93:e188a91d3eaa 353 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto 93:e188a91d3eaa 354 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto 93:e188a91d3eaa 355 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto 93:e188a91d3eaa 356
Kojto 93:e188a91d3eaa 357 /**
Kojto 93:e188a91d3eaa 358 * @brief Enable ETHERNET clock.
Kojto 93:e188a91d3eaa 359 */
Kojto 93:e188a91d3eaa 360 #define __ETH_CLK_ENABLE() do { \
Kojto 93:e188a91d3eaa 361 __ETHMAC_CLK_ENABLE(); \
Kojto 93:e188a91d3eaa 362 __ETHMACTX_CLK_ENABLE(); \
Kojto 93:e188a91d3eaa 363 __ETHMACRX_CLK_ENABLE(); \
Kojto 93:e188a91d3eaa 364 } while(0)
Kojto 93:e188a91d3eaa 365 /**
Kojto 93:e188a91d3eaa 366 * @brief Disable ETHERNET clock.
Kojto 93:e188a91d3eaa 367 */
Kojto 93:e188a91d3eaa 368 #define __ETH_CLK_DISABLE() do { \
Kojto 93:e188a91d3eaa 369 __ETHMACTX_CLK_DISABLE(); \
Kojto 93:e188a91d3eaa 370 __ETHMACRX_CLK_DISABLE(); \
Kojto 93:e188a91d3eaa 371 __ETHMAC_CLK_DISABLE(); \
Kojto 93:e188a91d3eaa 372 } while(0)
Kojto 93:e188a91d3eaa 373
Kojto 93:e188a91d3eaa 374 /** @brief Enable or disable the AHB2 peripheral clock.
Kojto 93:e188a91d3eaa 375 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 376 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 377 * using it.
Kojto 93:e188a91d3eaa 378 */
Kojto 93:e188a91d3eaa 379
Kojto 93:e188a91d3eaa 380 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
Kojto 93:e188a91d3eaa 381 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto 93:e188a91d3eaa 382
Kojto 93:e188a91d3eaa 383 #if defined(STM32F437xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 384 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
Kojto 93:e188a91d3eaa 385 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
Kojto 93:e188a91d3eaa 386
Kojto 93:e188a91d3eaa 387 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto 93:e188a91d3eaa 388 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto 93:e188a91d3eaa 389 #endif /* STM32F437xx || STM32F439xx */
Kojto 93:e188a91d3eaa 390
Kojto 93:e188a91d3eaa 391 /** @brief Enables or disables the AHB3 peripheral clock.
Kojto 93:e188a91d3eaa 392 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 393 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 394 * using it.
Kojto 93:e188a91d3eaa 395 */
Kojto 93:e188a91d3eaa 396 #define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
Kojto 93:e188a91d3eaa 397 #define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto 93:e188a91d3eaa 398
Kojto 93:e188a91d3eaa 399 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 93:e188a91d3eaa 400 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 401 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 402 * using it.
Kojto 93:e188a91d3eaa 403 */
Kojto 93:e188a91d3eaa 404 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
Kojto 93:e188a91d3eaa 405 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
Kojto 93:e188a91d3eaa 406 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
Kojto 93:e188a91d3eaa 407 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
Kojto 93:e188a91d3eaa 408 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
Kojto 93:e188a91d3eaa 409 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
Kojto 93:e188a91d3eaa 410 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
Kojto 93:e188a91d3eaa 411 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
Kojto 93:e188a91d3eaa 412 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
Kojto 93:e188a91d3eaa 413 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
Kojto 93:e188a91d3eaa 414 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
Kojto 93:e188a91d3eaa 415 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
Kojto 93:e188a91d3eaa 416 #define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
Kojto 93:e188a91d3eaa 417 #define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
Kojto 93:e188a91d3eaa 418
Kojto 93:e188a91d3eaa 419 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 93:e188a91d3eaa 420 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 93:e188a91d3eaa 421 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 93:e188a91d3eaa 422 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 93:e188a91d3eaa 423 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 93:e188a91d3eaa 424 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 93:e188a91d3eaa 425 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 93:e188a91d3eaa 426 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 93:e188a91d3eaa 427 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 93:e188a91d3eaa 428 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto 93:e188a91d3eaa 429 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto 93:e188a91d3eaa 430 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 93:e188a91d3eaa 431 #define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto 93:e188a91d3eaa 432 #define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto 93:e188a91d3eaa 433
Kojto 93:e188a91d3eaa 434 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 93:e188a91d3eaa 435 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 436 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 437 * using it.
Kojto 93:e188a91d3eaa 438 */
Kojto 93:e188a91d3eaa 439 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
Kojto 93:e188a91d3eaa 440 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
Kojto 93:e188a91d3eaa 441 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
Kojto 93:e188a91d3eaa 442 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
Kojto 93:e188a91d3eaa 443 #define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
Kojto 93:e188a91d3eaa 444 #define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
Kojto 93:e188a91d3eaa 445
Kojto 93:e188a91d3eaa 446 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 93:e188a91d3eaa 447 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto 93:e188a91d3eaa 448 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto 93:e188a91d3eaa 449 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto 93:e188a91d3eaa 450 #define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto 93:e188a91d3eaa 451 #define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto 93:e188a91d3eaa 452
Kojto 93:e188a91d3eaa 453 #if defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 454 #define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
Kojto 93:e188a91d3eaa 455
Kojto 93:e188a91d3eaa 456 #define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto 93:e188a91d3eaa 457 #endif /* STM32F429xx || STM32F439xx */
Kojto 93:e188a91d3eaa 458
Kojto 93:e188a91d3eaa 459 /** @brief Force or release AHB1 peripheral reset.
Kojto 93:e188a91d3eaa 460 */
Kojto 93:e188a91d3eaa 461 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
Kojto 93:e188a91d3eaa 462 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
Kojto 93:e188a91d3eaa 463 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
Kojto 93:e188a91d3eaa 464 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
Kojto 93:e188a91d3eaa 465 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
Kojto 93:e188a91d3eaa 466 #define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
Kojto 93:e188a91d3eaa 467 #define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
Kojto 93:e188a91d3eaa 468 #define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
Kojto 93:e188a91d3eaa 469
Kojto 93:e188a91d3eaa 470 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 93:e188a91d3eaa 471 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 93:e188a91d3eaa 472 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 93:e188a91d3eaa 473 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto 93:e188a91d3eaa 474 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto 93:e188a91d3eaa 475 #define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto 93:e188a91d3eaa 476 #define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto 93:e188a91d3eaa 477 #define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto 93:e188a91d3eaa 478
Kojto 93:e188a91d3eaa 479 /** @brief Force or release AHB2 peripheral reset.
Kojto 93:e188a91d3eaa 480 */
Kojto 93:e188a91d3eaa 481 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
Kojto 93:e188a91d3eaa 482 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto 93:e188a91d3eaa 483
Kojto 93:e188a91d3eaa 484 #if defined(STM32F437xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 485 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
Kojto 93:e188a91d3eaa 486 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
Kojto 93:e188a91d3eaa 487
Kojto 93:e188a91d3eaa 488 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto 93:e188a91d3eaa 489 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto 93:e188a91d3eaa 490 #endif /* STM32F437xx || STM32F439xx */
Kojto 93:e188a91d3eaa 491
Kojto 93:e188a91d3eaa 492 /** @brief Force or release AHB3 peripheral reset
Kojto 93:e188a91d3eaa 493 */
Kojto 93:e188a91d3eaa 494 #define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
Kojto 93:e188a91d3eaa 495 #define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto 93:e188a91d3eaa 496
Kojto 93:e188a91d3eaa 497 /** @brief Force or release APB1 peripheral reset.
Kojto 93:e188a91d3eaa 498 */
Kojto 93:e188a91d3eaa 499 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 93:e188a91d3eaa 500 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 93:e188a91d3eaa 501 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 93:e188a91d3eaa 502 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 93:e188a91d3eaa 503 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 93:e188a91d3eaa 504 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 93:e188a91d3eaa 505 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 93:e188a91d3eaa 506 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 93:e188a91d3eaa 507 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
Kojto 93:e188a91d3eaa 508 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
Kojto 93:e188a91d3eaa 509 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 93:e188a91d3eaa 510 #define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
Kojto 93:e188a91d3eaa 511 #define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
Kojto 93:e188a91d3eaa 512
Kojto 93:e188a91d3eaa 513 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 93:e188a91d3eaa 514 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 93:e188a91d3eaa 515 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 93:e188a91d3eaa 516 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 93:e188a91d3eaa 517 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 93:e188a91d3eaa 518 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 93:e188a91d3eaa 519 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 93:e188a91d3eaa 520 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 93:e188a91d3eaa 521 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto 93:e188a91d3eaa 522 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto 93:e188a91d3eaa 523 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 93:e188a91d3eaa 524 #define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto 93:e188a91d3eaa 525 #define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto 93:e188a91d3eaa 526
Kojto 93:e188a91d3eaa 527 /** @brief Force or release APB2 peripheral reset.
Kojto 93:e188a91d3eaa 528 */
Kojto 93:e188a91d3eaa 529 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 93:e188a91d3eaa 530 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
Kojto 93:e188a91d3eaa 531 #define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
Kojto 93:e188a91d3eaa 532 #define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
Kojto 93:e188a91d3eaa 533
Kojto 93:e188a91d3eaa 534 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 93:e188a91d3eaa 535 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto 93:e188a91d3eaa 536 #define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto 93:e188a91d3eaa 537 #define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto 93:e188a91d3eaa 538
Kojto 93:e188a91d3eaa 539 #if defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 540 #define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
Kojto 93:e188a91d3eaa 541 #define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto 93:e188a91d3eaa 542 #endif /* STM32F429xx|| STM32F439xx */
Kojto 93:e188a91d3eaa 543
Kojto 93:e188a91d3eaa 544 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 545 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 546 * power consumption.
Kojto 93:e188a91d3eaa 547 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 548 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 549 */
Kojto 93:e188a91d3eaa 550 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto 93:e188a91d3eaa 551 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto 93:e188a91d3eaa 552 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
Kojto 93:e188a91d3eaa 553 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto 93:e188a91d3eaa 554 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto 93:e188a91d3eaa 555 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 93:e188a91d3eaa 556 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 93:e188a91d3eaa 557 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 93:e188a91d3eaa 558 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto 93:e188a91d3eaa 559 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 93:e188a91d3eaa 560 #define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto 93:e188a91d3eaa 561 #define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto 93:e188a91d3eaa 562 #define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
Kojto 93:e188a91d3eaa 563 #define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto 93:e188a91d3eaa 564
Kojto 93:e188a91d3eaa 565 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto 93:e188a91d3eaa 566 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto 93:e188a91d3eaa 567 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto 93:e188a91d3eaa 568 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto 93:e188a91d3eaa 569 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto 93:e188a91d3eaa 570 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 93:e188a91d3eaa 571 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 93:e188a91d3eaa 572 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 93:e188a91d3eaa 573 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto 93:e188a91d3eaa 574 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 93:e188a91d3eaa 575 #define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto 93:e188a91d3eaa 576 #define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto 93:e188a91d3eaa 577 #define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto 93:e188a91d3eaa 578
Kojto 93:e188a91d3eaa 579 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 580 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 581 * power consumption.
Kojto 93:e188a91d3eaa 582 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 583 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 584 */
Kojto 93:e188a91d3eaa 585 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Kojto 93:e188a91d3eaa 586 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto 93:e188a91d3eaa 587
Kojto 93:e188a91d3eaa 588 #if defined(STM32F437xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 589 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
Kojto 93:e188a91d3eaa 590 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
Kojto 93:e188a91d3eaa 591
Kojto 93:e188a91d3eaa 592 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto 93:e188a91d3eaa 593 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto 93:e188a91d3eaa 594 #endif /* STM32F437xx || STM32F439xx */
Kojto 93:e188a91d3eaa 595
Kojto 93:e188a91d3eaa 596 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 597 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 598 * power consumption.
Kojto 93:e188a91d3eaa 599 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 600 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 601 */
Kojto 93:e188a91d3eaa 602 #define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
Kojto 93:e188a91d3eaa 603 #define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto 93:e188a91d3eaa 604
Kojto 93:e188a91d3eaa 605 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 606 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 607 * power consumption.
Kojto 93:e188a91d3eaa 608 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 609 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 610 */
Kojto 93:e188a91d3eaa 611 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
Kojto 93:e188a91d3eaa 612 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
Kojto 93:e188a91d3eaa 613 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
Kojto 93:e188a91d3eaa 614 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
Kojto 93:e188a91d3eaa 615 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
Kojto 93:e188a91d3eaa 616 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
Kojto 93:e188a91d3eaa 617 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
Kojto 93:e188a91d3eaa 618 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
Kojto 93:e188a91d3eaa 619 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
Kojto 93:e188a91d3eaa 620 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
Kojto 93:e188a91d3eaa 621 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
Kojto 93:e188a91d3eaa 622 #define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
Kojto 93:e188a91d3eaa 623 #define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
Kojto 93:e188a91d3eaa 624
Kojto 93:e188a91d3eaa 625 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto 93:e188a91d3eaa 626 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto 93:e188a91d3eaa 627 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto 93:e188a91d3eaa 628 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto 93:e188a91d3eaa 629 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto 93:e188a91d3eaa 630 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto 93:e188a91d3eaa 631 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto 93:e188a91d3eaa 632 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto 93:e188a91d3eaa 633 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto 93:e188a91d3eaa 634 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto 93:e188a91d3eaa 635 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto 93:e188a91d3eaa 636 #define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto 93:e188a91d3eaa 637 #define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto 93:e188a91d3eaa 638
Kojto 93:e188a91d3eaa 639 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 640 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 641 * power consumption.
Kojto 93:e188a91d3eaa 642 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 643 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 644 */
Kojto 93:e188a91d3eaa 645 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
Kojto 93:e188a91d3eaa 646 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
Kojto 93:e188a91d3eaa 647 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
Kojto 93:e188a91d3eaa 648 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
Kojto 93:e188a91d3eaa 649 #define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
Kojto 93:e188a91d3eaa 650 #define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
Kojto 93:e188a91d3eaa 651
Kojto 93:e188a91d3eaa 652 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto 93:e188a91d3eaa 653 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto 93:e188a91d3eaa 654 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto 93:e188a91d3eaa 655 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto 93:e188a91d3eaa 656 #define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto 93:e188a91d3eaa 657 #define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto 93:e188a91d3eaa 658
Kojto 93:e188a91d3eaa 659 #if defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 93:e188a91d3eaa 660 #define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
Kojto 93:e188a91d3eaa 661
Kojto 93:e188a91d3eaa 662 #define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto 93:e188a91d3eaa 663 #endif /* STM32F429xx || STM32F439xx */
Kojto 93:e188a91d3eaa 664 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
Kojto 93:e188a91d3eaa 665 /*---------------------------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 666
Kojto 93:e188a91d3eaa 667 /*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/
Kojto 93:e188a91d3eaa 668 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 93:e188a91d3eaa 669 /** @brief Enables or disables the AHB1 peripheral clock.
Kojto 93:e188a91d3eaa 670 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 671 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 672 * using it.
Kojto 93:e188a91d3eaa 673 */
Kojto 93:e188a91d3eaa 674 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
Kojto 93:e188a91d3eaa 675 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
Kojto 93:e188a91d3eaa 676 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
Kojto 93:e188a91d3eaa 677 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
Kojto 93:e188a91d3eaa 678 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
Kojto 93:e188a91d3eaa 679
Kojto 93:e188a91d3eaa 680 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 93:e188a91d3eaa 681 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 93:e188a91d3eaa 682 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto 93:e188a91d3eaa 683 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto 93:e188a91d3eaa 684 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto 93:e188a91d3eaa 685
Kojto 93:e188a91d3eaa 686 #if defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 93:e188a91d3eaa 687 /**
Kojto 93:e188a91d3eaa 688 * @brief Enable ETHERNET clock.
Kojto 93:e188a91d3eaa 689 */
Kojto 93:e188a91d3eaa 690 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
Kojto 93:e188a91d3eaa 691 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
Kojto 93:e188a91d3eaa 692 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
Kojto 93:e188a91d3eaa 693 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
Kojto 93:e188a91d3eaa 694 #define __ETH_CLK_ENABLE() do { \
Kojto 93:e188a91d3eaa 695 __ETHMAC_CLK_ENABLE(); \
Kojto 93:e188a91d3eaa 696 __ETHMACTX_CLK_ENABLE(); \
Kojto 93:e188a91d3eaa 697 __ETHMACRX_CLK_ENABLE(); \
Kojto 93:e188a91d3eaa 698 } while(0)
Kojto 93:e188a91d3eaa 699
Kojto 93:e188a91d3eaa 700 /**
Kojto 93:e188a91d3eaa 701 * @brief Disable ETHERNET clock.
Kojto 93:e188a91d3eaa 702 */
Kojto 93:e188a91d3eaa 703 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto 93:e188a91d3eaa 704 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto 93:e188a91d3eaa 705 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto 93:e188a91d3eaa 706 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto 93:e188a91d3eaa 707 #define __ETH_CLK_DISABLE() do { \
Kojto 93:e188a91d3eaa 708 __ETHMACTX_CLK_DISABLE(); \
Kojto 93:e188a91d3eaa 709 __ETHMACRX_CLK_DISABLE(); \
Kojto 93:e188a91d3eaa 710 __ETHMAC_CLK_DISABLE(); \
Kojto 93:e188a91d3eaa 711 } while(0)
Kojto 93:e188a91d3eaa 712 #endif /* STM32F407xx || STM32F417xx */
Kojto 93:e188a91d3eaa 713
Kojto 93:e188a91d3eaa 714 /** @brief Enable or disable the AHB2 peripheral clock.
Kojto 93:e188a91d3eaa 715 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 716 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 717 * using it.
Kojto 93:e188a91d3eaa 718 */
Kojto 93:e188a91d3eaa 719 #if defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 93:e188a91d3eaa 720 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
Kojto 93:e188a91d3eaa 721 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto 93:e188a91d3eaa 722 #endif /* STM32F407xx || STM32F417xx */
Kojto 93:e188a91d3eaa 723
Kojto 93:e188a91d3eaa 724 #if defined(STM32F415xx) || defined(STM32F417xx)
Kojto 93:e188a91d3eaa 725 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
Kojto 93:e188a91d3eaa 726 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
Kojto 93:e188a91d3eaa 727
Kojto 93:e188a91d3eaa 728 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto 93:e188a91d3eaa 729 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto 93:e188a91d3eaa 730 #endif /* STM32F415xx || STM32F417xx */
Kojto 93:e188a91d3eaa 731
Kojto 93:e188a91d3eaa 732 /** @brief Enables or disables the AHB3 peripheral clock.
Kojto 93:e188a91d3eaa 733 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 734 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 735 * using it.
Kojto 93:e188a91d3eaa 736 */
Kojto 93:e188a91d3eaa 737 #define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
Kojto 93:e188a91d3eaa 738 #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
Kojto 93:e188a91d3eaa 739
Kojto 93:e188a91d3eaa 740 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 93:e188a91d3eaa 741 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 742 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 743 * using it.
Kojto 93:e188a91d3eaa 744 */
Kojto 93:e188a91d3eaa 745 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
Kojto 93:e188a91d3eaa 746 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
Kojto 93:e188a91d3eaa 747 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
Kojto 93:e188a91d3eaa 748 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
Kojto 93:e188a91d3eaa 749 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
Kojto 93:e188a91d3eaa 750 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
Kojto 93:e188a91d3eaa 751 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
Kojto 93:e188a91d3eaa 752 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
Kojto 93:e188a91d3eaa 753 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
Kojto 93:e188a91d3eaa 754 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
Kojto 93:e188a91d3eaa 755 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
Kojto 93:e188a91d3eaa 756 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
Kojto 93:e188a91d3eaa 757
Kojto 93:e188a91d3eaa 758 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 93:e188a91d3eaa 759 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 93:e188a91d3eaa 760 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 93:e188a91d3eaa 761 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 93:e188a91d3eaa 762 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 93:e188a91d3eaa 763 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 93:e188a91d3eaa 764 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 93:e188a91d3eaa 765 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 93:e188a91d3eaa 766 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 93:e188a91d3eaa 767 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto 93:e188a91d3eaa 768 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto 93:e188a91d3eaa 769 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 93:e188a91d3eaa 770
Kojto 93:e188a91d3eaa 771 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 93:e188a91d3eaa 772 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 773 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 774 * using it.
Kojto 93:e188a91d3eaa 775 */
Kojto 93:e188a91d3eaa 776 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
Kojto 93:e188a91d3eaa 777 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
Kojto 93:e188a91d3eaa 778 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
Kojto 93:e188a91d3eaa 779
Kojto 93:e188a91d3eaa 780 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 93:e188a91d3eaa 781 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto 93:e188a91d3eaa 782 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto 93:e188a91d3eaa 783
Kojto 93:e188a91d3eaa 784 /** @brief Force or release AHB1 peripheral reset.
Kojto 93:e188a91d3eaa 785 */
Kojto 93:e188a91d3eaa 786 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
Kojto 93:e188a91d3eaa 787 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
Kojto 93:e188a91d3eaa 788 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
Kojto 93:e188a91d3eaa 789 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
Kojto 93:e188a91d3eaa 790 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
Kojto 93:e188a91d3eaa 791
Kojto 93:e188a91d3eaa 792 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 93:e188a91d3eaa 793 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 93:e188a91d3eaa 794 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 93:e188a91d3eaa 795 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto 93:e188a91d3eaa 796 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto 93:e188a91d3eaa 797
Kojto 93:e188a91d3eaa 798 /** @brief Force or release AHB2 peripheral reset.
Kojto 93:e188a91d3eaa 799 */
Kojto 93:e188a91d3eaa 800 #if defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 93:e188a91d3eaa 801 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
Kojto 93:e188a91d3eaa 802 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto 93:e188a91d3eaa 803 #endif /* STM32F407xx || STM32F417xx */
Kojto 93:e188a91d3eaa 804
Kojto 93:e188a91d3eaa 805 #if defined(STM32F415xx) || defined(STM32F417xx)
Kojto 93:e188a91d3eaa 806 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
Kojto 93:e188a91d3eaa 807 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
Kojto 93:e188a91d3eaa 808
Kojto 93:e188a91d3eaa 809 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto 93:e188a91d3eaa 810 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto 93:e188a91d3eaa 811
Kojto 93:e188a91d3eaa 812 #endif /* STM32F415xx || STM32F417xx */
Kojto 93:e188a91d3eaa 813
Kojto 93:e188a91d3eaa 814 /** @brief Force or release AHB3 peripheral reset
Kojto 93:e188a91d3eaa 815 */
Kojto 93:e188a91d3eaa 816 #define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
Kojto 93:e188a91d3eaa 817 #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
Kojto 93:e188a91d3eaa 818
Kojto 93:e188a91d3eaa 819 /** @brief Force or release APB1 peripheral reset.
Kojto 93:e188a91d3eaa 820 */
Kojto 93:e188a91d3eaa 821 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 93:e188a91d3eaa 822 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 93:e188a91d3eaa 823 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 93:e188a91d3eaa 824 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 93:e188a91d3eaa 825 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 93:e188a91d3eaa 826 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 93:e188a91d3eaa 827 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 93:e188a91d3eaa 828 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 93:e188a91d3eaa 829 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
Kojto 93:e188a91d3eaa 830 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
Kojto 93:e188a91d3eaa 831 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 93:e188a91d3eaa 832
Kojto 93:e188a91d3eaa 833 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 93:e188a91d3eaa 834 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 93:e188a91d3eaa 835 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 93:e188a91d3eaa 836 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 93:e188a91d3eaa 837 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 93:e188a91d3eaa 838 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 93:e188a91d3eaa 839 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 93:e188a91d3eaa 840 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 93:e188a91d3eaa 841 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto 93:e188a91d3eaa 842 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto 93:e188a91d3eaa 843 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 93:e188a91d3eaa 844
Kojto 93:e188a91d3eaa 845 /** @brief Force or release APB2 peripheral reset.
Kojto 93:e188a91d3eaa 846 */
Kojto 93:e188a91d3eaa 847 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 93:e188a91d3eaa 848 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 93:e188a91d3eaa 849
Kojto 93:e188a91d3eaa 850 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 851 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 852 * power consumption.
Kojto 93:e188a91d3eaa 853 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 854 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 855 */
Kojto 93:e188a91d3eaa 856 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto 93:e188a91d3eaa 857 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto 93:e188a91d3eaa 858 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
Kojto 93:e188a91d3eaa 859 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto 93:e188a91d3eaa 860 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto 93:e188a91d3eaa 861 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 93:e188a91d3eaa 862 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 93:e188a91d3eaa 863 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 93:e188a91d3eaa 864 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto 93:e188a91d3eaa 865 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 93:e188a91d3eaa 866
Kojto 93:e188a91d3eaa 867 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto 93:e188a91d3eaa 868 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto 93:e188a91d3eaa 869 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto 93:e188a91d3eaa 870 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto 93:e188a91d3eaa 871 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto 93:e188a91d3eaa 872 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 93:e188a91d3eaa 873 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 93:e188a91d3eaa 874 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 93:e188a91d3eaa 875 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto 93:e188a91d3eaa 876 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 93:e188a91d3eaa 877
Kojto 93:e188a91d3eaa 878 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 879 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 880 * power consumption.
Kojto 93:e188a91d3eaa 881 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 882 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 883 */
Kojto 93:e188a91d3eaa 884 #if defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 93:e188a91d3eaa 885 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Kojto 93:e188a91d3eaa 886 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto 93:e188a91d3eaa 887 #endif /* STM32F407xx || STM32F417xx */
Kojto 93:e188a91d3eaa 888
Kojto 93:e188a91d3eaa 889 #if defined(STM32F415xx) || defined(STM32F417xx)
Kojto 93:e188a91d3eaa 890 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
Kojto 93:e188a91d3eaa 891 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
Kojto 93:e188a91d3eaa 892
Kojto 93:e188a91d3eaa 893 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto 93:e188a91d3eaa 894 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto 93:e188a91d3eaa 895 #endif /* STM32F415xx || STM32F417xx */
Kojto 93:e188a91d3eaa 896
Kojto 93:e188a91d3eaa 897 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 898 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 899 * power consumption.
Kojto 93:e188a91d3eaa 900 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 901 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 902 */
Kojto 93:e188a91d3eaa 903 #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
Kojto 93:e188a91d3eaa 904 #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
Kojto 93:e188a91d3eaa 905
Kojto 93:e188a91d3eaa 906 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 907 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 908 * power consumption.
Kojto 93:e188a91d3eaa 909 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 910 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 911 */
Kojto 93:e188a91d3eaa 912 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
Kojto 93:e188a91d3eaa 913 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
Kojto 93:e188a91d3eaa 914 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
Kojto 93:e188a91d3eaa 915 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
Kojto 93:e188a91d3eaa 916 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
Kojto 93:e188a91d3eaa 917 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
Kojto 93:e188a91d3eaa 918 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
Kojto 93:e188a91d3eaa 919 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
Kojto 93:e188a91d3eaa 920 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
Kojto 93:e188a91d3eaa 921 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
Kojto 93:e188a91d3eaa 922 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
Kojto 93:e188a91d3eaa 923
Kojto 93:e188a91d3eaa 924 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto 93:e188a91d3eaa 925 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto 93:e188a91d3eaa 926 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto 93:e188a91d3eaa 927 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto 93:e188a91d3eaa 928 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto 93:e188a91d3eaa 929 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto 93:e188a91d3eaa 930 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto 93:e188a91d3eaa 931 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto 93:e188a91d3eaa 932 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto 93:e188a91d3eaa 933 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto 93:e188a91d3eaa 934 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto 93:e188a91d3eaa 935
Kojto 93:e188a91d3eaa 936 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 937 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 938 * power consumption.
Kojto 93:e188a91d3eaa 939 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 940 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 941 */
Kojto 93:e188a91d3eaa 942 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
Kojto 93:e188a91d3eaa 943 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
Kojto 93:e188a91d3eaa 944 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
Kojto 93:e188a91d3eaa 945
Kojto 93:e188a91d3eaa 946 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto 93:e188a91d3eaa 947 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto 93:e188a91d3eaa 948 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto 93:e188a91d3eaa 949 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 93:e188a91d3eaa 950 /*---------------------------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 951
Kojto 93:e188a91d3eaa 952 /*------------------------------------------ STM32F411xx --------------------------------------*/
Kojto 93:e188a91d3eaa 953 #if defined(STM32F411xE)
Kojto 93:e188a91d3eaa 954 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 93:e188a91d3eaa 955 */
Kojto 93:e188a91d3eaa 956 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
Kojto 93:e188a91d3eaa 957 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto 93:e188a91d3eaa 958
Kojto 93:e188a91d3eaa 959 /** @brief Force or release APB2 peripheral reset.
Kojto 93:e188a91d3eaa 960 */
Kojto 93:e188a91d3eaa 961 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
Kojto 93:e188a91d3eaa 962 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto 93:e188a91d3eaa 963
Kojto 93:e188a91d3eaa 964 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 965 */
Kojto 93:e188a91d3eaa 966 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
Kojto 93:e188a91d3eaa 967 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto 93:e188a91d3eaa 968
Kojto 93:e188a91d3eaa 969 #endif /* STM32F411xE */
Kojto 93:e188a91d3eaa 970 /*---------------------------------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 971
Kojto 93:e188a91d3eaa 972 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
Kojto 93:e188a91d3eaa 973 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
Kojto 93:e188a91d3eaa 974
Kojto 93:e188a91d3eaa 975 /** @brief Macro to configure the Timers clocks prescalers
Kojto 93:e188a91d3eaa 976 * @note This feature is only available with STM32F429x/439x Devices.
Kojto 93:e188a91d3eaa 977 * @param __PRESC__ : specifies the Timers clocks prescalers selection
Kojto 93:e188a91d3eaa 978 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 979 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
Kojto 93:e188a91d3eaa 980 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
Kojto 93:e188a91d3eaa 981 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
Kojto 93:e188a91d3eaa 982 * division by 4 or more.
Kojto 93:e188a91d3eaa 983 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
Kojto 93:e188a91d3eaa 984 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
Kojto 93:e188a91d3eaa 985 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
Kojto 93:e188a91d3eaa 986 * to division by 8 or more.
Kojto 93:e188a91d3eaa 987 */
Kojto 93:e188a91d3eaa 988 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
Kojto 93:e188a91d3eaa 989
Kojto 93:e188a91d3eaa 990 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */
Kojto 93:e188a91d3eaa 991
Kojto 93:e188a91d3eaa 992 #if defined(STM32F411xE)
Kojto 93:e188a91d3eaa 993
Kojto 93:e188a91d3eaa 994 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto 93:e188a91d3eaa 995 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 93:e188a91d3eaa 996 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 93:e188a91d3eaa 997 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 93:e188a91d3eaa 998 * HAL_RCC_ClockConfig() API).
Kojto 93:e188a91d3eaa 999 * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto 93:e188a91d3eaa 1000 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 93:e188a91d3eaa 1001 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto 93:e188a91d3eaa 1002 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 93:e188a91d3eaa 1003 * of 2 MHz to limit PLLI2S jitter.
Kojto 93:e188a91d3eaa 1004 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto 93:e188a91d3eaa 1005 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 93:e188a91d3eaa 1006 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 93:e188a91d3eaa 1007 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 93:e188a91d3eaa 1008 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 93:e188a91d3eaa 1009 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 93:e188a91d3eaa 1010 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 93:e188a91d3eaa 1011 * on the I2S clock frequency.
Kojto 93:e188a91d3eaa 1012 */
Kojto 93:e188a91d3eaa 1013 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
Kojto 93:e188a91d3eaa 1014 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__))
Kojto 93:e188a91d3eaa 1015 #endif /* STM32F411xE */
Kojto 93:e188a91d3eaa 1016
Kojto 93:e188a91d3eaa 1017
Kojto 93:e188a91d3eaa 1018 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 93:e188a91d3eaa 1019
Kojto 93:e188a91d3eaa 1020 /** @brief Macros to Enable or Disable the PLLISAI.
Kojto 93:e188a91d3eaa 1021 * @note The PLLSAI is only available with STM32F429x/439x Devices.
Kojto 93:e188a91d3eaa 1022 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 1023 */
Kojto 93:e188a91d3eaa 1024 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
Kojto 93:e188a91d3eaa 1025 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
Kojto 93:e188a91d3eaa 1026
Kojto 93:e188a91d3eaa 1027 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto 93:e188a91d3eaa 1028 * @note The PLLSAI is only available with STM32F429x/439x Devices.
Kojto 93:e188a91d3eaa 1029 * @note This function must be used only when the PLLSAI is disabled.
Kojto 93:e188a91d3eaa 1030 * @note PLLSAI clock source is common with the main PLL (configured in
Kojto 93:e188a91d3eaa 1031 * RCC_PLLConfig function )
Kojto 93:e188a91d3eaa 1032 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto 93:e188a91d3eaa 1033 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 93:e188a91d3eaa 1034 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto 93:e188a91d3eaa 1035 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 93:e188a91d3eaa 1036 * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
Kojto 93:e188a91d3eaa 1037 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 93:e188a91d3eaa 1038 * @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto 93:e188a91d3eaa 1039 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 93:e188a91d3eaa 1040 */
Kojto 93:e188a91d3eaa 1041 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
Kojto 93:e188a91d3eaa 1042
Kojto 93:e188a91d3eaa 1043 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
Kojto 93:e188a91d3eaa 1044 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 93:e188a91d3eaa 1045 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 93:e188a91d3eaa 1046 * HAL_RCC_ClockConfig() API)
Kojto 93:e188a91d3eaa 1047 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 93:e188a91d3eaa 1048 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 93:e188a91d3eaa 1049 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 93:e188a91d3eaa 1050 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 93:e188a91d3eaa 1051 * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
Kojto 93:e188a91d3eaa 1052 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 93:e188a91d3eaa 1053 * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
Kojto 93:e188a91d3eaa 1054 * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
Kojto 93:e188a91d3eaa 1055 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 93:e188a91d3eaa 1056 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 93:e188a91d3eaa 1057 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 93:e188a91d3eaa 1058 * on the I2S clock frequency.
Kojto 93:e188a91d3eaa 1059 */
Kojto 93:e188a91d3eaa 1060 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
Kojto 93:e188a91d3eaa 1061
Kojto 93:e188a91d3eaa 1062 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto 93:e188a91d3eaa 1063 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
Kojto 93:e188a91d3eaa 1064 * @note This function must be called before enabling the PLLI2S.
Kojto 93:e188a91d3eaa 1065 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
Kojto 93:e188a91d3eaa 1066 * This parameter must be a number between 1 and 32.
Kojto 93:e188a91d3eaa 1067 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto 93:e188a91d3eaa 1068 */
Kojto 93:e188a91d3eaa 1069 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto 93:e188a91d3eaa 1070
Kojto 93:e188a91d3eaa 1071 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto 93:e188a91d3eaa 1072 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
Kojto 93:e188a91d3eaa 1073 * @note This function must be called before enabling the PLLSAI.
Kojto 93:e188a91d3eaa 1074 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto 93:e188a91d3eaa 1075 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto 93:e188a91d3eaa 1076 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto 93:e188a91d3eaa 1077 */
Kojto 93:e188a91d3eaa 1078 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto 93:e188a91d3eaa 1079
Kojto 93:e188a91d3eaa 1080 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto 93:e188a91d3eaa 1081 *
Kojto 93:e188a91d3eaa 1082 * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
Kojto 93:e188a91d3eaa 1083 * @note This function must be called before enabling the PLLSAI.
Kojto 93:e188a91d3eaa 1084 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto 93:e188a91d3eaa 1085 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
Kojto 93:e188a91d3eaa 1086 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto 93:e188a91d3eaa 1087 */
Kojto 93:e188a91d3eaa 1088 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
Kojto 93:e188a91d3eaa 1089
Kojto 93:e188a91d3eaa 1090 /** @brief Macro to configure SAI1BlockA clock source selection.
Kojto 93:e188a91d3eaa 1091 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
Kojto 93:e188a91d3eaa 1092 * @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto 93:e188a91d3eaa 1093 * the SAI clock.
Kojto 93:e188a91d3eaa 1094 * @param __SOURCE__: specifies the SAI Block A clock source.
Kojto 93:e188a91d3eaa 1095 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1096 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 93:e188a91d3eaa 1097 * as SAI1 Block A clock.
Kojto 93:e188a91d3eaa 1098 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 93:e188a91d3eaa 1099 * as SAI1 Block A clock.
Kojto 93:e188a91d3eaa 1100 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto 93:e188a91d3eaa 1101 * used as SAI1 Block A clock.
Kojto 93:e188a91d3eaa 1102 */
Kojto 93:e188a91d3eaa 1103 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
Kojto 93:e188a91d3eaa 1104
Kojto 93:e188a91d3eaa 1105 /** @brief Macro to configure SAI1BlockB clock source selection.
Kojto 93:e188a91d3eaa 1106 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
Kojto 93:e188a91d3eaa 1107 * @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto 93:e188a91d3eaa 1108 * the SAI clock.
Kojto 93:e188a91d3eaa 1109 * @param __SOURCE__: specifies the SAI Block B clock source.
Kojto 93:e188a91d3eaa 1110 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1111 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 93:e188a91d3eaa 1112 * as SAI1 Block B clock.
Kojto 93:e188a91d3eaa 1113 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 93:e188a91d3eaa 1114 * as SAI1 Block B clock.
Kojto 93:e188a91d3eaa 1115 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto 93:e188a91d3eaa 1116 * used as SAI1 Block B clock.
Kojto 93:e188a91d3eaa 1117 */
Kojto 93:e188a91d3eaa 1118 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
Kojto 93:e188a91d3eaa 1119
Kojto 93:e188a91d3eaa 1120 /** @brief Enable PLLSAI_RDY interrupt.
Kojto 93:e188a91d3eaa 1121 */
Kojto 93:e188a91d3eaa 1122 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
Kojto 93:e188a91d3eaa 1123
Kojto 93:e188a91d3eaa 1124 /** @brief Disable PLLSAI_RDY interrupt.
Kojto 93:e188a91d3eaa 1125 */
Kojto 93:e188a91d3eaa 1126 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
Kojto 93:e188a91d3eaa 1127
Kojto 93:e188a91d3eaa 1128 /** @brief Clear the PLLSAI RDY interrupt pending bits.
Kojto 93:e188a91d3eaa 1129 */
Kojto 93:e188a91d3eaa 1130 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
Kojto 93:e188a91d3eaa 1131
Kojto 93:e188a91d3eaa 1132 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
Kojto 93:e188a91d3eaa 1133 * @retval The new state (TRUE or FALSE).
Kojto 93:e188a91d3eaa 1134 */
Kojto 93:e188a91d3eaa 1135 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
Kojto 93:e188a91d3eaa 1136
Kojto 93:e188a91d3eaa 1137 /** @brief Check PLLSAI RDY flag is set or not.
Kojto 93:e188a91d3eaa 1138 * @retval The new state (TRUE or FALSE).
Kojto 93:e188a91d3eaa 1139 */
Kojto 93:e188a91d3eaa 1140 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
Kojto 93:e188a91d3eaa 1141
Kojto 93:e188a91d3eaa 1142 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 93:e188a91d3eaa 1143
Kojto 93:e188a91d3eaa 1144 /* Exported functions --------------------------------------------------------*/
Kojto 93:e188a91d3eaa 1145 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 93:e188a91d3eaa 1146 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 93:e188a91d3eaa 1147
Kojto 93:e188a91d3eaa 1148 #if defined(STM32F411xE)
Kojto 93:e188a91d3eaa 1149 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
Kojto 93:e188a91d3eaa 1150 #endif /* STM32F411xE */
Kojto 93:e188a91d3eaa 1151 /**
Kojto 93:e188a91d3eaa 1152 * @}
Kojto 93:e188a91d3eaa 1153 */
Kojto 93:e188a91d3eaa 1154
Kojto 93:e188a91d3eaa 1155 /**
Kojto 93:e188a91d3eaa 1156 * @}
Kojto 93:e188a91d3eaa 1157 */
Kojto 93:e188a91d3eaa 1158
Kojto 93:e188a91d3eaa 1159 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 1160 }
Kojto 93:e188a91d3eaa 1161 #endif
Kojto 93:e188a91d3eaa 1162
Kojto 93:e188a91d3eaa 1163 #endif /* __STM32F4xx_HAL_RCC_EX_H */
Kojto 93:e188a91d3eaa 1164
Kojto 93:e188a91d3eaa 1165 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/