Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

Fork of mbed by mbed official

TARGET_EFM32ZG_STK3200/efm32zg_prs.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
98:8ab26030e058 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 98:8ab26030e058 1 /**************************************************************************//**
Kojto 98:8ab26030e058 2 * @file efm32zg_prs.h
Kojto 98:8ab26030e058 3 * @brief EFM32ZG_PRS register and bit field definitions
Kojto 98:8ab26030e058 4 * @version 3.20.6
Kojto 98:8ab26030e058 5 ******************************************************************************
Kojto 98:8ab26030e058 6 * @section License
Kojto 98:8ab26030e058 7 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
Kojto 98:8ab26030e058 8 ******************************************************************************
Kojto 98:8ab26030e058 9 *
Kojto 98:8ab26030e058 10 * Permission is granted to anyone to use this software for any purpose,
Kojto 98:8ab26030e058 11 * including commercial applications, and to alter it and redistribute it
Kojto 98:8ab26030e058 12 * freely, subject to the following restrictions:
Kojto 98:8ab26030e058 13 *
Kojto 98:8ab26030e058 14 * 1. The origin of this software must not be misrepresented; you must not
Kojto 98:8ab26030e058 15 * claim that you wrote the original software.@n
Kojto 98:8ab26030e058 16 * 2. Altered source versions must be plainly marked as such, and must not be
Kojto 98:8ab26030e058 17 * misrepresented as being the original software.@n
Kojto 98:8ab26030e058 18 * 3. This notice may not be removed or altered from any source distribution.
Kojto 98:8ab26030e058 19 *
Kojto 98:8ab26030e058 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
Kojto 98:8ab26030e058 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
Kojto 98:8ab26030e058 22 * providing the Software "AS IS", with no express or implied warranties of any
Kojto 98:8ab26030e058 23 * kind, including, but not limited to, any implied warranties of
Kojto 98:8ab26030e058 24 * merchantability or fitness for any particular purpose or warranties against
Kojto 98:8ab26030e058 25 * infringement of any proprietary rights of a third party.
Kojto 98:8ab26030e058 26 *
Kojto 98:8ab26030e058 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
Kojto 98:8ab26030e058 28 * incidental, or special damages, or any other relief, or for any claim by
Kojto 98:8ab26030e058 29 * any third party, arising from your use of this Software.
Kojto 98:8ab26030e058 30 *
Kojto 98:8ab26030e058 31 *****************************************************************************/
Kojto 98:8ab26030e058 32 /**************************************************************************//**
Kojto 98:8ab26030e058 33 * @defgroup EFM32ZG_PRS
Kojto 98:8ab26030e058 34 * @{
Kojto 98:8ab26030e058 35 * @brief EFM32ZG_PRS Register Declaration
Kojto 98:8ab26030e058 36 *****************************************************************************/
Kojto 98:8ab26030e058 37 typedef struct
Kojto 98:8ab26030e058 38 {
Kojto 98:8ab26030e058 39 __IO uint32_t SWPULSE; /**< Software Pulse Register */
Kojto 98:8ab26030e058 40 __IO uint32_t SWLEVEL; /**< Software Level Register */
Kojto 98:8ab26030e058 41 __IO uint32_t ROUTE; /**< I/O Routing Register */
Kojto 98:8ab26030e058 42
Kojto 98:8ab26030e058 43 uint32_t RESERVED0[1]; /**< Reserved registers */
Kojto 98:8ab26030e058 44
Kojto 98:8ab26030e058 45 PRS_CH_TypeDef CH[4]; /**< Channel registers */
Kojto 98:8ab26030e058 46 } PRS_TypeDef; /** @} */
Kojto 98:8ab26030e058 47
Kojto 98:8ab26030e058 48 /**************************************************************************//**
Kojto 98:8ab26030e058 49 * @defgroup EFM32ZG_PRS_BitFields
Kojto 98:8ab26030e058 50 * @{
Kojto 98:8ab26030e058 51 *****************************************************************************/
Kojto 98:8ab26030e058 52
Kojto 98:8ab26030e058 53 /* Bit fields for PRS SWPULSE */
Kojto 98:8ab26030e058 54 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
Kojto 98:8ab26030e058 55 #define _PRS_SWPULSE_MASK 0x0000000FUL /**< Mask for PRS_SWPULSE */
Kojto 98:8ab26030e058 56 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
Kojto 98:8ab26030e058 57 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
Kojto 98:8ab26030e058 58 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
Kojto 98:8ab26030e058 59 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
Kojto 98:8ab26030e058 60 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
Kojto 98:8ab26030e058 61 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
Kojto 98:8ab26030e058 62 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
Kojto 98:8ab26030e058 63 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
Kojto 98:8ab26030e058 64 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
Kojto 98:8ab26030e058 65 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
Kojto 98:8ab26030e058 66 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
Kojto 98:8ab26030e058 67 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
Kojto 98:8ab26030e058 68 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
Kojto 98:8ab26030e058 69 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
Kojto 98:8ab26030e058 70 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
Kojto 98:8ab26030e058 71 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
Kojto 98:8ab26030e058 72 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
Kojto 98:8ab26030e058 73 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
Kojto 98:8ab26030e058 74 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
Kojto 98:8ab26030e058 75 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
Kojto 98:8ab26030e058 76
Kojto 98:8ab26030e058 77 /* Bit fields for PRS SWLEVEL */
Kojto 98:8ab26030e058 78 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
Kojto 98:8ab26030e058 79 #define _PRS_SWLEVEL_MASK 0x0000000FUL /**< Mask for PRS_SWLEVEL */
Kojto 98:8ab26030e058 80 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
Kojto 98:8ab26030e058 81 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
Kojto 98:8ab26030e058 82 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
Kojto 98:8ab26030e058 83 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
Kojto 98:8ab26030e058 84 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
Kojto 98:8ab26030e058 85 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
Kojto 98:8ab26030e058 86 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
Kojto 98:8ab26030e058 87 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
Kojto 98:8ab26030e058 88 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
Kojto 98:8ab26030e058 89 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
Kojto 98:8ab26030e058 90 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
Kojto 98:8ab26030e058 91 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
Kojto 98:8ab26030e058 92 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
Kojto 98:8ab26030e058 93 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
Kojto 98:8ab26030e058 94 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
Kojto 98:8ab26030e058 95 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
Kojto 98:8ab26030e058 96 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
Kojto 98:8ab26030e058 97 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
Kojto 98:8ab26030e058 98 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
Kojto 98:8ab26030e058 99 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
Kojto 98:8ab26030e058 100
Kojto 98:8ab26030e058 101 /* Bit fields for PRS ROUTE */
Kojto 98:8ab26030e058 102 #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */
Kojto 98:8ab26030e058 103 #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */
Kojto 98:8ab26030e058 104 #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
Kojto 98:8ab26030e058 105 #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
Kojto 98:8ab26030e058 106 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
Kojto 98:8ab26030e058 107 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 108 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 109 #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
Kojto 98:8ab26030e058 110 #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
Kojto 98:8ab26030e058 111 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
Kojto 98:8ab26030e058 112 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 113 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 114 #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
Kojto 98:8ab26030e058 115 #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
Kojto 98:8ab26030e058 116 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
Kojto 98:8ab26030e058 117 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 118 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 119 #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
Kojto 98:8ab26030e058 120 #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
Kojto 98:8ab26030e058 121 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
Kojto 98:8ab26030e058 122 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 123 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 124 #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */
Kojto 98:8ab26030e058 125 #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */
Kojto 98:8ab26030e058 126 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */
Kojto 98:8ab26030e058 127 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 128 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */
Kojto 98:8ab26030e058 129 #define _PRS_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTE */
Kojto 98:8ab26030e058 130 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */
Kojto 98:8ab26030e058 131 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */
Kojto 98:8ab26030e058 132 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */
Kojto 98:8ab26030e058 133 #define PRS_ROUTE_LOCATION_LOC2 (_PRS_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTE */
Kojto 98:8ab26030e058 134
Kojto 98:8ab26030e058 135 /* Bit fields for PRS CH_CTRL */
Kojto 98:8ab26030e058 136 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
Kojto 98:8ab26030e058 137 #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */
Kojto 98:8ab26030e058 138 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
Kojto 98:8ab26030e058 139 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
Kojto 98:8ab26030e058 140 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */
Kojto 98:8ab26030e058 141 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
Kojto 98:8ab26030e058 142 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
Kojto 98:8ab26030e058 143 #define _PRS_CH_CTRL_SIGSEL_USART1IRTX 0x00000000UL /**< Mode USART1IRTX for PRS_CH_CTRL */
Kojto 98:8ab26030e058 144 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 145 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 146 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 147 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 148 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 149 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */
Kojto 98:8ab26030e058 150 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
Kojto 98:8ab26030e058 151 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
Kojto 98:8ab26030e058 152 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 153 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 154 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 155 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 156 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 157 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
Kojto 98:8ab26030e058 158 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 159 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 160 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 161 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 162 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 163 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 164 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 165 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 166 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 167 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 168 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 169 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 170 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 171 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 172 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 173 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 174 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 175 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 176 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 177 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
Kojto 98:8ab26030e058 178 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
Kojto 98:8ab26030e058 179 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
Kojto 98:8ab26030e058 180 #define PRS_CH_CTRL_SIGSEL_USART1IRTX (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0) /**< Shifted mode USART1IRTX for PRS_CH_CTRL */
Kojto 98:8ab26030e058 181 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 182 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 183 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 184 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 185 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 186 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */
Kojto 98:8ab26030e058 187 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
Kojto 98:8ab26030e058 188 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
Kojto 98:8ab26030e058 189 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 190 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 191 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 192 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 193 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 194 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
Kojto 98:8ab26030e058 195 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 196 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 197 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 198 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 199 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 200 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 201 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 202 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 203 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 204 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 205 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 206 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 207 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 208 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 209 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 210 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 211 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 212 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 213 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 214 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */
Kojto 98:8ab26030e058 215 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */
Kojto 98:8ab26030e058 216 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
Kojto 98:8ab26030e058 217 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */
Kojto 98:8ab26030e058 218 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 219 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 220 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 221 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 222 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 223 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */
Kojto 98:8ab26030e058 224 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
Kojto 98:8ab26030e058 225 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
Kojto 98:8ab26030e058 226 #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 227 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */
Kojto 98:8ab26030e058 228 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */
Kojto 98:8ab26030e058 229 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 230 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 231 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 232 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 233 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 234 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */
Kojto 98:8ab26030e058 235 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */
Kojto 98:8ab26030e058 236 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */
Kojto 98:8ab26030e058 237 #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16) /**< Shifted mode PCNT0 for PRS_CH_CTRL */
Kojto 98:8ab26030e058 238 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */
Kojto 98:8ab26030e058 239 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */
Kojto 98:8ab26030e058 240 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
Kojto 98:8ab26030e058 241 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 242 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
Kojto 98:8ab26030e058 243 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
Kojto 98:8ab26030e058 244 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
Kojto 98:8ab26030e058 245 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
Kojto 98:8ab26030e058 246 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */
Kojto 98:8ab26030e058 247 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
Kojto 98:8ab26030e058 248 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
Kojto 98:8ab26030e058 249 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
Kojto 98:8ab26030e058 250 #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */
Kojto 98:8ab26030e058 251 #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */
Kojto 98:8ab26030e058 252 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */
Kojto 98:8ab26030e058 253 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
Kojto 98:8ab26030e058 254 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
Kojto 98:8ab26030e058 255
Kojto 98:8ab26030e058 256 /** @} End of group EFM32ZG_PRS */
Kojto 98:8ab26030e058 257
Kojto 98:8ab26030e058 258