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TARGET_LPC812/LPC8xx.h@65:5798e58a58b1, 2013-08-12 (annotated)

Committer:
bogdanm
Date:
Mon Aug 12 13:17:46 2013 +0300
Revision:
65:5798e58a58b1
Parent:
64:e3affc9e7238
Child:
66:9c8f0e3462fb
New target (LPC4088), new features (interrupt chaining), bug fixes (KL25Z I2C).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 65:5798e58a58b1 1 /****************************************************************************
bogdanm 65:5798e58a58b1 2 * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
bogdanm 65:5798e58a58b1 3 * Project: NXP LPC8xx software example
bogdanm 65:5798e58a58b1 4 *
bogdanm 65:5798e58a58b1 5 * Description:
bogdanm 65:5798e58a58b1 6 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
bogdanm 65:5798e58a58b1 7 * NXP LPC800 Device Series
bogdanm 65:5798e58a58b1 8 *
bogdanm 65:5798e58a58b1 9 ****************************************************************************
bogdanm 65:5798e58a58b1 10 * Software that is described herein is for illustrative purposes only
bogdanm 65:5798e58a58b1 11 * which provides customers with programming information regarding the
bogdanm 65:5798e58a58b1 12 * products. This software is supplied "AS IS" without any warranties.
bogdanm 65:5798e58a58b1 13 * NXP Semiconductors assumes no responsibility or liability for the
bogdanm 65:5798e58a58b1 14 * use of the software, conveys no license or title under any patent,
bogdanm 65:5798e58a58b1 15 * copyright, or mask work right to the product. NXP Semiconductors
bogdanm 65:5798e58a58b1 16 * reserves the right to make changes in the software without
bogdanm 65:5798e58a58b1 17 * notification. NXP Semiconductors also make no representation or
bogdanm 65:5798e58a58b1 18 * warranty that such application will be suitable for the specified
bogdanm 65:5798e58a58b1 19 * use without further testing or modification.
bogdanm 65:5798e58a58b1 20
bogdanm 65:5798e58a58b1 21 * Permission to use, copy, modify, and distribute this software and its
bogdanm 65:5798e58a58b1 22 * documentation is hereby granted, under NXP Semiconductors'
bogdanm 65:5798e58a58b1 23 * relevant copyright in the software, without fee, provided that it
bogdanm 65:5798e58a58b1 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 65:5798e58a58b1 25 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 65:5798e58a58b1 26 * this code.
bogdanm 65:5798e58a58b1 27 ****************************************************************************/
bogdanm 65:5798e58a58b1 28 #ifndef __LPC8xx_H__
bogdanm 65:5798e58a58b1 29 #define __LPC8xx_H__
bogdanm 65:5798e58a58b1 30
bogdanm 65:5798e58a58b1 31 #ifdef __cplusplus
bogdanm 65:5798e58a58b1 32 extern "C" {
bogdanm 65:5798e58a58b1 33 #endif
bogdanm 65:5798e58a58b1 34
bogdanm 65:5798e58a58b1 35 /** @addtogroup LPC8xx_Definitions LPC8xx Definitions
bogdanm 65:5798e58a58b1 36 This file defines all structures and symbols for LPC8xx:
bogdanm 65:5798e58a58b1 37 - Registers and bitfields
bogdanm 65:5798e58a58b1 38 - peripheral base address
bogdanm 65:5798e58a58b1 39 - PIO definitions
bogdanm 65:5798e58a58b1 40 @{
bogdanm 65:5798e58a58b1 41 */
bogdanm 65:5798e58a58b1 42
bogdanm 65:5798e58a58b1 43
bogdanm 65:5798e58a58b1 44 /******************************************************************************/
bogdanm 65:5798e58a58b1 45 /* Processor and Core Peripherals */
bogdanm 65:5798e58a58b1 46 /******************************************************************************/
bogdanm 65:5798e58a58b1 47 /** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
bogdanm 65:5798e58a58b1 48 Configuration of the Cortex-M0+ Processor and Core Peripherals
bogdanm 65:5798e58a58b1 49 @{
bogdanm 65:5798e58a58b1 50 */
bogdanm 65:5798e58a58b1 51
bogdanm 65:5798e58a58b1 52 /*
bogdanm 65:5798e58a58b1 53 * ==========================================================================
bogdanm 65:5798e58a58b1 54 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 65:5798e58a58b1 55 * ==========================================================================
bogdanm 65:5798e58a58b1 56 */
bogdanm 65:5798e58a58b1 57 typedef enum IRQn
bogdanm 65:5798e58a58b1 58 {
bogdanm 65:5798e58a58b1 59 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
bogdanm 65:5798e58a58b1 60 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
bogdanm 65:5798e58a58b1 61 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 65:5798e58a58b1 62 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
bogdanm 65:5798e58a58b1 63 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
bogdanm 65:5798e58a58b1 64 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
bogdanm 65:5798e58a58b1 65 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
bogdanm 65:5798e58a58b1 66
bogdanm 65:5798e58a58b1 67 /****** LPC8xx Specific Interrupt Numbers ********************************************************/
bogdanm 65:5798e58a58b1 68 SPI0_IRQn = 0, /*!< SPI0 */
bogdanm 65:5798e58a58b1 69 SPI1_IRQn = 1, /*!< SPI1 */
bogdanm 65:5798e58a58b1 70 Reserved0_IRQn = 2, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 71 UART0_IRQn = 3, /*!< USART0 */
bogdanm 65:5798e58a58b1 72 UART1_IRQn = 4, /*!< USART1 */
bogdanm 65:5798e58a58b1 73 UART2_IRQn = 5, /*!< USART2 */
bogdanm 65:5798e58a58b1 74 Reserved1_IRQn = 6, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 75 Reserved2_IRQn = 7, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 76 I2C_IRQn = 8, /*!< I2C */
bogdanm 65:5798e58a58b1 77 SCT_IRQn = 9, /*!< SCT */
bogdanm 65:5798e58a58b1 78 MRT_IRQn = 10, /*!< MRT */
bogdanm 65:5798e58a58b1 79 CMP_IRQn = 11, /*!< CMP */
bogdanm 65:5798e58a58b1 80 WDT_IRQn = 12, /*!< WDT */
bogdanm 65:5798e58a58b1 81 BOD_IRQn = 13, /*!< BOD */
bogdanm 65:5798e58a58b1 82 Reserved3_IRQn = 14, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 83 WKT_IRQn = 15, /*!< WKT Interrupt */
bogdanm 65:5798e58a58b1 84 Reserved4_IRQn = 16, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 85 Reserved5_IRQn = 17, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 86 Reserved6_IRQn = 18, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 87 Reserved7_IRQn = 19, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 88 Reserved8_IRQn = 20, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 89 Reserved9_IRQn = 21, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 90 Reserved10_IRQn = 22, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 91 Reserved11_IRQn = 23, /*!< Reserved Interrupt */
bogdanm 65:5798e58a58b1 92 PININT0_IRQn = 24, /*!< External Interrupt 0 */
bogdanm 65:5798e58a58b1 93 PININT1_IRQn = 25, /*!< External Interrupt 1 */
bogdanm 65:5798e58a58b1 94 PININT2_IRQn = 26, /*!< External Interrupt 2 */
bogdanm 65:5798e58a58b1 95 PININT3_IRQn = 27, /*!< External Interrupt 3 */
bogdanm 65:5798e58a58b1 96 PININT4_IRQn = 28, /*!< External Interrupt 4 */
bogdanm 65:5798e58a58b1 97 PININT5_IRQn = 29, /*!< External Interrupt 5 */
bogdanm 65:5798e58a58b1 98 PININT6_IRQn = 30, /*!< External Interrupt 6 */
bogdanm 65:5798e58a58b1 99 PININT7_IRQn = 31, /*!< External Interrupt 7 */
bogdanm 65:5798e58a58b1 100 } IRQn_Type;
bogdanm 65:5798e58a58b1 101
bogdanm 65:5798e58a58b1 102 /*
bogdanm 65:5798e58a58b1 103 * ==========================================================================
bogdanm 65:5798e58a58b1 104 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 65:5798e58a58b1 105 * ==========================================================================
bogdanm 65:5798e58a58b1 106 */
bogdanm 65:5798e58a58b1 107
bogdanm 65:5798e58a58b1 108 /* Configuration of the Cortex-M0+ Processor and Core Peripherals */
bogdanm 65:5798e58a58b1 109 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 65:5798e58a58b1 110 #define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
bogdanm 65:5798e58a58b1 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 65:5798e58a58b1 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 65:5798e58a58b1 113
bogdanm 65:5798e58a58b1 114 /*@}*/ /* end of group LPC8xx_CMSIS */
bogdanm 65:5798e58a58b1 115
bogdanm 65:5798e58a58b1 116
bogdanm 65:5798e58a58b1 117 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
bogdanm 65:5798e58a58b1 118 #include "system_LPC8xx.h" /* System Header */
bogdanm 65:5798e58a58b1 119
bogdanm 65:5798e58a58b1 120
bogdanm 65:5798e58a58b1 121 /******************************************************************************/
bogdanm 65:5798e58a58b1 122 /* Device Specific Peripheral Registers structures */
bogdanm 65:5798e58a58b1 123 /******************************************************************************/
bogdanm 65:5798e58a58b1 124
bogdanm 65:5798e58a58b1 125 #if defined ( __CC_ARM )
bogdanm 65:5798e58a58b1 126 #pragma anon_unions
bogdanm 65:5798e58a58b1 127 #endif
bogdanm 65:5798e58a58b1 128
bogdanm 65:5798e58a58b1 129 /*------------- System Control (SYSCON) --------------------------------------*/
bogdanm 65:5798e58a58b1 130 /** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
bogdanm 65:5798e58a58b1 131 @{
bogdanm 65:5798e58a58b1 132 */
bogdanm 65:5798e58a58b1 133 typedef struct
bogdanm 65:5798e58a58b1 134 {
bogdanm 65:5798e58a58b1 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
bogdanm 65:5798e58a58b1 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
bogdanm 65:5798e58a58b1 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
bogdanm 65:5798e58a58b1 138 __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
bogdanm 65:5798e58a58b1 139 uint32_t RESERVED0[4];
bogdanm 65:5798e58a58b1 140
bogdanm 65:5798e58a58b1 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
bogdanm 65:5798e58a58b1 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
bogdanm 65:5798e58a58b1 143 uint32_t RESERVED1[2];
bogdanm 65:5798e58a58b1 144 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
bogdanm 65:5798e58a58b1 145 uint32_t RESERVED2[3];
bogdanm 65:5798e58a58b1 146 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
bogdanm 65:5798e58a58b1 147 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
bogdanm 65:5798e58a58b1 148 uint32_t RESERVED3[10];
bogdanm 65:5798e58a58b1 149
bogdanm 65:5798e58a58b1 150 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
bogdanm 65:5798e58a58b1 151 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
bogdanm 65:5798e58a58b1 152 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
bogdanm 65:5798e58a58b1 153 uint32_t RESERVED4[1];
bogdanm 65:5798e58a58b1 154
bogdanm 65:5798e58a58b1 155 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
bogdanm 65:5798e58a58b1 156 uint32_t RESERVED5[4];
bogdanm 65:5798e58a58b1 157 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
bogdanm 65:5798e58a58b1 158 uint32_t RESERVED6[18];
bogdanm 65:5798e58a58b1 159
bogdanm 65:5798e58a58b1 160 __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
bogdanm 65:5798e58a58b1 161 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
bogdanm 65:5798e58a58b1 162 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
bogdanm 65:5798e58a58b1 163 uint32_t RESERVED7;
bogdanm 65:5798e58a58b1 164 __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
bogdanm 65:5798e58a58b1 165 __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
bogdanm 65:5798e58a58b1 166 uint32_t RESERVED8[1];
bogdanm 65:5798e58a58b1 167 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
bogdanm 65:5798e58a58b1 168 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
bogdanm 65:5798e58a58b1 169 uint32_t RESERVED9[12];
bogdanm 65:5798e58a58b1 170 __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
bogdanm 65:5798e58a58b1 171 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
bogdanm 65:5798e58a58b1 172 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
bogdanm 65:5798e58a58b1 173 uint32_t RESERVED10[6];
bogdanm 65:5798e58a58b1 174 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
bogdanm 65:5798e58a58b1 175 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
bogdanm 65:5798e58a58b1 176 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
bogdanm 65:5798e58a58b1 177 uint32_t RESERVED11[27];
bogdanm 65:5798e58a58b1 178 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
bogdanm 65:5798e58a58b1 179 uint32_t RESERVED12[3];
bogdanm 65:5798e58a58b1 180 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
bogdanm 65:5798e58a58b1 181 uint32_t RESERVED13[6];
bogdanm 65:5798e58a58b1 182 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
bogdanm 65:5798e58a58b1 183 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
bogdanm 65:5798e58a58b1 184 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
bogdanm 65:5798e58a58b1 185 uint32_t RESERVED14[110];
bogdanm 65:5798e58a58b1 186 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
bogdanm 65:5798e58a58b1 187 } LPC_SYSCON_TypeDef;
bogdanm 65:5798e58a58b1 188 /*@}*/ /* end of group LPC8xx_SYSCON */
bogdanm 65:5798e58a58b1 189
bogdanm 65:5798e58a58b1 190
bogdanm 65:5798e58a58b1 191 /**
bogdanm 65:5798e58a58b1 192 * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
bogdanm 65:5798e58a58b1 193 */
bogdanm 65:5798e58a58b1 194
bogdanm 65:5798e58a58b1 195 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
bogdanm 65:5798e58a58b1 196 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
bogdanm 65:5798e58a58b1 197 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
bogdanm 65:5798e58a58b1 198 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
bogdanm 65:5798e58a58b1 199 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
bogdanm 65:5798e58a58b1 200 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
bogdanm 65:5798e58a58b1 201 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
bogdanm 65:5798e58a58b1 202 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
bogdanm 65:5798e58a58b1 203 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
bogdanm 65:5798e58a58b1 204 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
bogdanm 65:5798e58a58b1 205 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
bogdanm 65:5798e58a58b1 206 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
bogdanm 65:5798e58a58b1 207 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
bogdanm 65:5798e58a58b1 208 __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
bogdanm 65:5798e58a58b1 209 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
bogdanm 65:5798e58a58b1 210 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
bogdanm 65:5798e58a58b1 211 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
bogdanm 65:5798e58a58b1 212 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
bogdanm 65:5798e58a58b1 213 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
bogdanm 65:5798e58a58b1 214 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
bogdanm 65:5798e58a58b1 215 } LPC_IOCON_TypeDef;
bogdanm 65:5798e58a58b1 216 /*@}*/ /* end of group LPC8xx_IOCON */
bogdanm 65:5798e58a58b1 217
bogdanm 65:5798e58a58b1 218 /**
bogdanm 65:5798e58a58b1 219 * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
bogdanm 65:5798e58a58b1 220 */
bogdanm 65:5798e58a58b1 221 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
bogdanm 65:5798e58a58b1 222 __I uint32_t RESERVED0[4];
bogdanm 65:5798e58a58b1 223 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
bogdanm 65:5798e58a58b1 224 __I uint32_t RESERVED1[3];
bogdanm 65:5798e58a58b1 225 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
bogdanm 65:5798e58a58b1 226 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
bogdanm 65:5798e58a58b1 227 __I uint32_t RESERVED2;
bogdanm 65:5798e58a58b1 228 __I uint32_t FMSW0;
bogdanm 65:5798e58a58b1 229 } LPC_FLASHCTRL_TypeDef;
bogdanm 65:5798e58a58b1 230 /*@}*/ /* end of group LPC8xx_FLASHCTRL */
bogdanm 65:5798e58a58b1 231
bogdanm 65:5798e58a58b1 232
bogdanm 65:5798e58a58b1 233 /*------------- Power Management Unit (PMU) --------------------------*/
bogdanm 65:5798e58a58b1 234 /** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
bogdanm 65:5798e58a58b1 235 @{
bogdanm 65:5798e58a58b1 236 */
bogdanm 65:5798e58a58b1 237 typedef struct
bogdanm 65:5798e58a58b1 238 {
bogdanm 65:5798e58a58b1 239 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
bogdanm 65:5798e58a58b1 240 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
bogdanm 65:5798e58a58b1 241 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
bogdanm 65:5798e58a58b1 242 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
bogdanm 65:5798e58a58b1 243 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
bogdanm 65:5798e58a58b1 244 __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
bogdanm 65:5798e58a58b1 245 } LPC_PMU_TypeDef;
bogdanm 65:5798e58a58b1 246 /*@}*/ /* end of group LPC8xx_PMU */
bogdanm 65:5798e58a58b1 247
bogdanm 65:5798e58a58b1 248
bogdanm 65:5798e58a58b1 249 /*------------- Switch Matrix Port --------------------------*/
bogdanm 65:5798e58a58b1 250 /** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
bogdanm 65:5798e58a58b1 251 @{
bogdanm 65:5798e58a58b1 252 */
bogdanm 65:5798e58a58b1 253 typedef struct
bogdanm 65:5798e58a58b1 254 {
bogdanm 65:5798e58a58b1 255 union {
bogdanm 65:5798e58a58b1 256 __IO uint32_t PINASSIGN[9];
bogdanm 65:5798e58a58b1 257 struct {
bogdanm 65:5798e58a58b1 258 __IO uint32_t PINASSIGN0;
bogdanm 65:5798e58a58b1 259 __IO uint32_t PINASSIGN1;
bogdanm 65:5798e58a58b1 260 __IO uint32_t PINASSIGN2;
bogdanm 65:5798e58a58b1 261 __IO uint32_t PINASSIGN3;
bogdanm 65:5798e58a58b1 262 __IO uint32_t PINASSIGN4;
bogdanm 65:5798e58a58b1 263 __IO uint32_t PINASSIGN5;
bogdanm 65:5798e58a58b1 264 __IO uint32_t PINASSIGN6;
bogdanm 65:5798e58a58b1 265 __IO uint32_t PINASSIGN7;
bogdanm 65:5798e58a58b1 266 __IO uint32_t PINASSIGN8;
bogdanm 65:5798e58a58b1 267 };
bogdanm 65:5798e58a58b1 268 };
bogdanm 65:5798e58a58b1 269 __I uint32_t RESERVED0[103];
bogdanm 65:5798e58a58b1 270 __IO uint32_t PINENABLE0;
bogdanm 65:5798e58a58b1 271 } LPC_SWM_TypeDef;
bogdanm 65:5798e58a58b1 272 /*@}*/ /* end of group LPC8xx_SWM */
bogdanm 65:5798e58a58b1 273
bogdanm 65:5798e58a58b1 274
bogdanm 65:5798e58a58b1 275 // ------------------------------------------------------------------------------------------------
bogdanm 65:5798e58a58b1 276 // ----- GPIO_PORT -----
bogdanm 65:5798e58a58b1 277 // ------------------------------------------------------------------------------------------------
bogdanm 65:5798e58a58b1 278
bogdanm 65:5798e58a58b1 279 /**
bogdanm 65:5798e58a58b1 280 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
bogdanm 65:5798e58a58b1 281 */
bogdanm 65:5798e58a58b1 282
bogdanm 65:5798e58a58b1 283 typedef struct {
bogdanm 65:5798e58a58b1 284 __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
bogdanm 65:5798e58a58b1 285 __I uint16_t RESERVED0[2039];
bogdanm 65:5798e58a58b1 286 __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
bogdanm 65:5798e58a58b1 287 uint32_t RESERVED1[1006];
bogdanm 65:5798e58a58b1 288 __IO uint32_t DIR0; /* 0x2000 */
bogdanm 65:5798e58a58b1 289 uint32_t RESERVED2[31];
bogdanm 65:5798e58a58b1 290 __IO uint32_t MASK0; /* 0x2080 */
bogdanm 65:5798e58a58b1 291 uint32_t RESERVED3[31];
bogdanm 65:5798e58a58b1 292 __IO uint32_t PIN0; /* 0x2100 */
bogdanm 65:5798e58a58b1 293 uint32_t RESERVED4[31];
bogdanm 65:5798e58a58b1 294 __IO uint32_t MPIN0; /* 0x2180 */
bogdanm 65:5798e58a58b1 295 uint32_t RESERVED5[31];
bogdanm 65:5798e58a58b1 296 __IO uint32_t SET0; /* 0x2200 */
bogdanm 65:5798e58a58b1 297 uint32_t RESERVED6[31];
bogdanm 65:5798e58a58b1 298 __O uint32_t CLR0; /* 0x2280 */
bogdanm 65:5798e58a58b1 299 uint32_t RESERVED7[31];
bogdanm 65:5798e58a58b1 300 __O uint32_t NOT0; /* 0x2300 */
bogdanm 65:5798e58a58b1 301
bogdanm 65:5798e58a58b1 302 } LPC_GPIO_PORT_TypeDef;
bogdanm 65:5798e58a58b1 303
bogdanm 65:5798e58a58b1 304
bogdanm 65:5798e58a58b1 305 // ------------------------------------------------------------------------------------------------
bogdanm 65:5798e58a58b1 306 // ----- PIN_INT -----
bogdanm 65:5798e58a58b1 307 // ------------------------------------------------------------------------------------------------
bogdanm 65:5798e58a58b1 308
bogdanm 65:5798e58a58b1 309 /**
bogdanm 65:5798e58a58b1 310 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
bogdanm 65:5798e58a58b1 311 */
bogdanm 65:5798e58a58b1 312
bogdanm 65:5798e58a58b1 313 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
bogdanm 65:5798e58a58b1 314 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
bogdanm 65:5798e58a58b1 315 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
bogdanm 65:5798e58a58b1 316 __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
bogdanm 65:5798e58a58b1 317 __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
bogdanm 65:5798e58a58b1 318 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 65:5798e58a58b1 319 __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 65:5798e58a58b1 320 __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
bogdanm 65:5798e58a58b1 321 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
bogdanm 65:5798e58a58b1 322 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
bogdanm 65:5798e58a58b1 323 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
bogdanm 65:5798e58a58b1 324 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
bogdanm 65:5798e58a58b1 325 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
bogdanm 65:5798e58a58b1 326 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
bogdanm 65:5798e58a58b1 327 } LPC_PIN_INT_TypeDef;
bogdanm 65:5798e58a58b1 328
bogdanm 65:5798e58a58b1 329
bogdanm 65:5798e58a58b1 330 /*------------- CRC Engine (CRC) -----------------------------------------*/
bogdanm 65:5798e58a58b1 331 /** @addtogroup LPC8xx_CRC
bogdanm 65:5798e58a58b1 332 @{
bogdanm 65:5798e58a58b1 333 */
bogdanm 65:5798e58a58b1 334 typedef struct
bogdanm 65:5798e58a58b1 335 {
bogdanm 65:5798e58a58b1 336 __IO uint32_t MODE;
bogdanm 65:5798e58a58b1 337 __IO uint32_t SEED;
bogdanm 65:5798e58a58b1 338 union {
bogdanm 65:5798e58a58b1 339 __I uint32_t SUM;
bogdanm 65:5798e58a58b1 340 __O uint32_t WR_DATA_DWORD;
bogdanm 65:5798e58a58b1 341 __O uint16_t WR_DATA_WORD;
bogdanm 65:5798e58a58b1 342 uint16_t RESERVED_WORD;
bogdanm 65:5798e58a58b1 343 __O uint8_t WR_DATA_BYTE;
bogdanm 65:5798e58a58b1 344 uint8_t RESERVED_BYTE[3];
bogdanm 65:5798e58a58b1 345 };
bogdanm 65:5798e58a58b1 346 } LPC_CRC_TypeDef;
bogdanm 65:5798e58a58b1 347 /*@}*/ /* end of group LPC8xx_CRC */
bogdanm 65:5798e58a58b1 348
bogdanm 65:5798e58a58b1 349 /*------------- Comparator (CMP) --------------------------------------------------*/
bogdanm 65:5798e58a58b1 350 /** @addtogroup LPC8xx_CMP LPC8xx Comparator
bogdanm 65:5798e58a58b1 351 @{
bogdanm 65:5798e58a58b1 352 */
bogdanm 65:5798e58a58b1 353 typedef struct { /*!< (@ 0x40024000) CMP Structure */
bogdanm 65:5798e58a58b1 354 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
bogdanm 65:5798e58a58b1 355 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
bogdanm 65:5798e58a58b1 356 } LPC_CMP_TypeDef;
bogdanm 65:5798e58a58b1 357 /*@}*/ /* end of group LPC8xx_CMP */
bogdanm 65:5798e58a58b1 358
bogdanm 65:5798e58a58b1 359
bogdanm 65:5798e58a58b1 360 /*------------- Wakeup Timer (WKT) --------------------------------------------------*/
bogdanm 65:5798e58a58b1 361 /** @addtogroup LPC8xx_WKT
bogdanm 65:5798e58a58b1 362 @{
bogdanm 65:5798e58a58b1 363 */
bogdanm 65:5798e58a58b1 364 typedef struct { /*!< (@ 0x40028000) WKT Structure */
bogdanm 65:5798e58a58b1 365 __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
bogdanm 65:5798e58a58b1 366 uint32_t Reserved[2];
bogdanm 65:5798e58a58b1 367 __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
bogdanm 65:5798e58a58b1 368 } LPC_WKT_TypeDef;
bogdanm 65:5798e58a58b1 369 /*@}*/ /* end of group LPC8xx_WKT */
bogdanm 65:5798e58a58b1 370
bogdanm 65:5798e58a58b1 371
bogdanm 65:5798e58a58b1 372 /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
bogdanm 65:5798e58a58b1 373 typedef struct {
bogdanm 65:5798e58a58b1 374 __IO uint32_t INTVAL;
bogdanm 65:5798e58a58b1 375 __IO uint32_t TIMER;
bogdanm 65:5798e58a58b1 376 __IO uint32_t CTRL;
bogdanm 65:5798e58a58b1 377 __IO uint32_t STAT;
bogdanm 65:5798e58a58b1 378 } MRT_Channel_cfg_Type;
bogdanm 65:5798e58a58b1 379
bogdanm 65:5798e58a58b1 380 typedef struct {
bogdanm 65:5798e58a58b1 381 MRT_Channel_cfg_Type Channel[4];
bogdanm 65:5798e58a58b1 382 uint32_t Reserved0[1];
bogdanm 65:5798e58a58b1 383 __IO uint32_t IDLE_CH;
bogdanm 65:5798e58a58b1 384 __IO uint32_t IRQ_FLAG;
bogdanm 65:5798e58a58b1 385 } LPC_MRT_TypeDef;
bogdanm 65:5798e58a58b1 386
bogdanm 65:5798e58a58b1 387
bogdanm 65:5798e58a58b1 388 /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
bogdanm 65:5798e58a58b1 389 /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
bogdanm 65:5798e58a58b1 390 @{
bogdanm 65:5798e58a58b1 391 */
bogdanm 65:5798e58a58b1 392 /**
bogdanm 65:5798e58a58b1 393 * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
bogdanm 65:5798e58a58b1 394 */
bogdanm 65:5798e58a58b1 395 typedef struct
bogdanm 65:5798e58a58b1 396 {
bogdanm 65:5798e58a58b1 397 __IO uint32_t CFG; /* 0x00 */
bogdanm 65:5798e58a58b1 398 __IO uint32_t CTRL;
bogdanm 65:5798e58a58b1 399 __IO uint32_t STAT;
bogdanm 65:5798e58a58b1 400 __IO uint32_t INTENSET;
bogdanm 65:5798e58a58b1 401 __O uint32_t INTENCLR; /* 0x10 */
bogdanm 65:5798e58a58b1 402 __I uint32_t RXDATA;
bogdanm 65:5798e58a58b1 403 __I uint32_t RXDATA_STAT;
bogdanm 65:5798e58a58b1 404 __IO uint32_t TXDATA;
bogdanm 65:5798e58a58b1 405 __IO uint32_t BRG; /* 0x20 */
bogdanm 65:5798e58a58b1 406 __IO uint32_t INTSTAT;
bogdanm 65:5798e58a58b1 407 } LPC_USART_TypeDef;
bogdanm 65:5798e58a58b1 408
bogdanm 65:5798e58a58b1 409 /*@}*/ /* end of group LPC8xx_USART */
bogdanm 65:5798e58a58b1 410
bogdanm 65:5798e58a58b1 411
bogdanm 65:5798e58a58b1 412 /*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
bogdanm 65:5798e58a58b1 413 /** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
bogdanm 65:5798e58a58b1 414 @{
bogdanm 65:5798e58a58b1 415 */
bogdanm 65:5798e58a58b1 416 typedef struct
bogdanm 65:5798e58a58b1 417 {
bogdanm 65:5798e58a58b1 418 __IO uint32_t CFG; /* 0x00 */
bogdanm 65:5798e58a58b1 419 __IO uint32_t DLY;
bogdanm 65:5798e58a58b1 420 __IO uint32_t STAT;
bogdanm 65:5798e58a58b1 421 __IO uint32_t INTENSET;
bogdanm 65:5798e58a58b1 422 __O uint32_t INTENCLR; /* 0x10 */
bogdanm 65:5798e58a58b1 423 __I uint32_t RXDAT;
bogdanm 65:5798e58a58b1 424 __IO uint32_t TXDATCTL;
bogdanm 65:5798e58a58b1 425 __IO uint32_t TXDAT;
bogdanm 65:5798e58a58b1 426 __IO uint32_t TXCTRL; /* 0x20 */
bogdanm 65:5798e58a58b1 427 __IO uint32_t DIV;
bogdanm 65:5798e58a58b1 428 __I uint32_t INTSTAT;
bogdanm 65:5798e58a58b1 429 } LPC_SPI_TypeDef;
bogdanm 65:5798e58a58b1 430 /*@}*/ /* end of group LPC8xx_SPI */
bogdanm 65:5798e58a58b1 431
bogdanm 65:5798e58a58b1 432
bogdanm 65:5798e58a58b1 433 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 65:5798e58a58b1 434 /** @addtogroup LPC8xx_I2C I2C-Bus Interface
bogdanm 65:5798e58a58b1 435 @{
bogdanm 65:5798e58a58b1 436 */
bogdanm 65:5798e58a58b1 437 typedef struct
bogdanm 65:5798e58a58b1 438 {
bogdanm 65:5798e58a58b1 439 __IO uint32_t CFG; /* 0x00 */
bogdanm 65:5798e58a58b1 440 __IO uint32_t STAT;
bogdanm 65:5798e58a58b1 441 __IO uint32_t INTENSET;
bogdanm 65:5798e58a58b1 442 __O uint32_t INTENCLR;
bogdanm 65:5798e58a58b1 443 __IO uint32_t TIMEOUT; /* 0x10 */
bogdanm 65:5798e58a58b1 444 __IO uint32_t DIV;
bogdanm 65:5798e58a58b1 445 __IO uint32_t INTSTAT;
bogdanm 65:5798e58a58b1 446 uint32_t Reserved0[1];
bogdanm 65:5798e58a58b1 447 __IO uint32_t MSTCTL; /* 0x20 */
bogdanm 65:5798e58a58b1 448 __IO uint32_t MSTTIME;
bogdanm 65:5798e58a58b1 449 __IO uint32_t MSTDAT;
bogdanm 65:5798e58a58b1 450 uint32_t Reserved1[5];
bogdanm 65:5798e58a58b1 451 __IO uint32_t SLVCTL; /* 0x40 */
bogdanm 65:5798e58a58b1 452 __IO uint32_t SLVDAT;
bogdanm 65:5798e58a58b1 453 __IO uint32_t SLVADR0;
bogdanm 65:5798e58a58b1 454 __IO uint32_t SLVADR1;
bogdanm 65:5798e58a58b1 455 __IO uint32_t SLVADR2; /* 0x50 */
bogdanm 65:5798e58a58b1 456 __IO uint32_t SLVADR3;
bogdanm 65:5798e58a58b1 457 __IO uint32_t SLVQUAL0;
bogdanm 65:5798e58a58b1 458 uint32_t Reserved2[9];
bogdanm 65:5798e58a58b1 459 __I uint32_t MONRXDAT; /* 0x80 */
bogdanm 65:5798e58a58b1 460 } LPC_I2C_TypeDef;
bogdanm 65:5798e58a58b1 461
bogdanm 65:5798e58a58b1 462 /*@}*/ /* end of group LPC8xx_I2C */
bogdanm 65:5798e58a58b1 463
bogdanm 65:5798e58a58b1 464 /**
bogdanm 65:5798e58a58b1 465 * @brief State Configurable Timer (SCT) (SCT)
bogdanm 65:5798e58a58b1 466 */
bogdanm 65:5798e58a58b1 467
bogdanm 65:5798e58a58b1 468 /**
bogdanm 65:5798e58a58b1 469 * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
bogdanm 65:5798e58a58b1 470 */
bogdanm 65:5798e58a58b1 471
bogdanm 65:5798e58a58b1 472 #define CONFIG_SCT_nEV (6) /* Number of events */
bogdanm 65:5798e58a58b1 473 #define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
bogdanm 65:5798e58a58b1 474 #define CONFIG_SCT_nOU (4) /* Number of outputs */
bogdanm 65:5798e58a58b1 475
bogdanm 65:5798e58a58b1 476 typedef struct
bogdanm 65:5798e58a58b1 477 {
bogdanm 65:5798e58a58b1 478 __IO uint32_t CONFIG; /* 0x000 Configuration Register */
bogdanm 65:5798e58a58b1 479 union {
bogdanm 65:5798e58a58b1 480 __IO uint32_t CTRL_U; /* 0x004 Control Register */
bogdanm 65:5798e58a58b1 481 struct {
bogdanm 65:5798e58a58b1 482 __IO uint16_t CTRL_L; /* 0x004 low control register */
bogdanm 65:5798e58a58b1 483 __IO uint16_t CTRL_H; /* 0x006 high control register */
bogdanm 65:5798e58a58b1 484 };
bogdanm 65:5798e58a58b1 485 };
bogdanm 65:5798e58a58b1 486 __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
bogdanm 65:5798e58a58b1 487 __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
bogdanm 65:5798e58a58b1 488 __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
bogdanm 65:5798e58a58b1 489 __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
bogdanm 65:5798e58a58b1 490 __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
bogdanm 65:5798e58a58b1 491 __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
bogdanm 65:5798e58a58b1 492 __IO uint16_t START_L; /* 0x014 start register for counter L */
bogdanm 65:5798e58a58b1 493 __IO uint16_t START_H; /* 0x016 start register for counter H */
bogdanm 65:5798e58a58b1 494 uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
bogdanm 65:5798e58a58b1 495 union {
bogdanm 65:5798e58a58b1 496 __IO uint32_t COUNT_U; /* 0x040 counter register */
bogdanm 65:5798e58a58b1 497 struct {
bogdanm 65:5798e58a58b1 498 __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
bogdanm 65:5798e58a58b1 499 __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
bogdanm 65:5798e58a58b1 500 };
bogdanm 65:5798e58a58b1 501 };
bogdanm 65:5798e58a58b1 502 __IO uint16_t STATE_L; /* 0x044 state register for counter L */
bogdanm 65:5798e58a58b1 503 __IO uint16_t STATE_H; /* 0x046 state register for counter H */
bogdanm 65:5798e58a58b1 504 __I uint32_t INPUT; /* 0x048 input register */
bogdanm 65:5798e58a58b1 505 __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
bogdanm 65:5798e58a58b1 506 __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
bogdanm 65:5798e58a58b1 507 __IO uint32_t OUTPUT; /* 0x050 output register */
bogdanm 65:5798e58a58b1 508 __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
bogdanm 65:5798e58a58b1 509 __IO uint32_t RES; /* 0x058 conflict resolution register */
bogdanm 65:5798e58a58b1 510 uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
bogdanm 65:5798e58a58b1 511 __IO uint32_t EVEN; /* 0x0F0 event enable register */
bogdanm 65:5798e58a58b1 512 __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
bogdanm 65:5798e58a58b1 513 __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
bogdanm 65:5798e58a58b1 514 __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
bogdanm 65:5798e58a58b1 515
bogdanm 65:5798e58a58b1 516 union {
bogdanm 65:5798e58a58b1 517 __IO union { /* 0x100-... Match / Capture value */
bogdanm 65:5798e58a58b1 518 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
bogdanm 65:5798e58a58b1 519 struct {
bogdanm 65:5798e58a58b1 520 uint16_t L; /* SCTMATCH[i].L Access to L value */
bogdanm 65:5798e58a58b1 521 uint16_t H; /* SCTMATCH[i].H Access to H value */
bogdanm 65:5798e58a58b1 522 };
bogdanm 65:5798e58a58b1 523 } MATCH[CONFIG_SCT_nRG];
bogdanm 65:5798e58a58b1 524 __I union {
bogdanm 65:5798e58a58b1 525 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
bogdanm 65:5798e58a58b1 526 struct {
bogdanm 65:5798e58a58b1 527 uint16_t L; /* SCTCAP[i].L Access to H value */
bogdanm 65:5798e58a58b1 528 uint16_t H; /* SCTCAP[i].H Access to H value */
bogdanm 65:5798e58a58b1 529 };
bogdanm 65:5798e58a58b1 530 } CAP[CONFIG_SCT_nRG];
bogdanm 65:5798e58a58b1 531 };
bogdanm 65:5798e58a58b1 532
bogdanm 65:5798e58a58b1 533
bogdanm 65:5798e58a58b1 534 uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
bogdanm 65:5798e58a58b1 535
bogdanm 65:5798e58a58b1 536 union {
bogdanm 65:5798e58a58b1 537 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
bogdanm 65:5798e58a58b1 538 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
bogdanm 65:5798e58a58b1 539 };
bogdanm 65:5798e58a58b1 540 uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
bogdanm 65:5798e58a58b1 541 union {
bogdanm 65:5798e58a58b1 542 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
bogdanm 65:5798e58a58b1 543 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
bogdanm 65:5798e58a58b1 544 };
bogdanm 65:5798e58a58b1 545
bogdanm 65:5798e58a58b1 546 uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
bogdanm 65:5798e58a58b1 547
bogdanm 65:5798e58a58b1 548
bogdanm 65:5798e58a58b1 549 union {
bogdanm 65:5798e58a58b1 550 __IO union { /* 0x200-... Match Reload / Capture Control value */
bogdanm 65:5798e58a58b1 551 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
bogdanm 65:5798e58a58b1 552 struct {
bogdanm 65:5798e58a58b1 553 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
bogdanm 65:5798e58a58b1 554 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
bogdanm 65:5798e58a58b1 555 };
bogdanm 65:5798e58a58b1 556 } MATCHREL[CONFIG_SCT_nRG];
bogdanm 65:5798e58a58b1 557 __IO union {
bogdanm 65:5798e58a58b1 558 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
bogdanm 65:5798e58a58b1 559 struct {
bogdanm 65:5798e58a58b1 560 uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
bogdanm 65:5798e58a58b1 561 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
bogdanm 65:5798e58a58b1 562 };
bogdanm 65:5798e58a58b1 563 } CAPCTRL[CONFIG_SCT_nRG];
bogdanm 65:5798e58a58b1 564 };
bogdanm 65:5798e58a58b1 565
bogdanm 65:5798e58a58b1 566 uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
bogdanm 65:5798e58a58b1 567
bogdanm 65:5798e58a58b1 568 union {
bogdanm 65:5798e58a58b1 569 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
bogdanm 65:5798e58a58b1 570 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
bogdanm 65:5798e58a58b1 571 };
bogdanm 65:5798e58a58b1 572 uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
bogdanm 65:5798e58a58b1 573 union {
bogdanm 65:5798e58a58b1 574 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
bogdanm 65:5798e58a58b1 575 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
bogdanm 65:5798e58a58b1 576 };
bogdanm 65:5798e58a58b1 577 uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
bogdanm 65:5798e58a58b1 578
bogdanm 65:5798e58a58b1 579 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
bogdanm 65:5798e58a58b1 580 uint32_t STATE; /* Event State Register */
bogdanm 65:5798e58a58b1 581 uint32_t CTRL; /* Event Control Register */
bogdanm 65:5798e58a58b1 582 } EVENT[CONFIG_SCT_nEV];
bogdanm 65:5798e58a58b1 583
bogdanm 65:5798e58a58b1 584 uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
bogdanm 65:5798e58a58b1 585
bogdanm 65:5798e58a58b1 586 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
bogdanm 65:5798e58a58b1 587 uint32_t SET; /* Output n Set Register */
bogdanm 65:5798e58a58b1 588 uint32_t CLR; /* Output n Clear Register */
bogdanm 65:5798e58a58b1 589 } OUT[CONFIG_SCT_nOU];
bogdanm 65:5798e58a58b1 590
bogdanm 65:5798e58a58b1 591 uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
bogdanm 65:5798e58a58b1 592
bogdanm 65:5798e58a58b1 593 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
bogdanm 65:5798e58a58b1 594
bogdanm 65:5798e58a58b1 595 } LPC_SCT_TypeDef;
bogdanm 65:5798e58a58b1 596 /*@}*/ /* end of group LPC8xx_SCT */
bogdanm 65:5798e58a58b1 597
bogdanm 65:5798e58a58b1 598
bogdanm 65:5798e58a58b1 599 /*------------- Watchdog Timer (WWDT) -----------------------------------------*/
bogdanm 65:5798e58a58b1 600 /** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
bogdanm 65:5798e58a58b1 601 @{
bogdanm 65:5798e58a58b1 602 */
bogdanm 65:5798e58a58b1 603 typedef struct
bogdanm 65:5798e58a58b1 604 {
bogdanm 65:5798e58a58b1 605 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
bogdanm 65:5798e58a58b1 606 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
bogdanm 65:5798e58a58b1 607 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
bogdanm 65:5798e58a58b1 608 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
bogdanm 65:5798e58a58b1 609 uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
bogdanm 65:5798e58a58b1 610 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
bogdanm 65:5798e58a58b1 611 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
bogdanm 65:5798e58a58b1 612 } LPC_WWDT_TypeDef;
bogdanm 65:5798e58a58b1 613 /*@}*/ /* end of group LPC8xx_WDT */
bogdanm 65:5798e58a58b1 614
bogdanm 65:5798e58a58b1 615
bogdanm 65:5798e58a58b1 616 #if defined ( __CC_ARM )
bogdanm 65:5798e58a58b1 617 #pragma no_anon_unions
bogdanm 65:5798e58a58b1 618 #endif
bogdanm 65:5798e58a58b1 619
bogdanm 65:5798e58a58b1 620 /******************************************************************************/
bogdanm 65:5798e58a58b1 621 /* Peripheral memory map */
bogdanm 65:5798e58a58b1 622 /******************************************************************************/
bogdanm 65:5798e58a58b1 623 /* Base addresses */
bogdanm 65:5798e58a58b1 624 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 65:5798e58a58b1 625 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 65:5798e58a58b1 626 #define LPC_ROM_BASE (0x1FFF0000UL)
bogdanm 65:5798e58a58b1 627 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 65:5798e58a58b1 628 #define LPC_AHB_BASE (0x50000000UL)
bogdanm 65:5798e58a58b1 629
bogdanm 65:5798e58a58b1 630 /* APB0 peripherals */
bogdanm 65:5798e58a58b1 631 #define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 65:5798e58a58b1 632 #define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 65:5798e58a58b1 633 #define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 65:5798e58a58b1 634 #define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 65:5798e58a58b1 635 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
bogdanm 65:5798e58a58b1 636 #define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
bogdanm 65:5798e58a58b1 637
bogdanm 65:5798e58a58b1 638 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 65:5798e58a58b1 639 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 65:5798e58a58b1 640 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 65:5798e58a58b1 641 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
bogdanm 65:5798e58a58b1 642 #define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
bogdanm 65:5798e58a58b1 643 #define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
bogdanm 65:5798e58a58b1 644 #define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
bogdanm 65:5798e58a58b1 645 #define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
bogdanm 65:5798e58a58b1 646 #define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
bogdanm 65:5798e58a58b1 647
bogdanm 65:5798e58a58b1 648 /* AHB peripherals */
bogdanm 65:5798e58a58b1 649 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 65:5798e58a58b1 650 #define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
bogdanm 65:5798e58a58b1 651
bogdanm 65:5798e58a58b1 652 #define LPC_GPIO_PORT_BASE (0xA0000000)
bogdanm 65:5798e58a58b1 653 #define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
bogdanm 65:5798e58a58b1 654
bogdanm 65:5798e58a58b1 655 /******************************************************************************/
bogdanm 65:5798e58a58b1 656 /* Peripheral declaration */
bogdanm 65:5798e58a58b1 657 /******************************************************************************/
bogdanm 65:5798e58a58b1 658 #define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
bogdanm 65:5798e58a58b1 659 #define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
bogdanm 65:5798e58a58b1 660
bogdanm 65:5798e58a58b1 661
bogdanm 65:5798e58a58b1 662 #define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
bogdanm 65:5798e58a58b1 663 #define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
bogdanm 65:5798e58a58b1 664 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
bogdanm 65:5798e58a58b1 665 #define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
bogdanm 65:5798e58a58b1 666
bogdanm 65:5798e58a58b1 667 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
bogdanm 65:5798e58a58b1 668 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
bogdanm 65:5798e58a58b1 669 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
bogdanm 65:5798e58a58b1 670 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
bogdanm 65:5798e58a58b1 671 #define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
bogdanm 65:5798e58a58b1 672 #define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
bogdanm 65:5798e58a58b1 673 #define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
bogdanm 65:5798e58a58b1 674 #define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
bogdanm 65:5798e58a58b1 675 #define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
bogdanm 65:5798e58a58b1 676
bogdanm 65:5798e58a58b1 677 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
bogdanm 65:5798e58a58b1 678 #define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
bogdanm 65:5798e58a58b1 679
bogdanm 65:5798e58a58b1 680 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
bogdanm 65:5798e58a58b1 681 #define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
bogdanm 65:5798e58a58b1 682
bogdanm 65:5798e58a58b1 683 #ifdef __cplusplus
bogdanm 65:5798e58a58b1 684 }
bogdanm 65:5798e58a58b1 685 #endif
bogdanm 65:5798e58a58b1 686
bogdanm 65:5798e58a58b1 687 #endif /* __LPC8xx_H__ */