The official mbed C/C SDK provides the software platform and libraries to build your applications.

Fork of mbed by mbed official

Committer:
bogdanm
Date:
Wed Jul 02 13:22:23 2014 +0100
Revision:
86:04dd9b1680ae
Child:
92:4fc01daae5a5
Release 86 of the mbed library

Main changes:


- bug fixes in various backends
- mbed "error" replaced by assert logic (mbed_assert)
- new ST Nucleo targets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal_hrtim.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V1.0.1
bogdanm 86:04dd9b1680ae 6 * @date 18-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of HRTIM HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F3xx_HAL_HRTIM_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F3xx_HAL_HRTIM_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 47
bogdanm 86:04dd9b1680ae 48 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 49 #include "stm32f3xx_hal_def.h"
bogdanm 86:04dd9b1680ae 50
bogdanm 86:04dd9b1680ae 51 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 52 * @{
bogdanm 86:04dd9b1680ae 53 */
bogdanm 86:04dd9b1680ae 54
bogdanm 86:04dd9b1680ae 55 /** @addtogroup HRTIM
bogdanm 86:04dd9b1680ae 56 * @{
bogdanm 86:04dd9b1680ae 57 */
bogdanm 86:04dd9b1680ae 58
bogdanm 86:04dd9b1680ae 59 /* Exported types ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 60 #define MAX_HRTIM_TIMER 6
bogdanm 86:04dd9b1680ae 61
bogdanm 86:04dd9b1680ae 62 /**
bogdanm 86:04dd9b1680ae 63 * @brief HRTIM Configuration Structure definition - Time base related parameters
bogdanm 86:04dd9b1680ae 64 */
bogdanm 86:04dd9b1680ae 65 typedef struct
bogdanm 86:04dd9b1680ae 66 {
bogdanm 86:04dd9b1680ae 67 uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance
bogdanm 86:04dd9b1680ae 68 This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
bogdanm 86:04dd9b1680ae 69 uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals
bogdanm 86:04dd9b1680ae 70 This parameter can be a combination of @ref HRTIM_Synchronization_Options */
bogdanm 86:04dd9b1680ae 71 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source
bogdanm 86:04dd9b1680ae 72 This parameter can be a value of @ref HRTIM_Synchronization_Input_Source */
bogdanm 86:04dd9b1680ae 73 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
bogdanm 86:04dd9b1680ae 74 This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
bogdanm 86:04dd9b1680ae 75 uint32_t SyncOutputPolarity; /*!< Specifies the conditionning of the event to be sent on the external synchronization outputs
bogdanm 86:04dd9b1680ae 76 This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
bogdanm 86:04dd9b1680ae 77 } HRTIM_InitTypeDef;
bogdanm 86:04dd9b1680ae 78
bogdanm 86:04dd9b1680ae 79 /**
bogdanm 86:04dd9b1680ae 80 * @brief HAL State structures definition
bogdanm 86:04dd9b1680ae 81 */
bogdanm 86:04dd9b1680ae 82 typedef enum
bogdanm 86:04dd9b1680ae 83 {
bogdanm 86:04dd9b1680ae 84 HAL_HRTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 86:04dd9b1680ae 85 HAL_HRTIM_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
bogdanm 86:04dd9b1680ae 86 HAL_HRTIM_STATE_TIMEOUT = 0x06, /*!< Timeout state */
bogdanm 86:04dd9b1680ae 87 HAL_HRTIM_STATE_ERROR = 0x07, /*!< Error state */
bogdanm 86:04dd9b1680ae 88 } HAL_HRTIM_StateTypeDef;
bogdanm 86:04dd9b1680ae 89
bogdanm 86:04dd9b1680ae 90 /**
bogdanm 86:04dd9b1680ae 91 * @brief HRTIM Timer Structure definition
bogdanm 86:04dd9b1680ae 92 */
bogdanm 86:04dd9b1680ae 93 typedef struct
bogdanm 86:04dd9b1680ae 94 {
bogdanm 86:04dd9b1680ae 95 uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1 */
bogdanm 86:04dd9b1680ae 96 uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2 */
bogdanm 86:04dd9b1680ae 97 uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer */
bogdanm 86:04dd9b1680ae 98 uint32_t DMARequests; /*!< DMA requests enabled for the timer */
bogdanm 86:04dd9b1680ae 99 uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer */
bogdanm 86:04dd9b1680ae 100 uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer */
bogdanm 86:04dd9b1680ae 101 uint32_t DMASize; /*!< Ssize of the DMA transfer */
bogdanm 86:04dd9b1680ae 102 } HRTIM_TimerParamTypeDef;
bogdanm 86:04dd9b1680ae 103
bogdanm 86:04dd9b1680ae 104 /**
bogdanm 86:04dd9b1680ae 105 * @brief HRTIM Handle Structure definition
bogdanm 86:04dd9b1680ae 106 */
bogdanm 86:04dd9b1680ae 107 typedef struct __HRTIM_HandleTypeDef
bogdanm 86:04dd9b1680ae 108 {
bogdanm 86:04dd9b1680ae 109 HRTIM_TypeDef * Instance; /*!< Register base address */
bogdanm 86:04dd9b1680ae 110
bogdanm 86:04dd9b1680ae 111 HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */
bogdanm 86:04dd9b1680ae 112
bogdanm 86:04dd9b1680ae 113 HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */
bogdanm 86:04dd9b1680ae 114
bogdanm 86:04dd9b1680ae 115 HAL_LockTypeDef Lock; /*!< Locking object */
bogdanm 86:04dd9b1680ae 116
bogdanm 86:04dd9b1680ae 117 __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */
bogdanm 86:04dd9b1680ae 118
bogdanm 86:04dd9b1680ae 119 DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */
bogdanm 86:04dd9b1680ae 120 DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */
bogdanm 86:04dd9b1680ae 121 DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */
bogdanm 86:04dd9b1680ae 122 DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */
bogdanm 86:04dd9b1680ae 123 DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */
bogdanm 86:04dd9b1680ae 124 DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */
bogdanm 86:04dd9b1680ae 125 } HRTIM_HandleTypeDef;
bogdanm 86:04dd9b1680ae 126
bogdanm 86:04dd9b1680ae 127 /**
bogdanm 86:04dd9b1680ae 128 * @brief Simple output compare mode configuration definition
bogdanm 86:04dd9b1680ae 129 */
bogdanm 86:04dd9b1680ae 130 typedef struct {
bogdanm 86:04dd9b1680ae 131 uint32_t Period; /*!< Specifies the timer period
bogdanm 86:04dd9b1680ae 132 The period value must be above 3 periods of the fHRTIM clock.
bogdanm 86:04dd9b1680ae 133 Maximum value is = 0xFFDF */
bogdanm 86:04dd9b1680ae 134 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
bogdanm 86:04dd9b1680ae 135 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 86:04dd9b1680ae 136 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
bogdanm 86:04dd9b1680ae 137 This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
bogdanm 86:04dd9b1680ae 138 uint32_t Mode; /*!< Specifies the counter operating mode
bogdanm 86:04dd9b1680ae 139 This parameter can be any value of @ref HRTIM_Mode */
bogdanm 86:04dd9b1680ae 140 } HRTIM_TimeBaseCfgTypeDef;
bogdanm 86:04dd9b1680ae 141
bogdanm 86:04dd9b1680ae 142 /**
bogdanm 86:04dd9b1680ae 143 * @brief Simple output compare mode configuration definition
bogdanm 86:04dd9b1680ae 144 */
bogdanm 86:04dd9b1680ae 145 typedef struct {
bogdanm 86:04dd9b1680ae 146 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
bogdanm 86:04dd9b1680ae 147 This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
bogdanm 86:04dd9b1680ae 148 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
bogdanm 86:04dd9b1680ae 149 The compare value must be above or equal to 3 periods of the fHRTIM clock */
bogdanm 86:04dd9b1680ae 150 uint32_t Polarity; /*!< Specifies the output polarity
bogdanm 86:04dd9b1680ae 151 This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm 86:04dd9b1680ae 152 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm 86:04dd9b1680ae 153 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
bogdanm 86:04dd9b1680ae 154 } HRTIM_SimpleOCChannelCfgTypeDef;
bogdanm 86:04dd9b1680ae 155
bogdanm 86:04dd9b1680ae 156 /**
bogdanm 86:04dd9b1680ae 157 * @brief Simple PWM output mode configuration definition
bogdanm 86:04dd9b1680ae 158 */
bogdanm 86:04dd9b1680ae 159 typedef struct {
bogdanm 86:04dd9b1680ae 160 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
bogdanm 86:04dd9b1680ae 161 The compare value must be above or equal to 3 periods of the fHRTIM clock */
bogdanm 86:04dd9b1680ae 162 uint32_t Polarity; /*!< Specifies the output polarity
bogdanm 86:04dd9b1680ae 163 This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm 86:04dd9b1680ae 164 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm 86:04dd9b1680ae 165 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
bogdanm 86:04dd9b1680ae 166 } HRTIM_SimplePWMChannelCfgTypeDef;
bogdanm 86:04dd9b1680ae 167
bogdanm 86:04dd9b1680ae 168 /**
bogdanm 86:04dd9b1680ae 169 * @brief Simple capture mode configuration definition
bogdanm 86:04dd9b1680ae 170 */
bogdanm 86:04dd9b1680ae 171 typedef struct {
bogdanm 86:04dd9b1680ae 172 uint32_t Event; /*!< Specifies the external event triggering the capture
bogdanm 86:04dd9b1680ae 173 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
bogdanm 86:04dd9b1680ae 174 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
bogdanm 86:04dd9b1680ae 175 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
bogdanm 86:04dd9b1680ae 176 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
bogdanm 86:04dd9b1680ae 177 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
bogdanm 86:04dd9b1680ae 178 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
bogdanm 86:04dd9b1680ae 179 This parameter can be a value of @ref HRTIM_External_Event_Filter */
bogdanm 86:04dd9b1680ae 180 } HRTIM_SimpleCaptureChannelCfgTypeDef;
bogdanm 86:04dd9b1680ae 181
bogdanm 86:04dd9b1680ae 182 /**
bogdanm 86:04dd9b1680ae 183 * @brief Simple One Pulse mode configuration definition
bogdanm 86:04dd9b1680ae 184 */
bogdanm 86:04dd9b1680ae 185 typedef struct {
bogdanm 86:04dd9b1680ae 186 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
bogdanm 86:04dd9b1680ae 187 The compare value must be above or equal to 3 periods of the fHRTIM clock */
bogdanm 86:04dd9b1680ae 188 uint32_t OutputPolarity; /*!< Specifies the output polarity
bogdanm 86:04dd9b1680ae 189 This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm 86:04dd9b1680ae 190 uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm 86:04dd9b1680ae 191 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
bogdanm 86:04dd9b1680ae 192 uint32_t Event; /*!< Specifies the external event triggering the pulse generation
bogdanm 86:04dd9b1680ae 193 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
bogdanm 86:04dd9b1680ae 194 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
bogdanm 86:04dd9b1680ae 195 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
bogdanm 86:04dd9b1680ae 196 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
bogdanm 86:04dd9b1680ae 197 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
bogdanm 86:04dd9b1680ae 198 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
bogdanm 86:04dd9b1680ae 199 This parameter can be a value of @ref HRTIM_External_Event_Filter */
bogdanm 86:04dd9b1680ae 200 } HRTIM_SimpleOnePulseChannelCfgTypeDef;
bogdanm 86:04dd9b1680ae 201
bogdanm 86:04dd9b1680ae 202 /**
bogdanm 86:04dd9b1680ae 203 * @brief Timer configuration definition
bogdanm 86:04dd9b1680ae 204 */
bogdanm 86:04dd9b1680ae 205 typedef struct {
bogdanm 86:04dd9b1680ae 206 uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 207 Specifies which interrupts requests must enabled for the timer
bogdanm 86:04dd9b1680ae 208 This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
bogdanm 86:04dd9b1680ae 209 or HRTIM_Timing_Unit_Interrupt_Enable */
bogdanm 86:04dd9b1680ae 210 uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 211 Specifies which DMA requests must be enabled for the timer
bogdanm 86:04dd9b1680ae 212 This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
bogdanm 86:04dd9b1680ae 213 or HRTIM_Timing_Unit_DMA_Request_Enable */
bogdanm 86:04dd9b1680ae 214 uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 215 Specifies the address of the source address of the DMA transfer */
bogdanm 86:04dd9b1680ae 216 uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 217 Specifies the address of the destination address of the DMA transfer */
bogdanm 86:04dd9b1680ae 218 uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 219 Specifies the size of the DMA transfer */
bogdanm 86:04dd9b1680ae 220 uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 221 Specifies whether or not hald mode is enabled
bogdanm 86:04dd9b1680ae 222 This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
bogdanm 86:04dd9b1680ae 223 uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 224 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
bogdanm 86:04dd9b1680ae 225 This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
bogdanm 86:04dd9b1680ae 226 uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 227 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
bogdanm 86:04dd9b1680ae 228 This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
bogdanm 86:04dd9b1680ae 229 uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 230 Indicates whether or not the a DAC synchronization event is generated
bogdanm 86:04dd9b1680ae 231 This parameter can be any value of @ref HRTIM_DAC_Synchronization */
bogdanm 86:04dd9b1680ae 232 uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 233 Specifies whether or not register preload is enabled
bogdanm 86:04dd9b1680ae 234 This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
bogdanm 86:04dd9b1680ae 235 uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 236 Specifies how the update occurs with respect to a burst DMA transaction or
bogdanm 86:04dd9b1680ae 237 update enable inputs (Slave timers only)
bogdanm 86:04dd9b1680ae 238 This parameter can be any value of @ref HRTIM_Update_Gating */
bogdanm 86:04dd9b1680ae 239 uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 240 Specifies how the timer behaves during a burst mode operation
bogdanm 86:04dd9b1680ae 241 This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
bogdanm 86:04dd9b1680ae 242 uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master
bogdanm 86:04dd9b1680ae 243 Specifies whether or not registers update is triggered by the repetition event
bogdanm 86:04dd9b1680ae 244 This parameter can be any valuen of @ref HRTIM_Timer_Repetition_Update */
bogdanm 86:04dd9b1680ae 245 uint32_t PushPull; /*!< Relevant for Timer A to Timer E
bogdanm 86:04dd9b1680ae 246 Specifies whether or not the push-pull mode is enabled
bogdanm 86:04dd9b1680ae 247 This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
bogdanm 86:04dd9b1680ae 248 uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E
bogdanm 86:04dd9b1680ae 249 Specifies which fault channels are enabled for the timer
bogdanm 86:04dd9b1680ae 250 This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
bogdanm 86:04dd9b1680ae 251 uint32_t FaultLock; /*!< Relevant for Timer A to Timer E
bogdanm 86:04dd9b1680ae 252 Specifies whether or not fault enabling status is write protected
bogdanm 86:04dd9b1680ae 253 This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
bogdanm 86:04dd9b1680ae 254 uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E
bogdanm 86:04dd9b1680ae 255 Specifies whether or not deadtime insertion is enabled for the timer
bogdanm 86:04dd9b1680ae 256 This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
bogdanm 86:04dd9b1680ae 257 uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E
bogdanm 86:04dd9b1680ae 258 Specifies the delayed protection mode
bogdanm 86:04dd9b1680ae 259 This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
bogdanm 86:04dd9b1680ae 260 uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E
bogdanm 86:04dd9b1680ae 261 Specifies source(s) triggering the timer registers update
bogdanm 86:04dd9b1680ae 262 This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
bogdanm 86:04dd9b1680ae 263 uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E
bogdanm 86:04dd9b1680ae 264 Specifies source(s) triggering the timer counter reset
bogdanm 86:04dd9b1680ae 265 This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
bogdanm 86:04dd9b1680ae 266 uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E
bogdanm 86:04dd9b1680ae 267 Specifies whether or not registers update is triggered when the timer counter is reset
bogdanm 86:04dd9b1680ae 268 This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
bogdanm 86:04dd9b1680ae 269 } HRTIM_TimerCfgTypeDef;
bogdanm 86:04dd9b1680ae 270
bogdanm 86:04dd9b1680ae 271 /**
bogdanm 86:04dd9b1680ae 272 * @brief Compare unit configuration definition
bogdanm 86:04dd9b1680ae 273 */
bogdanm 86:04dd9b1680ae 274 typedef struct {
bogdanm 86:04dd9b1680ae 275 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
bogdanm 86:04dd9b1680ae 276 the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
bogdanm 86:04dd9b1680ae 277 the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
bogdanm 86:04dd9b1680ae 278 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
bogdanm 86:04dd9b1680ae 279 This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
bogdanm 86:04dd9b1680ae 280 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
bogdanm 86:04dd9b1680ae 281 CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
bogdanm 86:04dd9b1680ae 282 } HRTIM_CompareCfgTypeDef;
bogdanm 86:04dd9b1680ae 283
bogdanm 86:04dd9b1680ae 284 /**
bogdanm 86:04dd9b1680ae 285 * @brief Capture unit configuration definition
bogdanm 86:04dd9b1680ae 286 */
bogdanm 86:04dd9b1680ae 287 typedef struct {
bogdanm 86:04dd9b1680ae 288 uint32_t Trigger; /*!< Specifies source(s) triggering the capture
bogdanm 86:04dd9b1680ae 289 This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
bogdanm 86:04dd9b1680ae 290 } HRTIM_CaptureCfgTypeDef;
bogdanm 86:04dd9b1680ae 291
bogdanm 86:04dd9b1680ae 292 /**
bogdanm 86:04dd9b1680ae 293 * @brief Output configuration definition
bogdanm 86:04dd9b1680ae 294 */
bogdanm 86:04dd9b1680ae 295 typedef struct {
bogdanm 86:04dd9b1680ae 296 uint32_t Polarity; /*!< Specifies the output polarity
bogdanm 86:04dd9b1680ae 297 This parameter can be any value of @ref HRTIM_Output_Polarity */
bogdanm 86:04dd9b1680ae 298 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level
bogdanm 86:04dd9b1680ae 299 This parameter can be a combination of @ref HRTIM_Output_Set_Source */
bogdanm 86:04dd9b1680ae 300 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level
bogdanm 86:04dd9b1680ae 301 This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
bogdanm 86:04dd9b1680ae 302 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation
bogdanm 86:04dd9b1680ae 303 This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
bogdanm 86:04dd9b1680ae 304 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
bogdanm 86:04dd9b1680ae 305 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
bogdanm 86:04dd9b1680ae 306 uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state
bogdanm 86:04dd9b1680ae 307 This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
bogdanm 86:04dd9b1680ae 308 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
bogdanm 86:04dd9b1680ae 309 This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
bogdanm 86:04dd9b1680ae 310 uint32_t BurstModeEntryDelayed; /* !<Indicates whether or not deadtime is inserted when entering the IDLE state
bogdanm 86:04dd9b1680ae 311 during a burst mode operation
bogdanm 86:04dd9b1680ae 312 This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
bogdanm 86:04dd9b1680ae 313 } HRTIM_OutputCfgTypeDef;
bogdanm 86:04dd9b1680ae 314
bogdanm 86:04dd9b1680ae 315 /**
bogdanm 86:04dd9b1680ae 316 * @brief External event filtering in timing units configuration definition
bogdanm 86:04dd9b1680ae 317 */
bogdanm 86:04dd9b1680ae 318 typedef struct {
bogdanm 86:04dd9b1680ae 319 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit
bogdanm 86:04dd9b1680ae 320 This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
bogdanm 86:04dd9b1680ae 321 uint32_t Latch; /*!< Specifies whether or not the signal is latched
bogdanm 86:04dd9b1680ae 322 This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
bogdanm 86:04dd9b1680ae 323 } HRTIM_TimerEventFilteringCfgTypeDef;
bogdanm 86:04dd9b1680ae 324
bogdanm 86:04dd9b1680ae 325 /**
bogdanm 86:04dd9b1680ae 326 * @brief Dead time feature configuration definition
bogdanm 86:04dd9b1680ae 327 */
bogdanm 86:04dd9b1680ae 328 typedef struct {
bogdanm 86:04dd9b1680ae 329 uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler
bogdanm 86:04dd9b1680ae 330 This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
bogdanm 86:04dd9b1680ae 331 uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge
bogdanm 86:04dd9b1680ae 332 This parameter can be a number between 0x0 and 0x1FF */
bogdanm 86:04dd9b1680ae 333 uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge
bogdanm 86:04dd9b1680ae 334 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
bogdanm 86:04dd9b1680ae 335 uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected
bogdanm 86:04dd9b1680ae 336 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
bogdanm 86:04dd9b1680ae 337 uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected
bogdanm 86:04dd9b1680ae 338 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
bogdanm 86:04dd9b1680ae 339 uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge
bogdanm 86:04dd9b1680ae 340 This parameter can be a number between 0x0 and 0x1FF */
bogdanm 86:04dd9b1680ae 341 uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge
bogdanm 86:04dd9b1680ae 342 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
bogdanm 86:04dd9b1680ae 343 uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected
bogdanm 86:04dd9b1680ae 344 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
bogdanm 86:04dd9b1680ae 345 uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected
bogdanm 86:04dd9b1680ae 346 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
bogdanm 86:04dd9b1680ae 347 } HRTIM_DeadTimeCfgTypeDef ;
bogdanm 86:04dd9b1680ae 348
bogdanm 86:04dd9b1680ae 349 /**
bogdanm 86:04dd9b1680ae 350 * @brief Chopper mode configuration definition
bogdanm 86:04dd9b1680ae 351 */
bogdanm 86:04dd9b1680ae 352 typedef struct {
bogdanm 86:04dd9b1680ae 353 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
bogdanm 86:04dd9b1680ae 354 This parameter can be a value of @ref HRTIM_Chopper_Frequency */
bogdanm 86:04dd9b1680ae 355 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
bogdanm 86:04dd9b1680ae 356 This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
bogdanm 86:04dd9b1680ae 357 uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
bogdanm 86:04dd9b1680ae 358 This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
bogdanm 86:04dd9b1680ae 359 } HRTIM_ChopperModeCfgTypeDef;
bogdanm 86:04dd9b1680ae 360
bogdanm 86:04dd9b1680ae 361 /**
bogdanm 86:04dd9b1680ae 362 * @brief External event channel configuration definition
bogdanm 86:04dd9b1680ae 363 */
bogdanm 86:04dd9b1680ae 364 typedef struct {
bogdanm 86:04dd9b1680ae 365 uint32_t Source; /*!< Identifies the source of the external event
bogdanm 86:04dd9b1680ae 366 This parameter can be a value of @ref HRTIM_External_Event_Sources */
bogdanm 86:04dd9b1680ae 367 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
bogdanm 86:04dd9b1680ae 368 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
bogdanm 86:04dd9b1680ae 369 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event
bogdanm 86:04dd9b1680ae 370 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
bogdanm 86:04dd9b1680ae 371 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
bogdanm 86:04dd9b1680ae 372 This parameter can be a value of @ref HRTIM_External_Event_Filter */
bogdanm 86:04dd9b1680ae 373 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event
bogdanm 86:04dd9b1680ae 374 This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
bogdanm 86:04dd9b1680ae 375 } HRTIM_EventCfgTypeDef;
bogdanm 86:04dd9b1680ae 376
bogdanm 86:04dd9b1680ae 377 /**
bogdanm 86:04dd9b1680ae 378 * @brief Fault channel configuration definition
bogdanm 86:04dd9b1680ae 379 */
bogdanm 86:04dd9b1680ae 380 typedef struct {
bogdanm 86:04dd9b1680ae 381 uint32_t Source; /*!< Identifies the source of the fault
bogdanm 86:04dd9b1680ae 382 This parameter can be a value of @ref HRTIM_Fault_Sources */
bogdanm 86:04dd9b1680ae 383 uint32_t Polarity; /*!< Specifies the polarity of the fault event
bogdanm 86:04dd9b1680ae 384 This parameter can be a value of @ref HRTIM_Fault_Polarity */
bogdanm 86:04dd9b1680ae 385 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter
bogdanm 86:04dd9b1680ae 386 This parameter can be a value of @ref HRTIM_Fault_Filter */
bogdanm 86:04dd9b1680ae 387 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected
bogdanm 86:04dd9b1680ae 388 This parameter can be a value of @ref HRTIM_Fault_Lock */
bogdanm 86:04dd9b1680ae 389 } HRTIM_FaultCfgTypeDef;
bogdanm 86:04dd9b1680ae 390
bogdanm 86:04dd9b1680ae 391 /**
bogdanm 86:04dd9b1680ae 392 * @brief Burst mode configuration definition
bogdanm 86:04dd9b1680ae 393 */
bogdanm 86:04dd9b1680ae 394 typedef struct {
bogdanm 86:04dd9b1680ae 395 uint32_t Mode; /*!< Specifies the burst mode operating mode
bogdanm 86:04dd9b1680ae 396 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_mode */
bogdanm 86:04dd9b1680ae 397 uint32_t ClockSource; /*!< Specifies the burst mode clock source
bogdanm 86:04dd9b1680ae 398 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
bogdanm 86:04dd9b1680ae 399 uint32_t Prescaler; /*!< Specifies the burst mode prescaler
bogdanm 86:04dd9b1680ae 400 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
bogdanm 86:04dd9b1680ae 401 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER)
bogdanm 86:04dd9b1680ae 402 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
bogdanm 86:04dd9b1680ae 403 uint32_t Trigger; /*!< Specifies the event(s) trigering the burst operation
bogdanm 86:04dd9b1680ae 404 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
bogdanm 86:04dd9b1680ae 405 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state
bogdanm 86:04dd9b1680ae 406 This parameter can be a number between 0x0 and 0xFFFF */
bogdanm 86:04dd9b1680ae 407 uint32_t Period; /*!< Specifies burst mode repetition period
bogdanm 86:04dd9b1680ae 408 This parameter can be a number between 0x1 and 0xFFFF */
bogdanm 86:04dd9b1680ae 409 } HRTIM_BurstModeCfgTypeDef;
bogdanm 86:04dd9b1680ae 410
bogdanm 86:04dd9b1680ae 411 /**
bogdanm 86:04dd9b1680ae 412 * @brief ADC trigger configuration definition
bogdanm 86:04dd9b1680ae 413 */
bogdanm 86:04dd9b1680ae 414 typedef struct {
bogdanm 86:04dd9b1680ae 415 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source
bogdanm 86:04dd9b1680ae 416 This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source */
bogdanm 86:04dd9b1680ae 417 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion
bogdanm 86:04dd9b1680ae 418 This parameter can be a value of @ref HRTIM_ADC_Trigger_Event */
bogdanm 86:04dd9b1680ae 419 } HRTIM_ADCTriggerCfgTypeDef;
bogdanm 86:04dd9b1680ae 420
bogdanm 86:04dd9b1680ae 421
bogdanm 86:04dd9b1680ae 422 /* Exported constants --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 423 /** @defgroup HRTIM_Exported_Constants
bogdanm 86:04dd9b1680ae 424 * @{
bogdanm 86:04dd9b1680ae 425 */
bogdanm 86:04dd9b1680ae 426
bogdanm 86:04dd9b1680ae 427 /** @defgroup HRTIM_Timer_Index
bogdanm 86:04dd9b1680ae 428 * @{
bogdanm 86:04dd9b1680ae 429 * @brief Constants defining the timer indexes
bogdanm 86:04dd9b1680ae 430 */
bogdanm 86:04dd9b1680ae 431 #define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /*!< Index used to access timer A registers */
bogdanm 86:04dd9b1680ae 432 #define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /*!< Index used to access timer B registers */
bogdanm 86:04dd9b1680ae 433 #define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /*!< Index used to access timer C registers */
bogdanm 86:04dd9b1680ae 434 #define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /*!< Index used to access timer D registers */
bogdanm 86:04dd9b1680ae 435 #define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /*!< Index used to access timer E registers */
bogdanm 86:04dd9b1680ae 436 #define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /*!< Index used to access master registers */
bogdanm 86:04dd9b1680ae 437 #define HRTIM_TIMERINDEX_COMMON (uint32_t)0xFF /*!< Index used to access HRTIM common registers */
bogdanm 86:04dd9b1680ae 438
bogdanm 86:04dd9b1680ae 439 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
bogdanm 86:04dd9b1680ae 440 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
bogdanm 86:04dd9b1680ae 441 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
bogdanm 86:04dd9b1680ae 442 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
bogdanm 86:04dd9b1680ae 443 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
bogdanm 86:04dd9b1680ae 444 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
bogdanm 86:04dd9b1680ae 445 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
bogdanm 86:04dd9b1680ae 446
bogdanm 86:04dd9b1680ae 447 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
bogdanm 86:04dd9b1680ae 448 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
bogdanm 86:04dd9b1680ae 449 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
bogdanm 86:04dd9b1680ae 450 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
bogdanm 86:04dd9b1680ae 451 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
bogdanm 86:04dd9b1680ae 452 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
bogdanm 86:04dd9b1680ae 453 /**
bogdanm 86:04dd9b1680ae 454 * @}
bogdanm 86:04dd9b1680ae 455 */
bogdanm 86:04dd9b1680ae 456
bogdanm 86:04dd9b1680ae 457 /** @defgroup HRTIM_Timer_identifier
bogdanm 86:04dd9b1680ae 458 * @{
bogdanm 86:04dd9b1680ae 459 * @brief Constants defining timer identifiers
bogdanm 86:04dd9b1680ae 460 */
bogdanm 86:04dd9b1680ae 461 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/
bogdanm 86:04dd9b1680ae 462 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
bogdanm 86:04dd9b1680ae 463 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
bogdanm 86:04dd9b1680ae 464 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
bogdanm 86:04dd9b1680ae 465 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
bogdanm 86:04dd9b1680ae 466 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
bogdanm 86:04dd9b1680ae 467
bogdanm 86:04dd9b1680ae 468 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFF) == 0x00000000)
bogdanm 86:04dd9b1680ae 469
bogdanm 86:04dd9b1680ae 470 /**
bogdanm 86:04dd9b1680ae 471 * @}
bogdanm 86:04dd9b1680ae 472 */
bogdanm 86:04dd9b1680ae 473
bogdanm 86:04dd9b1680ae 474 /** @defgroup HRTIM_Compare_Unit
bogdanm 86:04dd9b1680ae 475 * @{
bogdanm 86:04dd9b1680ae 476 * @brief Constants defining compare unit identifiers
bogdanm 86:04dd9b1680ae 477 */
bogdanm 86:04dd9b1680ae 478 #define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /*!< Compare unit 1 identifier */
bogdanm 86:04dd9b1680ae 479 #define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /*!< Compare unit 2 identifier */
bogdanm 86:04dd9b1680ae 480 #define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /*!< Compare unit 3 identifier */
bogdanm 86:04dd9b1680ae 481 #define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /*!< Compare unit 4 identifier */
bogdanm 86:04dd9b1680ae 482
bogdanm 86:04dd9b1680ae 483 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
bogdanm 86:04dd9b1680ae 484 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
bogdanm 86:04dd9b1680ae 485 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
bogdanm 86:04dd9b1680ae 486 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
bogdanm 86:04dd9b1680ae 487 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
bogdanm 86:04dd9b1680ae 488 /**
bogdanm 86:04dd9b1680ae 489 * @}
bogdanm 86:04dd9b1680ae 490 */
bogdanm 86:04dd9b1680ae 491
bogdanm 86:04dd9b1680ae 492 /** @defgroup HRTIM_Capture_Unit
bogdanm 86:04dd9b1680ae 493 * @{
bogdanm 86:04dd9b1680ae 494 * @brief Constants defining capture unit identifiers
bogdanm 86:04dd9b1680ae 495 */
bogdanm 86:04dd9b1680ae 496 #define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /*!< Capture unit 1 identifier */
bogdanm 86:04dd9b1680ae 497 #define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /*!< Capture unit 2 identifier */
bogdanm 86:04dd9b1680ae 498
bogdanm 86:04dd9b1680ae 499 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
bogdanm 86:04dd9b1680ae 500 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
bogdanm 86:04dd9b1680ae 501 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
bogdanm 86:04dd9b1680ae 502 /**
bogdanm 86:04dd9b1680ae 503 * @}
bogdanm 86:04dd9b1680ae 504 */
bogdanm 86:04dd9b1680ae 505
bogdanm 86:04dd9b1680ae 506 /** @defgroup HRTIM_Timer_Output
bogdanm 86:04dd9b1680ae 507 * @{
bogdanm 86:04dd9b1680ae 508 * @brief Constants defining timer output identifiers
bogdanm 86:04dd9b1680ae 509 */
bogdanm 86:04dd9b1680ae 510 #define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /*!< Timer A - Ouput 1 identifier */
bogdanm 86:04dd9b1680ae 511 #define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /*!< Timer A - Ouput 2 identifier */
bogdanm 86:04dd9b1680ae 512 #define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /*!< Timer B - Ouput 1 identifier */
bogdanm 86:04dd9b1680ae 513 #define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /*!< Timer B - Ouput 2 identifier */
bogdanm 86:04dd9b1680ae 514 #define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /*!< Timer C - Ouput 1 identifier */
bogdanm 86:04dd9b1680ae 515 #define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /*!< Timer C - Ouput 2 identifier */
bogdanm 86:04dd9b1680ae 516 #define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /*!< Timer D - Ouput 1 identifier */
bogdanm 86:04dd9b1680ae 517 #define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /*!< Timer D - Ouput 2 identifier */
bogdanm 86:04dd9b1680ae 518 #define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /*!< Timer E - Ouput 1 identifier */
bogdanm 86:04dd9b1680ae 519 #define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /*!< Timer E - Ouput 2 identifier */
bogdanm 86:04dd9b1680ae 520
bogdanm 86:04dd9b1680ae 521 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00) == 0x00000000)
bogdanm 86:04dd9b1680ae 522
bogdanm 86:04dd9b1680ae 523 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
bogdanm 86:04dd9b1680ae 524 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
bogdanm 86:04dd9b1680ae 525 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
bogdanm 86:04dd9b1680ae 526 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
bogdanm 86:04dd9b1680ae 527 || \
bogdanm 86:04dd9b1680ae 528 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
bogdanm 86:04dd9b1680ae 529 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
bogdanm 86:04dd9b1680ae 530 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
bogdanm 86:04dd9b1680ae 531 || \
bogdanm 86:04dd9b1680ae 532 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
bogdanm 86:04dd9b1680ae 533 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
bogdanm 86:04dd9b1680ae 534 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
bogdanm 86:04dd9b1680ae 535 || \
bogdanm 86:04dd9b1680ae 536 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
bogdanm 86:04dd9b1680ae 537 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
bogdanm 86:04dd9b1680ae 538 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
bogdanm 86:04dd9b1680ae 539 || \
bogdanm 86:04dd9b1680ae 540 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
bogdanm 86:04dd9b1680ae 541 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
bogdanm 86:04dd9b1680ae 542 ((OUTPUT) == HRTIM_OUTPUT_TE2))))
bogdanm 86:04dd9b1680ae 543 /**
bogdanm 86:04dd9b1680ae 544 * @}
bogdanm 86:04dd9b1680ae 545 */
bogdanm 86:04dd9b1680ae 546
bogdanm 86:04dd9b1680ae 547 /** @defgroup HRTIM_ADC_Trigger
bogdanm 86:04dd9b1680ae 548 * @{
bogdanm 86:04dd9b1680ae 549 * @brief Constants defining ADC triggers identifiers
bogdanm 86:04dd9b1680ae 550 */
bogdanm 86:04dd9b1680ae 551 #define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /*!< ADC trigger 1 identifier */
bogdanm 86:04dd9b1680ae 552 #define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /*!< ADC trigger 2 identifier */
bogdanm 86:04dd9b1680ae 553 #define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /*!< ADC trigger 3 identifier */
bogdanm 86:04dd9b1680ae 554 #define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /*!< ADC trigger 4 identifier */
bogdanm 86:04dd9b1680ae 555
bogdanm 86:04dd9b1680ae 556 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
bogdanm 86:04dd9b1680ae 557 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
bogdanm 86:04dd9b1680ae 558 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
bogdanm 86:04dd9b1680ae 559 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
bogdanm 86:04dd9b1680ae 560 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
bogdanm 86:04dd9b1680ae 561 /**
bogdanm 86:04dd9b1680ae 562 * @}
bogdanm 86:04dd9b1680ae 563 */
bogdanm 86:04dd9b1680ae 564
bogdanm 86:04dd9b1680ae 565 /** @defgroup HRTIM_External_Event_Channels
bogdanm 86:04dd9b1680ae 566 * @{
bogdanm 86:04dd9b1680ae 567 * @brief Constants defining external event channel identifiers
bogdanm 86:04dd9b1680ae 568 */
bogdanm 86:04dd9b1680ae 569 #define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /*!< Undefined event channel */
bogdanm 86:04dd9b1680ae 570 #define HRTIM_EVENT_1 ((uint32_t)0x00000001) /*!< External event channel 1 identifier */
bogdanm 86:04dd9b1680ae 571 #define HRTIM_EVENT_2 ((uint32_t)0x00000002) /*!< External event channel 2 identifier */
bogdanm 86:04dd9b1680ae 572 #define HRTIM_EVENT_3 ((uint32_t)0x00000004) /*!< External event channel 3 identifier */
bogdanm 86:04dd9b1680ae 573 #define HRTIM_EVENT_4 ((uint32_t)0x00000008) /*!< External event channel 4 identifier */
bogdanm 86:04dd9b1680ae 574 #define HRTIM_EVENT_5 ((uint32_t)0x00000010) /*!< External event channel 5 identifier */
bogdanm 86:04dd9b1680ae 575 #define HRTIM_EVENT_6 ((uint32_t)0x00000020) /*!< External event channel 6 identifier */
bogdanm 86:04dd9b1680ae 576 #define HRTIM_EVENT_7 ((uint32_t)0x00000040) /*!< External event channel 7 identifier */
bogdanm 86:04dd9b1680ae 577 #define HRTIM_EVENT_8 ((uint32_t)0x00000080) /*!< External event channel 8 identifier */
bogdanm 86:04dd9b1680ae 578 #define HRTIM_EVENT_9 ((uint32_t)0x00000100) /*!< External event channel 9 identifier */
bogdanm 86:04dd9b1680ae 579 #define HRTIM_EVENT_10 ((uint32_t)0x00000200) /*!< External event channel 10 identifier */
bogdanm 86:04dd9b1680ae 580
bogdanm 86:04dd9b1680ae 581 #define IS_HRTIM_EVENT(EVENT)\
bogdanm 86:04dd9b1680ae 582 (((EVENT) == HRTIM_EVENT_1) || \
bogdanm 86:04dd9b1680ae 583 ((EVENT) == HRTIM_EVENT_2) || \
bogdanm 86:04dd9b1680ae 584 ((EVENT) == HRTIM_EVENT_3) || \
bogdanm 86:04dd9b1680ae 585 ((EVENT) == HRTIM_EVENT_4) || \
bogdanm 86:04dd9b1680ae 586 ((EVENT) == HRTIM_EVENT_5) || \
bogdanm 86:04dd9b1680ae 587 ((EVENT) == HRTIM_EVENT_6) || \
bogdanm 86:04dd9b1680ae 588 ((EVENT) == HRTIM_EVENT_7) || \
bogdanm 86:04dd9b1680ae 589 ((EVENT) == HRTIM_EVENT_8) || \
bogdanm 86:04dd9b1680ae 590 ((EVENT) == HRTIM_EVENT_9) || \
bogdanm 86:04dd9b1680ae 591 ((EVENT) == HRTIM_EVENT_10))
bogdanm 86:04dd9b1680ae 592 /**
bogdanm 86:04dd9b1680ae 593 * @}
bogdanm 86:04dd9b1680ae 594 */
bogdanm 86:04dd9b1680ae 595
bogdanm 86:04dd9b1680ae 596 /** @defgroup HRTIM_Fault_Channel
bogdanm 86:04dd9b1680ae 597 * @{
bogdanm 86:04dd9b1680ae 598 * @brief Constants defining fault channel identifiers
bogdanm 86:04dd9b1680ae 599 */
bogdanm 86:04dd9b1680ae 600 #define HRTIM_FAULT_1 ((uint32_t)0x01) /*!< Fault channel 1 identifier */
bogdanm 86:04dd9b1680ae 601 #define HRTIM_FAULT_2 ((uint32_t)0x02) /*!< Fault channel 2 identifier */
bogdanm 86:04dd9b1680ae 602 #define HRTIM_FAULT_3 ((uint32_t)0x04) /*!< Fault channel 3 identifier */
bogdanm 86:04dd9b1680ae 603 #define HRTIM_FAULT_4 ((uint32_t)0x08) /*!< Fault channel 4 identifier */
bogdanm 86:04dd9b1680ae 604 #define HRTIM_FAULT_5 ((uint32_t)0x10) /*!< Fault channel 5 identifier */
bogdanm 86:04dd9b1680ae 605
bogdanm 86:04dd9b1680ae 606 #define IS_HRTIM_FAULT(FAULT)\
bogdanm 86:04dd9b1680ae 607 (((FAULT) == HRTIM_FAULT_1) || \
bogdanm 86:04dd9b1680ae 608 ((FAULT) == HRTIM_FAULT_2) || \
bogdanm 86:04dd9b1680ae 609 ((FAULT) == HRTIM_FAULT_3) || \
bogdanm 86:04dd9b1680ae 610 ((FAULT) == HRTIM_FAULT_4) || \
bogdanm 86:04dd9b1680ae 611 ((FAULT) == HRTIM_FAULT_5))
bogdanm 86:04dd9b1680ae 612 /**
bogdanm 86:04dd9b1680ae 613 * @}
bogdanm 86:04dd9b1680ae 614 */
bogdanm 86:04dd9b1680ae 615
bogdanm 86:04dd9b1680ae 616
bogdanm 86:04dd9b1680ae 617 /** @defgroup HRTIM_Prescaler_Ratio
bogdanm 86:04dd9b1680ae 618 * @{
bogdanm 86:04dd9b1680ae 619 * @brief Constants defining timer high-resolution clock prescaler ratio.
bogdanm 86:04dd9b1680ae 620 */
bogdanm 86:04dd9b1680ae 621 #define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /*!< fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
bogdanm 86:04dd9b1680ae 622 #define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /*!< fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
bogdanm 86:04dd9b1680ae 623 #define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /*!< fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
bogdanm 86:04dd9b1680ae 624 #define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /*!< fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
bogdanm 86:04dd9b1680ae 625 #define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /*!< fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
bogdanm 86:04dd9b1680ae 626 #define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /*!< fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
bogdanm 86:04dd9b1680ae 627 #define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /*!< fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
bogdanm 86:04dd9b1680ae 628 #define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /*!< fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
bogdanm 86:04dd9b1680ae 629
bogdanm 86:04dd9b1680ae 630 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
bogdanm 86:04dd9b1680ae 631 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
bogdanm 86:04dd9b1680ae 632 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
bogdanm 86:04dd9b1680ae 633 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
bogdanm 86:04dd9b1680ae 634 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
bogdanm 86:04dd9b1680ae 635 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
bogdanm 86:04dd9b1680ae 636 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
bogdanm 86:04dd9b1680ae 637 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
bogdanm 86:04dd9b1680ae 638 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
bogdanm 86:04dd9b1680ae 639 /**
bogdanm 86:04dd9b1680ae 640 * @}
bogdanm 86:04dd9b1680ae 641 */
bogdanm 86:04dd9b1680ae 642
bogdanm 86:04dd9b1680ae 643 /** @defgroup HRTIM_Mode
bogdanm 86:04dd9b1680ae 644 * @{
bogdanm 86:04dd9b1680ae 645 * @brief Constants defining timer counter operating mode.
bogdanm 86:04dd9b1680ae 646 */
bogdanm 86:04dd9b1680ae 647 #define HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008) /*!< The timer operates in continuous (free-running) mode */
bogdanm 86:04dd9b1680ae 648 #define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /*!< The timer operates in non retriggerable single-shot mode */
bogdanm 86:04dd9b1680ae 649 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /*!< The timer operates in retriggerable single-shot mode */
bogdanm 86:04dd9b1680ae 650
bogdanm 86:04dd9b1680ae 651 #define IS_HRTIM_MODE(MODE)\
bogdanm 86:04dd9b1680ae 652 (((MODE) == HRTIM_MODE_CONTINUOUS) || \
bogdanm 86:04dd9b1680ae 653 ((MODE) == HRTIM_MODE_SINGLESHOT) || \
bogdanm 86:04dd9b1680ae 654 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
bogdanm 86:04dd9b1680ae 655
bogdanm 86:04dd9b1680ae 656 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
bogdanm 86:04dd9b1680ae 657 (((MODE) == HRTIM_MODE_SINGLESHOT) || \
bogdanm 86:04dd9b1680ae 658 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
bogdanm 86:04dd9b1680ae 659
bogdanm 86:04dd9b1680ae 660 /**
bogdanm 86:04dd9b1680ae 661 * @}
bogdanm 86:04dd9b1680ae 662 */
bogdanm 86:04dd9b1680ae 663
bogdanm 86:04dd9b1680ae 664 /** @defgroup HRTIM_Half_Mode_Enable
bogdanm 86:04dd9b1680ae 665 * @{
bogdanm 86:04dd9b1680ae 666 * @brief Constants defining half mode enabling status.
bogdanm 86:04dd9b1680ae 667 */
bogdanm 86:04dd9b1680ae 668 #define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /*!< Half mode is disabled */
bogdanm 86:04dd9b1680ae 669 #define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /*!< Half mode is enabled */
bogdanm 86:04dd9b1680ae 670
bogdanm 86:04dd9b1680ae 671 #define IS_HRTIM_HALFMODE(HALFMODE)\
bogdanm 86:04dd9b1680ae 672 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
bogdanm 86:04dd9b1680ae 673 ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
bogdanm 86:04dd9b1680ae 674 /**
bogdanm 86:04dd9b1680ae 675 * @}
bogdanm 86:04dd9b1680ae 676 */
bogdanm 86:04dd9b1680ae 677
bogdanm 86:04dd9b1680ae 678 /** @defgroup HRTIM_Start_On_Sync_Input_Event
bogdanm 86:04dd9b1680ae 679 * @{
bogdanm 86:04dd9b1680ae 680 * @brief Constants defining the timer behavior following the synchronization event
bogdanm 86:04dd9b1680ae 681 */
bogdanm 86:04dd9b1680ae 682 #define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
bogdanm 86:04dd9b1680ae 683 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
bogdanm 86:04dd9b1680ae 684
bogdanm 86:04dd9b1680ae 685 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
bogdanm 86:04dd9b1680ae 686 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
bogdanm 86:04dd9b1680ae 687 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
bogdanm 86:04dd9b1680ae 688 /**
bogdanm 86:04dd9b1680ae 689 * @}
bogdanm 86:04dd9b1680ae 690 */
bogdanm 86:04dd9b1680ae 691
bogdanm 86:04dd9b1680ae 692 /** @defgroup HRTIM_Reset_On_Sync_Input_Event
bogdanm 86:04dd9b1680ae 693 * @{
bogdanm 86:04dd9b1680ae 694 * @brief Constants defining the timer behavior following the synchronization event
bogdanm 86:04dd9b1680ae 695 */
bogdanm 86:04dd9b1680ae 696 #define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
bogdanm 86:04dd9b1680ae 697 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
bogdanm 86:04dd9b1680ae 698
bogdanm 86:04dd9b1680ae 699 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
bogdanm 86:04dd9b1680ae 700 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
bogdanm 86:04dd9b1680ae 701 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
bogdanm 86:04dd9b1680ae 702 /**
bogdanm 86:04dd9b1680ae 703 * @}
bogdanm 86:04dd9b1680ae 704 */
bogdanm 86:04dd9b1680ae 705
bogdanm 86:04dd9b1680ae 706 /** @defgroup HRTIM_DAC_Synchronization
bogdanm 86:04dd9b1680ae 707 * @{
bogdanm 86:04dd9b1680ae 708 * @brief Constants defining on which output the DAC synchronization event is sent
bogdanm 86:04dd9b1680ae 709 */
bogdanm 86:04dd9b1680ae 710 #define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /*!< No DAC synchronization event generated */
bogdanm 86:04dd9b1680ae 711 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
bogdanm 86:04dd9b1680ae 712 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
bogdanm 86:04dd9b1680ae 713 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
bogdanm 86:04dd9b1680ae 714
bogdanm 86:04dd9b1680ae 715 #define IS_HHRTIM_DACSYNC(DACSYNC)\
bogdanm 86:04dd9b1680ae 716 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
bogdanm 86:04dd9b1680ae 717 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
bogdanm 86:04dd9b1680ae 718 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
bogdanm 86:04dd9b1680ae 719 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
bogdanm 86:04dd9b1680ae 720 /**
bogdanm 86:04dd9b1680ae 721 * @}
bogdanm 86:04dd9b1680ae 722 */
bogdanm 86:04dd9b1680ae 723
bogdanm 86:04dd9b1680ae 724 /** @defgroup HRTIM_Register_Preload_Enable
bogdanm 86:04dd9b1680ae 725 * @{
bogdanm 86:04dd9b1680ae 726 * @brief Constants defining whether a write access into a preloadable
bogdanm 86:04dd9b1680ae 727 * register is done into the active or the preload register.
bogdanm 86:04dd9b1680ae 728 */
bogdanm 86:04dd9b1680ae 729 #define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into the active register */
bogdanm 86:04dd9b1680ae 730 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
bogdanm 86:04dd9b1680ae 731
bogdanm 86:04dd9b1680ae 732 #define IS_HRTIM_PRELOAD(PRELOAD)\
bogdanm 86:04dd9b1680ae 733 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
bogdanm 86:04dd9b1680ae 734 ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
bogdanm 86:04dd9b1680ae 735 /**
bogdanm 86:04dd9b1680ae 736 * @}
bogdanm 86:04dd9b1680ae 737 */
bogdanm 86:04dd9b1680ae 738
bogdanm 86:04dd9b1680ae 739 /** @defgroup HRTIM_Update_Gating
bogdanm 86:04dd9b1680ae 740 * @{
bogdanm 86:04dd9b1680ae 741 * @brief Constants defining how the update occurs relatively to the burst DMA
bogdanm 86:04dd9b1680ae 742 * transaction and the external update request on update enable inputs 1 to 3.
bogdanm 86:04dd9b1680ae 743 */
bogdanm 86:04dd9b1680ae 744 #define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /*!< Update done independently from the DMA burst transfer completion */
bogdanm 86:04dd9b1680ae 745 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
bogdanm 86:04dd9b1680ae 746 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
bogdanm 86:04dd9b1680ae 747 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
bogdanm 86:04dd9b1680ae 748 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
bogdanm 86:04dd9b1680ae 749 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
bogdanm 86:04dd9b1680ae 750 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
bogdanm 86:04dd9b1680ae 751 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
bogdanm 86:04dd9b1680ae 752 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
bogdanm 86:04dd9b1680ae 753
bogdanm 86:04dd9b1680ae 754 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
bogdanm 86:04dd9b1680ae 755 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
bogdanm 86:04dd9b1680ae 756 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
bogdanm 86:04dd9b1680ae 757 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
bogdanm 86:04dd9b1680ae 758
bogdanm 86:04dd9b1680ae 759 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
bogdanm 86:04dd9b1680ae 760 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
bogdanm 86:04dd9b1680ae 761 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
bogdanm 86:04dd9b1680ae 762 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
bogdanm 86:04dd9b1680ae 763 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
bogdanm 86:04dd9b1680ae 764 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
bogdanm 86:04dd9b1680ae 765 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
bogdanm 86:04dd9b1680ae 766 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
bogdanm 86:04dd9b1680ae 767 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
bogdanm 86:04dd9b1680ae 768 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
bogdanm 86:04dd9b1680ae 769 /**
bogdanm 86:04dd9b1680ae 770 * @}
bogdanm 86:04dd9b1680ae 771 */
bogdanm 86:04dd9b1680ae 772
bogdanm 86:04dd9b1680ae 773 /** @defgroup HRTIM_Timer_Burst_Mode
bogdanm 86:04dd9b1680ae 774 * @{
bogdanm 86:04dd9b1680ae 775 * @brief Constants defining how the timer behaves during a burst
bogdanm 86:04dd9b1680ae 776 mode operation.
bogdanm 86:04dd9b1680ae 777 */
bogdanm 86:04dd9b1680ae 778 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
bogdanm 86:04dd9b1680ae 779 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
bogdanm 86:04dd9b1680ae 780
bogdanm 86:04dd9b1680ae 781 #define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
bogdanm 86:04dd9b1680ae 782 (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
bogdanm 86:04dd9b1680ae 783 ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
bogdanm 86:04dd9b1680ae 784 /**
bogdanm 86:04dd9b1680ae 785 * @}
bogdanm 86:04dd9b1680ae 786 */
bogdanm 86:04dd9b1680ae 787
bogdanm 86:04dd9b1680ae 788 /** @defgroup HRTIM_Timer_Repetition_Update
bogdanm 86:04dd9b1680ae 789 * @{
bogdanm 86:04dd9b1680ae 790 * @brief Constants defining whether registers are updated when the timer
bogdanm 86:04dd9b1680ae 791 * repetition period is completed (either due to roll-over or
bogdanm 86:04dd9b1680ae 792 * reset events)
bogdanm 86:04dd9b1680ae 793 */
bogdanm 86:04dd9b1680ae 794 #define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /*!< Update on repetition disabled */
bogdanm 86:04dd9b1680ae 795 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
bogdanm 86:04dd9b1680ae 796
bogdanm 86:04dd9b1680ae 797 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
bogdanm 86:04dd9b1680ae 798 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
bogdanm 86:04dd9b1680ae 799 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
bogdanm 86:04dd9b1680ae 800 /**
bogdanm 86:04dd9b1680ae 801 * @}
bogdanm 86:04dd9b1680ae 802 */
bogdanm 86:04dd9b1680ae 803
bogdanm 86:04dd9b1680ae 804
bogdanm 86:04dd9b1680ae 805 /** @defgroup HRTIM_Timer_Push_Pull_Mode
bogdanm 86:04dd9b1680ae 806 * @{
bogdanm 86:04dd9b1680ae 807 * @brief Constants defining whether or not the puhs-pull mode is enabled for
bogdanm 86:04dd9b1680ae 808 * a timer.
bogdanm 86:04dd9b1680ae 809 */
bogdanm 86:04dd9b1680ae 810 #define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /*!< Push-Pull mode disabled */
bogdanm 86:04dd9b1680ae 811 #define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
bogdanm 86:04dd9b1680ae 812
bogdanm 86:04dd9b1680ae 813 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
bogdanm 86:04dd9b1680ae 814 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
bogdanm 86:04dd9b1680ae 815 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
bogdanm 86:04dd9b1680ae 816 /**
bogdanm 86:04dd9b1680ae 817 * @}
bogdanm 86:04dd9b1680ae 818 */
bogdanm 86:04dd9b1680ae 819
bogdanm 86:04dd9b1680ae 820 /** @defgroup HRTIM_Timer_Fault_Enabling
bogdanm 86:04dd9b1680ae 821 * @{
bogdanm 86:04dd9b1680ae 822 * @brief Constants defining whether a faut channel is enabled for a timer
bogdanm 86:04dd9b1680ae 823 */
bogdanm 86:04dd9b1680ae 824 #define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /*!< No fault enabled */
bogdanm 86:04dd9b1680ae 825 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
bogdanm 86:04dd9b1680ae 826 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
bogdanm 86:04dd9b1680ae 827 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
bogdanm 86:04dd9b1680ae 828 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
bogdanm 86:04dd9b1680ae 829 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
bogdanm 86:04dd9b1680ae 830
bogdanm 86:04dd9b1680ae 831 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000)
bogdanm 86:04dd9b1680ae 832
bogdanm 86:04dd9b1680ae 833 /**
bogdanm 86:04dd9b1680ae 834 * @}
bogdanm 86:04dd9b1680ae 835 */
bogdanm 86:04dd9b1680ae 836
bogdanm 86:04dd9b1680ae 837 /** @defgroup HRTIM_Timer_Fault_Lock
bogdanm 86:04dd9b1680ae 838 * @{
bogdanm 86:04dd9b1680ae 839 * @brief Constants defining whether or not fault enabling bits are write
bogdanm 86:04dd9b1680ae 840 * protected for a timer
bogdanm 86:04dd9b1680ae 841 */
bogdanm 86:04dd9b1680ae 842 #define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Timer fault enabling bits are read/write */
bogdanm 86:04dd9b1680ae 843 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */
bogdanm 86:04dd9b1680ae 844
bogdanm 86:04dd9b1680ae 845 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
bogdanm 86:04dd9b1680ae 846 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
bogdanm 86:04dd9b1680ae 847 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
bogdanm 86:04dd9b1680ae 848 /**
bogdanm 86:04dd9b1680ae 849 * @}
bogdanm 86:04dd9b1680ae 850 */
bogdanm 86:04dd9b1680ae 851
bogdanm 86:04dd9b1680ae 852 /** @defgroup HRTIM_Timer_Deadtime_Insertion
bogdanm 86:04dd9b1680ae 853 * @{
bogdanm 86:04dd9b1680ae 854 * @brief Constants defining whether or not fault the dead time insertion
bogdanm 86:04dd9b1680ae 855 * feature is enabled for a timer
bogdanm 86:04dd9b1680ae 856 */
bogdanm 86:04dd9b1680ae 857 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /*!< Output 1 and output 2 signals are independent */
bogdanm 86:04dd9b1680ae 858 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2 */
bogdanm 86:04dd9b1680ae 859
bogdanm 86:04dd9b1680ae 860 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
bogdanm 86:04dd9b1680ae 861 ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
bogdanm 86:04dd9b1680ae 862 ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
bogdanm 86:04dd9b1680ae 863 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
bogdanm 86:04dd9b1680ae 864 || \
bogdanm 86:04dd9b1680ae 865 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
bogdanm 86:04dd9b1680ae 866 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
bogdanm 86:04dd9b1680ae 867 /**
bogdanm 86:04dd9b1680ae 868 * @}
bogdanm 86:04dd9b1680ae 869 */
bogdanm 86:04dd9b1680ae 870
bogdanm 86:04dd9b1680ae 871 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode
bogdanm 86:04dd9b1680ae 872 * @{
bogdanm 86:04dd9b1680ae 873 * @brief Constants defining all possible delayed protection modes
bogdanm 86:04dd9b1680ae 874 * for a timer. Also definethe source and outputs on which the delayed
bogdanm 86:04dd9b1680ae 875 * protection schemes are applied
bogdanm 86:04dd9b1680ae 876 */
bogdanm 86:04dd9b1680ae 877 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */
bogdanm 86:04dd9b1680ae 878 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 6 or 8 */
bogdanm 86:04dd9b1680ae 879 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 6 or 8 */
bogdanm 86:04dd9b1680ae 880 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output 2 delayed Idle on external Event 6 or 8 */
bogdanm 86:04dd9b1680ae 881 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 6 or 8 */
bogdanm 86:04dd9b1680ae 882 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 7 or 9 */
bogdanm 86:04dd9b1680ae 883 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 7 or 9 */
bogdanm 86:04dd9b1680ae 884 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output2 delayed Idle on external Event 7 or 9 */
bogdanm 86:04dd9b1680ae 885 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 7 or 9 */
bogdanm 86:04dd9b1680ae 886
bogdanm 86:04dd9b1680ae 887 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
bogdanm 86:04dd9b1680ae 888 ((((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DISABLED) || \
bogdanm 86:04dd9b1680ae 889 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68) || \
bogdanm 86:04dd9b1680ae 890 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68) || \
bogdanm 86:04dd9b1680ae 891 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68) || \
bogdanm 86:04dd9b1680ae 892 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79) || \
bogdanm 86:04dd9b1680ae 893 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79) || \
bogdanm 86:04dd9b1680ae 894 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79)) \
bogdanm 86:04dd9b1680ae 895 || \
bogdanm 86:04dd9b1680ae 896 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
bogdanm 86:04dd9b1680ae 897 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68) || \
bogdanm 86:04dd9b1680ae 898 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79)))
bogdanm 86:04dd9b1680ae 899 /**
bogdanm 86:04dd9b1680ae 900 * @}
bogdanm 86:04dd9b1680ae 901 */
bogdanm 86:04dd9b1680ae 902
bogdanm 86:04dd9b1680ae 903 /** @defgroup HRTIM_Timer_Update_Trigger
bogdanm 86:04dd9b1680ae 904 * @{
bogdanm 86:04dd9b1680ae 905 * @brief Constants defining whether the registers update is done synchronously
bogdanm 86:04dd9b1680ae 906 * with any other timer or master update
bogdanm 86:04dd9b1680ae 907 */
bogdanm 86:04dd9b1680ae 908 #define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /*!< Register update is disabled */
bogdanm 86:04dd9b1680ae 909 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
bogdanm 86:04dd9b1680ae 910 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
bogdanm 86:04dd9b1680ae 911 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
bogdanm 86:04dd9b1680ae 912 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
bogdanm 86:04dd9b1680ae 913 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
bogdanm 86:04dd9b1680ae 914 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
bogdanm 86:04dd9b1680ae 915
bogdanm 86:04dd9b1680ae 916 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000)
bogdanm 86:04dd9b1680ae 917 /**
bogdanm 86:04dd9b1680ae 918 * @}
bogdanm 86:04dd9b1680ae 919 */
bogdanm 86:04dd9b1680ae 920
bogdanm 86:04dd9b1680ae 921 /** @defgroup HRTIM_Timer_Reset_Trigger
bogdanm 86:04dd9b1680ae 922 * @{
bogdanm 86:04dd9b1680ae 923 * @brief Constants defining the events that can be selected to trigger the reset
bogdanm 86:04dd9b1680ae 924 * of the timer counter
bogdanm 86:04dd9b1680ae 925 */
bogdanm 86:04dd9b1680ae 926 #define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /*!< No counter reset trigger */
bogdanm 86:04dd9b1680ae 927 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
bogdanm 86:04dd9b1680ae 928 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
bogdanm 86:04dd9b1680ae 929 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
bogdanm 86:04dd9b1680ae 930 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timercounter is reset upon master timer period event */
bogdanm 86:04dd9b1680ae 931 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
bogdanm 86:04dd9b1680ae 932 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
bogdanm 86:04dd9b1680ae 933 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
bogdanm 86:04dd9b1680ae 934 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
bogdanm 86:04dd9b1680ae 935 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1 */
bogdanm 86:04dd9b1680ae 936 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2 */
bogdanm 86:04dd9b1680ae 937 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3 */
bogdanm 86:04dd9b1680ae 938 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4 */
bogdanm 86:04dd9b1680ae 939 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5 */
bogdanm 86:04dd9b1680ae 940 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6 */
bogdanm 86:04dd9b1680ae 941 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7 */
bogdanm 86:04dd9b1680ae 942 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8 */
bogdanm 86:04dd9b1680ae 943 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9 */
bogdanm 86:04dd9b1680ae 944 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10 */
bogdanm 86:04dd9b1680ae 945 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
bogdanm 86:04dd9b1680ae 946 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
bogdanm 86:04dd9b1680ae 947 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
bogdanm 86:04dd9b1680ae 948 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
bogdanm 86:04dd9b1680ae 949 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
bogdanm 86:04dd9b1680ae 950 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
bogdanm 86:04dd9b1680ae 951 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
bogdanm 86:04dd9b1680ae 952 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
bogdanm 86:04dd9b1680ae 953 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
bogdanm 86:04dd9b1680ae 954 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
bogdanm 86:04dd9b1680ae 955 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
bogdanm 86:04dd9b1680ae 956 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
bogdanm 86:04dd9b1680ae 957
bogdanm 86:04dd9b1680ae 958 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000)
bogdanm 86:04dd9b1680ae 959
bogdanm 86:04dd9b1680ae 960 /**
bogdanm 86:04dd9b1680ae 961 * @}
bogdanm 86:04dd9b1680ae 962 */
bogdanm 86:04dd9b1680ae 963
bogdanm 86:04dd9b1680ae 964 /** @defgroup HRTIM_Timer_Reset_Update
bogdanm 86:04dd9b1680ae 965 * @{
bogdanm 86:04dd9b1680ae 966 * @brief Constants defining whether the register are updated upon Timerx
bogdanm 86:04dd9b1680ae 967 * counter reset or roll-over to 0 after reaching the period value
bogdanm 86:04dd9b1680ae 968 * in continuous mode
bogdanm 86:04dd9b1680ae 969 */
bogdanm 86:04dd9b1680ae 970 #define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /*!< Update by timer x reset / roll-over disabled */
bogdanm 86:04dd9b1680ae 971 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */
bogdanm 86:04dd9b1680ae 972
bogdanm 86:04dd9b1680ae 973 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
bogdanm 86:04dd9b1680ae 974 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
bogdanm 86:04dd9b1680ae 975 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
bogdanm 86:04dd9b1680ae 976 /**
bogdanm 86:04dd9b1680ae 977 * @}
bogdanm 86:04dd9b1680ae 978 */
bogdanm 86:04dd9b1680ae 979
bogdanm 86:04dd9b1680ae 980 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode
bogdanm 86:04dd9b1680ae 981 * @{
bogdanm 86:04dd9b1680ae 982 * @brief Constants defining whether the compare register is behaving in
bogdanm 86:04dd9b1680ae 983 * regular mode (compare match issued as soon as counter equal compare),
bogdanm 86:04dd9b1680ae 984 * or in auto-delayed mode
bogdanm 86:04dd9b1680ae 985 */
bogdanm 86:04dd9b1680ae 986 #define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /*!< standard compare mode */
bogdanm 86:04dd9b1680ae 987 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occured */
bogdanm 86:04dd9b1680ae 988 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occured or after a Compare 1 match (timeout if capture event is missing) */
bogdanm 86:04dd9b1680ae 989 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occured or after a Compare 3 match (timeout if capture event is missing) */
bogdanm 86:04dd9b1680ae 990
bogdanm 86:04dd9b1680ae 991 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
bogdanm 86:04dd9b1680ae 992 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
bogdanm 86:04dd9b1680ae 993 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
bogdanm 86:04dd9b1680ae 994 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
bogdanm 86:04dd9b1680ae 995 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
bogdanm 86:04dd9b1680ae 996
bogdanm 86:04dd9b1680ae 997 /* Auto delayed mode is only available for compare units 2 and 4 */
bogdanm 86:04dd9b1680ae 998 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
bogdanm 86:04dd9b1680ae 999 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
bogdanm 86:04dd9b1680ae 1000 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
bogdanm 86:04dd9b1680ae 1001 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
bogdanm 86:04dd9b1680ae 1002 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
bogdanm 86:04dd9b1680ae 1003 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
bogdanm 86:04dd9b1680ae 1004 || \
bogdanm 86:04dd9b1680ae 1005 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
bogdanm 86:04dd9b1680ae 1006 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
bogdanm 86:04dd9b1680ae 1007 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
bogdanm 86:04dd9b1680ae 1008 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
bogdanm 86:04dd9b1680ae 1009 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
bogdanm 86:04dd9b1680ae 1010 /**
bogdanm 86:04dd9b1680ae 1011 * @}
bogdanm 86:04dd9b1680ae 1012 */
bogdanm 86:04dd9b1680ae 1013
bogdanm 86:04dd9b1680ae 1014 /** @defgroup HRTIM_Simple_OC_Mode
bogdanm 86:04dd9b1680ae 1015 * @{
bogdanm 86:04dd9b1680ae 1016 * @brief Constants defining the behavior of the output signal when the timer
bogdanm 86:04dd9b1680ae 1017 operates in basic output compare mode
bogdanm 86:04dd9b1680ae 1018 */
bogdanm 86:04dd9b1680ae 1019 #define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) /*!< Ouput toggles when the timer counter reaches the compare value */
bogdanm 86:04dd9b1680ae 1020 #define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) /*!< Ouput forced to active level when the timer counter reaches the compare value */
bogdanm 86:04dd9b1680ae 1021 #define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) /*!< Ouput forced to inactive level when the timer counter reaches the compare value */
bogdanm 86:04dd9b1680ae 1022
bogdanm 86:04dd9b1680ae 1023 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
bogdanm 86:04dd9b1680ae 1024 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
bogdanm 86:04dd9b1680ae 1025 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
bogdanm 86:04dd9b1680ae 1026 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
bogdanm 86:04dd9b1680ae 1027 /**
bogdanm 86:04dd9b1680ae 1028 * @}
bogdanm 86:04dd9b1680ae 1029 */
bogdanm 86:04dd9b1680ae 1030
bogdanm 86:04dd9b1680ae 1031 /** @defgroup HRTIM_Output_Polarity
bogdanm 86:04dd9b1680ae 1032 * @{
bogdanm 86:04dd9b1680ae 1033 * @brief Constants defining the polarity of a timer output
bogdanm 86:04dd9b1680ae 1034 */
bogdanm 86:04dd9b1680ae 1035 #define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< Output is acitve HIGH */
bogdanm 86:04dd9b1680ae 1036 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
bogdanm 86:04dd9b1680ae 1037
bogdanm 86:04dd9b1680ae 1038 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
bogdanm 86:04dd9b1680ae 1039 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
bogdanm 86:04dd9b1680ae 1040 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
bogdanm 86:04dd9b1680ae 1041 /**
bogdanm 86:04dd9b1680ae 1042 * @}
bogdanm 86:04dd9b1680ae 1043 */
bogdanm 86:04dd9b1680ae 1044
bogdanm 86:04dd9b1680ae 1045 /** @defgroup HRTIM_Output_Set_Source
bogdanm 86:04dd9b1680ae 1046 * @{
bogdanm 86:04dd9b1680ae 1047 * @brief Constants defining the events that can be selected to configure the
bogdanm 86:04dd9b1680ae 1048 * set crossbar of a timer output
bogdanm 86:04dd9b1680ae 1049 */
bogdanm 86:04dd9b1680ae 1050 #define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /*!< Reset the output set crossbar */
bogdanm 86:04dd9b1680ae 1051 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
bogdanm 86:04dd9b1680ae 1052 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1053 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1054 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1055 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1056 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1057 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1058 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1059 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1060 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1061 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1062 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1063 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1064 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1065 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1066 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1067 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1068 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1069 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1070 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1071 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1072 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1073 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1074 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1075 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1076 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1077 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1078 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1079 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1080 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
bogdanm 86:04dd9b1680ae 1081 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
bogdanm 86:04dd9b1680ae 1082
bogdanm 86:04dd9b1680ae 1083 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
bogdanm 86:04dd9b1680ae 1084 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
bogdanm 86:04dd9b1680ae 1085 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
bogdanm 86:04dd9b1680ae 1086 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
bogdanm 86:04dd9b1680ae 1087 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
bogdanm 86:04dd9b1680ae 1088 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
bogdanm 86:04dd9b1680ae 1089 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
bogdanm 86:04dd9b1680ae 1090 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
bogdanm 86:04dd9b1680ae 1091 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
bogdanm 86:04dd9b1680ae 1092 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
bogdanm 86:04dd9b1680ae 1093 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
bogdanm 86:04dd9b1680ae 1094 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
bogdanm 86:04dd9b1680ae 1095 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
bogdanm 86:04dd9b1680ae 1096 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
bogdanm 86:04dd9b1680ae 1097 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
bogdanm 86:04dd9b1680ae 1098 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
bogdanm 86:04dd9b1680ae 1099 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
bogdanm 86:04dd9b1680ae 1100 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
bogdanm 86:04dd9b1680ae 1101 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
bogdanm 86:04dd9b1680ae 1102 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
bogdanm 86:04dd9b1680ae 1103 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
bogdanm 86:04dd9b1680ae 1104 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
bogdanm 86:04dd9b1680ae 1105 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
bogdanm 86:04dd9b1680ae 1106 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
bogdanm 86:04dd9b1680ae 1107 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
bogdanm 86:04dd9b1680ae 1108 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
bogdanm 86:04dd9b1680ae 1109 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
bogdanm 86:04dd9b1680ae 1110 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
bogdanm 86:04dd9b1680ae 1111 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
bogdanm 86:04dd9b1680ae 1112 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
bogdanm 86:04dd9b1680ae 1113 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
bogdanm 86:04dd9b1680ae 1114 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
bogdanm 86:04dd9b1680ae 1115 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
bogdanm 86:04dd9b1680ae 1116 /**
bogdanm 86:04dd9b1680ae 1117 * @}
bogdanm 86:04dd9b1680ae 1118 */
bogdanm 86:04dd9b1680ae 1119
bogdanm 86:04dd9b1680ae 1120 /** @defgroup HRTIM_Output_Reset_Source
bogdanm 86:04dd9b1680ae 1121 * @{
bogdanm 86:04dd9b1680ae 1122 * @brief Constants defining the events that can be selected to configure the
bogdanm 86:04dd9b1680ae 1123 * set crossbar of a timer output
bogdanm 86:04dd9b1680ae 1124 */
bogdanm 86:04dd9b1680ae 1125 #define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /*!< Reset the output reset crossbar */
bogdanm 86:04dd9b1680ae 1126 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1127 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1128 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1129 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1130 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1131 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1132 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1133 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1134 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1135 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1136 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1137 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1138 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1139 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1140 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1141 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1142 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1143 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1144 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1145 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1146 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1147 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1148 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1149 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1150 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1151 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1152 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1153 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1154 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1155 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1156 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 1157
bogdanm 86:04dd9b1680ae 1158 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
bogdanm 86:04dd9b1680ae 1159 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
bogdanm 86:04dd9b1680ae 1160 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
bogdanm 86:04dd9b1680ae 1161 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
bogdanm 86:04dd9b1680ae 1162 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
bogdanm 86:04dd9b1680ae 1163 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
bogdanm 86:04dd9b1680ae 1164 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
bogdanm 86:04dd9b1680ae 1165 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
bogdanm 86:04dd9b1680ae 1166 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
bogdanm 86:04dd9b1680ae 1167 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
bogdanm 86:04dd9b1680ae 1168 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
bogdanm 86:04dd9b1680ae 1169 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
bogdanm 86:04dd9b1680ae 1170 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
bogdanm 86:04dd9b1680ae 1171 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
bogdanm 86:04dd9b1680ae 1172 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
bogdanm 86:04dd9b1680ae 1173 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
bogdanm 86:04dd9b1680ae 1174 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
bogdanm 86:04dd9b1680ae 1175 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
bogdanm 86:04dd9b1680ae 1176 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
bogdanm 86:04dd9b1680ae 1177 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
bogdanm 86:04dd9b1680ae 1178 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
bogdanm 86:04dd9b1680ae 1179 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
bogdanm 86:04dd9b1680ae 1180 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
bogdanm 86:04dd9b1680ae 1181 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
bogdanm 86:04dd9b1680ae 1182 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
bogdanm 86:04dd9b1680ae 1183 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
bogdanm 86:04dd9b1680ae 1184 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
bogdanm 86:04dd9b1680ae 1185 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
bogdanm 86:04dd9b1680ae 1186 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
bogdanm 86:04dd9b1680ae 1187 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
bogdanm 86:04dd9b1680ae 1188 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
bogdanm 86:04dd9b1680ae 1189 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
bogdanm 86:04dd9b1680ae 1190 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
bogdanm 86:04dd9b1680ae 1191 /**
bogdanm 86:04dd9b1680ae 1192 * @}
bogdanm 86:04dd9b1680ae 1193 */
bogdanm 86:04dd9b1680ae 1194
bogdanm 86:04dd9b1680ae 1195 /** @defgroup HRTIM_Output_Idle_Mode
bogdanm 86:04dd9b1680ae 1196 * @{
bogdanm 86:04dd9b1680ae 1197 * @brief Constants defining whether or not the timer output transition to its
bogdanm 86:04dd9b1680ae 1198 IDLE state when burst mode is entered
bogdanm 86:04dd9b1680ae 1199 */
bogdanm 86:04dd9b1680ae 1200 #define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the burst mode operation */
bogdanm 86:04dd9b1680ae 1201 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
bogdanm 86:04dd9b1680ae 1202
bogdanm 86:04dd9b1680ae 1203 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
bogdanm 86:04dd9b1680ae 1204 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
bogdanm 86:04dd9b1680ae 1205 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
bogdanm 86:04dd9b1680ae 1206 /**
bogdanm 86:04dd9b1680ae 1207 * @}
bogdanm 86:04dd9b1680ae 1208 */
bogdanm 86:04dd9b1680ae 1209
bogdanm 86:04dd9b1680ae 1210 /** @defgroup HRTIM_Output_IDLE_Level
bogdanm 86:04dd9b1680ae 1211 * @{
bogdanm 86:04dd9b1680ae 1212 * @brief Constants defining the output level when output is in IDLE state
bogdanm 86:04dd9b1680ae 1213 */
bogdanm 86:04dd9b1680ae 1214 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE (uint32_t)0x00000000 /*!< Output at inactive level when in IDLE state */
bogdanm 86:04dd9b1680ae 1215 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
bogdanm 86:04dd9b1680ae 1216
bogdanm 86:04dd9b1680ae 1217 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
bogdanm 86:04dd9b1680ae 1218 (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
bogdanm 86:04dd9b1680ae 1219 ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
bogdanm 86:04dd9b1680ae 1220 /**
bogdanm 86:04dd9b1680ae 1221 * @}
bogdanm 86:04dd9b1680ae 1222 */
bogdanm 86:04dd9b1680ae 1223
bogdanm 86:04dd9b1680ae 1224 /** @defgroup HRTIM_Output_FAULT_Level
bogdanm 86:04dd9b1680ae 1225 * @{
bogdanm 86:04dd9b1680ae 1226 * @brief Constants defining the output level when output is in FAULT state
bogdanm 86:04dd9b1680ae 1227 */
bogdanm 86:04dd9b1680ae 1228 #define HRTIM_OUTPUTFAULTLEVEL_NONE (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
bogdanm 86:04dd9b1680ae 1229 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
bogdanm 86:04dd9b1680ae 1230 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
bogdanm 86:04dd9b1680ae 1231 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
bogdanm 86:04dd9b1680ae 1232
bogdanm 86:04dd9b1680ae 1233 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
bogdanm 86:04dd9b1680ae 1234 (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \
bogdanm 86:04dd9b1680ae 1235 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \
bogdanm 86:04dd9b1680ae 1236 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
bogdanm 86:04dd9b1680ae 1237 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
bogdanm 86:04dd9b1680ae 1238 /**
bogdanm 86:04dd9b1680ae 1239 * @}
bogdanm 86:04dd9b1680ae 1240 */
bogdanm 86:04dd9b1680ae 1241
bogdanm 86:04dd9b1680ae 1242 /** @defgroup HRTIM_Output_Chopper_Mode_Enable
bogdanm 86:04dd9b1680ae 1243 * @{
bogdanm 86:04dd9b1680ae 1244 * @brief Constants defining whether or not chopper mode is enabled for a timer
bogdanm 86:04dd9b1680ae 1245 output
bogdanm 86:04dd9b1680ae 1246 */
bogdanm 86:04dd9b1680ae 1247 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
bogdanm 86:04dd9b1680ae 1248 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output at active level when in FAULT state */
bogdanm 86:04dd9b1680ae 1249
bogdanm 86:04dd9b1680ae 1250 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
bogdanm 86:04dd9b1680ae 1251 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
bogdanm 86:04dd9b1680ae 1252 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
bogdanm 86:04dd9b1680ae 1253 /**
bogdanm 86:04dd9b1680ae 1254 * @}
bogdanm 86:04dd9b1680ae 1255 */
bogdanm 86:04dd9b1680ae 1256
bogdanm 86:04dd9b1680ae 1257 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed
bogdanm 86:04dd9b1680ae 1258 * @{
bogdanm 86:04dd9b1680ae 1259 * @brief Constants defining the idle mode entry is delayed by forcing a
bogdanm 86:04dd9b1680ae 1260 deadtime insertion before switching the outputs to their idle state
bogdanm 86:04dd9b1680ae 1261 */
bogdanm 86:04dd9b1680ae 1262 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /*!< The programmed Idle state is applied immediately to the Output */
bogdanm 86:04dd9b1680ae 1263 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
bogdanm 86:04dd9b1680ae 1264
bogdanm 86:04dd9b1680ae 1265 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
bogdanm 86:04dd9b1680ae 1266 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
bogdanm 86:04dd9b1680ae 1267 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
bogdanm 86:04dd9b1680ae 1268 /**
bogdanm 86:04dd9b1680ae 1269 * @}
bogdanm 86:04dd9b1680ae 1270 */
bogdanm 86:04dd9b1680ae 1271
bogdanm 86:04dd9b1680ae 1272 /** @defgroup HRTIM_Capture_Unit_Trigger
bogdanm 86:04dd9b1680ae 1273 * @{
bogdanm 86:04dd9b1680ae 1274 * @brief Constants defining the events that can be selected to trigger the
bogdanm 86:04dd9b1680ae 1275 * capture of the timing unit counter
bogdanm 86:04dd9b1680ae 1276 */
bogdanm 86:04dd9b1680ae 1277 #define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /*!< Capture trigger is disabled */
bogdanm 86:04dd9b1680ae 1278 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
bogdanm 86:04dd9b1680ae 1279 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
bogdanm 86:04dd9b1680ae 1280 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
bogdanm 86:04dd9b1680ae 1281 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
bogdanm 86:04dd9b1680ae 1282 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
bogdanm 86:04dd9b1680ae 1283 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
bogdanm 86:04dd9b1680ae 1284 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
bogdanm 86:04dd9b1680ae 1285 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
bogdanm 86:04dd9b1680ae 1286 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
bogdanm 86:04dd9b1680ae 1287 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
bogdanm 86:04dd9b1680ae 1288 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
bogdanm 86:04dd9b1680ae 1289 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
bogdanm 86:04dd9b1680ae 1290 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
bogdanm 86:04dd9b1680ae 1291 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */
bogdanm 86:04dd9b1680ae 1292 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */
bogdanm 86:04dd9b1680ae 1293 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
bogdanm 86:04dd9b1680ae 1294 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
bogdanm 86:04dd9b1680ae 1295 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */
bogdanm 86:04dd9b1680ae 1296 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */
bogdanm 86:04dd9b1680ae 1297 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
bogdanm 86:04dd9b1680ae 1298 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
bogdanm 86:04dd9b1680ae 1299 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */
bogdanm 86:04dd9b1680ae 1300 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */
bogdanm 86:04dd9b1680ae 1301 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
bogdanm 86:04dd9b1680ae 1302 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
bogdanm 86:04dd9b1680ae 1303 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */
bogdanm 86:04dd9b1680ae 1304 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */
bogdanm 86:04dd9b1680ae 1305 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
bogdanm 86:04dd9b1680ae 1306 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
bogdanm 86:04dd9b1680ae 1307 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */
bogdanm 86:04dd9b1680ae 1308 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */
bogdanm 86:04dd9b1680ae 1309
bogdanm 86:04dd9b1680ae 1310 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
bogdanm 86:04dd9b1680ae 1311 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
bogdanm 86:04dd9b1680ae 1312 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
bogdanm 86:04dd9b1680ae 1313 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
bogdanm 86:04dd9b1680ae 1314 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
bogdanm 86:04dd9b1680ae 1315 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
bogdanm 86:04dd9b1680ae 1316 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
bogdanm 86:04dd9b1680ae 1317 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
bogdanm 86:04dd9b1680ae 1318 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
bogdanm 86:04dd9b1680ae 1319 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
bogdanm 86:04dd9b1680ae 1320 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
bogdanm 86:04dd9b1680ae 1321 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
bogdanm 86:04dd9b1680ae 1322 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
bogdanm 86:04dd9b1680ae 1323 || \
bogdanm 86:04dd9b1680ae 1324 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
bogdanm 86:04dd9b1680ae 1325 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
bogdanm 86:04dd9b1680ae 1326 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
bogdanm 86:04dd9b1680ae 1327 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
bogdanm 86:04dd9b1680ae 1328 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
bogdanm 86:04dd9b1680ae 1329 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
bogdanm 86:04dd9b1680ae 1330 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
bogdanm 86:04dd9b1680ae 1331 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
bogdanm 86:04dd9b1680ae 1332 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
bogdanm 86:04dd9b1680ae 1333 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
bogdanm 86:04dd9b1680ae 1334 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
bogdanm 86:04dd9b1680ae 1335 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
bogdanm 86:04dd9b1680ae 1336 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
bogdanm 86:04dd9b1680ae 1337 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
bogdanm 86:04dd9b1680ae 1338 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
bogdanm 86:04dd9b1680ae 1339 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
bogdanm 86:04dd9b1680ae 1340 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
bogdanm 86:04dd9b1680ae 1341 || \
bogdanm 86:04dd9b1680ae 1342 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
bogdanm 86:04dd9b1680ae 1343 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
bogdanm 86:04dd9b1680ae 1344 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
bogdanm 86:04dd9b1680ae 1345 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
bogdanm 86:04dd9b1680ae 1346 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
bogdanm 86:04dd9b1680ae 1347 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
bogdanm 86:04dd9b1680ae 1348 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
bogdanm 86:04dd9b1680ae 1349 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
bogdanm 86:04dd9b1680ae 1350 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
bogdanm 86:04dd9b1680ae 1351 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
bogdanm 86:04dd9b1680ae 1352 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
bogdanm 86:04dd9b1680ae 1353 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
bogdanm 86:04dd9b1680ae 1354 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
bogdanm 86:04dd9b1680ae 1355 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
bogdanm 86:04dd9b1680ae 1356 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
bogdanm 86:04dd9b1680ae 1357 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
bogdanm 86:04dd9b1680ae 1358 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
bogdanm 86:04dd9b1680ae 1359 || \
bogdanm 86:04dd9b1680ae 1360 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
bogdanm 86:04dd9b1680ae 1361 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
bogdanm 86:04dd9b1680ae 1362 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
bogdanm 86:04dd9b1680ae 1363 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
bogdanm 86:04dd9b1680ae 1364 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
bogdanm 86:04dd9b1680ae 1365 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
bogdanm 86:04dd9b1680ae 1366 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
bogdanm 86:04dd9b1680ae 1367 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
bogdanm 86:04dd9b1680ae 1368 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
bogdanm 86:04dd9b1680ae 1369 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
bogdanm 86:04dd9b1680ae 1370 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
bogdanm 86:04dd9b1680ae 1371 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
bogdanm 86:04dd9b1680ae 1372 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
bogdanm 86:04dd9b1680ae 1373 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
bogdanm 86:04dd9b1680ae 1374 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
bogdanm 86:04dd9b1680ae 1375 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
bogdanm 86:04dd9b1680ae 1376 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
bogdanm 86:04dd9b1680ae 1377 || \
bogdanm 86:04dd9b1680ae 1378 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
bogdanm 86:04dd9b1680ae 1379 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
bogdanm 86:04dd9b1680ae 1380 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
bogdanm 86:04dd9b1680ae 1381 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
bogdanm 86:04dd9b1680ae 1382 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
bogdanm 86:04dd9b1680ae 1383 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
bogdanm 86:04dd9b1680ae 1384 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
bogdanm 86:04dd9b1680ae 1385 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
bogdanm 86:04dd9b1680ae 1386 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
bogdanm 86:04dd9b1680ae 1387 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
bogdanm 86:04dd9b1680ae 1388 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
bogdanm 86:04dd9b1680ae 1389 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
bogdanm 86:04dd9b1680ae 1390 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
bogdanm 86:04dd9b1680ae 1391 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
bogdanm 86:04dd9b1680ae 1392 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
bogdanm 86:04dd9b1680ae 1393 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
bogdanm 86:04dd9b1680ae 1394 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
bogdanm 86:04dd9b1680ae 1395 || \
bogdanm 86:04dd9b1680ae 1396 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
bogdanm 86:04dd9b1680ae 1397 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
bogdanm 86:04dd9b1680ae 1398 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
bogdanm 86:04dd9b1680ae 1399 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
bogdanm 86:04dd9b1680ae 1400 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
bogdanm 86:04dd9b1680ae 1401 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
bogdanm 86:04dd9b1680ae 1402 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
bogdanm 86:04dd9b1680ae 1403 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
bogdanm 86:04dd9b1680ae 1404 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
bogdanm 86:04dd9b1680ae 1405 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
bogdanm 86:04dd9b1680ae 1406 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
bogdanm 86:04dd9b1680ae 1407 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
bogdanm 86:04dd9b1680ae 1408 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
bogdanm 86:04dd9b1680ae 1409 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
bogdanm 86:04dd9b1680ae 1410 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
bogdanm 86:04dd9b1680ae 1411 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
bogdanm 86:04dd9b1680ae 1412 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
bogdanm 86:04dd9b1680ae 1413 /**
bogdanm 86:04dd9b1680ae 1414 * @}
bogdanm 86:04dd9b1680ae 1415 */
bogdanm 86:04dd9b1680ae 1416
bogdanm 86:04dd9b1680ae 1417 /** @defgroup HRTIM_Timer_External_Event_Filter
bogdanm 86:04dd9b1680ae 1418 * @{
bogdanm 86:04dd9b1680ae 1419 * @brief Constants defining the event filtering apploed to external events
bogdanm 86:04dd9b1680ae 1420 * by a timer
bogdanm 86:04dd9b1680ae 1421 */
bogdanm 86:04dd9b1680ae 1422 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
bogdanm 86:04dd9b1680ae 1423 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
bogdanm 86:04dd9b1680ae 1424 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
bogdanm 86:04dd9b1680ae 1425 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
bogdanm 86:04dd9b1680ae 1426 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
bogdanm 86:04dd9b1680ae 1427 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
bogdanm 86:04dd9b1680ae 1428 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
bogdanm 86:04dd9b1680ae 1429 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
bogdanm 86:04dd9b1680ae 1430 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
bogdanm 86:04dd9b1680ae 1431 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
bogdanm 86:04dd9b1680ae 1432 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
bogdanm 86:04dd9b1680ae 1433 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
bogdanm 86:04dd9b1680ae 1434 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
bogdanm 86:04dd9b1680ae 1435 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
bogdanm 86:04dd9b1680ae 1436 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
bogdanm 86:04dd9b1680ae 1437 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
bogdanm 86:04dd9b1680ae 1438
bogdanm 86:04dd9b1680ae 1439 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
bogdanm 86:04dd9b1680ae 1440 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
bogdanm 86:04dd9b1680ae 1441 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
bogdanm 86:04dd9b1680ae 1442 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
bogdanm 86:04dd9b1680ae 1443 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
bogdanm 86:04dd9b1680ae 1444 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
bogdanm 86:04dd9b1680ae 1445 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
bogdanm 86:04dd9b1680ae 1446 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
bogdanm 86:04dd9b1680ae 1447 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
bogdanm 86:04dd9b1680ae 1448 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
bogdanm 86:04dd9b1680ae 1449 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
bogdanm 86:04dd9b1680ae 1450 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
bogdanm 86:04dd9b1680ae 1451 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
bogdanm 86:04dd9b1680ae 1452 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
bogdanm 86:04dd9b1680ae 1453 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
bogdanm 86:04dd9b1680ae 1454 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
bogdanm 86:04dd9b1680ae 1455 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
bogdanm 86:04dd9b1680ae 1456 /**
bogdanm 86:04dd9b1680ae 1457 * @}
bogdanm 86:04dd9b1680ae 1458 */
bogdanm 86:04dd9b1680ae 1459
bogdanm 86:04dd9b1680ae 1460 /** @defgroup HRTIM_Timer_External_Event_Latch
bogdanm 86:04dd9b1680ae 1461 * @{
bogdanm 86:04dd9b1680ae 1462 * @brief Constants defining whether or not the external event is
bogdanm 86:04dd9b1680ae 1463 * memorized (latched) and generated as soon as the blanking period
bogdanm 86:04dd9b1680ae 1464 * is completed or the window ends
bogdanm 86:04dd9b1680ae 1465 */
bogdanm 86:04dd9b1680ae 1466 #define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /*!< Event is ignored if it happens during a blank, or passed through during a window */
bogdanm 86:04dd9b1680ae 1467 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
bogdanm 86:04dd9b1680ae 1468
bogdanm 86:04dd9b1680ae 1469 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
bogdanm 86:04dd9b1680ae 1470 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
bogdanm 86:04dd9b1680ae 1471 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
bogdanm 86:04dd9b1680ae 1472 /**
bogdanm 86:04dd9b1680ae 1473 * @}
bogdanm 86:04dd9b1680ae 1474 */
bogdanm 86:04dd9b1680ae 1475
bogdanm 86:04dd9b1680ae 1476 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio
bogdanm 86:04dd9b1680ae 1477 * @{
bogdanm 86:04dd9b1680ae 1478 * @brief Constants defining division ratio between the timer clock frequency
bogdanm 86:04dd9b1680ae 1479 * (fHRTIM) and the deadtime generator clock (fDTG)
bogdanm 86:04dd9b1680ae 1480 */
bogdanm 86:04dd9b1680ae 1481 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 ((uint32_t)0x00000000) /*!< fDTG = fHRTIM * 8 */
bogdanm 86:04dd9b1680ae 1482 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
bogdanm 86:04dd9b1680ae 1483 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
bogdanm 86:04dd9b1680ae 1484 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
bogdanm 86:04dd9b1680ae 1485 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
bogdanm 86:04dd9b1680ae 1486 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
bogdanm 86:04dd9b1680ae 1487 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
bogdanm 86:04dd9b1680ae 1488 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1489
bogdanm 86:04dd9b1680ae 1490 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
bogdanm 86:04dd9b1680ae 1491 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
bogdanm 86:04dd9b1680ae 1492 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
bogdanm 86:04dd9b1680ae 1493 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
bogdanm 86:04dd9b1680ae 1494 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
bogdanm 86:04dd9b1680ae 1495 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
bogdanm 86:04dd9b1680ae 1496 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
bogdanm 86:04dd9b1680ae 1497 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
bogdanm 86:04dd9b1680ae 1498 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
bogdanm 86:04dd9b1680ae 1499 /**
bogdanm 86:04dd9b1680ae 1500 * @}
bogdanm 86:04dd9b1680ae 1501 */
bogdanm 86:04dd9b1680ae 1502
bogdanm 86:04dd9b1680ae 1503 /** @defgroup HRTIM_Deadtime_Rising_Sign
bogdanm 86:04dd9b1680ae 1504 * @{
bogdanm 86:04dd9b1680ae 1505 * @brief Constants defining whether the deadtime is positive or negative
bogdanm 86:04dd9b1680ae 1506 * (overlapping signal) on rising edge
bogdanm 86:04dd9b1680ae 1507 */
bogdanm 86:04dd9b1680ae 1508 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on rising edge */
bogdanm 86:04dd9b1680ae 1509 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
bogdanm 86:04dd9b1680ae 1510
bogdanm 86:04dd9b1680ae 1511 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
bogdanm 86:04dd9b1680ae 1512 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
bogdanm 86:04dd9b1680ae 1513 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
bogdanm 86:04dd9b1680ae 1514 /**
bogdanm 86:04dd9b1680ae 1515 * @}
bogdanm 86:04dd9b1680ae 1516 */
bogdanm 86:04dd9b1680ae 1517
bogdanm 86:04dd9b1680ae 1518 /** @defgroup HRTIM_Deadtime_Rising_Lock
bogdanm 86:04dd9b1680ae 1519 * @{
bogdanm 86:04dd9b1680ae 1520 * @brief Constants defining whether or not the deadtime (rising sign and
bogdanm 86:04dd9b1680ae 1521 * value) is write protected
bogdanm 86:04dd9b1680ae 1522 */
bogdanm 86:04dd9b1680ae 1523 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising value and sign is writable */
bogdanm 86:04dd9b1680ae 1524 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
bogdanm 86:04dd9b1680ae 1525
bogdanm 86:04dd9b1680ae 1526 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
bogdanm 86:04dd9b1680ae 1527 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
bogdanm 86:04dd9b1680ae 1528 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
bogdanm 86:04dd9b1680ae 1529 /**
bogdanm 86:04dd9b1680ae 1530 * @}
bogdanm 86:04dd9b1680ae 1531 */
bogdanm 86:04dd9b1680ae 1532
bogdanm 86:04dd9b1680ae 1533 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock
bogdanm 86:04dd9b1680ae 1534 * @{
bogdanm 86:04dd9b1680ae 1535 * @brief Constants defining whether or not the deadtime rising sign is write
bogdanm 86:04dd9b1680ae 1536 * protected
bogdanm 86:04dd9b1680ae 1537 */
bogdanm 86:04dd9b1680ae 1538 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising sign is writable */
bogdanm 86:04dd9b1680ae 1539 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
bogdanm 86:04dd9b1680ae 1540
bogdanm 86:04dd9b1680ae 1541 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
bogdanm 86:04dd9b1680ae 1542 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
bogdanm 86:04dd9b1680ae 1543 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
bogdanm 86:04dd9b1680ae 1544 /**
bogdanm 86:04dd9b1680ae 1545 * @}
bogdanm 86:04dd9b1680ae 1546 */
bogdanm 86:04dd9b1680ae 1547
bogdanm 86:04dd9b1680ae 1548 /** @defgroup HRTIM_Deadtime_Falling_Sign
bogdanm 86:04dd9b1680ae 1549 * @{
bogdanm 86:04dd9b1680ae 1550 * @brief Constants defining whether the deadtime is positive or negative
bogdanm 86:04dd9b1680ae 1551 * (overlapping signal) on falling edge
bogdanm 86:04dd9b1680ae 1552 */
bogdanm 86:04dd9b1680ae 1553 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on falling edge */
bogdanm 86:04dd9b1680ae 1554 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
bogdanm 86:04dd9b1680ae 1555
bogdanm 86:04dd9b1680ae 1556 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
bogdanm 86:04dd9b1680ae 1557 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
bogdanm 86:04dd9b1680ae 1558 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
bogdanm 86:04dd9b1680ae 1559 /**
bogdanm 86:04dd9b1680ae 1560 * @}
bogdanm 86:04dd9b1680ae 1561 */
bogdanm 86:04dd9b1680ae 1562
bogdanm 86:04dd9b1680ae 1563 /** @defgroup HRTIM_Deadtime_Falling_Lock
bogdanm 86:04dd9b1680ae 1564 * @{
bogdanm 86:04dd9b1680ae 1565 * @brief Constants defining whether or not the deadtime (falling sign and
bogdanm 86:04dd9b1680ae 1566 * value) is write protected
bogdanm 86:04dd9b1680ae 1567 */
bogdanm 86:04dd9b1680ae 1568 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling value and sign is writable */
bogdanm 86:04dd9b1680ae 1569 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
bogdanm 86:04dd9b1680ae 1570
bogdanm 86:04dd9b1680ae 1571 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
bogdanm 86:04dd9b1680ae 1572 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
bogdanm 86:04dd9b1680ae 1573 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
bogdanm 86:04dd9b1680ae 1574 /**
bogdanm 86:04dd9b1680ae 1575 * @}
bogdanm 86:04dd9b1680ae 1576 */
bogdanm 86:04dd9b1680ae 1577
bogdanm 86:04dd9b1680ae 1578 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock
bogdanm 86:04dd9b1680ae 1579 * @{
bogdanm 86:04dd9b1680ae 1580 * @brief Constants defining whether or not the deadtime falling sign is write
bogdanm 86:04dd9b1680ae 1581 * protected
bogdanm 86:04dd9b1680ae 1582 */
bogdanm 86:04dd9b1680ae 1583 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling sign is writable */
bogdanm 86:04dd9b1680ae 1584 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
bogdanm 86:04dd9b1680ae 1585
bogdanm 86:04dd9b1680ae 1586 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
bogdanm 86:04dd9b1680ae 1587 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
bogdanm 86:04dd9b1680ae 1588 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
bogdanm 86:04dd9b1680ae 1589 /**
bogdanm 86:04dd9b1680ae 1590 * @}
bogdanm 86:04dd9b1680ae 1591 */
bogdanm 86:04dd9b1680ae 1592
bogdanm 86:04dd9b1680ae 1593 /** @defgroup HRTIM_Chopper_Frequency
bogdanm 86:04dd9b1680ae 1594 * @{
bogdanm 86:04dd9b1680ae 1595 * @brief Constants defining the frequency of the generated high frequency carrier
bogdanm 86:04dd9b1680ae 1596 */
bogdanm 86:04dd9b1680ae 1597 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 ((uint32_t)0x000000) /*!< fCHPFRQ = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1598 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
bogdanm 86:04dd9b1680ae 1599 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
bogdanm 86:04dd9b1680ae 1600 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
bogdanm 86:04dd9b1680ae 1601 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
bogdanm 86:04dd9b1680ae 1602 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
bogdanm 86:04dd9b1680ae 1603 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
bogdanm 86:04dd9b1680ae 1604 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
bogdanm 86:04dd9b1680ae 1605 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
bogdanm 86:04dd9b1680ae 1606 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
bogdanm 86:04dd9b1680ae 1607 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
bogdanm 86:04dd9b1680ae 1608 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
bogdanm 86:04dd9b1680ae 1609 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
bogdanm 86:04dd9b1680ae 1610 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
bogdanm 86:04dd9b1680ae 1611 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
bogdanm 86:04dd9b1680ae 1612 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
bogdanm 86:04dd9b1680ae 1613
bogdanm 86:04dd9b1680ae 1614 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
bogdanm 86:04dd9b1680ae 1615 (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \
bogdanm 86:04dd9b1680ae 1616 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \
bogdanm 86:04dd9b1680ae 1617 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \
bogdanm 86:04dd9b1680ae 1618 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \
bogdanm 86:04dd9b1680ae 1619 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \
bogdanm 86:04dd9b1680ae 1620 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \
bogdanm 86:04dd9b1680ae 1621 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \
bogdanm 86:04dd9b1680ae 1622 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \
bogdanm 86:04dd9b1680ae 1623 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \
bogdanm 86:04dd9b1680ae 1624 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \
bogdanm 86:04dd9b1680ae 1625 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \
bogdanm 86:04dd9b1680ae 1626 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \
bogdanm 86:04dd9b1680ae 1627 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \
bogdanm 86:04dd9b1680ae 1628 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \
bogdanm 86:04dd9b1680ae 1629 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \
bogdanm 86:04dd9b1680ae 1630 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
bogdanm 86:04dd9b1680ae 1631 /**
bogdanm 86:04dd9b1680ae 1632 * @}
bogdanm 86:04dd9b1680ae 1633 */
bogdanm 86:04dd9b1680ae 1634
bogdanm 86:04dd9b1680ae 1635 /** @defgroup HRTIM_Chopper_Duty_Cycle
bogdanm 86:04dd9b1680ae 1636 * @{
bogdanm 86:04dd9b1680ae 1637 * @brief Constants defining the duty cycle of the generated high frequency carrier
bogdanm 86:04dd9b1680ae 1638 * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
bogdanm 86:04dd9b1680ae 1639 */
bogdanm 86:04dd9b1680ae 1640 #define HRTIM_CHOPPER_DUTYCYCLE_0 ((uint32_t)0x000000) /*!< 0/8 (i.e. only 1st pulse is present) */ /*!< fCHPFRQ = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1641 #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< 1/8 (12.5 %)*/ /*!< fCHPFRQ = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1642 #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< 2/8 (25 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1643 #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< 3/8 (37.5 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1644 #define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< 4/8 (50 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1645 #define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< 5/8 (62.5 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1646 #define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< 6/8 (75 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1647 #define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< 7/8 (87.5 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
bogdanm 86:04dd9b1680ae 1648
bogdanm 86:04dd9b1680ae 1649 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
bogdanm 86:04dd9b1680ae 1650 (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \
bogdanm 86:04dd9b1680ae 1651 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \
bogdanm 86:04dd9b1680ae 1652 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \
bogdanm 86:04dd9b1680ae 1653 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \
bogdanm 86:04dd9b1680ae 1654 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \
bogdanm 86:04dd9b1680ae 1655 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \
bogdanm 86:04dd9b1680ae 1656 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \
bogdanm 86:04dd9b1680ae 1657 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
bogdanm 86:04dd9b1680ae 1658 /**
bogdanm 86:04dd9b1680ae 1659 * @}
bogdanm 86:04dd9b1680ae 1660 */
bogdanm 86:04dd9b1680ae 1661
bogdanm 86:04dd9b1680ae 1662 /** @defgroup HRTIM_Chopper_Start_Pulse_Width
bogdanm 86:04dd9b1680ae 1663 * @{
bogdanm 86:04dd9b1680ae 1664 * @brief Constants defining the pulse width of the first pulse of the generated
bogdanm 86:04dd9b1680ae 1665 * high frequency carrier
bogdanm 86:04dd9b1680ae 1666 */
bogdanm 86:04dd9b1680ae 1667 #define HRTIM_CHOPPER_PULSEWIDTH_16 ((uint32_t)0x000000) /*!< tSTPW = tHRTIM x 16 */
bogdanm 86:04dd9b1680ae 1668 #define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
bogdanm 86:04dd9b1680ae 1669 #define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
bogdanm 86:04dd9b1680ae 1670 #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
bogdanm 86:04dd9b1680ae 1671 #define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
bogdanm 86:04dd9b1680ae 1672 #define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
bogdanm 86:04dd9b1680ae 1673 #define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
bogdanm 86:04dd9b1680ae 1674 #define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
bogdanm 86:04dd9b1680ae 1675 #define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
bogdanm 86:04dd9b1680ae 1676 #define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
bogdanm 86:04dd9b1680ae 1677 #define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
bogdanm 86:04dd9b1680ae 1678 #define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
bogdanm 86:04dd9b1680ae 1679 #define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
bogdanm 86:04dd9b1680ae 1680 #define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
bogdanm 86:04dd9b1680ae 1681 #define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
bogdanm 86:04dd9b1680ae 1682 #define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
bogdanm 86:04dd9b1680ae 1683
bogdanm 86:04dd9b1680ae 1684 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
bogdanm 86:04dd9b1680ae 1685 (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \
bogdanm 86:04dd9b1680ae 1686 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \
bogdanm 86:04dd9b1680ae 1687 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \
bogdanm 86:04dd9b1680ae 1688 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \
bogdanm 86:04dd9b1680ae 1689 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \
bogdanm 86:04dd9b1680ae 1690 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \
bogdanm 86:04dd9b1680ae 1691 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \
bogdanm 86:04dd9b1680ae 1692 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \
bogdanm 86:04dd9b1680ae 1693 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \
bogdanm 86:04dd9b1680ae 1694 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \
bogdanm 86:04dd9b1680ae 1695 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \
bogdanm 86:04dd9b1680ae 1696 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \
bogdanm 86:04dd9b1680ae 1697 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \
bogdanm 86:04dd9b1680ae 1698 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \
bogdanm 86:04dd9b1680ae 1699 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \
bogdanm 86:04dd9b1680ae 1700 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
bogdanm 86:04dd9b1680ae 1701 /**
bogdanm 86:04dd9b1680ae 1702 * @}
bogdanm 86:04dd9b1680ae 1703 */
bogdanm 86:04dd9b1680ae 1704
bogdanm 86:04dd9b1680ae 1705 /** @defgroup HRTIM_Synchronization_Options
bogdanm 86:04dd9b1680ae 1706 * @{
bogdanm 86:04dd9b1680ae 1707 * @brief Constants defining the options for synchronizing multiple HRTIM
bogdanm 86:04dd9b1680ae 1708 * instances, as a master unit (generating a synchronization signal)
bogdanm 86:04dd9b1680ae 1709 * or as a slave (waiting for a trigger to be synchronized)
bogdanm 86:04dd9b1680ae 1710 */
bogdanm 86:04dd9b1680ae 1711 #define HRTIM_SYNCOPTION_NONE (uint32_t)0x00000000 /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
bogdanm 86:04dd9b1680ae 1712 #define HRTIM_SYNCOPTION_MASTER (uint32_t)0x00000001 /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
bogdanm 86:04dd9b1680ae 1713 #define HRTIM_SYNCOPTION_SLAVE (uint32_t)0x00000002 /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
bogdanm 86:04dd9b1680ae 1714 /**
bogdanm 86:04dd9b1680ae 1715 * @}
bogdanm 86:04dd9b1680ae 1716 */
bogdanm 86:04dd9b1680ae 1717
bogdanm 86:04dd9b1680ae 1718 /** @defgroup HRTIM_Synchronization_Input_Source
bogdanm 86:04dd9b1680ae 1719 * @{
bogdanm 86:04dd9b1680ae 1720 * @brief Constants defining defining the synchronization input source
bogdanm 86:04dd9b1680ae 1721 */
bogdanm 86:04dd9b1680ae 1722 #define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
bogdanm 86:04dd9b1680ae 1723 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
bogdanm 86:04dd9b1680ae 1724 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
bogdanm 86:04dd9b1680ae 1725
bogdanm 86:04dd9b1680ae 1726 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
bogdanm 86:04dd9b1680ae 1727 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
bogdanm 86:04dd9b1680ae 1728 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
bogdanm 86:04dd9b1680ae 1729 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
bogdanm 86:04dd9b1680ae 1730 /**
bogdanm 86:04dd9b1680ae 1731 * @}
bogdanm 86:04dd9b1680ae 1732 */
bogdanm 86:04dd9b1680ae 1733
bogdanm 86:04dd9b1680ae 1734 /** @defgroup HRTIM_Synchronization_Output_Source
bogdanm 86:04dd9b1680ae 1735 * @{
bogdanm 86:04dd9b1680ae 1736 * @brief Constants defining the source and event to be sent on the
bogdanm 86:04dd9b1680ae 1737 * synchronization outputs
bogdanm 86:04dd9b1680ae 1738 */
bogdanm 86:04dd9b1680ae 1739 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer start event */
bogdanm 86:04dd9b1680ae 1740 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer compare 1 event*/
bogdanm 86:04dd9b1680ae 1741 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A start or reset events */
bogdanm 86:04dd9b1680ae 1742 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A compare 1 event */
bogdanm 86:04dd9b1680ae 1743
bogdanm 86:04dd9b1680ae 1744 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
bogdanm 86:04dd9b1680ae 1745 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
bogdanm 86:04dd9b1680ae 1746 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
bogdanm 86:04dd9b1680ae 1747 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
bogdanm 86:04dd9b1680ae 1748 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
bogdanm 86:04dd9b1680ae 1749 /**
bogdanm 86:04dd9b1680ae 1750 * @}
bogdanm 86:04dd9b1680ae 1751 */
bogdanm 86:04dd9b1680ae 1752
bogdanm 86:04dd9b1680ae 1753 /** @defgroup HRTIM_Synchronization_Output_Polarity
bogdanm 86:04dd9b1680ae 1754 * @{
bogdanm 86:04dd9b1680ae 1755 * @brief Constants defining the routing and conditioning of the synchronization output event
bogdanm 86:04dd9b1680ae 1756 */
bogdanm 86:04dd9b1680ae 1757 #define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /*!< Synchronization output event is disabled */
bogdanm 86:04dd9b1680ae 1758 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
bogdanm 86:04dd9b1680ae 1759 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
bogdanm 86:04dd9b1680ae 1760
bogdanm 86:04dd9b1680ae 1761 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
bogdanm 86:04dd9b1680ae 1762 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
bogdanm 86:04dd9b1680ae 1763 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
bogdanm 86:04dd9b1680ae 1764 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
bogdanm 86:04dd9b1680ae 1765 /**
bogdanm 86:04dd9b1680ae 1766 * @}
bogdanm 86:04dd9b1680ae 1767 */
bogdanm 86:04dd9b1680ae 1768
bogdanm 86:04dd9b1680ae 1769 /** @defgroup HRTIM_External_Event_Sources
bogdanm 86:04dd9b1680ae 1770 * @{
bogdanm 86:04dd9b1680ae 1771 * @brief Constants defining available sources associated to external events
bogdanm 86:04dd9b1680ae 1772 */
bogdanm 86:04dd9b1680ae 1773 #define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /*!< External event source 1 */
bogdanm 86:04dd9b1680ae 1774 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 */
bogdanm 86:04dd9b1680ae 1775 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 */
bogdanm 86:04dd9b1680ae 1776 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 */
bogdanm 86:04dd9b1680ae 1777
bogdanm 86:04dd9b1680ae 1778 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
bogdanm 86:04dd9b1680ae 1779 (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
bogdanm 86:04dd9b1680ae 1780 ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
bogdanm 86:04dd9b1680ae 1781 ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
bogdanm 86:04dd9b1680ae 1782 ((EVENTSRC) == HRTIM_EVENTSRC_4))
bogdanm 86:04dd9b1680ae 1783 /**
bogdanm 86:04dd9b1680ae 1784 * @}
bogdanm 86:04dd9b1680ae 1785 */
bogdanm 86:04dd9b1680ae 1786
bogdanm 86:04dd9b1680ae 1787 /** @defgroup HRTIM_External_Event_Polarity
bogdanm 86:04dd9b1680ae 1788 * @{
bogdanm 86:04dd9b1680ae 1789 * @brief Constants defining the polarity of an external event
bogdanm 86:04dd9b1680ae 1790 */
bogdanm 86:04dd9b1680ae 1791 #define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< External event is active high */
bogdanm 86:04dd9b1680ae 1792 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
bogdanm 86:04dd9b1680ae 1793
bogdanm 86:04dd9b1680ae 1794 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
bogdanm 86:04dd9b1680ae 1795 ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
bogdanm 86:04dd9b1680ae 1796 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
bogdanm 86:04dd9b1680ae 1797 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
bogdanm 86:04dd9b1680ae 1798 || \
bogdanm 86:04dd9b1680ae 1799 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
bogdanm 86:04dd9b1680ae 1800 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
bogdanm 86:04dd9b1680ae 1801 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
bogdanm 86:04dd9b1680ae 1802 /**
bogdanm 86:04dd9b1680ae 1803 * @}
bogdanm 86:04dd9b1680ae 1804 */
bogdanm 86:04dd9b1680ae 1805
bogdanm 86:04dd9b1680ae 1806 /** @defgroup HRTIM_External_Event_Sensitivity
bogdanm 86:04dd9b1680ae 1807 * @{
bogdanm 86:04dd9b1680ae 1808 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
bogdanm 86:04dd9b1680ae 1809 * of an external event
bogdanm 86:04dd9b1680ae 1810 */
bogdanm 86:04dd9b1680ae 1811 #define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /*!< External event is active on level */
bogdanm 86:04dd9b1680ae 1812 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
bogdanm 86:04dd9b1680ae 1813 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
bogdanm 86:04dd9b1680ae 1814 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
bogdanm 86:04dd9b1680ae 1815
bogdanm 86:04dd9b1680ae 1816 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
bogdanm 86:04dd9b1680ae 1817 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
bogdanm 86:04dd9b1680ae 1818 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
bogdanm 86:04dd9b1680ae 1819 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
bogdanm 86:04dd9b1680ae 1820 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
bogdanm 86:04dd9b1680ae 1821 /**
bogdanm 86:04dd9b1680ae 1822 * @}
bogdanm 86:04dd9b1680ae 1823 */
bogdanm 86:04dd9b1680ae 1824
bogdanm 86:04dd9b1680ae 1825 /** @defgroup HRTIM_External_Event_Fast_Mode
bogdanm 86:04dd9b1680ae 1826 * @{
bogdanm 86:04dd9b1680ae 1827 * @brief Constants defining whether or not an external event is programmed in
bogdanm 86:04dd9b1680ae 1828 fast mode
bogdanm 86:04dd9b1680ae 1829 */
bogdanm 86:04dd9b1680ae 1830 #define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /*!< External Event is acting asynchronously on outputs (low latency mode) */
bogdanm 86:04dd9b1680ae 1831 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
bogdanm 86:04dd9b1680ae 1832
bogdanm 86:04dd9b1680ae 1833 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
bogdanm 86:04dd9b1680ae 1834 (((((EVENT) == HRTIM_EVENT_1) || \
bogdanm 86:04dd9b1680ae 1835 ((EVENT) == HRTIM_EVENT_2) || \
bogdanm 86:04dd9b1680ae 1836 ((EVENT) == HRTIM_EVENT_3) || \
bogdanm 86:04dd9b1680ae 1837 ((EVENT) == HRTIM_EVENT_4) || \
bogdanm 86:04dd9b1680ae 1838 ((EVENT) == HRTIM_EVENT_5)) && \
bogdanm 86:04dd9b1680ae 1839 (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
bogdanm 86:04dd9b1680ae 1840 ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
bogdanm 86:04dd9b1680ae 1841 || \
bogdanm 86:04dd9b1680ae 1842 (((EVENT) == HRTIM_EVENT_6) || \
bogdanm 86:04dd9b1680ae 1843 ((EVENT) == HRTIM_EVENT_7) || \
bogdanm 86:04dd9b1680ae 1844 ((EVENT) == HRTIM_EVENT_8) || \
bogdanm 86:04dd9b1680ae 1845 ((EVENT) == HRTIM_EVENT_9) || \
bogdanm 86:04dd9b1680ae 1846 ((EVENT) == HRTIM_EVENT_10)))
bogdanm 86:04dd9b1680ae 1847
bogdanm 86:04dd9b1680ae 1848 /**
bogdanm 86:04dd9b1680ae 1849 * @}
bogdanm 86:04dd9b1680ae 1850 */
bogdanm 86:04dd9b1680ae 1851
bogdanm 86:04dd9b1680ae 1852 /** @defgroup HRTIM_External_Event_Filter
bogdanm 86:04dd9b1680ae 1853 * @{
bogdanm 86:04dd9b1680ae 1854 * @brief Constants defining the frequency used to sample an external event 6
bogdanm 86:04dd9b1680ae 1855 * input and the length (N) of the digital filter applied
bogdanm 86:04dd9b1680ae 1856 */
bogdanm 86:04dd9b1680ae 1857 #define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
bogdanm 86:04dd9b1680ae 1858 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2 */
bogdanm 86:04dd9b1680ae 1859 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4 */
bogdanm 86:04dd9b1680ae 1860 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8 */
bogdanm 86:04dd9b1680ae 1861 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2, N=6 */
bogdanm 86:04dd9b1680ae 1862 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2, N=8 */
bogdanm 86:04dd9b1680ae 1863 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4, N=6 */
bogdanm 86:04dd9b1680ae 1864 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4, N=8 */
bogdanm 86:04dd9b1680ae 1865 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8, N=6 */
bogdanm 86:04dd9b1680ae 1866 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8, N=8 */
bogdanm 86:04dd9b1680ae 1867 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16, N=5 */
bogdanm 86:04dd9b1680ae 1868 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16, N=6 */
bogdanm 86:04dd9b1680ae 1869 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16, N=8 */
bogdanm 86:04dd9b1680ae 1870 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=5 */
bogdanm 86:04dd9b1680ae 1871 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32, N=6 */
bogdanm 86:04dd9b1680ae 1872 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=8 */
bogdanm 86:04dd9b1680ae 1873
bogdanm 86:04dd9b1680ae 1874 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
bogdanm 86:04dd9b1680ae 1875 ((((EVENT) == HRTIM_EVENT_1) || \
bogdanm 86:04dd9b1680ae 1876 ((EVENT) == HRTIM_EVENT_2) || \
bogdanm 86:04dd9b1680ae 1877 ((EVENT) == HRTIM_EVENT_3) || \
bogdanm 86:04dd9b1680ae 1878 ((EVENT) == HRTIM_EVENT_4) || \
bogdanm 86:04dd9b1680ae 1879 ((EVENT) == HRTIM_EVENT_5)) \
bogdanm 86:04dd9b1680ae 1880 || \
bogdanm 86:04dd9b1680ae 1881 ((((EVENT) == HRTIM_EVENT_6) || \
bogdanm 86:04dd9b1680ae 1882 ((EVENT) == HRTIM_EVENT_7) || \
bogdanm 86:04dd9b1680ae 1883 ((EVENT) == HRTIM_EVENT_8) || \
bogdanm 86:04dd9b1680ae 1884 ((EVENT) == HRTIM_EVENT_9) || \
bogdanm 86:04dd9b1680ae 1885 ((EVENT) == HRTIM_EVENT_10)) && \
bogdanm 86:04dd9b1680ae 1886 (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
bogdanm 86:04dd9b1680ae 1887 ((FILTER) == HRTIM_EVENTFILTER_1) || \
bogdanm 86:04dd9b1680ae 1888 ((FILTER) == HRTIM_EVENTFILTER_2) || \
bogdanm 86:04dd9b1680ae 1889 ((FILTER) == HRTIM_EVENTFILTER_3) || \
bogdanm 86:04dd9b1680ae 1890 ((FILTER) == HRTIM_EVENTFILTER_4) || \
bogdanm 86:04dd9b1680ae 1891 ((FILTER) == HRTIM_EVENTFILTER_5) || \
bogdanm 86:04dd9b1680ae 1892 ((FILTER) == HRTIM_EVENTFILTER_6) || \
bogdanm 86:04dd9b1680ae 1893 ((FILTER) == HRTIM_EVENTFILTER_7) || \
bogdanm 86:04dd9b1680ae 1894 ((FILTER) == HRTIM_EVENTFILTER_8) || \
bogdanm 86:04dd9b1680ae 1895 ((FILTER) == HRTIM_EVENTFILTER_9) || \
bogdanm 86:04dd9b1680ae 1896 ((FILTER) == HRTIM_EVENTFILTER_10) || \
bogdanm 86:04dd9b1680ae 1897 ((FILTER) == HRTIM_EVENTFILTER_11) || \
bogdanm 86:04dd9b1680ae 1898 ((FILTER) == HRTIM_EVENTFILTER_12) || \
bogdanm 86:04dd9b1680ae 1899 ((FILTER) == HRTIM_EVENTFILTER_13) || \
bogdanm 86:04dd9b1680ae 1900 ((FILTER) == HRTIM_EVENTFILTER_14) || \
bogdanm 86:04dd9b1680ae 1901 ((FILTER) == HRTIM_EVENTFILTER_15))))
bogdanm 86:04dd9b1680ae 1902 /**
bogdanm 86:04dd9b1680ae 1903 * @}
bogdanm 86:04dd9b1680ae 1904 */
bogdanm 86:04dd9b1680ae 1905
bogdanm 86:04dd9b1680ae 1906 /** @defgroup External_Event_Prescaler
bogdanm 86:04dd9b1680ae 1907 * @{
bogdanm 86:04dd9b1680ae 1908 * @brief Constants defining division ratio between the timer clock frequency
bogdanm 86:04dd9b1680ae 1909 * fHRTIM) and the external event signal sampling clock (fEEVS)
bogdanm 86:04dd9b1680ae 1910 * used by the digital filters
bogdanm 86:04dd9b1680ae 1911 */
bogdanm 86:04dd9b1680ae 1912 #define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fEEVS=fHRTIM */
bogdanm 86:04dd9b1680ae 1913 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2 */
bogdanm 86:04dd9b1680ae 1914 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4 */
bogdanm 86:04dd9b1680ae 1915 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8 */
bogdanm 86:04dd9b1680ae 1916
bogdanm 86:04dd9b1680ae 1917 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
bogdanm 86:04dd9b1680ae 1918 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
bogdanm 86:04dd9b1680ae 1919 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
bogdanm 86:04dd9b1680ae 1920 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
bogdanm 86:04dd9b1680ae 1921 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
bogdanm 86:04dd9b1680ae 1922 /**
bogdanm 86:04dd9b1680ae 1923 * @}
bogdanm 86:04dd9b1680ae 1924 */
bogdanm 86:04dd9b1680ae 1925
bogdanm 86:04dd9b1680ae 1926 /** @defgroup HRTIM_Fault_Sources
bogdanm 86:04dd9b1680ae 1927 * @{
bogdanm 86:04dd9b1680ae 1928 * @brief Constants defining whether a faults is be triggered by any external
bogdanm 86:04dd9b1680ae 1929 * or internal fault source
bogdanm 86:04dd9b1680ae 1930 */
bogdanm 86:04dd9b1680ae 1931 #define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /*!< Fault input is FLT input pin */
bogdanm 86:04dd9b1680ae 1932 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
bogdanm 86:04dd9b1680ae 1933
bogdanm 86:04dd9b1680ae 1934
bogdanm 86:04dd9b1680ae 1935 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
bogdanm 86:04dd9b1680ae 1936 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
bogdanm 86:04dd9b1680ae 1937 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
bogdanm 86:04dd9b1680ae 1938 /**
bogdanm 86:04dd9b1680ae 1939 * @}
bogdanm 86:04dd9b1680ae 1940 */
bogdanm 86:04dd9b1680ae 1941
bogdanm 86:04dd9b1680ae 1942 /** @defgroup HRTIM_Fault_Polarity
bogdanm 86:04dd9b1680ae 1943 * @{
bogdanm 86:04dd9b1680ae 1944 * @brief Constants defining the polarity of a fault event
bogdanm 86:04dd9b1680ae 1945 */
bogdanm 86:04dd9b1680ae 1946 #define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /*!< Fault input is active low */
bogdanm 86:04dd9b1680ae 1947 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
bogdanm 86:04dd9b1680ae 1948
bogdanm 86:04dd9b1680ae 1949 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
bogdanm 86:04dd9b1680ae 1950 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
bogdanm 86:04dd9b1680ae 1951 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
bogdanm 86:04dd9b1680ae 1952 /**
bogdanm 86:04dd9b1680ae 1953 * @}
bogdanm 86:04dd9b1680ae 1954 */
bogdanm 86:04dd9b1680ae 1955
bogdanm 86:04dd9b1680ae 1956 /** @defgroup HRTIM_Fault_Filter
bogdanm 86:04dd9b1680ae 1957 * @{
bogdanm 86:04dd9b1680ae 1958 * @ brief Constants defining the frequency used to sample the fault input and
bogdanm 86:04dd9b1680ae 1959 * the length (N) of the digital filter applied
bogdanm 86:04dd9b1680ae 1960 */
bogdanm 86:04dd9b1680ae 1961 #define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
bogdanm 86:04dd9b1680ae 1962 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
bogdanm 86:04dd9b1680ae 1963 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
bogdanm 86:04dd9b1680ae 1964 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
bogdanm 86:04dd9b1680ae 1965 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
bogdanm 86:04dd9b1680ae 1966 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
bogdanm 86:04dd9b1680ae 1967 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
bogdanm 86:04dd9b1680ae 1968 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
bogdanm 86:04dd9b1680ae 1969 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
bogdanm 86:04dd9b1680ae 1970 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
bogdanm 86:04dd9b1680ae 1971 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
bogdanm 86:04dd9b1680ae 1972 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
bogdanm 86:04dd9b1680ae 1973 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
bogdanm 86:04dd9b1680ae 1974 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
bogdanm 86:04dd9b1680ae 1975 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
bogdanm 86:04dd9b1680ae 1976 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
bogdanm 86:04dd9b1680ae 1977
bogdanm 86:04dd9b1680ae 1978 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
bogdanm 86:04dd9b1680ae 1979 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
bogdanm 86:04dd9b1680ae 1980 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
bogdanm 86:04dd9b1680ae 1981 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
bogdanm 86:04dd9b1680ae 1982 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
bogdanm 86:04dd9b1680ae 1983 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
bogdanm 86:04dd9b1680ae 1984 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
bogdanm 86:04dd9b1680ae 1985 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
bogdanm 86:04dd9b1680ae 1986 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
bogdanm 86:04dd9b1680ae 1987 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
bogdanm 86:04dd9b1680ae 1988 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
bogdanm 86:04dd9b1680ae 1989 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
bogdanm 86:04dd9b1680ae 1990 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
bogdanm 86:04dd9b1680ae 1991 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
bogdanm 86:04dd9b1680ae 1992 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
bogdanm 86:04dd9b1680ae 1993 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
bogdanm 86:04dd9b1680ae 1994 ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
bogdanm 86:04dd9b1680ae 1995 /**
bogdanm 86:04dd9b1680ae 1996 * @}
bogdanm 86:04dd9b1680ae 1997 */
bogdanm 86:04dd9b1680ae 1998
bogdanm 86:04dd9b1680ae 1999 /** @defgroup HRTIM_Fault_Lock
bogdanm 86:04dd9b1680ae 2000 * @{
bogdanm 86:04dd9b1680ae 2001 * @brief Constants defining whether or not the fault programming bits are
bogdanm 86:04dd9b1680ae 2002 write protected
bogdanm 86:04dd9b1680ae 2003 */
bogdanm 86:04dd9b1680ae 2004 #define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Fault settings bits are read/write */
bogdanm 86:04dd9b1680ae 2005 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
bogdanm 86:04dd9b1680ae 2006
bogdanm 86:04dd9b1680ae 2007 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
bogdanm 86:04dd9b1680ae 2008 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
bogdanm 86:04dd9b1680ae 2009 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
bogdanm 86:04dd9b1680ae 2010 /**
bogdanm 86:04dd9b1680ae 2011 * @}
bogdanm 86:04dd9b1680ae 2012 */
bogdanm 86:04dd9b1680ae 2013
bogdanm 86:04dd9b1680ae 2014 /** @defgroup External_Fault_Prescaler
bogdanm 86:04dd9b1680ae 2015 * @{
bogdanm 86:04dd9b1680ae 2016 * @brief Constants defining the division ratio between the timer clock
bogdanm 86:04dd9b1680ae 2017 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
bogdanm 86:04dd9b1680ae 2018 * by the digital filters.
bogdanm 86:04dd9b1680ae 2019 */
bogdanm 86:04dd9b1680ae 2020 #define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fFLTS=fHRTIM */
bogdanm 86:04dd9b1680ae 2021 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2 */
bogdanm 86:04dd9b1680ae 2022 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4 */
bogdanm 86:04dd9b1680ae 2023 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8 */
bogdanm 86:04dd9b1680ae 2024
bogdanm 86:04dd9b1680ae 2025 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
bogdanm 86:04dd9b1680ae 2026 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
bogdanm 86:04dd9b1680ae 2027 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
bogdanm 86:04dd9b1680ae 2028 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
bogdanm 86:04dd9b1680ae 2029 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
bogdanm 86:04dd9b1680ae 2030 /**
bogdanm 86:04dd9b1680ae 2031 * @}
bogdanm 86:04dd9b1680ae 2032 */
bogdanm 86:04dd9b1680ae 2033
bogdanm 86:04dd9b1680ae 2034 /** @defgroup HRTIM_Burst_Mode_Operating_mode
bogdanm 86:04dd9b1680ae 2035 * @{
bogdanm 86:04dd9b1680ae 2036 * @brief Constants defining if the burst mode is entered once or if it is
bogdanm 86:04dd9b1680ae 2037 * continuously operating
bogdanm 86:04dd9b1680ae 2038 */
bogdanm 86:04dd9b1680ae 2039 #define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /*!< Burst mode operates in single shot mode */
bogdanm 86:04dd9b1680ae 2040 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
bogdanm 86:04dd9b1680ae 2041
bogdanm 86:04dd9b1680ae 2042 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
bogdanm 86:04dd9b1680ae 2043 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
bogdanm 86:04dd9b1680ae 2044 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
bogdanm 86:04dd9b1680ae 2045 /**
bogdanm 86:04dd9b1680ae 2046 * @}
bogdanm 86:04dd9b1680ae 2047 */
bogdanm 86:04dd9b1680ae 2048
bogdanm 86:04dd9b1680ae 2049 /** @defgroup HRTIM_Burst_Mode_Clock_Source
bogdanm 86:04dd9b1680ae 2050 * @{
bogdanm 86:04dd9b1680ae 2051 * @brief Constants defining the clock source for the burst mode counter
bogdanm 86:04dd9b1680ae 2052 */
bogdanm 86:04dd9b1680ae 2053 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
bogdanm 86:04dd9b1680ae 2054 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
bogdanm 86:04dd9b1680ae 2055 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
bogdanm 86:04dd9b1680ae 2056 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
bogdanm 86:04dd9b1680ae 2057 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
bogdanm 86:04dd9b1680ae 2058 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
bogdanm 86:04dd9b1680ae 2059 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
bogdanm 86:04dd9b1680ae 2060 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
bogdanm 86:04dd9b1680ae 2061 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
bogdanm 86:04dd9b1680ae 2062 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
bogdanm 86:04dd9b1680ae 2063
bogdanm 86:04dd9b1680ae 2064 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
bogdanm 86:04dd9b1680ae 2065 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
bogdanm 86:04dd9b1680ae 2066 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
bogdanm 86:04dd9b1680ae 2067 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
bogdanm 86:04dd9b1680ae 2068 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
bogdanm 86:04dd9b1680ae 2069 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
bogdanm 86:04dd9b1680ae 2070 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
bogdanm 86:04dd9b1680ae 2071 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \
bogdanm 86:04dd9b1680ae 2072 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \
bogdanm 86:04dd9b1680ae 2073 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \
bogdanm 86:04dd9b1680ae 2074 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
bogdanm 86:04dd9b1680ae 2075 /**
bogdanm 86:04dd9b1680ae 2076 * @}
bogdanm 86:04dd9b1680ae 2077 */
bogdanm 86:04dd9b1680ae 2078
bogdanm 86:04dd9b1680ae 2079 /** @defgroup HRTIM_Burst_Mode_Prescaler
bogdanm 86:04dd9b1680ae 2080 * @{
bogdanm 86:04dd9b1680ae 2081 * @brief Constants defining the prescaling ratio of the fHRTIM clock
bogdanm 86:04dd9b1680ae 2082 * for the burst mode controller
bogdanm 86:04dd9b1680ae 2083 */
bogdanm 86:04dd9b1680ae 2084 #define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fBRST = fHRTIM */
bogdanm 86:04dd9b1680ae 2085 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
bogdanm 86:04dd9b1680ae 2086 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
bogdanm 86:04dd9b1680ae 2087 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
bogdanm 86:04dd9b1680ae 2088 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
bogdanm 86:04dd9b1680ae 2089 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
bogdanm 86:04dd9b1680ae 2090 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
bogdanm 86:04dd9b1680ae 2091 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
bogdanm 86:04dd9b1680ae 2092 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
bogdanm 86:04dd9b1680ae 2093 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
bogdanm 86:04dd9b1680ae 2094 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
bogdanm 86:04dd9b1680ae 2095 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
bogdanm 86:04dd9b1680ae 2096 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
bogdanm 86:04dd9b1680ae 2097 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
bogdanm 86:04dd9b1680ae 2098 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
bogdanm 86:04dd9b1680ae 2099 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
bogdanm 86:04dd9b1680ae 2100
bogdanm 86:04dd9b1680ae 2101 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
bogdanm 86:04dd9b1680ae 2102 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
bogdanm 86:04dd9b1680ae 2103 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
bogdanm 86:04dd9b1680ae 2104 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
bogdanm 86:04dd9b1680ae 2105 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
bogdanm 86:04dd9b1680ae 2106 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
bogdanm 86:04dd9b1680ae 2107 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
bogdanm 86:04dd9b1680ae 2108 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
bogdanm 86:04dd9b1680ae 2109 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
bogdanm 86:04dd9b1680ae 2110 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
bogdanm 86:04dd9b1680ae 2111 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
bogdanm 86:04dd9b1680ae 2112 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
bogdanm 86:04dd9b1680ae 2113 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
bogdanm 86:04dd9b1680ae 2114 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
bogdanm 86:04dd9b1680ae 2115 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
bogdanm 86:04dd9b1680ae 2116 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
bogdanm 86:04dd9b1680ae 2117 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
bogdanm 86:04dd9b1680ae 2118 /**
bogdanm 86:04dd9b1680ae 2119 * @}
bogdanm 86:04dd9b1680ae 2120 */
bogdanm 86:04dd9b1680ae 2121
bogdanm 86:04dd9b1680ae 2122 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable
bogdanm 86:04dd9b1680ae 2123 * @{
bogdanm 86:04dd9b1680ae 2124 * @brief Constants defining whether or not burst mode registers preload
bogdanm 86:04dd9b1680ae 2125 mechanism is enabled, i.e. a write access into a preloadable register
bogdanm 86:04dd9b1680ae 2126 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
bogdanm 86:04dd9b1680ae 2127 */
bogdanm 86:04dd9b1680ae 2128 #define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into active registers */
bogdanm 86:04dd9b1680ae 2129 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
bogdanm 86:04dd9b1680ae 2130
bogdanm 86:04dd9b1680ae 2131 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
bogdanm 86:04dd9b1680ae 2132 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
bogdanm 86:04dd9b1680ae 2133 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
bogdanm 86:04dd9b1680ae 2134 /**
bogdanm 86:04dd9b1680ae 2135 * @}
bogdanm 86:04dd9b1680ae 2136 */
bogdanm 86:04dd9b1680ae 2137
bogdanm 86:04dd9b1680ae 2138 /** @defgroup HRTIM_Burst_Mode_Trigger
bogdanm 86:04dd9b1680ae 2139 * @{
bogdanm 86:04dd9b1680ae 2140 * @brief Constants defining the events that can be used tor trig the burst
bogdanm 86:04dd9b1680ae 2141 * mode operation
bogdanm 86:04dd9b1680ae 2142 */
bogdanm 86:04dd9b1680ae 2143 #define HRTIM_BURSTMODETRIGGER_NONE (uint32_t)0x00000000 /*!< No trigger */
bogdanm 86:04dd9b1680ae 2144 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
bogdanm 86:04dd9b1680ae 2145 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
bogdanm 86:04dd9b1680ae 2146 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1 */
bogdanm 86:04dd9b1680ae 2147 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2 */
bogdanm 86:04dd9b1680ae 2148 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3 */
bogdanm 86:04dd9b1680ae 2149 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4 */
bogdanm 86:04dd9b1680ae 2150 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
bogdanm 86:04dd9b1680ae 2151 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
bogdanm 86:04dd9b1680ae 2152 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
bogdanm 86:04dd9b1680ae 2153 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
bogdanm 86:04dd9b1680ae 2154 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
bogdanm 86:04dd9b1680ae 2155 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
bogdanm 86:04dd9b1680ae 2156 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
bogdanm 86:04dd9b1680ae 2157 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
bogdanm 86:04dd9b1680ae 2158 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
bogdanm 86:04dd9b1680ae 2159 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
bogdanm 86:04dd9b1680ae 2160 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
bogdanm 86:04dd9b1680ae 2161 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */
bogdanm 86:04dd9b1680ae 2162 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
bogdanm 86:04dd9b1680ae 2163 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
bogdanm 86:04dd9b1680ae 2164 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */
bogdanm 86:04dd9b1680ae 2165 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
bogdanm 86:04dd9b1680ae 2166 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */
bogdanm 86:04dd9b1680ae 2167 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
bogdanm 86:04dd9b1680ae 2168 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
bogdanm 86:04dd9b1680ae 2169 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
bogdanm 86:04dd9b1680ae 2170 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
bogdanm 86:04dd9b1680ae 2171 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
bogdanm 86:04dd9b1680ae 2172 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */
bogdanm 86:04dd9b1680ae 2173 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/
bogdanm 86:04dd9b1680ae 2174 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
bogdanm 86:04dd9b1680ae 2175
bogdanm 86:04dd9b1680ae 2176 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
bogdanm 86:04dd9b1680ae 2177 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
bogdanm 86:04dd9b1680ae 2178 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
bogdanm 86:04dd9b1680ae 2179 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
bogdanm 86:04dd9b1680ae 2180 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
bogdanm 86:04dd9b1680ae 2181 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
bogdanm 86:04dd9b1680ae 2182 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
bogdanm 86:04dd9b1680ae 2183 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
bogdanm 86:04dd9b1680ae 2184 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
bogdanm 86:04dd9b1680ae 2185 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
bogdanm 86:04dd9b1680ae 2186 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
bogdanm 86:04dd9b1680ae 2187 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
bogdanm 86:04dd9b1680ae 2188 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
bogdanm 86:04dd9b1680ae 2189 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
bogdanm 86:04dd9b1680ae 2190 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
bogdanm 86:04dd9b1680ae 2191 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
bogdanm 86:04dd9b1680ae 2192 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
bogdanm 86:04dd9b1680ae 2193 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
bogdanm 86:04dd9b1680ae 2194 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
bogdanm 86:04dd9b1680ae 2195 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
bogdanm 86:04dd9b1680ae 2196 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
bogdanm 86:04dd9b1680ae 2197 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
bogdanm 86:04dd9b1680ae 2198 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
bogdanm 86:04dd9b1680ae 2199 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
bogdanm 86:04dd9b1680ae 2200 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
bogdanm 86:04dd9b1680ae 2201 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
bogdanm 86:04dd9b1680ae 2202 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
bogdanm 86:04dd9b1680ae 2203 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
bogdanm 86:04dd9b1680ae 2204 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
bogdanm 86:04dd9b1680ae 2205 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
bogdanm 86:04dd9b1680ae 2206 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
bogdanm 86:04dd9b1680ae 2207 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
bogdanm 86:04dd9b1680ae 2208 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
bogdanm 86:04dd9b1680ae 2209 /**
bogdanm 86:04dd9b1680ae 2210 * @}
bogdanm 86:04dd9b1680ae 2211 */
bogdanm 86:04dd9b1680ae 2212
bogdanm 86:04dd9b1680ae 2213 /** @defgroup HRTIM_ADC_Trigger_Update_Source
bogdanm 86:04dd9b1680ae 2214 * @{
bogdanm 86:04dd9b1680ae 2215 * @brief constants defining the source triggering the update of the
bogdanm 86:04dd9b1680ae 2216 HRTIM_ADCxR register (transfer from preload to active register).
bogdanm 86:04dd9b1680ae 2217 */
bogdanm 86:04dd9b1680ae 2218 #define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /*!< Master timer */
bogdanm 86:04dd9b1680ae 2219 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
bogdanm 86:04dd9b1680ae 2220 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
bogdanm 86:04dd9b1680ae 2221 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
bogdanm 86:04dd9b1680ae 2222 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
bogdanm 86:04dd9b1680ae 2223 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
bogdanm 86:04dd9b1680ae 2224
bogdanm 86:04dd9b1680ae 2225 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
bogdanm 86:04dd9b1680ae 2226 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
bogdanm 86:04dd9b1680ae 2227 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
bogdanm 86:04dd9b1680ae 2228 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
bogdanm 86:04dd9b1680ae 2229 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
bogdanm 86:04dd9b1680ae 2230 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
bogdanm 86:04dd9b1680ae 2231 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
bogdanm 86:04dd9b1680ae 2232 /**
bogdanm 86:04dd9b1680ae 2233 * @}
bogdanm 86:04dd9b1680ae 2234 */
bogdanm 86:04dd9b1680ae 2235
bogdanm 86:04dd9b1680ae 2236 /** @defgroup HRTIM_ADC_Trigger_Event
bogdanm 86:04dd9b1680ae 2237 * @{
bogdanm 86:04dd9b1680ae 2238 * @brief constants defining the events triggering ADC conversion.
bogdanm 86:04dd9b1680ae 2239 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
bogdanm 86:04dd9b1680ae 2240 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
bogdanm 86:04dd9b1680ae 2241 */
bogdanm 86:04dd9b1680ae 2242 #define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
bogdanm 86:04dd9b1680ae 2243 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1 */
bogdanm 86:04dd9b1680ae 2244 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2 */
bogdanm 86:04dd9b1680ae 2245 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3 */
bogdanm 86:04dd9b1680ae 2246 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4 */
bogdanm 86:04dd9b1680ae 2247 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
bogdanm 86:04dd9b1680ae 2248 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1 */
bogdanm 86:04dd9b1680ae 2249 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2 */
bogdanm 86:04dd9b1680ae 2250 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3 */
bogdanm 86:04dd9b1680ae 2251 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4 */
bogdanm 86:04dd9b1680ae 2252 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5 */
bogdanm 86:04dd9b1680ae 2253 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2 */
bogdanm 86:04dd9b1680ae 2254 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3 */
bogdanm 86:04dd9b1680ae 2255 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4 */
bogdanm 86:04dd9b1680ae 2256 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
bogdanm 86:04dd9b1680ae 2257 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
bogdanm 86:04dd9b1680ae 2258 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2 */
bogdanm 86:04dd9b1680ae 2259 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3 */
bogdanm 86:04dd9b1680ae 2260 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4 */
bogdanm 86:04dd9b1680ae 2261 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
bogdanm 86:04dd9b1680ae 2262 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
bogdanm 86:04dd9b1680ae 2263 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2 */
bogdanm 86:04dd9b1680ae 2264 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3 */
bogdanm 86:04dd9b1680ae 2265 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4 */
bogdanm 86:04dd9b1680ae 2266 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
bogdanm 86:04dd9b1680ae 2267 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2 */
bogdanm 86:04dd9b1680ae 2268 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3 */
bogdanm 86:04dd9b1680ae 2269 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4 */
bogdanm 86:04dd9b1680ae 2270 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
bogdanm 86:04dd9b1680ae 2271 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2 */
bogdanm 86:04dd9b1680ae 2272 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3 */
bogdanm 86:04dd9b1680ae 2273 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4 */
bogdanm 86:04dd9b1680ae 2274 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
bogdanm 86:04dd9b1680ae 2275
bogdanm 86:04dd9b1680ae 2276 #define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
bogdanm 86:04dd9b1680ae 2277 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1 */
bogdanm 86:04dd9b1680ae 2278 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2 */
bogdanm 86:04dd9b1680ae 2279 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3 */
bogdanm 86:04dd9b1680ae 2280 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4 */
bogdanm 86:04dd9b1680ae 2281 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
bogdanm 86:04dd9b1680ae 2282 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6 */
bogdanm 86:04dd9b1680ae 2283 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7 */
bogdanm 86:04dd9b1680ae 2284 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8 */
bogdanm 86:04dd9b1680ae 2285 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9 */
bogdanm 86:04dd9b1680ae 2286 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10 */
bogdanm 86:04dd9b1680ae 2287 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2 */
bogdanm 86:04dd9b1680ae 2288 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3 */
bogdanm 86:04dd9b1680ae 2289 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4 */
bogdanm 86:04dd9b1680ae 2290 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
bogdanm 86:04dd9b1680ae 2291 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2 */
bogdanm 86:04dd9b1680ae 2292 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3 */
bogdanm 86:04dd9b1680ae 2293 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4 */
bogdanm 86:04dd9b1680ae 2294 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
bogdanm 86:04dd9b1680ae 2295 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2 */
bogdanm 86:04dd9b1680ae 2296 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3 */
bogdanm 86:04dd9b1680ae 2297 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4 */
bogdanm 86:04dd9b1680ae 2298 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
bogdanm 86:04dd9b1680ae 2299 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
bogdanm 86:04dd9b1680ae 2300 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2 */
bogdanm 86:04dd9b1680ae 2301 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3 */
bogdanm 86:04dd9b1680ae 2302 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4 */
bogdanm 86:04dd9b1680ae 2303 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
bogdanm 86:04dd9b1680ae 2304 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
bogdanm 86:04dd9b1680ae 2305 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2 */
bogdanm 86:04dd9b1680ae 2306 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3 */
bogdanm 86:04dd9b1680ae 2307 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4 */
bogdanm 86:04dd9b1680ae 2308 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
bogdanm 86:04dd9b1680ae 2309
bogdanm 86:04dd9b1680ae 2310 /**
bogdanm 86:04dd9b1680ae 2311 * @}
bogdanm 86:04dd9b1680ae 2312 */
bogdanm 86:04dd9b1680ae 2313
bogdanm 86:04dd9b1680ae 2314 /** @defgroup DLL_Calibration_Rate
bogdanm 86:04dd9b1680ae 2315 * @{
bogdanm 86:04dd9b1680ae 2316 * @brief Constants defining the DLL calibration periods (in micro seconds)
bogdanm 86:04dd9b1680ae 2317 */
bogdanm 86:04dd9b1680ae 2318 #define HRTIM_SINGLE_CALIBRATION (uint32_t)0xFFFFFFFF /*!< Non periodic DLL calibration */
bogdanm 86:04dd9b1680ae 2319 #define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 /*!< Periodic DLL calibration: T = 1048576 * tHRTIM (7.3 ms) */
bogdanm 86:04dd9b1680ae 2320 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072 * tHRTIM (910 µs) */
bogdanm 86:04dd9b1680ae 2321 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384 * tHRTIM (114 µs) */
bogdanm 86:04dd9b1680ae 2322 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048 * tHRTIM (14 µs) */
bogdanm 86:04dd9b1680ae 2323
bogdanm 86:04dd9b1680ae 2324 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
bogdanm 86:04dd9b1680ae 2325 (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
bogdanm 86:04dd9b1680ae 2326 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
bogdanm 86:04dd9b1680ae 2327 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
bogdanm 86:04dd9b1680ae 2328 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
bogdanm 86:04dd9b1680ae 2329 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
bogdanm 86:04dd9b1680ae 2330 /**
bogdanm 86:04dd9b1680ae 2331 * @}
bogdanm 86:04dd9b1680ae 2332 */
bogdanm 86:04dd9b1680ae 2333
bogdanm 86:04dd9b1680ae 2334 /** @defgroup Burst_DMA_Registers_Update
bogdanm 86:04dd9b1680ae 2335 * @{
bogdanm 86:04dd9b1680ae 2336 * @brief Constants defining the registers that can be written during a burst
bogdanm 86:04dd9b1680ae 2337 * DMA operation
bogdanm 86:04dd9b1680ae 2338 */
bogdanm 86:04dd9b1680ae 2339 #define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /*!< No register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2340 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2341 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2342 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2343 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2344 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2345 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2346 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2347 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2348 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2349 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2350 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2351 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2352 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2353 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2354 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2355 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2356 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2357 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2358 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2359 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2360 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
bogdanm 86:04dd9b1680ae 2361
bogdanm 86:04dd9b1680ae 2362 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
bogdanm 86:04dd9b1680ae 2363 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \
bogdanm 86:04dd9b1680ae 2364 || \
bogdanm 86:04dd9b1680ae 2365 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm 86:04dd9b1680ae 2366 || \
bogdanm 86:04dd9b1680ae 2367 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm 86:04dd9b1680ae 2368 || \
bogdanm 86:04dd9b1680ae 2369 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm 86:04dd9b1680ae 2370 || \
bogdanm 86:04dd9b1680ae 2371 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
bogdanm 86:04dd9b1680ae 2372 || \
bogdanm 86:04dd9b1680ae 2373 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)))
bogdanm 86:04dd9b1680ae 2374 /**
bogdanm 86:04dd9b1680ae 2375 * @}
bogdanm 86:04dd9b1680ae 2376 */
bogdanm 86:04dd9b1680ae 2377
bogdanm 86:04dd9b1680ae 2378 /** @defgroup Burst_Mode_Control
bogdanm 86:04dd9b1680ae 2379 * @{
bogdanm 86:04dd9b1680ae 2380 * @brief Constants used to enable or disable the burst mode controller
bogdanm 86:04dd9b1680ae 2381 */
bogdanm 86:04dd9b1680ae 2382 #define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Burst mode disabled */
bogdanm 86:04dd9b1680ae 2383 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
bogdanm 86:04dd9b1680ae 2384
bogdanm 86:04dd9b1680ae 2385 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
bogdanm 86:04dd9b1680ae 2386 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
bogdanm 86:04dd9b1680ae 2387 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
bogdanm 86:04dd9b1680ae 2388 /**
bogdanm 86:04dd9b1680ae 2389 * @}
bogdanm 86:04dd9b1680ae 2390 */
bogdanm 86:04dd9b1680ae 2391
bogdanm 86:04dd9b1680ae 2392 /** @defgroup Fault_Mode_Control
bogdanm 86:04dd9b1680ae 2393 * @{
bogdanm 86:04dd9b1680ae 2394 * @brief Constants used to enable or disable a fault channel
bogdanm 86:04dd9b1680ae 2395 */
bogdanm 86:04dd9b1680ae 2396 #define HRTIM_FAULTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Fault channel is disabled */
bogdanm 86:04dd9b1680ae 2397 #define HRTIM_FAULTMODECTL_ENABLED (uint32_t)0x00000001 /*!< Fault channel is enabled */
bogdanm 86:04dd9b1680ae 2398
bogdanm 86:04dd9b1680ae 2399 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
bogdanm 86:04dd9b1680ae 2400 (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \
bogdanm 86:04dd9b1680ae 2401 ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
bogdanm 86:04dd9b1680ae 2402 /**
bogdanm 86:04dd9b1680ae 2403 * @}
bogdanm 86:04dd9b1680ae 2404 */
bogdanm 86:04dd9b1680ae 2405
bogdanm 86:04dd9b1680ae 2406 /** @defgroup Software_Timer_Update
bogdanm 86:04dd9b1680ae 2407 * @{
bogdanm 86:04dd9b1680ae 2408 * @brief Constants used to force timer registers update
bogdanm 86:04dd9b1680ae 2409 */
bogdanm 86:04dd9b1680ae 2410 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
bogdanm 86:04dd9b1680ae 2411 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
bogdanm 86:04dd9b1680ae 2412 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
bogdanm 86:04dd9b1680ae 2413 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
bogdanm 86:04dd9b1680ae 2414 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
bogdanm 86:04dd9b1680ae 2415 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
bogdanm 86:04dd9b1680ae 2416
bogdanm 86:04dd9b1680ae 2417 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000)
bogdanm 86:04dd9b1680ae 2418 /**
bogdanm 86:04dd9b1680ae 2419 * @}
bogdanm 86:04dd9b1680ae 2420 */
bogdanm 86:04dd9b1680ae 2421
bogdanm 86:04dd9b1680ae 2422 /** @defgroup Software_Timer_Reset
bogdanm 86:04dd9b1680ae 2423 * @{
bogdanm 86:04dd9b1680ae 2424 * @brief Constants used to force timer counter reset
bogdanm 86:04dd9b1680ae 2425 */
bogdanm 86:04dd9b1680ae 2426 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */
bogdanm 86:04dd9b1680ae 2427 #define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */
bogdanm 86:04dd9b1680ae 2428 #define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */
bogdanm 86:04dd9b1680ae 2429 #define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */
bogdanm 86:04dd9b1680ae 2430 #define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */
bogdanm 86:04dd9b1680ae 2431 #define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */
bogdanm 86:04dd9b1680ae 2432
bogdanm 86:04dd9b1680ae 2433 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000)
bogdanm 86:04dd9b1680ae 2434 /**
bogdanm 86:04dd9b1680ae 2435 * @}
bogdanm 86:04dd9b1680ae 2436 */
bogdanm 86:04dd9b1680ae 2437
bogdanm 86:04dd9b1680ae 2438 /** @defgroup Output_Level
bogdanm 86:04dd9b1680ae 2439 * @{
bogdanm 86:04dd9b1680ae 2440 * @brief Constants defining the level of a timer output
bogdanm 86:04dd9b1680ae 2441 */
bogdanm 86:04dd9b1680ae 2442 #define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 /*!< Forces the output to its active state */
bogdanm 86:04dd9b1680ae 2443 #define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 /*!< Forces the output to its inactive state */
bogdanm 86:04dd9b1680ae 2444
bogdanm 86:04dd9b1680ae 2445 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
bogdanm 86:04dd9b1680ae 2446 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
bogdanm 86:04dd9b1680ae 2447 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
bogdanm 86:04dd9b1680ae 2448 /**
bogdanm 86:04dd9b1680ae 2449 * @}
bogdanm 86:04dd9b1680ae 2450 */
bogdanm 86:04dd9b1680ae 2451
bogdanm 86:04dd9b1680ae 2452 /** @defgroup Output_State
bogdanm 86:04dd9b1680ae 2453 * @{
bogdanm 86:04dd9b1680ae 2454 * @brief Constants defining the state of a timer output
bogdanm 86:04dd9b1680ae 2455 */
bogdanm 86:04dd9b1680ae 2456 #define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 /*!< Main operating mode, where the output can take the active or
bogdanm 86:04dd9b1680ae 2457 inactive level as programmed in the crossbar unit */
bogdanm 86:04dd9b1680ae 2458 #define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 /*!< Default operating state (e.g. after an HRTIM reset, when the
bogdanm 86:04dd9b1680ae 2459 outputs are disabled by software or during a burst mode operation */
bogdanm 86:04dd9b1680ae 2460 #define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 /*!< Safety state, entered in case of a shut-down request on
bogdanm 86:04dd9b1680ae 2461 FAULTx inputs */
bogdanm 86:04dd9b1680ae 2462 /**
bogdanm 86:04dd9b1680ae 2463 * @}
bogdanm 86:04dd9b1680ae 2464 */
bogdanm 86:04dd9b1680ae 2465
bogdanm 86:04dd9b1680ae 2466 /** @defgroup Burst_Mode_Status
bogdanm 86:04dd9b1680ae 2467 * @{
bogdanm 86:04dd9b1680ae 2468 * @brief Constants defining the operating state of the burst mode controller
bogdanm 86:04dd9b1680ae 2469 */
bogdanm 86:04dd9b1680ae 2470 #define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /*!< Normal operation */
bogdanm 86:04dd9b1680ae 2471 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
bogdanm 86:04dd9b1680ae 2472 /**
bogdanm 86:04dd9b1680ae 2473 * @}
bogdanm 86:04dd9b1680ae 2474 */
bogdanm 86:04dd9b1680ae 2475
bogdanm 86:04dd9b1680ae 2476 /** @defgroup Current_Push_Pull_Status
bogdanm 86:04dd9b1680ae 2477 * @{
bogdanm 86:04dd9b1680ae 2478 * @brief Constants defining on which output the signal is currently applied
bogdanm 86:04dd9b1680ae 2479 * in push-pull mode
bogdanm 86:04dd9b1680ae 2480 */
bogdanm 86:04dd9b1680ae 2481 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Signal applied on output 1 and output 2 forced inactive */
bogdanm 86:04dd9b1680ae 2482 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
bogdanm 86:04dd9b1680ae 2483 /**
bogdanm 86:04dd9b1680ae 2484 * @}
bogdanm 86:04dd9b1680ae 2485 */
bogdanm 86:04dd9b1680ae 2486
bogdanm 86:04dd9b1680ae 2487 /** @defgroup Idle_Push_Pull_Status
bogdanm 86:04dd9b1680ae 2488 * @{
bogdanm 86:04dd9b1680ae 2489 * @brief Constants defining on which output the signal was applied, in
bogdanm 86:04dd9b1680ae 2490 * push-pull mode balanced fault mode or delayed idle mode, when the
bogdanm 86:04dd9b1680ae 2491 * protection was triggered
bogdanm 86:04dd9b1680ae 2492 */
bogdanm 86:04dd9b1680ae 2493 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
bogdanm 86:04dd9b1680ae 2494 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
bogdanm 86:04dd9b1680ae 2495 /**
bogdanm 86:04dd9b1680ae 2496 * @}
bogdanm 86:04dd9b1680ae 2497 */
bogdanm 86:04dd9b1680ae 2498
bogdanm 86:04dd9b1680ae 2499 /** @defgroup HRTIM_Common_Interrupt_Enable
bogdanm 86:04dd9b1680ae 2500 * @{
bogdanm 86:04dd9b1680ae 2501 */
bogdanm 86:04dd9b1680ae 2502 #define HRTIM_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
bogdanm 86:04dd9b1680ae 2503 #define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */
bogdanm 86:04dd9b1680ae 2504 #define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */
bogdanm 86:04dd9b1680ae 2505 #define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */
bogdanm 86:04dd9b1680ae 2506 #define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */
bogdanm 86:04dd9b1680ae 2507 #define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */
bogdanm 86:04dd9b1680ae 2508 #define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */
bogdanm 86:04dd9b1680ae 2509 #define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */
bogdanm 86:04dd9b1680ae 2510 #define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */
bogdanm 86:04dd9b1680ae 2511
bogdanm 86:04dd9b1680ae 2512 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0) == 0x00000000)
bogdanm 86:04dd9b1680ae 2513
bogdanm 86:04dd9b1680ae 2514 /**
bogdanm 86:04dd9b1680ae 2515 * @}
bogdanm 86:04dd9b1680ae 2516 */
bogdanm 86:04dd9b1680ae 2517
bogdanm 86:04dd9b1680ae 2518 /** @defgroup HRTIM_Master_Interrupt_Enable
bogdanm 86:04dd9b1680ae 2519 * @{
bogdanm 86:04dd9b1680ae 2520 */
bogdanm 86:04dd9b1680ae 2521 #define HRTIM_MASTER_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
bogdanm 86:04dd9b1680ae 2522 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */
bogdanm 86:04dd9b1680ae 2523 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */
bogdanm 86:04dd9b1680ae 2524 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */
bogdanm 86:04dd9b1680ae 2525 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */
bogdanm 86:04dd9b1680ae 2526 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */
bogdanm 86:04dd9b1680ae 2527 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */
bogdanm 86:04dd9b1680ae 2528 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */
bogdanm 86:04dd9b1680ae 2529
bogdanm 86:04dd9b1680ae 2530 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80) == 0x00000000)
bogdanm 86:04dd9b1680ae 2531
bogdanm 86:04dd9b1680ae 2532 /**
bogdanm 86:04dd9b1680ae 2533 * @}
bogdanm 86:04dd9b1680ae 2534 */
bogdanm 86:04dd9b1680ae 2535
bogdanm 86:04dd9b1680ae 2536 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable
bogdanm 86:04dd9b1680ae 2537 * @{
bogdanm 86:04dd9b1680ae 2538 */
bogdanm 86:04dd9b1680ae 2539 #define HRTIM_TIM_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
bogdanm 86:04dd9b1680ae 2540 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */
bogdanm 86:04dd9b1680ae 2541 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */
bogdanm 86:04dd9b1680ae 2542 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */
bogdanm 86:04dd9b1680ae 2543 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */
bogdanm 86:04dd9b1680ae 2544 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */
bogdanm 86:04dd9b1680ae 2545 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */
bogdanm 86:04dd9b1680ae 2546 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */
bogdanm 86:04dd9b1680ae 2547 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */
bogdanm 86:04dd9b1680ae 2548 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */
bogdanm 86:04dd9b1680ae 2549 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */
bogdanm 86:04dd9b1680ae 2550 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */
bogdanm 86:04dd9b1680ae 2551 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */
bogdanm 86:04dd9b1680ae 2552 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */
bogdanm 86:04dd9b1680ae 2553 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */
bogdanm 86:04dd9b1680ae 2554
bogdanm 86:04dd9b1680ae 2555 #define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020) == 0x00000000)
bogdanm 86:04dd9b1680ae 2556
bogdanm 86:04dd9b1680ae 2557 /**
bogdanm 86:04dd9b1680ae 2558 * @}
bogdanm 86:04dd9b1680ae 2559 */
bogdanm 86:04dd9b1680ae 2560
bogdanm 86:04dd9b1680ae 2561 /** @defgroup HRTIM_Common_Interrupt_Flag
bogdanm 86:04dd9b1680ae 2562 * @{
bogdanm 86:04dd9b1680ae 2563 */
bogdanm 86:04dd9b1680ae 2564 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
bogdanm 86:04dd9b1680ae 2565 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
bogdanm 86:04dd9b1680ae 2566 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
bogdanm 86:04dd9b1680ae 2567 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
bogdanm 86:04dd9b1680ae 2568 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
bogdanm 86:04dd9b1680ae 2569 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
bogdanm 86:04dd9b1680ae 2570 #define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
bogdanm 86:04dd9b1680ae 2571 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
bogdanm 86:04dd9b1680ae 2572
bogdanm 86:04dd9b1680ae 2573 /**
bogdanm 86:04dd9b1680ae 2574 * @}
bogdanm 86:04dd9b1680ae 2575 */
bogdanm 86:04dd9b1680ae 2576
bogdanm 86:04dd9b1680ae 2577 /** @defgroup HRTIM_Master_Interrupt_Flag
bogdanm 86:04dd9b1680ae 2578 * @{
bogdanm 86:04dd9b1680ae 2579 */
bogdanm 86:04dd9b1680ae 2580 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
bogdanm 86:04dd9b1680ae 2581 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
bogdanm 86:04dd9b1680ae 2582 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
bogdanm 86:04dd9b1680ae 2583 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
bogdanm 86:04dd9b1680ae 2584 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
bogdanm 86:04dd9b1680ae 2585 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
bogdanm 86:04dd9b1680ae 2586 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
bogdanm 86:04dd9b1680ae 2587
bogdanm 86:04dd9b1680ae 2588 /**
bogdanm 86:04dd9b1680ae 2589 * @}
bogdanm 86:04dd9b1680ae 2590 */
bogdanm 86:04dd9b1680ae 2591
bogdanm 86:04dd9b1680ae 2592 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag
bogdanm 86:04dd9b1680ae 2593 * @{
bogdanm 86:04dd9b1680ae 2594 */
bogdanm 86:04dd9b1680ae 2595 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
bogdanm 86:04dd9b1680ae 2596 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
bogdanm 86:04dd9b1680ae 2597 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
bogdanm 86:04dd9b1680ae 2598 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
bogdanm 86:04dd9b1680ae 2599 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
bogdanm 86:04dd9b1680ae 2600 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
bogdanm 86:04dd9b1680ae 2601 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
bogdanm 86:04dd9b1680ae 2602 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
bogdanm 86:04dd9b1680ae 2603 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
bogdanm 86:04dd9b1680ae 2604 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
bogdanm 86:04dd9b1680ae 2605 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
bogdanm 86:04dd9b1680ae 2606 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
bogdanm 86:04dd9b1680ae 2607 #define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */
bogdanm 86:04dd9b1680ae 2608 #define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
bogdanm 86:04dd9b1680ae 2609
bogdanm 86:04dd9b1680ae 2610 /**
bogdanm 86:04dd9b1680ae 2611 * @}
bogdanm 86:04dd9b1680ae 2612 */
bogdanm 86:04dd9b1680ae 2613
bogdanm 86:04dd9b1680ae 2614 /** @defgroup HRTIM_Master_DMA_Request_Enable
bogdanm 86:04dd9b1680ae 2615 * @{
bogdanm 86:04dd9b1680ae 2616 */
bogdanm 86:04dd9b1680ae 2617 #define HRTIM_MASTER_DMA_NONE (uint32_t)0x00000000 /*!< No DMA request enable */
bogdanm 86:04dd9b1680ae 2618 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */
bogdanm 86:04dd9b1680ae 2619 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */
bogdanm 86:04dd9b1680ae 2620 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */
bogdanm 86:04dd9b1680ae 2621 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */
bogdanm 86:04dd9b1680ae 2622 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */
bogdanm 86:04dd9b1680ae 2623 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */
bogdanm 86:04dd9b1680ae 2624 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */
bogdanm 86:04dd9b1680ae 2625
bogdanm 86:04dd9b1680ae 2626 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFF) == 0x00000000)
bogdanm 86:04dd9b1680ae 2627 /**
bogdanm 86:04dd9b1680ae 2628 * @}
bogdanm 86:04dd9b1680ae 2629 */
bogdanm 86:04dd9b1680ae 2630
bogdanm 86:04dd9b1680ae 2631 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable
bogdanm 86:04dd9b1680ae 2632 * @{
bogdanm 86:04dd9b1680ae 2633 */
bogdanm 86:04dd9b1680ae 2634 #define HRTIM_TIM_DMA_NONE (uint32_t)0x00000000 /*!< No DMA request enable */
bogdanm 86:04dd9b1680ae 2635 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */
bogdanm 86:04dd9b1680ae 2636 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */
bogdanm 86:04dd9b1680ae 2637 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */
bogdanm 86:04dd9b1680ae 2638 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */
bogdanm 86:04dd9b1680ae 2639 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */
bogdanm 86:04dd9b1680ae 2640 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */
bogdanm 86:04dd9b1680ae 2641 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */
bogdanm 86:04dd9b1680ae 2642 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */
bogdanm 86:04dd9b1680ae 2643 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */
bogdanm 86:04dd9b1680ae 2644 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */
bogdanm 86:04dd9b1680ae 2645 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */
bogdanm 86:04dd9b1680ae 2646 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */
bogdanm 86:04dd9b1680ae 2647 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */
bogdanm 86:04dd9b1680ae 2648 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */
bogdanm 86:04dd9b1680ae 2649
bogdanm 86:04dd9b1680ae 2650 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFF) == 0x00000000)
bogdanm 86:04dd9b1680ae 2651
bogdanm 86:04dd9b1680ae 2652 /**
bogdanm 86:04dd9b1680ae 2653 * @}
bogdanm 86:04dd9b1680ae 2654 */
bogdanm 86:04dd9b1680ae 2655
bogdanm 86:04dd9b1680ae 2656 /** @defgroup HRTIM_Instance_definition
bogdanm 86:04dd9b1680ae 2657 * @{
bogdanm 86:04dd9b1680ae 2658 */
bogdanm 86:04dd9b1680ae 2659 #define IS_HRTIM_INSTANCE(INSTANCE) (INSTANCE) == HRTIM1)
bogdanm 86:04dd9b1680ae 2660 /**
bogdanm 86:04dd9b1680ae 2661 * @}
bogdanm 86:04dd9b1680ae 2662 */
bogdanm 86:04dd9b1680ae 2663
bogdanm 86:04dd9b1680ae 2664 /**
bogdanm 86:04dd9b1680ae 2665 * @}
bogdanm 86:04dd9b1680ae 2666 */
bogdanm 86:04dd9b1680ae 2667
bogdanm 86:04dd9b1680ae 2668 /* Exported macros -----------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 2669
bogdanm 86:04dd9b1680ae 2670 /** @brief Reset HRTIM handle state
bogdanm 86:04dd9b1680ae 2671 * @param __HANDLE__: HRTIM handle.
bogdanm 86:04dd9b1680ae 2672 * @retval None
bogdanm 86:04dd9b1680ae 2673 */
bogdanm 86:04dd9b1680ae 2674 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
bogdanm 86:04dd9b1680ae 2675
bogdanm 86:04dd9b1680ae 2676 /** @brief Enables or disables the timer counter(s)
bogdanm 86:04dd9b1680ae 2677 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2678 * @param __TIMERS__: timersto enable/disable
bogdanm 86:04dd9b1680ae 2679 * This parameter can be any combinations of the following values:
bogdanm 86:04dd9b1680ae 2680 * @arg HRTIM_TIMERID_MASTER: Master timer identifier
bogdanm 86:04dd9b1680ae 2681 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
bogdanm 86:04dd9b1680ae 2682 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
bogdanm 86:04dd9b1680ae 2683 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
bogdanm 86:04dd9b1680ae 2684 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
bogdanm 86:04dd9b1680ae 2685 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
bogdanm 86:04dd9b1680ae 2686 * @retval None
bogdanm 86:04dd9b1680ae 2687 */
bogdanm 86:04dd9b1680ae 2688 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
bogdanm 86:04dd9b1680ae 2689
bogdanm 86:04dd9b1680ae 2690 /* The counter of a timing unit is disabled only if all the timer outputs */
bogdanm 86:04dd9b1680ae 2691 /* are disabled and no capture is configured */
bogdanm 86:04dd9b1680ae 2692 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
bogdanm 86:04dd9b1680ae 2693 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
bogdanm 86:04dd9b1680ae 2694 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
bogdanm 86:04dd9b1680ae 2695 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
bogdanm 86:04dd9b1680ae 2696 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
bogdanm 86:04dd9b1680ae 2697 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
bogdanm 86:04dd9b1680ae 2698 do {\
bogdanm 86:04dd9b1680ae 2699 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
bogdanm 86:04dd9b1680ae 2700 {\
bogdanm 86:04dd9b1680ae 2701 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
bogdanm 86:04dd9b1680ae 2702 }\
bogdanm 86:04dd9b1680ae 2703 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
bogdanm 86:04dd9b1680ae 2704 {\
bogdanm 86:04dd9b1680ae 2705 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
bogdanm 86:04dd9b1680ae 2706 {\
bogdanm 86:04dd9b1680ae 2707 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
bogdanm 86:04dd9b1680ae 2708 }\
bogdanm 86:04dd9b1680ae 2709 }\
bogdanm 86:04dd9b1680ae 2710 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
bogdanm 86:04dd9b1680ae 2711 {\
bogdanm 86:04dd9b1680ae 2712 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
bogdanm 86:04dd9b1680ae 2713 {\
bogdanm 86:04dd9b1680ae 2714 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
bogdanm 86:04dd9b1680ae 2715 }\
bogdanm 86:04dd9b1680ae 2716 }\
bogdanm 86:04dd9b1680ae 2717 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
bogdanm 86:04dd9b1680ae 2718 {\
bogdanm 86:04dd9b1680ae 2719 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
bogdanm 86:04dd9b1680ae 2720 {\
bogdanm 86:04dd9b1680ae 2721 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
bogdanm 86:04dd9b1680ae 2722 }\
bogdanm 86:04dd9b1680ae 2723 }\
bogdanm 86:04dd9b1680ae 2724 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
bogdanm 86:04dd9b1680ae 2725 {\
bogdanm 86:04dd9b1680ae 2726 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
bogdanm 86:04dd9b1680ae 2727 {\
bogdanm 86:04dd9b1680ae 2728 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
bogdanm 86:04dd9b1680ae 2729 }\
bogdanm 86:04dd9b1680ae 2730 }\
bogdanm 86:04dd9b1680ae 2731 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
bogdanm 86:04dd9b1680ae 2732 {\
bogdanm 86:04dd9b1680ae 2733 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
bogdanm 86:04dd9b1680ae 2734 {\
bogdanm 86:04dd9b1680ae 2735 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
bogdanm 86:04dd9b1680ae 2736 }\
bogdanm 86:04dd9b1680ae 2737 }\
bogdanm 86:04dd9b1680ae 2738 } while(0)
bogdanm 86:04dd9b1680ae 2739
bogdanm 86:04dd9b1680ae 2740 /** @brief Enables or disables the specified HRTIM common interrupts.
bogdanm 86:04dd9b1680ae 2741 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2742 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 86:04dd9b1680ae 2743 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2744 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
bogdanm 86:04dd9b1680ae 2745 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
bogdanm 86:04dd9b1680ae 2746 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
bogdanm 86:04dd9b1680ae 2747 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
bogdanm 86:04dd9b1680ae 2748 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
bogdanm 86:04dd9b1680ae 2749 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
bogdanm 86:04dd9b1680ae 2750 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
bogdanm 86:04dd9b1680ae 2751 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
bogdanm 86:04dd9b1680ae 2752 * @retval None
bogdanm 86:04dd9b1680ae 2753 */
bogdanm 86:04dd9b1680ae 2754 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2755 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2756
bogdanm 86:04dd9b1680ae 2757 /** @brief Enables or disables the specified HRTIM Master timer interrupts.
bogdanm 86:04dd9b1680ae 2758 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2759 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 86:04dd9b1680ae 2760 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2761 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
bogdanm 86:04dd9b1680ae 2762 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
bogdanm 86:04dd9b1680ae 2763 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
bogdanm 86:04dd9b1680ae 2764 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
bogdanm 86:04dd9b1680ae 2765 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
bogdanm 86:04dd9b1680ae 2766 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
bogdanm 86:04dd9b1680ae 2767 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
bogdanm 86:04dd9b1680ae 2768 * @retval None
bogdanm 86:04dd9b1680ae 2769 */
bogdanm 86:04dd9b1680ae 2770 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2771 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2772
bogdanm 86:04dd9b1680ae 2773 /** @brief Enables or disables the specified HRTIM Timerx interrupts.
bogdanm 86:04dd9b1680ae 2774 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2775 * @param __TIMER__: specified the timing unit (Timer A to E)
bogdanm 86:04dd9b1680ae 2776 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 86:04dd9b1680ae 2777 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2778 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
bogdanm 86:04dd9b1680ae 2779 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
bogdanm 86:04dd9b1680ae 2780 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
bogdanm 86:04dd9b1680ae 2781 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
bogdanm 86:04dd9b1680ae 2782 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
bogdanm 86:04dd9b1680ae 2783 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
bogdanm 86:04dd9b1680ae 2784 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
bogdanm 86:04dd9b1680ae 2785 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
bogdanm 86:04dd9b1680ae 2786 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
bogdanm 86:04dd9b1680ae 2787 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
bogdanm 86:04dd9b1680ae 2788 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
bogdanm 86:04dd9b1680ae 2789 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
bogdanm 86:04dd9b1680ae 2790 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
bogdanm 86:04dd9b1680ae 2791 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
bogdanm 86:04dd9b1680ae 2792 * @retval None
bogdanm 86:04dd9b1680ae 2793 */
bogdanm 86:04dd9b1680ae 2794 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2795 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2796
bogdanm 86:04dd9b1680ae 2797 /** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
bogdanm 86:04dd9b1680ae 2798 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2799 * @param __INTERRUPT__: specifies the interrupt source to check.
bogdanm 86:04dd9b1680ae 2800 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2801 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
bogdanm 86:04dd9b1680ae 2802 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
bogdanm 86:04dd9b1680ae 2803 * @arg HRTIM_IT_FLT3: Fault 3 enable
bogdanm 86:04dd9b1680ae 2804 * @arg HRTIM_IT_FLT4: Fault 4 enable
bogdanm 86:04dd9b1680ae 2805 * @arg HRTIM_IT_FLT5: Fault 5 enable
bogdanm 86:04dd9b1680ae 2806 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
bogdanm 86:04dd9b1680ae 2807 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
bogdanm 86:04dd9b1680ae 2808 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
bogdanm 86:04dd9b1680ae 2809 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 86:04dd9b1680ae 2810 */
bogdanm 86:04dd9b1680ae 2811 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 86:04dd9b1680ae 2812
bogdanm 86:04dd9b1680ae 2813 /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
bogdanm 86:04dd9b1680ae 2814 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2815 * @param __INTERRUPT__: specifies the interrupt source to check.
bogdanm 86:04dd9b1680ae 2816 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2817 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
bogdanm 86:04dd9b1680ae 2818 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
bogdanm 86:04dd9b1680ae 2819 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
bogdanm 86:04dd9b1680ae 2820 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
bogdanm 86:04dd9b1680ae 2821 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
bogdanm 86:04dd9b1680ae 2822 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
bogdanm 86:04dd9b1680ae 2823 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
bogdanm 86:04dd9b1680ae 2824 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 86:04dd9b1680ae 2825 */
bogdanm 86:04dd9b1680ae 2826 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 86:04dd9b1680ae 2827
bogdanm 86:04dd9b1680ae 2828 /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
bogdanm 86:04dd9b1680ae 2829 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2830 * @param __TIMER__: specified the timing unit (Timer A to E)
bogdanm 86:04dd9b1680ae 2831 * @param __INTERRUPT__: specifies the interrupt source to check.
bogdanm 86:04dd9b1680ae 2832 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2833 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
bogdanm 86:04dd9b1680ae 2834 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
bogdanm 86:04dd9b1680ae 2835 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
bogdanm 86:04dd9b1680ae 2836 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
bogdanm 86:04dd9b1680ae 2837 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
bogdanm 86:04dd9b1680ae 2838 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
bogdanm 86:04dd9b1680ae 2839 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
bogdanm 86:04dd9b1680ae 2840 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
bogdanm 86:04dd9b1680ae 2841 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
bogdanm 86:04dd9b1680ae 2842 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
bogdanm 86:04dd9b1680ae 2843 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
bogdanm 86:04dd9b1680ae 2844 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
bogdanm 86:04dd9b1680ae 2845 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
bogdanm 86:04dd9b1680ae 2846 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
bogdanm 86:04dd9b1680ae 2847 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
bogdanm 86:04dd9b1680ae 2848 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
bogdanm 86:04dd9b1680ae 2849 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
bogdanm 86:04dd9b1680ae 2850 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
bogdanm 86:04dd9b1680ae 2851 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
bogdanm 86:04dd9b1680ae 2852 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
bogdanm 86:04dd9b1680ae 2853 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
bogdanm 86:04dd9b1680ae 2854 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 86:04dd9b1680ae 2855 */
bogdanm 86:04dd9b1680ae 2856 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 86:04dd9b1680ae 2857
bogdanm 86:04dd9b1680ae 2858 /** @brief Clears the specified HRTIM common pending flag.
bogdanm 86:04dd9b1680ae 2859 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2860 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 86:04dd9b1680ae 2861 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2862 * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
bogdanm 86:04dd9b1680ae 2863 * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
bogdanm 86:04dd9b1680ae 2864 * @arg HRTIM_IT_FLT3: Fault 3 clear flag
bogdanm 86:04dd9b1680ae 2865 * @arg HRTIM_IT_FLT4: Fault 4 clear flag
bogdanm 86:04dd9b1680ae 2866 * @arg HRTIM_IT_FLT5: Fault 5 clear flag
bogdanm 86:04dd9b1680ae 2867 * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
bogdanm 86:04dd9b1680ae 2868 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
bogdanm 86:04dd9b1680ae 2869 * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
bogdanm 86:04dd9b1680ae 2870 * @retval None
bogdanm 86:04dd9b1680ae 2871 */
bogdanm 86:04dd9b1680ae 2872 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2873
bogdanm 86:04dd9b1680ae 2874 /** @brief Clears the specified HRTIM Master pending flag.
bogdanm 86:04dd9b1680ae 2875 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2876 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 86:04dd9b1680ae 2877 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2878 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
bogdanm 86:04dd9b1680ae 2879 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
bogdanm 86:04dd9b1680ae 2880 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
bogdanm 86:04dd9b1680ae 2881 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
bogdanm 86:04dd9b1680ae 2882 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
bogdanm 86:04dd9b1680ae 2883 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
bogdanm 86:04dd9b1680ae 2884 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
bogdanm 86:04dd9b1680ae 2885 * @retval None
bogdanm 86:04dd9b1680ae 2886 */
bogdanm 86:04dd9b1680ae 2887 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2888
bogdanm 86:04dd9b1680ae 2889 /** @brief Clears the specified HRTIM Timerx pending flag.
bogdanm 86:04dd9b1680ae 2890 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2891 * @param __TIMER__: specified the timing unit (Timer A to E)
bogdanm 86:04dd9b1680ae 2892 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 86:04dd9b1680ae 2893 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2894 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
bogdanm 86:04dd9b1680ae 2895 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
bogdanm 86:04dd9b1680ae 2896 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
bogdanm 86:04dd9b1680ae 2897 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
bogdanm 86:04dd9b1680ae 2898 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
bogdanm 86:04dd9b1680ae 2899 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
bogdanm 86:04dd9b1680ae 2900 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
bogdanm 86:04dd9b1680ae 2901 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
bogdanm 86:04dd9b1680ae 2902 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
bogdanm 86:04dd9b1680ae 2903 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
bogdanm 86:04dd9b1680ae 2904 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
bogdanm 86:04dd9b1680ae 2905 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
bogdanm 86:04dd9b1680ae 2906 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
bogdanm 86:04dd9b1680ae 2907 * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
bogdanm 86:04dd9b1680ae 2908 * @retval None
bogdanm 86:04dd9b1680ae 2909 */
bogdanm 86:04dd9b1680ae 2910 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2911
bogdanm 86:04dd9b1680ae 2912 /* DMA HANDLING */
bogdanm 86:04dd9b1680ae 2913 /** @brief Enables or disables the specified HRTIM common interrupts.
bogdanm 86:04dd9b1680ae 2914 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2915 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 86:04dd9b1680ae 2916 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2917 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
bogdanm 86:04dd9b1680ae 2918 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
bogdanm 86:04dd9b1680ae 2919 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
bogdanm 86:04dd9b1680ae 2920 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
bogdanm 86:04dd9b1680ae 2921 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
bogdanm 86:04dd9b1680ae 2922 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
bogdanm 86:04dd9b1680ae 2923 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
bogdanm 86:04dd9b1680ae 2924 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
bogdanm 86:04dd9b1680ae 2925 * @retval None
bogdanm 86:04dd9b1680ae 2926 */
bogdanm 86:04dd9b1680ae 2927 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2928 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 2929
bogdanm 86:04dd9b1680ae 2930 /** @brief Enables or disables the specified HRTIM Master timer DMA requets.
bogdanm 86:04dd9b1680ae 2931 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2932 * @param __DMA__: specifies the DMA request to enable or disable.
bogdanm 86:04dd9b1680ae 2933 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2934 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
bogdanm 86:04dd9b1680ae 2935 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
bogdanm 86:04dd9b1680ae 2936 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
bogdanm 86:04dd9b1680ae 2937 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
bogdanm 86:04dd9b1680ae 2938 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
bogdanm 86:04dd9b1680ae 2939 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
bogdanm 86:04dd9b1680ae 2940 * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
bogdanm 86:04dd9b1680ae 2941 * @retval None
bogdanm 86:04dd9b1680ae 2942 */
bogdanm 86:04dd9b1680ae 2943 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
bogdanm 86:04dd9b1680ae 2944 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
bogdanm 86:04dd9b1680ae 2945
bogdanm 86:04dd9b1680ae 2946 /** @brief Enables or disables the specified HRTIM Timerx DMA requests.
bogdanm 86:04dd9b1680ae 2947 * @param __HANDLE__: specifies the HRTIM Handle.
bogdanm 86:04dd9b1680ae 2948 * @param __TIMER__: specified the timing unit (Timer A to E)
bogdanm 86:04dd9b1680ae 2949 * @param __DMA__: specifies the DMA request to enable or disable.
bogdanm 86:04dd9b1680ae 2950 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2951 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
bogdanm 86:04dd9b1680ae 2952 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
bogdanm 86:04dd9b1680ae 2953 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
bogdanm 86:04dd9b1680ae 2954 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
bogdanm 86:04dd9b1680ae 2955 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
bogdanm 86:04dd9b1680ae 2956 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
bogdanm 86:04dd9b1680ae 2957 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
bogdanm 86:04dd9b1680ae 2958 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
bogdanm 86:04dd9b1680ae 2959 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
bogdanm 86:04dd9b1680ae 2960 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
bogdanm 86:04dd9b1680ae 2961 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
bogdanm 86:04dd9b1680ae 2962 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
bogdanm 86:04dd9b1680ae 2963 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
bogdanm 86:04dd9b1680ae 2964 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
bogdanm 86:04dd9b1680ae 2965 * @retval None
bogdanm 86:04dd9b1680ae 2966 */
bogdanm 86:04dd9b1680ae 2967 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
bogdanm 86:04dd9b1680ae 2968 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
bogdanm 86:04dd9b1680ae 2969
bogdanm 86:04dd9b1680ae 2970 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
bogdanm 86:04dd9b1680ae 2971 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
bogdanm 86:04dd9b1680ae 2972
bogdanm 86:04dd9b1680ae 2973 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
bogdanm 86:04dd9b1680ae 2974 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
bogdanm 86:04dd9b1680ae 2975
bogdanm 86:04dd9b1680ae 2976 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
bogdanm 86:04dd9b1680ae 2977 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
bogdanm 86:04dd9b1680ae 2978
bogdanm 86:04dd9b1680ae 2979 /** @brief Sets the HRTIM timer Counter Register value on runtime
bogdanm 86:04dd9b1680ae 2980 * @param __HANDLE__: HRTIM Handle.
bogdanm 86:04dd9b1680ae 2981 * @param __TIMER__: HRTIM timer
bogdanm 86:04dd9b1680ae 2982 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2983 * @arg 0x5 for master timer
bogdanm 86:04dd9b1680ae 2984 * @arg 0x0 to 0x4 for timers A to E
bogdanm 86:04dd9b1680ae 2985 * @param __COUNTER__: specifies the Counter Register new value.
bogdanm 86:04dd9b1680ae 2986 * @retval None
bogdanm 86:04dd9b1680ae 2987 */
bogdanm 86:04dd9b1680ae 2988 #define __HAL_HRTIM_SetCounter(__HANDLE__, __TIMER__, __COUNTER__) \
bogdanm 86:04dd9b1680ae 2989 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
bogdanm 86:04dd9b1680ae 2990 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
bogdanm 86:04dd9b1680ae 2991
bogdanm 86:04dd9b1680ae 2992 /** @brief Gets the HRTIM timer Counter Register value on runtime
bogdanm 86:04dd9b1680ae 2993 * @param __HANDLE__: HRTIM Handle.
bogdanm 86:04dd9b1680ae 2994 * @param __TIMER__: HRTIM timer
bogdanm 86:04dd9b1680ae 2995 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 2996 * @arg 0x5 for master timer
bogdanm 86:04dd9b1680ae 2997 * @arg 0x0 to 0x4 for timers A to E
bogdanm 86:04dd9b1680ae 2998 * @retval HRTIM timer Counter Register value
bogdanm 86:04dd9b1680ae 2999 */
bogdanm 86:04dd9b1680ae 3000 #define __HAL_HRTIM_GetCounter(__HANDLE__, __TIMER__) \
bogdanm 86:04dd9b1680ae 3001 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
bogdanm 86:04dd9b1680ae 3002 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
bogdanm 86:04dd9b1680ae 3003
bogdanm 86:04dd9b1680ae 3004 /** @brief Sets the HRTIM timer Period value on runtime
bogdanm 86:04dd9b1680ae 3005 * @param __HANDLE__: HRTIM Handle.
bogdanm 86:04dd9b1680ae 3006 * @param __TIMER__: HRTIM timer
bogdanm 86:04dd9b1680ae 3007 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 3008 * @arg 0x5 for master timer
bogdanm 86:04dd9b1680ae 3009 * @arg 0x0 to 0x4 for timers A to E
bogdanm 86:04dd9b1680ae 3010 * @param __PERIOD__: specifies the Period Register new value.
bogdanm 86:04dd9b1680ae 3011 * @retval None
bogdanm 86:04dd9b1680ae 3012 */
bogdanm 86:04dd9b1680ae 3013 #define __HAL_HRTIM_SetPeriod(__HANDLE__, __TIMER__, __PERIOD__) \
bogdanm 86:04dd9b1680ae 3014 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
bogdanm 86:04dd9b1680ae 3015 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
bogdanm 86:04dd9b1680ae 3016
bogdanm 86:04dd9b1680ae 3017 /** @brief Gets the HRTIM timer Period Register value on runtime
bogdanm 86:04dd9b1680ae 3018 * @param __HANDLE__: HRTIM Handle.
bogdanm 86:04dd9b1680ae 3019 * @param __TIMER__: HRTIM timer
bogdanm 86:04dd9b1680ae 3020 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 3021 * @arg 0x5 for master timer
bogdanm 86:04dd9b1680ae 3022 * @arg 0x0 to 0x4 for timers A to E
bogdanm 86:04dd9b1680ae 3023 * @retval timer Period Register
bogdanm 86:04dd9b1680ae 3024 */
bogdanm 86:04dd9b1680ae 3025 #define __HAL_HRTIM_GetPeriod(__HANDLE__, __TIMER__) \
bogdanm 86:04dd9b1680ae 3026 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
bogdanm 86:04dd9b1680ae 3027 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
bogdanm 86:04dd9b1680ae 3028
bogdanm 86:04dd9b1680ae 3029 /** @brief Sets the HRTIM timer clock prescaler value on runtime
bogdanm 86:04dd9b1680ae 3030 * @param __HANDLE__: HRTIM Handle.
bogdanm 86:04dd9b1680ae 3031 * @param __TIMER__: HRTIM timer
bogdanm 86:04dd9b1680ae 3032 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 3033 * @arg 0x5 for master timer
bogdanm 86:04dd9b1680ae 3034 * @arg 0x0 to 0x4 for timers A to E
bogdanm 86:04dd9b1680ae 3035 * @param __PRESCALER__: specifies the clock prescaler new value.
bogdanm 86:04dd9b1680ae 3036 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 3037 * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
bogdanm 86:04dd9b1680ae 3038 * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
bogdanm 86:04dd9b1680ae 3039 * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
bogdanm 86:04dd9b1680ae 3040 * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
bogdanm 86:04dd9b1680ae 3041 * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
bogdanm 86:04dd9b1680ae 3042 * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
bogdanm 86:04dd9b1680ae 3043 * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
bogdanm 86:04dd9b1680ae 3044 * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
bogdanm 86:04dd9b1680ae 3045 * @retval None
bogdanm 86:04dd9b1680ae 3046 */
bogdanm 86:04dd9b1680ae 3047 #define __HAL_HRTIM_SetClockPrescaler(__HANDLE__, __TIMER__, __PRESCALER__) \
bogdanm 86:04dd9b1680ae 3048 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__PRESCALER__)) :\
bogdanm 86:04dd9b1680ae 3049 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR |= (__PRESCALER__)))
bogdanm 86:04dd9b1680ae 3050
bogdanm 86:04dd9b1680ae 3051 /** @brief Gets the HRTIM timer clock prescaler value on runtime
bogdanm 86:04dd9b1680ae 3052 * @param __HANDLE__: HRTIM Handle.
bogdanm 86:04dd9b1680ae 3053 * @param __TIMER__: HRTIM timer
bogdanm 86:04dd9b1680ae 3054 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 3055 * @arg 0x5 for master timer
bogdanm 86:04dd9b1680ae 3056 * @arg 0x0 to 0x4 for timers A to E
bogdanm 86:04dd9b1680ae 3057 * @retval timer clock prescaler value
bogdanm 86:04dd9b1680ae 3058 */
bogdanm 86:04dd9b1680ae 3059 #define __HAL_HRTIM_GetClockPrescaler(__HANDLE__, __TIMER__) \
bogdanm 86:04dd9b1680ae 3060 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
bogdanm 86:04dd9b1680ae 3061 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
bogdanm 86:04dd9b1680ae 3062
bogdanm 86:04dd9b1680ae 3063 /** @brief Sets the HRTIM timer Compare Register value on runtime
bogdanm 86:04dd9b1680ae 3064 * @param __HANDLE__: HRTIM Handle.
bogdanm 86:04dd9b1680ae 3065 * @param __TIMER__: HRTIM timer
bogdanm 86:04dd9b1680ae 3066 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 3067 * @arg 0x0 to 0x4 for timers A to E
bogdanm 86:04dd9b1680ae 3068 * @param __COMPAREUNIT__: timer compare unit
bogdanm 86:04dd9b1680ae 3069 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 3070 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
bogdanm 86:04dd9b1680ae 3071 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
bogdanm 86:04dd9b1680ae 3072 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
bogdanm 86:04dd9b1680ae 3073 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
bogdanm 86:04dd9b1680ae 3074 * @param __COMPARE__: specifies the Compare new value.
bogdanm 86:04dd9b1680ae 3075 * @retval None
bogdanm 86:04dd9b1680ae 3076 */
bogdanm 86:04dd9b1680ae 3077 #define __HAL_HRTIM_SetCompare(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
bogdanm 86:04dd9b1680ae 3078 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
bogdanm 86:04dd9b1680ae 3079 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 3080 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 3081 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 3082 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
bogdanm 86:04dd9b1680ae 3083 : \
bogdanm 86:04dd9b1680ae 3084 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 3085 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 3086 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
bogdanm 86:04dd9b1680ae 3087 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
bogdanm 86:04dd9b1680ae 3088
bogdanm 86:04dd9b1680ae 3089 /** @brief Gets the HRTIM timer Compare Register value on runtime
bogdanm 86:04dd9b1680ae 3090 * @param __HANDLE__: HRTIM Handle.
bogdanm 86:04dd9b1680ae 3091 * @param __TIMER__: HRTIM timer
bogdanm 86:04dd9b1680ae 3092 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 3093 * @arg 0x0 to 0x4 for timers A to E
bogdanm 86:04dd9b1680ae 3094 * @param __COMPAREUNIT__: timer compare unit
bogdanm 86:04dd9b1680ae 3095 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 3096 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
bogdanm 86:04dd9b1680ae 3097 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
bogdanm 86:04dd9b1680ae 3098 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
bogdanm 86:04dd9b1680ae 3099 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
bogdanm 86:04dd9b1680ae 3100 * @retval Compare value
bogdanm 86:04dd9b1680ae 3101 */
bogdanm 86:04dd9b1680ae 3102 #define __HAL_HRTIM_GetCompare(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
bogdanm 86:04dd9b1680ae 3103 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
bogdanm 86:04dd9b1680ae 3104 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
bogdanm 86:04dd9b1680ae 3105 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
bogdanm 86:04dd9b1680ae 3106 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
bogdanm 86:04dd9b1680ae 3107 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
bogdanm 86:04dd9b1680ae 3108 : \
bogdanm 86:04dd9b1680ae 3109 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
bogdanm 86:04dd9b1680ae 3110 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
bogdanm 86:04dd9b1680ae 3111 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
bogdanm 86:04dd9b1680ae 3112 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
bogdanm 86:04dd9b1680ae 3113
bogdanm 86:04dd9b1680ae 3114 /* Exported functions --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 3115
bogdanm 86:04dd9b1680ae 3116 /* HRTIM common functions *****************************************************/
bogdanm 86:04dd9b1680ae 3117 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3118
bogdanm 86:04dd9b1680ae 3119 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3120
bogdanm 86:04dd9b1680ae 3121 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3122
bogdanm 86:04dd9b1680ae 3123 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3124
bogdanm 86:04dd9b1680ae 3125 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3126 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3127 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
bogdanm 86:04dd9b1680ae 3128
bogdanm 86:04dd9b1680ae 3129 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3130 uint32_t CalibrationRate);
bogdanm 86:04dd9b1680ae 3131
bogdanm 86:04dd9b1680ae 3132 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3133 uint32_t CalibrationRate);
bogdanm 86:04dd9b1680ae 3134
bogdanm 86:04dd9b1680ae 3135 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3136 uint32_t Timeout);
bogdanm 86:04dd9b1680ae 3137
bogdanm 86:04dd9b1680ae 3138 /* Simple time base related functions *****************************************/
bogdanm 86:04dd9b1680ae 3139 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3140 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3141
bogdanm 86:04dd9b1680ae 3142 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3143 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3144
bogdanm 86:04dd9b1680ae 3145 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3146 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3147
bogdanm 86:04dd9b1680ae 3148 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3149 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3150
bogdanm 86:04dd9b1680ae 3151 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3152 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3153 uint32_t SrcAddr,
bogdanm 86:04dd9b1680ae 3154 uint32_t DestAddr,
bogdanm 86:04dd9b1680ae 3155 uint32_t Length);
bogdanm 86:04dd9b1680ae 3156
bogdanm 86:04dd9b1680ae 3157 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3158 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3159
bogdanm 86:04dd9b1680ae 3160 /* Simple output compare related functions ************************************/
bogdanm 86:04dd9b1680ae 3161 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3162 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3163 uint32_t OCChannel,
bogdanm 86:04dd9b1680ae 3164 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
bogdanm 86:04dd9b1680ae 3165
bogdanm 86:04dd9b1680ae 3166 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3167 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3168 uint32_t OCChannel);
bogdanm 86:04dd9b1680ae 3169
bogdanm 86:04dd9b1680ae 3170 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3171 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3172 uint32_t OCChannel);
bogdanm 86:04dd9b1680ae 3173
bogdanm 86:04dd9b1680ae 3174 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3175 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3176 uint32_t OCChannel);
bogdanm 86:04dd9b1680ae 3177
bogdanm 86:04dd9b1680ae 3178 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3179 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3180 uint32_t OCChannel);
bogdanm 86:04dd9b1680ae 3181
bogdanm 86:04dd9b1680ae 3182 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3183 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3184 uint32_t OCChannel,
bogdanm 86:04dd9b1680ae 3185 uint32_t SrcAddr,
bogdanm 86:04dd9b1680ae 3186 uint32_t DestAddr,
bogdanm 86:04dd9b1680ae 3187 uint32_t Length);
bogdanm 86:04dd9b1680ae 3188
bogdanm 86:04dd9b1680ae 3189 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3190 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3191 uint32_t OCChannel);
bogdanm 86:04dd9b1680ae 3192
bogdanm 86:04dd9b1680ae 3193 /* Simple PWM output related functions ****************************************/
bogdanm 86:04dd9b1680ae 3194 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3195 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3196 uint32_t PWMChannel,
bogdanm 86:04dd9b1680ae 3197 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
bogdanm 86:04dd9b1680ae 3198
bogdanm 86:04dd9b1680ae 3199 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3200 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3201 uint32_t PWMChannel);
bogdanm 86:04dd9b1680ae 3202
bogdanm 86:04dd9b1680ae 3203 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3204 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3205 uint32_t PWMChannel);
bogdanm 86:04dd9b1680ae 3206
bogdanm 86:04dd9b1680ae 3207 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3208 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3209 uint32_t PWMChannel);
bogdanm 86:04dd9b1680ae 3210
bogdanm 86:04dd9b1680ae 3211 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3212 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3213 uint32_t PWMChannel);
bogdanm 86:04dd9b1680ae 3214
bogdanm 86:04dd9b1680ae 3215 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3216 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3217 uint32_t PWMChannel,
bogdanm 86:04dd9b1680ae 3218 uint32_t SrcAddr,
bogdanm 86:04dd9b1680ae 3219 uint32_t DestAddr,
bogdanm 86:04dd9b1680ae 3220 uint32_t Length);
bogdanm 86:04dd9b1680ae 3221
bogdanm 86:04dd9b1680ae 3222 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3223 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3224 uint32_t PWMChannel);
bogdanm 86:04dd9b1680ae 3225
bogdanm 86:04dd9b1680ae 3226 /* Simple capture related functions *******************************************/
bogdanm 86:04dd9b1680ae 3227 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3228 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3229 uint32_t CaptureChannel,
bogdanm 86:04dd9b1680ae 3230 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
bogdanm 86:04dd9b1680ae 3231
bogdanm 86:04dd9b1680ae 3232 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3233 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3234 uint32_t CaptureChannel);
bogdanm 86:04dd9b1680ae 3235
bogdanm 86:04dd9b1680ae 3236 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3237 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3238 uint32_t CaptureChannel);
bogdanm 86:04dd9b1680ae 3239
bogdanm 86:04dd9b1680ae 3240 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3241 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3242 uint32_t CaptureChannel);
bogdanm 86:04dd9b1680ae 3243
bogdanm 86:04dd9b1680ae 3244 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3245 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3246 uint32_t CaptureChannel);
bogdanm 86:04dd9b1680ae 3247
bogdanm 86:04dd9b1680ae 3248 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3249 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3250 uint32_t CaptureChannel,
bogdanm 86:04dd9b1680ae 3251 uint32_t SrcAddr,
bogdanm 86:04dd9b1680ae 3252 uint32_t DestAddr,
bogdanm 86:04dd9b1680ae 3253 uint32_t Length);
bogdanm 86:04dd9b1680ae 3254
bogdanm 86:04dd9b1680ae 3255 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3256 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3257 uint32_t CaptureChannel);
bogdanm 86:04dd9b1680ae 3258
bogdanm 86:04dd9b1680ae 3259 /* Simple one pulse related functions *****************************************/
bogdanm 86:04dd9b1680ae 3260 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3261 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3262 uint32_t OnePulseChannel,
bogdanm 86:04dd9b1680ae 3263 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
bogdanm 86:04dd9b1680ae 3264
bogdanm 86:04dd9b1680ae 3265 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3266 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3267 uint32_t OnePulseChannel);
bogdanm 86:04dd9b1680ae 3268
bogdanm 86:04dd9b1680ae 3269 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3270 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3271 uint32_t OnePulseChannel);
bogdanm 86:04dd9b1680ae 3272
bogdanm 86:04dd9b1680ae 3273 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3274 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3275 uint32_t OnePulseChannel);
bogdanm 86:04dd9b1680ae 3276
bogdanm 86:04dd9b1680ae 3277 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3278 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3279 uint32_t OnePulseChannel);
bogdanm 86:04dd9b1680ae 3280
bogdanm 86:04dd9b1680ae 3281 /* Waveform related functions *************************************************/
bogdanm 86:04dd9b1680ae 3282 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3283 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3284 HRTIM_TimerCfgTypeDef * pTimerCfg);
bogdanm 86:04dd9b1680ae 3285
bogdanm 86:04dd9b1680ae 3286 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3287 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3288 uint32_t CompareUnit,
bogdanm 86:04dd9b1680ae 3289 HRTIM_CompareCfgTypeDef* pCompareCfg);
bogdanm 86:04dd9b1680ae 3290
bogdanm 86:04dd9b1680ae 3291 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3292 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3293 uint32_t CaptureUnit,
bogdanm 86:04dd9b1680ae 3294 HRTIM_CaptureCfgTypeDef* pCaptureCfg);
bogdanm 86:04dd9b1680ae 3295
bogdanm 86:04dd9b1680ae 3296 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3297 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3298 uint32_t Output,
bogdanm 86:04dd9b1680ae 3299 HRTIM_OutputCfgTypeDef * pOutputCfg);
bogdanm 86:04dd9b1680ae 3300
bogdanm 86:04dd9b1680ae 3301 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3302 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3303 uint32_t Event,
bogdanm 86:04dd9b1680ae 3304 HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
bogdanm 86:04dd9b1680ae 3305
bogdanm 86:04dd9b1680ae 3306 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3307 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3308 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
bogdanm 86:04dd9b1680ae 3309
bogdanm 86:04dd9b1680ae 3310 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3311 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3312 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
bogdanm 86:04dd9b1680ae 3313
bogdanm 86:04dd9b1680ae 3314 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3315 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3316 uint32_t RegistersToUpdate);
bogdanm 86:04dd9b1680ae 3317
bogdanm 86:04dd9b1680ae 3318 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3319 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
bogdanm 86:04dd9b1680ae 3320
bogdanm 86:04dd9b1680ae 3321 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3322 uint32_t Event,
bogdanm 86:04dd9b1680ae 3323 HRTIM_EventCfgTypeDef* pEventCfg);
bogdanm 86:04dd9b1680ae 3324
bogdanm 86:04dd9b1680ae 3325 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3326 uint32_t Prescaler);
bogdanm 86:04dd9b1680ae 3327
bogdanm 86:04dd9b1680ae 3328 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3329 uint32_t Fault,
bogdanm 86:04dd9b1680ae 3330 HRTIM_FaultCfgTypeDef* pFaultCfg);
bogdanm 86:04dd9b1680ae 3331
bogdanm 86:04dd9b1680ae 3332 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3333 uint32_t Prescaler);
bogdanm 86:04dd9b1680ae 3334
bogdanm 86:04dd9b1680ae 3335 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3336 uint32_t ADCTrigger,
bogdanm 86:04dd9b1680ae 3337 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
bogdanm 86:04dd9b1680ae 3338
bogdanm 86:04dd9b1680ae 3339 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3340 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3341
bogdanm 86:04dd9b1680ae 3342 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3343 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3344
bogdanm 86:04dd9b1680ae 3345
bogdanm 86:04dd9b1680ae 3346 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3347 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3348
bogdanm 86:04dd9b1680ae 3349 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3350 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3351
bogdanm 86:04dd9b1680ae 3352
bogdanm 86:04dd9b1680ae 3353 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3354 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3355
bogdanm 86:04dd9b1680ae 3356 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3357 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3358
bogdanm 86:04dd9b1680ae 3359 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3360 uint32_t OutputsToStart);
bogdanm 86:04dd9b1680ae 3361
bogdanm 86:04dd9b1680ae 3362 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3363 uint32_t OutputsToStop);
bogdanm 86:04dd9b1680ae 3364
bogdanm 86:04dd9b1680ae 3365 /* IRQ handler */
bogdanm 86:04dd9b1680ae 3366 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3367 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3368
bogdanm 86:04dd9b1680ae 3369 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3370 uint32_t Enable);
bogdanm 86:04dd9b1680ae 3371
bogdanm 86:04dd9b1680ae 3372 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3373
bogdanm 86:04dd9b1680ae 3374 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
bogdanm 86:04dd9b1680ae 3375 uint32_t Faults,
bogdanm 86:04dd9b1680ae 3376 uint32_t Enable);
bogdanm 86:04dd9b1680ae 3377
bogdanm 86:04dd9b1680ae 3378 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3379 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3380 uint32_t CaptureUnit);
bogdanm 86:04dd9b1680ae 3381
bogdanm 86:04dd9b1680ae 3382 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3383 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3384
bogdanm 86:04dd9b1680ae 3385 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3386 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3387
bogdanm 86:04dd9b1680ae 3388 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
bogdanm 86:04dd9b1680ae 3389
bogdanm 86:04dd9b1680ae 3390 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3391 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3392
bogdanm 86:04dd9b1680ae 3393 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3394 uint32_t Timers);
bogdanm 86:04dd9b1680ae 3395
bogdanm 86:04dd9b1680ae 3396 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3397 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3398 uint32_t BurstBufferAddress,
bogdanm 86:04dd9b1680ae 3399 uint32_t BurstBufferLength);
bogdanm 86:04dd9b1680ae 3400
bogdanm 86:04dd9b1680ae 3401 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3402 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3403 uint32_t CaptureUnit);
bogdanm 86:04dd9b1680ae 3404
bogdanm 86:04dd9b1680ae 3405 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3406 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3407 uint32_t Output,
bogdanm 86:04dd9b1680ae 3408 uint32_t OutputLevel);
bogdanm 86:04dd9b1680ae 3409
bogdanm 86:04dd9b1680ae 3410 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3411 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3412 uint32_t Output);
bogdanm 86:04dd9b1680ae 3413
bogdanm 86:04dd9b1680ae 3414 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
bogdanm 86:04dd9b1680ae 3415 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3416 uint32_t Output);
bogdanm 86:04dd9b1680ae 3417
bogdanm 86:04dd9b1680ae 3418 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3419 uint32_t TimerIdx,
bogdanm 86:04dd9b1680ae 3420 uint32_t Output);
bogdanm 86:04dd9b1680ae 3421
bogdanm 86:04dd9b1680ae 3422 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3423
bogdanm 86:04dd9b1680ae 3424 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3425 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3426
bogdanm 86:04dd9b1680ae 3427 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3428 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3429
bogdanm 86:04dd9b1680ae 3430 /* HRTIM events related callback functions */
bogdanm 86:04dd9b1680ae 3431 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3432 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3433 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3434 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3435 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3436 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3437 void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3438 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3439 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3440
bogdanm 86:04dd9b1680ae 3441 /* Timer events related callback functions */
bogdanm 86:04dd9b1680ae 3442 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3443 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3444 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3445 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3446 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3447 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3448 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3449 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3450 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3451 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3452 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3453 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3454 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3455 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3456 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3457 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3458 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3459 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3460 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3461 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3462 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3463 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3464 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3465 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3466 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3467 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3468 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3469 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3470 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
bogdanm 86:04dd9b1680ae 3471 uint32_t TimerIdx);
bogdanm 86:04dd9b1680ae 3472 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
bogdanm 86:04dd9b1680ae 3473
bogdanm 86:04dd9b1680ae 3474 /**
bogdanm 86:04dd9b1680ae 3475 * @}
bogdanm 86:04dd9b1680ae 3476 */
bogdanm 86:04dd9b1680ae 3477
bogdanm 86:04dd9b1680ae 3478 /**
bogdanm 86:04dd9b1680ae 3479 * @}
bogdanm 86:04dd9b1680ae 3480 */
bogdanm 86:04dd9b1680ae 3481
bogdanm 86:04dd9b1680ae 3482 #endif /* defined(STM32F334x8) */
bogdanm 86:04dd9b1680ae 3483
bogdanm 86:04dd9b1680ae 3484 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 3485 }
bogdanm 86:04dd9b1680ae 3486 #endif
bogdanm 86:04dd9b1680ae 3487
bogdanm 86:04dd9b1680ae 3488 #endif /* __STM32F3xx_HAL_HRTIM_H */
bogdanm 86:04dd9b1680ae 3489
bogdanm 86:04dd9b1680ae 3490 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/