不韋 呂 / F746_SD_Player_Demo

Demo program for library named SD_PlayerSkeleton of SD card player skeleton. SD カードプレーヤのための骨組みとして使うためのライブラリ SD_PlayerSkeleton の使用例．このプログラムについては，CQ出版社インターフェース誌 2018年7月号で解説している．

Dependencies:   F746_GUI F746_SAI_IO SD_PlayerSkeleton

mbed_src_STM32F7/common/SPI.cpp@19:3c3833ec00d2, 2017-04-09 (annotated)

Committer:
MikamiUitOpen
Date:
Sun Apr 09 12:44:17 2017 +0000
Revision:
19:3c3833ec00d2
Parent:
2:cf42e62a97dc 
20

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 2:cf42e62a97dc 1 /* mbed Microcontroller Library
MikamiUitOpen 2:cf42e62a97dc 2 * Copyright (c) 2006-2013 ARM Limited
MikamiUitOpen 2:cf42e62a97dc 3 *
MikamiUitOpen 2:cf42e62a97dc 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 2:cf42e62a97dc 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 2:cf42e62a97dc 6 * You may obtain a copy of the License at
MikamiUitOpen 2:cf42e62a97dc 7 *
MikamiUitOpen 2:cf42e62a97dc 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 2:cf42e62a97dc 9 *
MikamiUitOpen 2:cf42e62a97dc 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 2:cf42e62a97dc 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 2:cf42e62a97dc 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 2:cf42e62a97dc 13 * See the License for the specific language governing permissions and
MikamiUitOpen 2:cf42e62a97dc 14 * limitations under the License.
MikamiUitOpen 2:cf42e62a97dc 15 */
MikamiUitOpen 2:cf42e62a97dc 16 #include "SPI.h"
MikamiUitOpen 2:cf42e62a97dc 17
MikamiUitOpen 2:cf42e62a97dc 18 #if DEVICE_SPI
MikamiUitOpen 2:cf42e62a97dc 19
MikamiUitOpen 2:cf42e62a97dc 20 namespace mbed {
MikamiUitOpen 2:cf42e62a97dc 21
MikamiUitOpen 2:cf42e62a97dc 22 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 2:cf42e62a97dc 23 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
MikamiUitOpen 2:cf42e62a97dc 24 #endif
MikamiUitOpen 2:cf42e62a97dc 25
MikamiUitOpen 2:cf42e62a97dc 26 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
MikamiUitOpen 2:cf42e62a97dc 27 _spi(),
MikamiUitOpen 2:cf42e62a97dc 28 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 2:cf42e62a97dc 29 _irq(this),
MikamiUitOpen 2:cf42e62a97dc 30 _usage(DMA_USAGE_NEVER),
MikamiUitOpen 2:cf42e62a97dc 31 #endif
MikamiUitOpen 2:cf42e62a97dc 32 _bits(8),
MikamiUitOpen 2:cf42e62a97dc 33 _mode(0),
MikamiUitOpen 2:cf42e62a97dc 34 _hz(1000000) {
MikamiUitOpen 2:cf42e62a97dc 35 spi_init(&_spi, mosi, miso, sclk, ssel);
MikamiUitOpen 2:cf42e62a97dc 36 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 2:cf42e62a97dc 37 spi_frequency(&_spi, _hz);
MikamiUitOpen 2:cf42e62a97dc 38 }
MikamiUitOpen 2:cf42e62a97dc 39
MikamiUitOpen 2:cf42e62a97dc 40 void SPI::format(int bits, int mode) {
MikamiUitOpen 2:cf42e62a97dc 41 _bits = bits;
MikamiUitOpen 2:cf42e62a97dc 42 _mode = mode;
MikamiUitOpen 2:cf42e62a97dc 43 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 2:cf42e62a97dc 44 aquire();
MikamiUitOpen 2:cf42e62a97dc 45 }
MikamiUitOpen 2:cf42e62a97dc 46
MikamiUitOpen 2:cf42e62a97dc 47 void SPI::frequency(int hz) {
MikamiUitOpen 2:cf42e62a97dc 48 _hz = hz;
MikamiUitOpen 2:cf42e62a97dc 49 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
MikamiUitOpen 2:cf42e62a97dc 50 aquire();
MikamiUitOpen 2:cf42e62a97dc 51 }
MikamiUitOpen 2:cf42e62a97dc 52
MikamiUitOpen 2:cf42e62a97dc 53 SPI* SPI::_owner = NULL;
MikamiUitOpen 2:cf42e62a97dc 54
MikamiUitOpen 2:cf42e62a97dc 55 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
MikamiUitOpen 2:cf42e62a97dc 56 void SPI::aquire() {
MikamiUitOpen 2:cf42e62a97dc 57 if (_owner != this) {
MikamiUitOpen 2:cf42e62a97dc 58 spi_format(&_spi, _bits, _mode, 0);
MikamiUitOpen 2:cf42e62a97dc 59 spi_frequency(&_spi, _hz);
MikamiUitOpen 2:cf42e62a97dc 60 _owner = this;
MikamiUitOpen 2:cf42e62a97dc 61 }
MikamiUitOpen 2:cf42e62a97dc 62 }
MikamiUitOpen 2:cf42e62a97dc 63
MikamiUitOpen 2:cf42e62a97dc 64 int SPI::write(int value) {
MikamiUitOpen 2:cf42e62a97dc 65 aquire();
MikamiUitOpen 2:cf42e62a97dc 66 return spi_master_write(&_spi, value);
MikamiUitOpen 2:cf42e62a97dc 67 }
MikamiUitOpen 2:cf42e62a97dc 68
MikamiUitOpen 2:cf42e62a97dc 69 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 2:cf42e62a97dc 70
MikamiUitOpen 2:cf42e62a97dc 71 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 2:cf42e62a97dc 72 {
MikamiUitOpen 2:cf42e62a97dc 73 if (spi_active(&_spi)) {
MikamiUitOpen 2:cf42e62a97dc 74 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 2:cf42e62a97dc 75 }
MikamiUitOpen 2:cf42e62a97dc 76 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
MikamiUitOpen 2:cf42e62a97dc 77 return 0;
MikamiUitOpen 2:cf42e62a97dc 78 }
MikamiUitOpen 2:cf42e62a97dc 79
MikamiUitOpen 2:cf42e62a97dc 80 void SPI::abort_transfer()
MikamiUitOpen 2:cf42e62a97dc 81 {
MikamiUitOpen 2:cf42e62a97dc 82 spi_abort_asynch(&_spi);
MikamiUitOpen 2:cf42e62a97dc 83 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 2:cf42e62a97dc 84 dequeue_transaction();
MikamiUitOpen 2:cf42e62a97dc 85 #endif
MikamiUitOpen 2:cf42e62a97dc 86 }
MikamiUitOpen 2:cf42e62a97dc 87
MikamiUitOpen 2:cf42e62a97dc 88
MikamiUitOpen 2:cf42e62a97dc 89 void SPI::clear_transfer_buffer()
MikamiUitOpen 2:cf42e62a97dc 90 {
MikamiUitOpen 2:cf42e62a97dc 91 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 2:cf42e62a97dc 92 _transaction_buffer.reset();
MikamiUitOpen 2:cf42e62a97dc 93 #endif
MikamiUitOpen 2:cf42e62a97dc 94 }
MikamiUitOpen 2:cf42e62a97dc 95
MikamiUitOpen 2:cf42e62a97dc 96 void SPI::abort_all_transfers()
MikamiUitOpen 2:cf42e62a97dc 97 {
MikamiUitOpen 2:cf42e62a97dc 98 clear_transfer_buffer();
MikamiUitOpen 2:cf42e62a97dc 99 abort_transfer();
MikamiUitOpen 2:cf42e62a97dc 100 }
MikamiUitOpen 2:cf42e62a97dc 101
MikamiUitOpen 2:cf42e62a97dc 102 int SPI::set_dma_usage(DMAUsage usage)
MikamiUitOpen 2:cf42e62a97dc 103 {
MikamiUitOpen 2:cf42e62a97dc 104 if (spi_active(&_spi)) {
MikamiUitOpen 2:cf42e62a97dc 105 return -1;
MikamiUitOpen 2:cf42e62a97dc 106 }
MikamiUitOpen 2:cf42e62a97dc 107 _usage = usage;
MikamiUitOpen 2:cf42e62a97dc 108 return 0;
MikamiUitOpen 2:cf42e62a97dc 109 }
MikamiUitOpen 2:cf42e62a97dc 110
MikamiUitOpen 2:cf42e62a97dc 111 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 2:cf42e62a97dc 112 {
MikamiUitOpen 2:cf42e62a97dc 113 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 2:cf42e62a97dc 114 transaction_t t;
MikamiUitOpen 2:cf42e62a97dc 115
MikamiUitOpen 2:cf42e62a97dc 116 t.tx_buffer = const_cast<void *>(tx_buffer);
MikamiUitOpen 2:cf42e62a97dc 117 t.tx_length = tx_length;
MikamiUitOpen 2:cf42e62a97dc 118 t.rx_buffer = rx_buffer;
MikamiUitOpen 2:cf42e62a97dc 119 t.rx_length = rx_length;
MikamiUitOpen 2:cf42e62a97dc 120 t.event = event;
MikamiUitOpen 2:cf42e62a97dc 121 t.callback = callback;
MikamiUitOpen 2:cf42e62a97dc 122 t.width = bit_width;
MikamiUitOpen 2:cf42e62a97dc 123 Transaction<SPI> transaction(this, t);
MikamiUitOpen 2:cf42e62a97dc 124 if (_transaction_buffer.full()) {
MikamiUitOpen 2:cf42e62a97dc 125 return -1; // the buffer is full
MikamiUitOpen 2:cf42e62a97dc 126 } else {
MikamiUitOpen 2:cf42e62a97dc 127 __disable_irq();
MikamiUitOpen 2:cf42e62a97dc 128 _transaction_buffer.push(transaction);
MikamiUitOpen 2:cf42e62a97dc 129 if (!spi_active(&_spi)) {
MikamiUitOpen 2:cf42e62a97dc 130 dequeue_transaction();
MikamiUitOpen 2:cf42e62a97dc 131 }
MikamiUitOpen 2:cf42e62a97dc 132 __enable_irq();
MikamiUitOpen 2:cf42e62a97dc 133 return 0;
MikamiUitOpen 2:cf42e62a97dc 134 }
MikamiUitOpen 2:cf42e62a97dc 135 #else
MikamiUitOpen 2:cf42e62a97dc 136 return -1;
MikamiUitOpen 2:cf42e62a97dc 137 #endif
MikamiUitOpen 2:cf42e62a97dc 138 }
MikamiUitOpen 2:cf42e62a97dc 139
MikamiUitOpen 2:cf42e62a97dc 140 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
MikamiUitOpen 2:cf42e62a97dc 141 {
MikamiUitOpen 2:cf42e62a97dc 142 aquire();
MikamiUitOpen 2:cf42e62a97dc 143 _callback = callback;
MikamiUitOpen 2:cf42e62a97dc 144 _irq.callback(&SPI::irq_handler_asynch);
MikamiUitOpen 2:cf42e62a97dc 145 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
MikamiUitOpen 2:cf42e62a97dc 146 }
MikamiUitOpen 2:cf42e62a97dc 147
MikamiUitOpen 2:cf42e62a97dc 148 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 2:cf42e62a97dc 149
MikamiUitOpen 2:cf42e62a97dc 150 void SPI::start_transaction(transaction_t *data)
MikamiUitOpen 2:cf42e62a97dc 151 {
MikamiUitOpen 2:cf42e62a97dc 152 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
MikamiUitOpen 2:cf42e62a97dc 153 }
MikamiUitOpen 2:cf42e62a97dc 154
MikamiUitOpen 2:cf42e62a97dc 155 void SPI::dequeue_transaction()
MikamiUitOpen 2:cf42e62a97dc 156 {
MikamiUitOpen 2:cf42e62a97dc 157 Transaction<SPI> t;
MikamiUitOpen 2:cf42e62a97dc 158 if (_transaction_buffer.pop(t)) {
MikamiUitOpen 2:cf42e62a97dc 159 SPI* obj = t.get_object();
MikamiUitOpen 2:cf42e62a97dc 160 transaction_t* data = t.get_transaction();
MikamiUitOpen 2:cf42e62a97dc 161 obj->start_transaction(data);
MikamiUitOpen 2:cf42e62a97dc 162 }
MikamiUitOpen 2:cf42e62a97dc 163 }
MikamiUitOpen 2:cf42e62a97dc 164
MikamiUitOpen 2:cf42e62a97dc 165 #endif
MikamiUitOpen 2:cf42e62a97dc 166
MikamiUitOpen 2:cf42e62a97dc 167 void SPI::irq_handler_asynch(void)
MikamiUitOpen 2:cf42e62a97dc 168 {
MikamiUitOpen 2:cf42e62a97dc 169 int event = spi_irq_handler_asynch(&_spi);
MikamiUitOpen 2:cf42e62a97dc 170 if (_callback && (event & SPI_EVENT_ALL)) {
MikamiUitOpen 2:cf42e62a97dc 171 _callback.call(event & SPI_EVENT_ALL);
MikamiUitOpen 2:cf42e62a97dc 172 }
MikamiUitOpen 2:cf42e62a97dc 173 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 2:cf42e62a97dc 174 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
MikamiUitOpen 2:cf42e62a97dc 175 // SPI peripheral is free (event happend), dequeue transaction
MikamiUitOpen 2:cf42e62a97dc 176 dequeue_transaction();
MikamiUitOpen 2:cf42e62a97dc 177 }
MikamiUitOpen 2:cf42e62a97dc 178 #endif
MikamiUitOpen 2:cf42e62a97dc 179 }
MikamiUitOpen 2:cf42e62a97dc 180
MikamiUitOpen 2:cf42e62a97dc 181 #endif
MikamiUitOpen 2:cf42e62a97dc 182
MikamiUitOpen 2:cf42e62a97dc 183 } // namespace mbed
MikamiUitOpen 2:cf42e62a97dc 184
MikamiUitOpen 2:cf42e62a97dc 185 #endif