不韋 呂 / F746_SD_Player_Demo

Demo program for library named SD_PlayerSkeleton of SD card player skeleton. SD カードプレーヤのための骨組みとして使うためのライブラリ SD_PlayerSkeleton の使用例．このプログラムについては，CQ出版社インターフェース誌 2018年7月号で解説している．

Dependencies:   F746_GUI F746_SAI_IO SD_PlayerSkeleton

mbed_src_STM32F7/api/SPI.h@19:3c3833ec00d2, 2017-04-09 (annotated)

Committer:
MikamiUitOpen
Date:
Sun Apr 09 12:44:17 2017 +0000
Revision:
19:3c3833ec00d2
Parent:
2:cf42e62a97dc 
20

Who changed what in which revision?

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MikamiUitOpen 2:cf42e62a97dc 1 /* mbed Microcontroller Library
MikamiUitOpen 2:cf42e62a97dc 2 * Copyright (c) 2006-2015 ARM Limited
MikamiUitOpen 2:cf42e62a97dc 3 *
MikamiUitOpen 2:cf42e62a97dc 4 * Licensed under the Apache License, Version 2.0 (the "License");
MikamiUitOpen 2:cf42e62a97dc 5 * you may not use this file except in compliance with the License.
MikamiUitOpen 2:cf42e62a97dc 6 * You may obtain a copy of the License at
MikamiUitOpen 2:cf42e62a97dc 7 *
MikamiUitOpen 2:cf42e62a97dc 8 * http://www.apache.org/licenses/LICENSE-2.0
MikamiUitOpen 2:cf42e62a97dc 9 *
MikamiUitOpen 2:cf42e62a97dc 10 * Unless required by applicable law or agreed to in writing, software
MikamiUitOpen 2:cf42e62a97dc 11 * distributed under the License is distributed on an "AS IS" BASIS,
MikamiUitOpen 2:cf42e62a97dc 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MikamiUitOpen 2:cf42e62a97dc 13 * See the License for the specific language governing permissions and
MikamiUitOpen 2:cf42e62a97dc 14 * limitations under the License.
MikamiUitOpen 2:cf42e62a97dc 15 */
MikamiUitOpen 2:cf42e62a97dc 16 #ifndef MBED_SPI_H
MikamiUitOpen 2:cf42e62a97dc 17 #define MBED_SPI_H
MikamiUitOpen 2:cf42e62a97dc 18
MikamiUitOpen 2:cf42e62a97dc 19 #include "platform.h"
MikamiUitOpen 2:cf42e62a97dc 20
MikamiUitOpen 2:cf42e62a97dc 21 #if DEVICE_SPI
MikamiUitOpen 2:cf42e62a97dc 22
MikamiUitOpen 2:cf42e62a97dc 23 #include "spi_api.h"
MikamiUitOpen 2:cf42e62a97dc 24
MikamiUitOpen 2:cf42e62a97dc 25 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 2:cf42e62a97dc 26 #include "CThunk.h"
MikamiUitOpen 2:cf42e62a97dc 27 #include "dma_api.h"
MikamiUitOpen 2:cf42e62a97dc 28 #include "CircularBuffer.h"
MikamiUitOpen 2:cf42e62a97dc 29 #include "FunctionPointer.h"
MikamiUitOpen 2:cf42e62a97dc 30 #include "Transaction.h"
MikamiUitOpen 2:cf42e62a97dc 31 #endif
MikamiUitOpen 2:cf42e62a97dc 32
MikamiUitOpen 2:cf42e62a97dc 33 namespace mbed {
MikamiUitOpen 2:cf42e62a97dc 34
MikamiUitOpen 2:cf42e62a97dc 35 /** A SPI Master, used for communicating with SPI slave devices
MikamiUitOpen 2:cf42e62a97dc 36 *
MikamiUitOpen 2:cf42e62a97dc 37 * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
MikamiUitOpen 2:cf42e62a97dc 38 *
MikamiUitOpen 2:cf42e62a97dc 39 * Most SPI devices will also require Chip Select and Reset signals. These
MikamiUitOpen 2:cf42e62a97dc 40 * can be controlled using <DigitalOut> pins
MikamiUitOpen 2:cf42e62a97dc 41 *
MikamiUitOpen 2:cf42e62a97dc 42 * Example:
MikamiUitOpen 2:cf42e62a97dc 43 * @code
MikamiUitOpen 2:cf42e62a97dc 44 * // Send a byte to a SPI slave, and record the response
MikamiUitOpen 2:cf42e62a97dc 45 *
MikamiUitOpen 2:cf42e62a97dc 46 * #include "mbed.h"
MikamiUitOpen 2:cf42e62a97dc 47 *
MikamiUitOpen 2:cf42e62a97dc 48 * // hardware ssel (where applicable)
MikamiUitOpen 2:cf42e62a97dc 49 * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
MikamiUitOpen 2:cf42e62a97dc 50 *
MikamiUitOpen 2:cf42e62a97dc 51 * // software ssel
MikamiUitOpen 2:cf42e62a97dc 52 * SPI device(p5, p6, p7); // mosi, miso, sclk
MikamiUitOpen 2:cf42e62a97dc 53 * DigitalOut cs(p8); // ssel
MikamiUitOpen 2:cf42e62a97dc 54 *
MikamiUitOpen 2:cf42e62a97dc 55 * int main() {
MikamiUitOpen 2:cf42e62a97dc 56 * // hardware ssel (where applicable)
MikamiUitOpen 2:cf42e62a97dc 57 * //int response = device.write(0xFF);
MikamiUitOpen 2:cf42e62a97dc 58 *
MikamiUitOpen 2:cf42e62a97dc 59 * // software ssel
MikamiUitOpen 2:cf42e62a97dc 60 * cs = 0;
MikamiUitOpen 2:cf42e62a97dc 61 * int response = device.write(0xFF);
MikamiUitOpen 2:cf42e62a97dc 62 * cs = 1;
MikamiUitOpen 2:cf42e62a97dc 63 * }
MikamiUitOpen 2:cf42e62a97dc 64 * @endcode
MikamiUitOpen 2:cf42e62a97dc 65 */
MikamiUitOpen 2:cf42e62a97dc 66 class SPI {
MikamiUitOpen 2:cf42e62a97dc 67
MikamiUitOpen 2:cf42e62a97dc 68 public:
MikamiUitOpen 2:cf42e62a97dc 69
MikamiUitOpen 2:cf42e62a97dc 70 /** Create a SPI master connected to the specified pins
MikamiUitOpen 2:cf42e62a97dc 71 *
MikamiUitOpen 2:cf42e62a97dc 72 * mosi or miso can be specfied as NC if not used
MikamiUitOpen 2:cf42e62a97dc 73 *
MikamiUitOpen 2:cf42e62a97dc 74 * @param mosi SPI Master Out, Slave In pin
MikamiUitOpen 2:cf42e62a97dc 75 * @param miso SPI Master In, Slave Out pin
MikamiUitOpen 2:cf42e62a97dc 76 * @param sclk SPI Clock pin
MikamiUitOpen 2:cf42e62a97dc 77 * @param ssel SPI chip select pin
MikamiUitOpen 2:cf42e62a97dc 78 */
MikamiUitOpen 2:cf42e62a97dc 79 SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
MikamiUitOpen 2:cf42e62a97dc 80
MikamiUitOpen 2:cf42e62a97dc 81 /** Configure the data transmission format
MikamiUitOpen 2:cf42e62a97dc 82 *
MikamiUitOpen 2:cf42e62a97dc 83 * @param bits Number of bits per SPI frame (4 - 16)
MikamiUitOpen 2:cf42e62a97dc 84 * @param mode Clock polarity and phase mode (0 - 3)
MikamiUitOpen 2:cf42e62a97dc 85 *
MikamiUitOpen 2:cf42e62a97dc 86 * @code
MikamiUitOpen 2:cf42e62a97dc 87 * mode | POL PHA
MikamiUitOpen 2:cf42e62a97dc 88 * -----+--------
MikamiUitOpen 2:cf42e62a97dc 89 * 0 | 0 0
MikamiUitOpen 2:cf42e62a97dc 90 * 1 | 0 1
MikamiUitOpen 2:cf42e62a97dc 91 * 2 | 1 0
MikamiUitOpen 2:cf42e62a97dc 92 * 3 | 1 1
MikamiUitOpen 2:cf42e62a97dc 93 * @endcode
MikamiUitOpen 2:cf42e62a97dc 94 */
MikamiUitOpen 2:cf42e62a97dc 95 void format(int bits, int mode = 0);
MikamiUitOpen 2:cf42e62a97dc 96
MikamiUitOpen 2:cf42e62a97dc 97 /** Set the spi bus clock frequency
MikamiUitOpen 2:cf42e62a97dc 98 *
MikamiUitOpen 2:cf42e62a97dc 99 * @param hz SCLK frequency in hz (default = 1MHz)
MikamiUitOpen 2:cf42e62a97dc 100 */
MikamiUitOpen 2:cf42e62a97dc 101 void frequency(int hz = 1000000);
MikamiUitOpen 2:cf42e62a97dc 102
MikamiUitOpen 2:cf42e62a97dc 103 /** Write to the SPI Slave and return the response
MikamiUitOpen 2:cf42e62a97dc 104 *
MikamiUitOpen 2:cf42e62a97dc 105 * @param value Data to be sent to the SPI slave
MikamiUitOpen 2:cf42e62a97dc 106 *
MikamiUitOpen 2:cf42e62a97dc 107 * @returns
MikamiUitOpen 2:cf42e62a97dc 108 * Response from the SPI slave
MikamiUitOpen 2:cf42e62a97dc 109 */
MikamiUitOpen 2:cf42e62a97dc 110 virtual int write(int value);
MikamiUitOpen 2:cf42e62a97dc 111
MikamiUitOpen 2:cf42e62a97dc 112 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 2:cf42e62a97dc 113
MikamiUitOpen 2:cf42e62a97dc 114 /** Start non-blocking SPI transfer using 8bit buffers.
MikamiUitOpen 2:cf42e62a97dc 115 *
MikamiUitOpen 2:cf42e62a97dc 116 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
MikamiUitOpen 2:cf42e62a97dc 117 * the default SPI value is sent
MikamiUitOpen 2:cf42e62a97dc 118 * @param tx_length The length of TX buffer in bytes
MikamiUitOpen 2:cf42e62a97dc 119 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
MikamiUitOpen 2:cf42e62a97dc 120 * received data are ignored
MikamiUitOpen 2:cf42e62a97dc 121 * @param rx_length The length of RX buffer in bytes
MikamiUitOpen 2:cf42e62a97dc 122 * @param callback The event callback function
MikamiUitOpen 2:cf42e62a97dc 123 * @param event The logical OR of events to modify. Look at spi hal header file for SPI events.
MikamiUitOpen 2:cf42e62a97dc 124 * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
MikamiUitOpen 2:cf42e62a97dc 125 */
MikamiUitOpen 2:cf42e62a97dc 126 template<typename Type>
MikamiUitOpen 2:cf42e62a97dc 127 int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
MikamiUitOpen 2:cf42e62a97dc 128 if (spi_active(&_spi)) {
MikamiUitOpen 2:cf42e62a97dc 129 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
MikamiUitOpen 2:cf42e62a97dc 130 }
MikamiUitOpen 2:cf42e62a97dc 131 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
MikamiUitOpen 2:cf42e62a97dc 132 return 0;
MikamiUitOpen 2:cf42e62a97dc 133 }
MikamiUitOpen 2:cf42e62a97dc 134
MikamiUitOpen 2:cf42e62a97dc 135 /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
MikamiUitOpen 2:cf42e62a97dc 136 */
MikamiUitOpen 2:cf42e62a97dc 137 void abort_transfer();
MikamiUitOpen 2:cf42e62a97dc 138
MikamiUitOpen 2:cf42e62a97dc 139 /** Clear the transaction buffer
MikamiUitOpen 2:cf42e62a97dc 140 */
MikamiUitOpen 2:cf42e62a97dc 141 void clear_transfer_buffer();
MikamiUitOpen 2:cf42e62a97dc 142
MikamiUitOpen 2:cf42e62a97dc 143 /** Clear the transaction buffer and abort on-going transfer.
MikamiUitOpen 2:cf42e62a97dc 144 */
MikamiUitOpen 2:cf42e62a97dc 145 void abort_all_transfers();
MikamiUitOpen 2:cf42e62a97dc 146
MikamiUitOpen 2:cf42e62a97dc 147 /** Configure DMA usage suggestion for non-blocking transfers
MikamiUitOpen 2:cf42e62a97dc 148 *
MikamiUitOpen 2:cf42e62a97dc 149 * @param usage The usage DMA hint for peripheral
MikamiUitOpen 2:cf42e62a97dc 150 * @return Zero if the usage was set, -1 if a transaction is on-going
MikamiUitOpen 2:cf42e62a97dc 151 */
MikamiUitOpen 2:cf42e62a97dc 152 int set_dma_usage(DMAUsage usage);
MikamiUitOpen 2:cf42e62a97dc 153
MikamiUitOpen 2:cf42e62a97dc 154 protected:
MikamiUitOpen 2:cf42e62a97dc 155 /** SPI IRQ handler
MikamiUitOpen 2:cf42e62a97dc 156 *
MikamiUitOpen 2:cf42e62a97dc 157 */
MikamiUitOpen 2:cf42e62a97dc 158 void irq_handler_asynch(void);
MikamiUitOpen 2:cf42e62a97dc 159
MikamiUitOpen 2:cf42e62a97dc 160 /** Common transfer method
MikamiUitOpen 2:cf42e62a97dc 161 *
MikamiUitOpen 2:cf42e62a97dc 162 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
MikamiUitOpen 2:cf42e62a97dc 163 * the default SPI value is sent
MikamiUitOpen 2:cf42e62a97dc 164 * @param tx_length The length of TX buffer in bytes
MikamiUitOpen 2:cf42e62a97dc 165 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
MikamiUitOpen 2:cf42e62a97dc 166 * received data are ignored
MikamiUitOpen 2:cf42e62a97dc 167 * @param rx_length The length of RX buffer in bytes
MikamiUitOpen 2:cf42e62a97dc 168 * @param bit_width The buffers element width
MikamiUitOpen 2:cf42e62a97dc 169 * @param callback The event callback function
MikamiUitOpen 2:cf42e62a97dc 170 * @param event The logical OR of events to modify
MikamiUitOpen 2:cf42e62a97dc 171 * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
MikamiUitOpen 2:cf42e62a97dc 172 */
MikamiUitOpen 2:cf42e62a97dc 173 int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
MikamiUitOpen 2:cf42e62a97dc 174
MikamiUitOpen 2:cf42e62a97dc 175 /**
MikamiUitOpen 2:cf42e62a97dc 176 *
MikamiUitOpen 2:cf42e62a97dc 177 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
MikamiUitOpen 2:cf42e62a97dc 178 * the default SPI value is sent
MikamiUitOpen 2:cf42e62a97dc 179 * @param tx_length The length of TX buffer in bytes
MikamiUitOpen 2:cf42e62a97dc 180 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
MikamiUitOpen 2:cf42e62a97dc 181 * received data are ignored
MikamiUitOpen 2:cf42e62a97dc 182 * @param rx_length The length of RX buffer in bytes
MikamiUitOpen 2:cf42e62a97dc 183 * @param bit_width The buffers element width
MikamiUitOpen 2:cf42e62a97dc 184 * @param callback The event callback function
MikamiUitOpen 2:cf42e62a97dc 185 * @param event The logical OR of events to modify
MikamiUitOpen 2:cf42e62a97dc 186 * @return Zero if a transfer was added to the queue, or -1 if the queue is full
MikamiUitOpen 2:cf42e62a97dc 187 */
MikamiUitOpen 2:cf42e62a97dc 188 int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
MikamiUitOpen 2:cf42e62a97dc 189
MikamiUitOpen 2:cf42e62a97dc 190 /** Configures a callback, spi peripheral and initiate a new transfer
MikamiUitOpen 2:cf42e62a97dc 191 *
MikamiUitOpen 2:cf42e62a97dc 192 * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
MikamiUitOpen 2:cf42e62a97dc 193 * the default SPI value is sent
MikamiUitOpen 2:cf42e62a97dc 194 * @param tx_length The length of TX buffer in bytes
MikamiUitOpen 2:cf42e62a97dc 195 * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
MikamiUitOpen 2:cf42e62a97dc 196 * received data are ignored
MikamiUitOpen 2:cf42e62a97dc 197 * @param rx_length The length of RX buffer in bytes
MikamiUitOpen 2:cf42e62a97dc 198 * @param bit_width The buffers element width
MikamiUitOpen 2:cf42e62a97dc 199 * @param callback The event callback function
MikamiUitOpen 2:cf42e62a97dc 200 * @param event The logical OR of events to modify
MikamiUitOpen 2:cf42e62a97dc 201 */
MikamiUitOpen 2:cf42e62a97dc 202 void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
MikamiUitOpen 2:cf42e62a97dc 203
MikamiUitOpen 2:cf42e62a97dc 204 #if TRANSACTION_QUEUE_SIZE_SPI
MikamiUitOpen 2:cf42e62a97dc 205
MikamiUitOpen 2:cf42e62a97dc 206 /** Start a new transaction
MikamiUitOpen 2:cf42e62a97dc 207 *
MikamiUitOpen 2:cf42e62a97dc 208 * @param data Transaction data
MikamiUitOpen 2:cf42e62a97dc 209 */
MikamiUitOpen 2:cf42e62a97dc 210 void start_transaction(transaction_t *data);
MikamiUitOpen 2:cf42e62a97dc 211
MikamiUitOpen 2:cf42e62a97dc 212 /** Dequeue a transaction
MikamiUitOpen 2:cf42e62a97dc 213 *
MikamiUitOpen 2:cf42e62a97dc 214 */
MikamiUitOpen 2:cf42e62a97dc 215 void dequeue_transaction();
MikamiUitOpen 2:cf42e62a97dc 216 static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
MikamiUitOpen 2:cf42e62a97dc 217 #endif
MikamiUitOpen 2:cf42e62a97dc 218
MikamiUitOpen 2:cf42e62a97dc 219 #endif
MikamiUitOpen 2:cf42e62a97dc 220
MikamiUitOpen 2:cf42e62a97dc 221 public:
MikamiUitOpen 2:cf42e62a97dc 222 virtual ~SPI() {
MikamiUitOpen 2:cf42e62a97dc 223 }
MikamiUitOpen 2:cf42e62a97dc 224
MikamiUitOpen 2:cf42e62a97dc 225 protected:
MikamiUitOpen 2:cf42e62a97dc 226 spi_t _spi;
MikamiUitOpen 2:cf42e62a97dc 227
MikamiUitOpen 2:cf42e62a97dc 228 #if DEVICE_SPI_ASYNCH
MikamiUitOpen 2:cf42e62a97dc 229 CThunk<SPI> _irq;
MikamiUitOpen 2:cf42e62a97dc 230 event_callback_t _callback;
MikamiUitOpen 2:cf42e62a97dc 231 DMAUsage _usage;
MikamiUitOpen 2:cf42e62a97dc 232 #endif
MikamiUitOpen 2:cf42e62a97dc 233
MikamiUitOpen 2:cf42e62a97dc 234 void aquire(void);
MikamiUitOpen 2:cf42e62a97dc 235 static SPI *_owner;
MikamiUitOpen 2:cf42e62a97dc 236 int _bits;
MikamiUitOpen 2:cf42e62a97dc 237 int _mode;
MikamiUitOpen 2:cf42e62a97dc 238 int _hz;
MikamiUitOpen 2:cf42e62a97dc 239 };
MikamiUitOpen 2:cf42e62a97dc 240
MikamiUitOpen 2:cf42e62a97dc 241 } // namespace mbed
MikamiUitOpen 2:cf42e62a97dc 242
MikamiUitOpen 2:cf42e62a97dc 243 #endif
MikamiUitOpen 2:cf42e62a97dc 244
MikamiUitOpen 2:cf42e62a97dc 245 #endif