Toyomasa Watarai / easy-connect-type-yd

Easily add all supported connectivity methods to your mbed OS project

Dependencies:   type-yd-driver

atmel-rf-driver/source/AT86RFReg.h@0:615f90842ce8, 2017-07-12 (annotated)

Committer:
MACRUM
Date:
Wed Jul 12 10:52:58 2017 +0000
Revision:
0:615f90842ce8
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MACRUM 0:615f90842ce8 1 /*
MACRUM 0:615f90842ce8 2 * Copyright (c) 2014-2015 ARM Limited. All rights reserved.
MACRUM 0:615f90842ce8 3 * SPDX-License-Identifier: Apache-2.0
MACRUM 0:615f90842ce8 4 * Licensed under the Apache License, Version 2.0 (the License); you may
MACRUM 0:615f90842ce8 5 * not use this file except in compliance with the License.
MACRUM 0:615f90842ce8 6 * You may obtain a copy of the License at
MACRUM 0:615f90842ce8 7 *
MACRUM 0:615f90842ce8 8 * http://www.apache.org/licenses/LICENSE-2.0
MACRUM 0:615f90842ce8 9 *
MACRUM 0:615f90842ce8 10 * Unless required by applicable law or agreed to in writing, software
MACRUM 0:615f90842ce8 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
MACRUM 0:615f90842ce8 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MACRUM 0:615f90842ce8 13 * See the License for the specific language governing permissions and
MACRUM 0:615f90842ce8 14 * limitations under the License.
MACRUM 0:615f90842ce8 15 */
MACRUM 0:615f90842ce8 16
MACRUM 0:615f90842ce8 17 #ifndef AT86RFREG_H_
MACRUM 0:615f90842ce8 18 #define AT86RFREG_H_
MACRUM 0:615f90842ce8 19 #ifdef __cplusplus
MACRUM 0:615f90842ce8 20 extern "C" {
MACRUM 0:615f90842ce8 21 #endif
MACRUM 0:615f90842ce8 22
MACRUM 0:615f90842ce8 23 /*AT86RF212 PHY Modes*/
MACRUM 0:615f90842ce8 24 #define BPSK_20 0x00
MACRUM 0:615f90842ce8 25 #define BPSK_40 0x04
MACRUM 0:615f90842ce8 26 #define BPSK_40_ALT 0x14
MACRUM 0:615f90842ce8 27 #define OQPSK_SIN_RC_100 0x08
MACRUM 0:615f90842ce8 28 #define OQPSK_SIN_RC_200 0x09
MACRUM 0:615f90842ce8 29 #define OQPSK_RC_100 0x18
MACRUM 0:615f90842ce8 30 #define OQPSK_RC_200 0x19
MACRUM 0:615f90842ce8 31 #define OQPSK_SIN_250 0x0c
MACRUM 0:615f90842ce8 32 #define OQPSK_SIN_500 0x0d
MACRUM 0:615f90842ce8 33 #define OQPSK_SIN_500_ALT 0x0f
MACRUM 0:615f90842ce8 34 #define OQPSK_RC_250 0x1c
MACRUM 0:615f90842ce8 35 #define OQPSK_RC_500 0x1d
MACRUM 0:615f90842ce8 36 #define OQPSK_RC_500_ALT 0x1f
MACRUM 0:615f90842ce8 37 #define OQPSK_SIN_RC_400_SCR_ON 0x2A
MACRUM 0:615f90842ce8 38 #define OQPSK_SIN_RC_400_SCR_OFF 0x0A
MACRUM 0:615f90842ce8 39 #define OQPSK_RC_400_SCR_ON 0x3A
MACRUM 0:615f90842ce8 40 #define OQPSK_RC_400_SCR_OFF 0x1A
MACRUM 0:615f90842ce8 41 #define OQPSK_SIN_1000_SCR_ON 0x2E
MACRUM 0:615f90842ce8 42 #define OQPSK_SIN_1000_SCR_OFF 0x0E
MACRUM 0:615f90842ce8 43 #define OQPSK_RC_1000_SCR_ON 0x3E
MACRUM 0:615f90842ce8 44 #define OQPSK_RC_1000_SCR_OFF 0x1E
MACRUM 0:615f90842ce8 45
MACRUM 0:615f90842ce8 46 /*Supported transceivers*/
MACRUM 0:615f90842ce8 47 #define PART_AT86RF231 0x03
MACRUM 0:615f90842ce8 48 #define PART_AT86RF212 0x07
MACRUM 0:615f90842ce8 49 #define PART_AT86RF233 0x0B
MACRUM 0:615f90842ce8 50 #define VERSION_AT86RF212 0x01
MACRUM 0:615f90842ce8 51 #define VERSION_AT86RF212B 0x03
MACRUM 0:615f90842ce8 52
MACRUM 0:615f90842ce8 53 /*RF Configuration Registers*/
MACRUM 0:615f90842ce8 54 #define TRX_STATUS 0x01
MACRUM 0:615f90842ce8 55 #define TRX_STATE 0x02
MACRUM 0:615f90842ce8 56 #define TRX_CTRL_0 0x03
MACRUM 0:615f90842ce8 57 #define TRX_CTRL_1 0x04
MACRUM 0:615f90842ce8 58 #define PHY_TX_PWR 0x05
MACRUM 0:615f90842ce8 59 #define PHY_RSSI 0x06
MACRUM 0:615f90842ce8 60 #define PHY_ED_LEVEL 0x07
MACRUM 0:615f90842ce8 61 #define PHY_CC_CCA 0x08
MACRUM 0:615f90842ce8 62 #define RX_CTRL 0x0A
MACRUM 0:615f90842ce8 63 #define SFD_VALUE 0x0B
MACRUM 0:615f90842ce8 64 #define TRX_CTRL_2 0x0C
MACRUM 0:615f90842ce8 65 #define ANT_DIV 0x0D
MACRUM 0:615f90842ce8 66 #define IRQ_MASK 0x0E
MACRUM 0:615f90842ce8 67 #define IRQ_STATUS 0x0F
MACRUM 0:615f90842ce8 68 #define VREG_CTRL 0x10
MACRUM 0:615f90842ce8 69 #define BATMON 0x11
MACRUM 0:615f90842ce8 70 #define XOSC_CTRL 0x12
MACRUM 0:615f90842ce8 71 #define CC_CTRL_0 0x13
MACRUM 0:615f90842ce8 72 #define CC_CTRL_1 0x14
MACRUM 0:615f90842ce8 73 #define RX_SYN 0x15
MACRUM 0:615f90842ce8 74 #define TRX_RPC 0x16
MACRUM 0:615f90842ce8 75 #define RF_CTRL_0 0x16
MACRUM 0:615f90842ce8 76 #define XAH_CTRL_1 0x17
MACRUM 0:615f90842ce8 77 #define FTN_CTRL 0x18
MACRUM 0:615f90842ce8 78 #define PLL_CF 0x1A
MACRUM 0:615f90842ce8 79 #define PLL_DCU 0x1B
MACRUM 0:615f90842ce8 80 #define PART_NUM 0x1C
MACRUM 0:615f90842ce8 81 #define VERSION_NUM 0x1D
MACRUM 0:615f90842ce8 82 #define MAN_ID_0 0x1E
MACRUM 0:615f90842ce8 83 #define MAN_ID_1 0x1F
MACRUM 0:615f90842ce8 84 #define SHORT_ADDR_0 0x20
MACRUM 0:615f90842ce8 85 #define SHORT_ADDR_1 0x21
MACRUM 0:615f90842ce8 86 #define PAN_ID_0 0x22
MACRUM 0:615f90842ce8 87 #define PAN_ID_1 0x23
MACRUM 0:615f90842ce8 88 #define IEEE_ADDR_0 0x24
MACRUM 0:615f90842ce8 89 #define IEEE_ADDR_1 0x25
MACRUM 0:615f90842ce8 90 #define IEEE_ADDR_2 0x26
MACRUM 0:615f90842ce8 91 #define IEEE_ADDR_3 0x27
MACRUM 0:615f90842ce8 92 #define IEEE_ADDR_4 0x28
MACRUM 0:615f90842ce8 93 #define IEEE_ADDR_5 0x29
MACRUM 0:615f90842ce8 94 #define IEEE_ADDR_6 0x2A
MACRUM 0:615f90842ce8 95 #define IEEE_ADDR_7 0x2B
MACRUM 0:615f90842ce8 96 #define XAH_CTRL_0 0x2C
MACRUM 0:615f90842ce8 97 #define CSMA_SEED_0 0x2D
MACRUM 0:615f90842ce8 98 #define CSMA_SEED_1 0x2E
MACRUM 0:615f90842ce8 99 #define CSMA_BE 0x2F
MACRUM 0:615f90842ce8 100
MACRUM 0:615f90842ce8 101 /* CSMA_SEED_1*/
MACRUM 0:615f90842ce8 102 #define AACK_FVN_MODE1 7
MACRUM 0:615f90842ce8 103 #define AACK_FVN_MODE0 6
MACRUM 0:615f90842ce8 104 #define AACK_SET_PD 5
MACRUM 0:615f90842ce8 105 #define AACK_DIS_ACK 4
MACRUM 0:615f90842ce8 106 #define AACK_I_AM_COORD 3
MACRUM 0:615f90842ce8 107 #define CSMA_SEED_12 2
MACRUM 0:615f90842ce8 108 #define CSMA_SEED_11 1
MACRUM 0:615f90842ce8 109 #define CSMA_SEED_10 0
MACRUM 0:615f90842ce8 110
MACRUM 0:615f90842ce8 111 /*TRX_STATUS bits*/
MACRUM 0:615f90842ce8 112 #define CCA_STATUS 0x40
MACRUM 0:615f90842ce8 113 #define CCA_DONE 0x80
MACRUM 0:615f90842ce8 114
MACRUM 0:615f90842ce8 115 /*PHY_CC_CCA bits*/
MACRUM 0:615f90842ce8 116 #define CCA_REQUEST 0x80
MACRUM 0:615f90842ce8 117 #define CCA_MODE_1 0x20
MACRUM 0:615f90842ce8 118 #define CCA_MODE_3 0x60
MACRUM 0:615f90842ce8 119
MACRUM 0:615f90842ce8 120 /*IRQ_MASK bits*/
MACRUM 0:615f90842ce8 121 #define RX_START 0x04
MACRUM 0:615f90842ce8 122 #define TRX_END 0x08
MACRUM 0:615f90842ce8 123 #define CCA_ED_DONE 0x10
MACRUM 0:615f90842ce8 124 #define AMI 0x20
MACRUM 0:615f90842ce8 125 #define TRX_UR 0x40
MACRUM 0:615f90842ce8 126
MACRUM 0:615f90842ce8 127 /*ANT_DIV bits*/
MACRUM 0:615f90842ce8 128 #define ANT_DIV_EN 0x08
MACRUM 0:615f90842ce8 129 #define ANT_EXT_SW_EN 0x04
MACRUM 0:615f90842ce8 130 #define ANT_CTRL_DEFAULT 0x03
MACRUM 0:615f90842ce8 131
MACRUM 0:615f90842ce8 132 /*TRX_CTRL_1 bits*/
MACRUM 0:615f90842ce8 133 #define PA_EXT_EN 0x80
MACRUM 0:615f90842ce8 134
MACRUM 0:615f90842ce8 135 /*FTN_CTRL bits*/
MACRUM 0:615f90842ce8 136 #define FTN_START 0x80
MACRUM 0:615f90842ce8 137
MACRUM 0:615f90842ce8 138 /*PHY_RSSI bits*/
MACRUM 0:615f90842ce8 139 #define CRC_VALID 0x80
MACRUM 0:615f90842ce8 140
MACRUM 0:615f90842ce8 141 /*RX_SYN bits*/
MACRUM 0:615f90842ce8 142 #define RX_PDT_DIS 0x80
MACRUM 0:615f90842ce8 143
MACRUM 0:615f90842ce8 144 /*TRX_RPC bits */
MACRUM 0:615f90842ce8 145 #define RX_RPC_CTRL 0xC0
MACRUM 0:615f90842ce8 146 #define RX_RPC_EN 0x20
MACRUM 0:615f90842ce8 147 #define PDT_RPC_EN 0x10
MACRUM 0:615f90842ce8 148 #define PLL_RPC_EN 0x08
MACRUM 0:615f90842ce8 149 #define XAH_TX_RPC_EN 0x04
MACRUM 0:615f90842ce8 150 #define IPAN_RPC_EN 0x02
MACRUM 0:615f90842ce8 151 #define TRX_RPC_RSVD_1 0x01
MACRUM 0:615f90842ce8 152
MACRUM 0:615f90842ce8 153 /*XAH_CTRL_1 bits*/
MACRUM 0:615f90842ce8 154 #define AACK_PROM_MODE 0x02
MACRUM 0:615f90842ce8 155
MACRUM 0:615f90842ce8 156
MACRUM 0:615f90842ce8 157 #ifdef __cplusplus
MACRUM 0:615f90842ce8 158 }
MACRUM 0:615f90842ce8 159 #endif
MACRUM 0:615f90842ce8 160
MACRUM 0:615f90842ce8 161 #endif /* AT86RFREG_H_ */