Diff: system_LPC17xx.c

Revision:

164:6f43f85fdd8d

Parent:

150:29c9f7671bac

Child:

214:4c70e452c491

--- a/system_LPC17xx.c	Mon May 16 14:03:16 2016 +0000
+++ b/system_LPC17xx.c	Tue May 17 14:04:34 2016 +0000
@@ -323,8 +323,8 @@
 //  bits 0...14 - PLL0 multiplier value minus 1. Supported multiplier M range 6...512
 //  bits 16...23 - PLL0 Pre-Divider value minus 1. Supported divider N range 1...32
 //  Fcc0 = (2 * M * Fin) / N
-#define PLL0CFG_Val           0x00040055//M - 86, N - 5, output = 2 * 86 * 12MHz / 5 = 400MHz
-
+    #define PLL0CFG_Val           0x00040055//M - 86, N - 5, output = 2 * 86 * 12MHz / 5 = 400MHz
+   // #define PLL0CFG_Val           0x0003003d//M - 86, N - 5, output = 2 * 86 * 12MHz / 5 = 400MHz
 #define PLL1_SETUP            1
 #define PLL1CFG_Val           0x00000023//M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz?
 //CPU Clock Configure Register
@@ -359,7 +359,8 @@
 //  10 PCLK_peripheral = CCLK/2
 //  11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6.
 //#define PCLKSEL0_Val          0x00000010//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
-#define PCLKSEL0_Val          0x00000150//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
+  #define PCLKSEL0_Val          0x00000150//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
+//#define PCLKSEL0_Val          0x000003d0//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
 //Peripheral Clock Selection register 1
 //  1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface.00
 //  3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00