Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/core_cmInstr.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file core_cmInstr.h
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
<> 144:ef7eb2e8f9f7 4 * @version V4.10
<> 144:ef7eb2e8f9f7 5 * @date 18. March 2015
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @note
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ******************************************************************************/
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 All rights reserved.
<> 144:ef7eb2e8f9f7 13 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 14 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 18 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 19 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 21 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 22 specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 34 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #ifndef __CORE_CMINSTR_H
<> 144:ef7eb2e8f9f7 39 #define __CORE_CMINSTR_H
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* ########################## Core Instruction Access ######################### */
<> 144:ef7eb2e8f9f7 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
<> 144:ef7eb2e8f9f7 44 Access to dedicated instructions
<> 144:ef7eb2e8f9f7 45 @{
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 144:ef7eb2e8f9f7 49 /* ARM armcc specific functions */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #if (__ARMCC_VERSION < 400677)
<> 144:ef7eb2e8f9f7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 144:ef7eb2e8f9f7 53 #endif
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /** \brief No Operation
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 #define __NOP __nop
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** \brief Wait For Interrupt
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 Wait For Interrupt is a hint instruction that suspends execution
<> 144:ef7eb2e8f9f7 66 until one of a number of events occurs.
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 #define __WFI __wfi
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /** \brief Wait For Event
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 Wait For Event is a hint instruction that permits the processor to enter
<> 144:ef7eb2e8f9f7 74 a low-power state until one of a number of events occurs.
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76 #define __WFE __wfe
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /** \brief Send Event
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 #define __SEV __sev
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** \brief Instruction Synchronization Barrier
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 144:ef7eb2e8f9f7 89 so that all instructions following the ISB are fetched from cache or
<> 144:ef7eb2e8f9f7 90 memory, after the instruction has been completed.
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92 #define __ISB() do {\
<> 144:ef7eb2e8f9f7 93 __schedule_barrier();\
<> 144:ef7eb2e8f9f7 94 __isb(0xF);\
<> 144:ef7eb2e8f9f7 95 __schedule_barrier();\
<> 144:ef7eb2e8f9f7 96 } while (0)
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** \brief Data Synchronization Barrier
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 This function acts as a special kind of Data Memory Barrier.
<> 144:ef7eb2e8f9f7 101 It completes when all explicit memory accesses before this instruction complete.
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 #define __DSB() do {\
<> 144:ef7eb2e8f9f7 104 __schedule_barrier();\
<> 144:ef7eb2e8f9f7 105 __dsb(0xF);\
<> 144:ef7eb2e8f9f7 106 __schedule_barrier();\
<> 144:ef7eb2e8f9f7 107 } while (0)
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** \brief Data Memory Barrier
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 This function ensures the apparent order of the explicit memory operations before
<> 144:ef7eb2e8f9f7 112 and after the instruction, without ensuring their completion.
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 #define __DMB() do {\
<> 144:ef7eb2e8f9f7 115 __schedule_barrier();\
<> 144:ef7eb2e8f9f7 116 __dmb(0xF);\
<> 144:ef7eb2e8f9f7 117 __schedule_barrier();\
<> 144:ef7eb2e8f9f7 118 } while (0)
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /** \brief Reverse byte order (32 bit)
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 This function reverses the byte order in integer value.
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 \param [in] value Value to reverse
<> 144:ef7eb2e8f9f7 125 \return Reversed value
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 #define __REV __rev
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** \brief Reverse byte order (16 bit)
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 This function reverses the byte order in two unsigned short values.
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 \param [in] value Value to reverse
<> 144:ef7eb2e8f9f7 135 \return Reversed value
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 #ifndef __NO_EMBEDDED_ASM
<> 144:ef7eb2e8f9f7 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
<> 144:ef7eb2e8f9f7 139 {
<> 144:ef7eb2e8f9f7 140 rev16 r0, r0
<> 144:ef7eb2e8f9f7 141 bx lr
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143 #endif
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** \brief Reverse byte order in signed short value
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 This function reverses the byte order in a signed short value with sign extension to integer.
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 \param [in] value Value to reverse
<> 144:ef7eb2e8f9f7 150 \return Reversed value
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 #ifndef __NO_EMBEDDED_ASM
<> 144:ef7eb2e8f9f7 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
<> 144:ef7eb2e8f9f7 154 {
<> 144:ef7eb2e8f9f7 155 revsh r0, r0
<> 144:ef7eb2e8f9f7 156 bx lr
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158 #endif
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** \brief Rotate Right in unsigned value (32 bit)
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 \param [in] value Value to rotate
<> 144:ef7eb2e8f9f7 166 \param [in] value Number of Bits to rotate
<> 144:ef7eb2e8f9f7 167 \return Rotated value
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 #define __ROR __ror
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /** \brief Breakpoint
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 This function causes the processor to enter Debug state.
<> 144:ef7eb2e8f9f7 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 \param [in] value is ignored by the processor.
<> 144:ef7eb2e8f9f7 178 If required, a debugger can use it to store additional information about the breakpoint.
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180 #define __BKPT(value) __breakpoint(value)
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /** \brief Reverse bit order of value
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 This function reverses the bit order of the given value.
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 \param [in] value Value to reverse
<> 144:ef7eb2e8f9f7 188 \return Reversed value
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 144:ef7eb2e8f9f7 191 #define __RBIT __rbit
<> 144:ef7eb2e8f9f7 192 #else
<> 144:ef7eb2e8f9f7 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 uint32_t result;
<> 144:ef7eb2e8f9f7 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 result = value; // r will be reversed bits of v; first get LSB of v
<> 144:ef7eb2e8f9f7 199 for (value >>= 1; value; value >>= 1)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 result <<= 1;
<> 144:ef7eb2e8f9f7 202 result |= value & 1;
<> 144:ef7eb2e8f9f7 203 s--;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205 result <<= s; // shift when v's highest bits are zero
<> 144:ef7eb2e8f9f7 206 return(result);
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208 #endif
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** \brief Count leading zeros
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 This function counts the number of leading zeros of a data value.
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 \param [in] value Value to count the leading zeros
<> 144:ef7eb2e8f9f7 216 \return number of leading zeros in value
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 #define __CLZ __clz
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /** \brief LDR Exclusive (8 bit)
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 This function executes a exclusive LDR instruction for 8 bit value.
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 228 \return value of type uint8_t at (*ptr)
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /** \brief LDR Exclusive (16 bit)
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 This function executes a exclusive LDR instruction for 16 bit values.
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 238 \return value of type uint16_t at (*ptr)
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /** \brief LDR Exclusive (32 bit)
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 This function executes a exclusive LDR instruction for 32 bit values.
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 248 \return value of type uint32_t at (*ptr)
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** \brief STR Exclusive (8 bit)
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 This function executes a exclusive STR instruction for 8 bit values.
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 258 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 259 \return 0 Function succeeded
<> 144:ef7eb2e8f9f7 260 \return 1 Function failed
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 #define __STREXB(value, ptr) __strex(value, ptr)
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /** \brief STR Exclusive (16 bit)
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 This function executes a exclusive STR instruction for 16 bit values.
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 270 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 271 \return 0 Function succeeded
<> 144:ef7eb2e8f9f7 272 \return 1 Function failed
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 #define __STREXH(value, ptr) __strex(value, ptr)
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /** \brief STR Exclusive (32 bit)
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 This function executes a exclusive STR instruction for 32 bit values.
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 282 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 283 \return 0 Function succeeded
<> 144:ef7eb2e8f9f7 284 \return 1 Function failed
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define __STREXW(value, ptr) __strex(value, ptr)
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /** \brief Remove the exclusive lock
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 This function removes the exclusive lock which is created by LDREX.
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 #define __CLREX __clrex
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /** \brief Signed Saturate
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 This function saturates a signed value.
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 \param [in] value Value to be saturated
<> 144:ef7eb2e8f9f7 302 \param [in] sat Bit position to saturate to (1..32)
<> 144:ef7eb2e8f9f7 303 \return Saturated value
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305 #define __SSAT __ssat
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** \brief Unsigned Saturate
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 This function saturates an unsigned value.
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 \param [in] value Value to be saturated
<> 144:ef7eb2e8f9f7 313 \param [in] sat Bit position to saturate to (0..31)
<> 144:ef7eb2e8f9f7 314 \return Saturated value
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 #define __USAT __usat
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /** \brief Rotate Right with Extend (32 bit)
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 This function moves each bit of a bitstring right by one bit.
<> 144:ef7eb2e8f9f7 322 The carry input is shifted in at the left end of the bitstring.
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 \param [in] value Value to rotate
<> 144:ef7eb2e8f9f7 325 \return Rotated value
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 #ifndef __NO_EMBEDDED_ASM
<> 144:ef7eb2e8f9f7 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 rrx r0, r0
<> 144:ef7eb2e8f9f7 331 bx lr
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333 #endif
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /** \brief LDRT Unprivileged (8 bit)
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 341 \return value of type uint8_t at (*ptr)
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /** \brief LDRT Unprivileged (16 bit)
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 351 \return value of type uint16_t at (*ptr)
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /** \brief LDRT Unprivileged (32 bit)
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 361 \return value of type uint32_t at (*ptr)
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /** \brief STRT Unprivileged (8 bit)
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 371 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 372 */
<> 144:ef7eb2e8f9f7 373 #define __STRBT(value, ptr) __strt(value, ptr)
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /** \brief STRT Unprivileged (16 bit)
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 381 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 #define __STRHT(value, ptr) __strt(value, ptr)
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /** \brief STRT Unprivileged (32 bit)
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 391 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 392 */
<> 144:ef7eb2e8f9f7 393 #define __STRT(value, ptr) __strt(value, ptr)
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 144:ef7eb2e8f9f7 399 /* GNU gcc specific functions */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* Define macros for porting to both thumb1 and thumb2.
<> 144:ef7eb2e8f9f7 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
<> 144:ef7eb2e8f9f7 403 * Otherwise, use general registers, specified by constrant "r" */
<> 144:ef7eb2e8f9f7 404 #if defined (__thumb__) && !defined (__thumb2__)
<> 144:ef7eb2e8f9f7 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
<> 144:ef7eb2e8f9f7 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
<> 144:ef7eb2e8f9f7 407 #else
<> 144:ef7eb2e8f9f7 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
<> 144:ef7eb2e8f9f7 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
<> 144:ef7eb2e8f9f7 410 #endif
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /** \brief No Operation
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 No Operation does nothing. This instruction can be used for code alignment purposes.
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
<> 144:ef7eb2e8f9f7 417 {
<> 144:ef7eb2e8f9f7 418 __ASM volatile ("nop");
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /** \brief Wait For Interrupt
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 Wait For Interrupt is a hint instruction that suspends execution
<> 144:ef7eb2e8f9f7 425 until one of a number of events occurs.
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
<> 144:ef7eb2e8f9f7 428 {
<> 144:ef7eb2e8f9f7 429 __ASM volatile ("wfi");
<> 144:ef7eb2e8f9f7 430 }
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /** \brief Wait For Event
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 Wait For Event is a hint instruction that permits the processor to enter
<> 144:ef7eb2e8f9f7 436 a low-power state until one of a number of events occurs.
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 __ASM volatile ("wfe");
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /** \brief Send Event
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 __ASM volatile ("sev");
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /** \brief Instruction Synchronization Barrier
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
<> 144:ef7eb2e8f9f7 457 so that all instructions following the ISB are fetched from cache or
<> 144:ef7eb2e8f9f7 458 memory, after the instruction has been completed.
<> 144:ef7eb2e8f9f7 459 */
<> 144:ef7eb2e8f9f7 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
<> 144:ef7eb2e8f9f7 461 {
<> 144:ef7eb2e8f9f7 462 __ASM volatile ("isb 0xF":::"memory");
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /** \brief Data Synchronization Barrier
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 This function acts as a special kind of Data Memory Barrier.
<> 144:ef7eb2e8f9f7 469 It completes when all explicit memory accesses before this instruction complete.
<> 144:ef7eb2e8f9f7 470 */
<> 144:ef7eb2e8f9f7 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 __ASM volatile ("dsb 0xF":::"memory");
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /** \brief Data Memory Barrier
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 This function ensures the apparent order of the explicit memory operations before
<> 144:ef7eb2e8f9f7 480 and after the instruction, without ensuring their completion.
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 __ASM volatile ("dmb 0xF":::"memory");
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /** \brief Reverse byte order (32 bit)
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 This function reverses the byte order in integer value.
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 \param [in] value Value to reverse
<> 144:ef7eb2e8f9f7 493 \return Reversed value
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
<> 144:ef7eb2e8f9f7 498 return __builtin_bswap32(value);
<> 144:ef7eb2e8f9f7 499 #else
<> 144:ef7eb2e8f9f7 500 uint32_t result;
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 144:ef7eb2e8f9f7 503 return(result);
<> 144:ef7eb2e8f9f7 504 #endif
<> 144:ef7eb2e8f9f7 505 }
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /** \brief Reverse byte order (16 bit)
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 This function reverses the byte order in two unsigned short values.
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 \param [in] value Value to reverse
<> 144:ef7eb2e8f9f7 513 \return Reversed value
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 uint32_t result;
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 144:ef7eb2e8f9f7 520 return(result);
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /** \brief Reverse byte order in signed short value
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 This function reverses the byte order in a signed short value with sign extension to integer.
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 \param [in] value Value to reverse
<> 144:ef7eb2e8f9f7 529 \return Reversed value
<> 144:ef7eb2e8f9f7 530 */
<> 144:ef7eb2e8f9f7 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 144:ef7eb2e8f9f7 534 return (short)__builtin_bswap16(value);
<> 144:ef7eb2e8f9f7 535 #else
<> 144:ef7eb2e8f9f7 536 uint32_t result;
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 144:ef7eb2e8f9f7 539 return(result);
<> 144:ef7eb2e8f9f7 540 #endif
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /** \brief Rotate Right in unsigned value (32 bit)
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 \param [in] value Value to rotate
<> 144:ef7eb2e8f9f7 549 \param [in] value Number of Bits to rotate
<> 144:ef7eb2e8f9f7 550 \return Rotated value
<> 144:ef7eb2e8f9f7 551 */
<> 144:ef7eb2e8f9f7 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 return (op1 >> op2) | (op1 << (32 - op2));
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 /** \brief Breakpoint
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 This function causes the processor to enter Debug state.
<> 144:ef7eb2e8f9f7 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 \param [in] value is ignored by the processor.
<> 144:ef7eb2e8f9f7 564 If required, a debugger can use it to store additional information about the breakpoint.
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /** \brief Reverse bit order of value
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 This function reverses the bit order of the given value.
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 \param [in] value Value to reverse
<> 144:ef7eb2e8f9f7 574 \return Reversed value
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 uint32_t result;
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 144:ef7eb2e8f9f7 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
<> 144:ef7eb2e8f9f7 582 #else
<> 144:ef7eb2e8f9f7 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 result = value; // r will be reversed bits of v; first get LSB of v
<> 144:ef7eb2e8f9f7 586 for (value >>= 1; value; value >>= 1)
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 result <<= 1;
<> 144:ef7eb2e8f9f7 589 result |= value & 1;
<> 144:ef7eb2e8f9f7 590 s--;
<> 144:ef7eb2e8f9f7 591 }
<> 144:ef7eb2e8f9f7 592 result <<= s; // shift when v's highest bits are zero
<> 144:ef7eb2e8f9f7 593 #endif
<> 144:ef7eb2e8f9f7 594 return(result);
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /** \brief Count leading zeros
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 This function counts the number of leading zeros of a data value.
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 \param [in] value Value to count the leading zeros
<> 144:ef7eb2e8f9f7 603 \return number of leading zeros in value
<> 144:ef7eb2e8f9f7 604 */
<> 144:ef7eb2e8f9f7 605 #define __CLZ __builtin_clz
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /** \brief LDR Exclusive (8 bit)
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 This function executes a exclusive LDR instruction for 8 bit value.
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 615 \return value of type uint8_t at (*ptr)
<> 144:ef7eb2e8f9f7 616 */
<> 144:ef7eb2e8f9f7 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
<> 144:ef7eb2e8f9f7 618 {
<> 144:ef7eb2e8f9f7 619 uint32_t result;
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 144:ef7eb2e8f9f7 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
<> 144:ef7eb2e8f9f7 623 #else
<> 144:ef7eb2e8f9f7 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 144:ef7eb2e8f9f7 625 accepted by assembler. So has to use following less efficient pattern.
<> 144:ef7eb2e8f9f7 626 */
<> 144:ef7eb2e8f9f7 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 144:ef7eb2e8f9f7 628 #endif
<> 144:ef7eb2e8f9f7 629 return ((uint8_t) result); /* Add explicit type cast here */
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /** \brief LDR Exclusive (16 bit)
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 This function executes a exclusive LDR instruction for 16 bit values.
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 638 \return value of type uint16_t at (*ptr)
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 uint32_t result;
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 144:ef7eb2e8f9f7 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
<> 144:ef7eb2e8f9f7 646 #else
<> 144:ef7eb2e8f9f7 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 144:ef7eb2e8f9f7 648 accepted by assembler. So has to use following less efficient pattern.
<> 144:ef7eb2e8f9f7 649 */
<> 144:ef7eb2e8f9f7 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 144:ef7eb2e8f9f7 651 #endif
<> 144:ef7eb2e8f9f7 652 return ((uint16_t) result); /* Add explicit type cast here */
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /** \brief LDR Exclusive (32 bit)
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 This function executes a exclusive LDR instruction for 32 bit values.
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 661 \return value of type uint32_t at (*ptr)
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 uint32_t result;
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
<> 144:ef7eb2e8f9f7 668 return(result);
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /** \brief STR Exclusive (8 bit)
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 This function executes a exclusive STR instruction for 8 bit values.
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 677 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 678 \return 0 Function succeeded
<> 144:ef7eb2e8f9f7 679 \return 1 Function failed
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 uint32_t result;
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 144:ef7eb2e8f9f7 686 return(result);
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /** \brief STR Exclusive (16 bit)
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 This function executes a exclusive STR instruction for 16 bit values.
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 695 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 696 \return 0 Function succeeded
<> 144:ef7eb2e8f9f7 697 \return 1 Function failed
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 uint32_t result;
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
<> 144:ef7eb2e8f9f7 704 return(result);
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /** \brief STR Exclusive (32 bit)
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 This function executes a exclusive STR instruction for 32 bit values.
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 713 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 714 \return 0 Function succeeded
<> 144:ef7eb2e8f9f7 715 \return 1 Function failed
<> 144:ef7eb2e8f9f7 716 */
<> 144:ef7eb2e8f9f7 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 uint32_t result;
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
<> 144:ef7eb2e8f9f7 722 return(result);
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /** \brief Remove the exclusive lock
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 This function removes the exclusive lock which is created by LDREX.
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 */
<> 144:ef7eb2e8f9f7 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 __ASM volatile ("clrex" ::: "memory");
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /** \brief Signed Saturate
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 This function saturates a signed value.
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 \param [in] value Value to be saturated
<> 144:ef7eb2e8f9f7 742 \param [in] sat Bit position to saturate to (1..32)
<> 144:ef7eb2e8f9f7 743 \return Saturated value
<> 144:ef7eb2e8f9f7 744 */
<> 144:ef7eb2e8f9f7 745 #define __SSAT(ARG1,ARG2) \
<> 144:ef7eb2e8f9f7 746 ({ \
<> 144:ef7eb2e8f9f7 747 uint32_t __RES, __ARG1 = (ARG1); \
<> 144:ef7eb2e8f9f7 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 144:ef7eb2e8f9f7 749 __RES; \
<> 144:ef7eb2e8f9f7 750 })
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /** \brief Unsigned Saturate
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 This function saturates an unsigned value.
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 \param [in] value Value to be saturated
<> 144:ef7eb2e8f9f7 758 \param [in] sat Bit position to saturate to (0..31)
<> 144:ef7eb2e8f9f7 759 \return Saturated value
<> 144:ef7eb2e8f9f7 760 */
<> 144:ef7eb2e8f9f7 761 #define __USAT(ARG1,ARG2) \
<> 144:ef7eb2e8f9f7 762 ({ \
<> 144:ef7eb2e8f9f7 763 uint32_t __RES, __ARG1 = (ARG1); \
<> 144:ef7eb2e8f9f7 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 144:ef7eb2e8f9f7 765 __RES; \
<> 144:ef7eb2e8f9f7 766 })
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /** \brief Rotate Right with Extend (32 bit)
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 This function moves each bit of a bitstring right by one bit.
<> 144:ef7eb2e8f9f7 772 The carry input is shifted in at the left end of the bitstring.
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 \param [in] value Value to rotate
<> 144:ef7eb2e8f9f7 775 \return Rotated value
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
<> 144:ef7eb2e8f9f7 778 {
<> 144:ef7eb2e8f9f7 779 uint32_t result;
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
<> 144:ef7eb2e8f9f7 782 return(result);
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /** \brief LDRT Unprivileged (8 bit)
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 791 \return value of type uint8_t at (*ptr)
<> 144:ef7eb2e8f9f7 792 */
<> 144:ef7eb2e8f9f7 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 uint32_t result;
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 144:ef7eb2e8f9f7 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 144:ef7eb2e8f9f7 799 #else
<> 144:ef7eb2e8f9f7 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 144:ef7eb2e8f9f7 801 accepted by assembler. So has to use following less efficient pattern.
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 144:ef7eb2e8f9f7 804 #endif
<> 144:ef7eb2e8f9f7 805 return ((uint8_t) result); /* Add explicit type cast here */
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /** \brief LDRT Unprivileged (16 bit)
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 814 \return value of type uint16_t at (*ptr)
<> 144:ef7eb2e8f9f7 815 */
<> 144:ef7eb2e8f9f7 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 uint32_t result;
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
<> 144:ef7eb2e8f9f7 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
<> 144:ef7eb2e8f9f7 822 #else
<> 144:ef7eb2e8f9f7 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
<> 144:ef7eb2e8f9f7 824 accepted by assembler. So has to use following less efficient pattern.
<> 144:ef7eb2e8f9f7 825 */
<> 144:ef7eb2e8f9f7 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
<> 144:ef7eb2e8f9f7 827 #endif
<> 144:ef7eb2e8f9f7 828 return ((uint16_t) result); /* Add explicit type cast here */
<> 144:ef7eb2e8f9f7 829 }
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /** \brief LDRT Unprivileged (32 bit)
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 \param [in] ptr Pointer to data
<> 144:ef7eb2e8f9f7 837 \return value of type uint32_t at (*ptr)
<> 144:ef7eb2e8f9f7 838 */
<> 144:ef7eb2e8f9f7 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
<> 144:ef7eb2e8f9f7 840 {
<> 144:ef7eb2e8f9f7 841 uint32_t result;
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
<> 144:ef7eb2e8f9f7 844 return(result);
<> 144:ef7eb2e8f9f7 845 }
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /** \brief STRT Unprivileged (8 bit)
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 This function executes a Unprivileged STRT instruction for 8 bit values.
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 853 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /** \brief STRT Unprivileged (16 bit)
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 This function executes a Unprivileged STRT instruction for 16 bit values.
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 866 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 867 */
<> 144:ef7eb2e8f9f7 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
<> 144:ef7eb2e8f9f7 869 {
<> 144:ef7eb2e8f9f7 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /** \brief STRT Unprivileged (32 bit)
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 This function executes a Unprivileged STRT instruction for 32 bit values.
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 \param [in] value Value to store
<> 144:ef7eb2e8f9f7 879 \param [in] ptr Pointer to location
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
<> 144:ef7eb2e8f9f7 882 {
<> 144:ef7eb2e8f9f7 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
<> 144:ef7eb2e8f9f7 884 }
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 144:ef7eb2e8f9f7 890 /* IAR iccarm specific functions */
<> 144:ef7eb2e8f9f7 891 #include <cmsis_iar.h>
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 144:ef7eb2e8f9f7 895 /* TI CCS specific functions */
<> 144:ef7eb2e8f9f7 896 #include <cmsis_ccs.h>
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 144:ef7eb2e8f9f7 900 /* TASKING carm specific functions */
<> 144:ef7eb2e8f9f7 901 /*
<> 144:ef7eb2e8f9f7 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 144:ef7eb2e8f9f7 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 144:ef7eb2e8f9f7 904 * Including the CMSIS ones.
<> 144:ef7eb2e8f9f7 905 */
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 144:ef7eb2e8f9f7 909 /* Cosmic specific functions */
<> 144:ef7eb2e8f9f7 910 #include <cmsis_csm.h>
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 #endif
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 #endif /* __CORE_CMINSTR_H */