Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/core_cm4_simd.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:
JojoS
Date:
Sat Sep 10 15:32:04 2016 +0000
Revision:
147:ba84b7dc41a7
Parent:
144:ef7eb2e8f9f7 
added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file core_cm4_simd.h
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-M4 SIMD Header File
<> 144:ef7eb2e8f9f7 4 * @version V3.20
<> 144:ef7eb2e8f9f7 5 * @date 25. February 2013
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @note
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ******************************************************************************/
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 All rights reserved.
<> 144:ef7eb2e8f9f7 13 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 14 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 18 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 19 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 21 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 22 specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 34 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 39 extern "C" {
<> 144:ef7eb2e8f9f7 40 #endif
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifndef __CORE_CM4_SIMD_H
<> 144:ef7eb2e8f9f7 43 #define __CORE_CM4_SIMD_H
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /*******************************************************************************
<> 144:ef7eb2e8f9f7 47 * Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 48 ******************************************************************************/
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /* ################### Compiler specific Intrinsics ########################### */
<> 144:ef7eb2e8f9f7 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
<> 144:ef7eb2e8f9f7 53 Access to dedicated SIMD instructions
<> 144:ef7eb2e8f9f7 54 @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 144:ef7eb2e8f9f7 58 /* ARM armcc specific functions */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 #define __SADD8 __sadd8
<> 144:ef7eb2e8f9f7 62 #define __QADD8 __qadd8
<> 144:ef7eb2e8f9f7 63 #define __SHADD8 __shadd8
<> 144:ef7eb2e8f9f7 64 #define __UADD8 __uadd8
<> 144:ef7eb2e8f9f7 65 #define __UQADD8 __uqadd8
<> 144:ef7eb2e8f9f7 66 #define __UHADD8 __uhadd8
<> 144:ef7eb2e8f9f7 67 #define __SSUB8 __ssub8
<> 144:ef7eb2e8f9f7 68 #define __QSUB8 __qsub8
<> 144:ef7eb2e8f9f7 69 #define __SHSUB8 __shsub8
<> 144:ef7eb2e8f9f7 70 #define __USUB8 __usub8
<> 144:ef7eb2e8f9f7 71 #define __UQSUB8 __uqsub8
<> 144:ef7eb2e8f9f7 72 #define __UHSUB8 __uhsub8
<> 144:ef7eb2e8f9f7 73 #define __SADD16 __sadd16
<> 144:ef7eb2e8f9f7 74 #define __QADD16 __qadd16
<> 144:ef7eb2e8f9f7 75 #define __SHADD16 __shadd16
<> 144:ef7eb2e8f9f7 76 #define __UADD16 __uadd16
<> 144:ef7eb2e8f9f7 77 #define __UQADD16 __uqadd16
<> 144:ef7eb2e8f9f7 78 #define __UHADD16 __uhadd16
<> 144:ef7eb2e8f9f7 79 #define __SSUB16 __ssub16
<> 144:ef7eb2e8f9f7 80 #define __QSUB16 __qsub16
<> 144:ef7eb2e8f9f7 81 #define __SHSUB16 __shsub16
<> 144:ef7eb2e8f9f7 82 #define __USUB16 __usub16
<> 144:ef7eb2e8f9f7 83 #define __UQSUB16 __uqsub16
<> 144:ef7eb2e8f9f7 84 #define __UHSUB16 __uhsub16
<> 144:ef7eb2e8f9f7 85 #define __SASX __sasx
<> 144:ef7eb2e8f9f7 86 #define __QASX __qasx
<> 144:ef7eb2e8f9f7 87 #define __SHASX __shasx
<> 144:ef7eb2e8f9f7 88 #define __UASX __uasx
<> 144:ef7eb2e8f9f7 89 #define __UQASX __uqasx
<> 144:ef7eb2e8f9f7 90 #define __UHASX __uhasx
<> 144:ef7eb2e8f9f7 91 #define __SSAX __ssax
<> 144:ef7eb2e8f9f7 92 #define __QSAX __qsax
<> 144:ef7eb2e8f9f7 93 #define __SHSAX __shsax
<> 144:ef7eb2e8f9f7 94 #define __USAX __usax
<> 144:ef7eb2e8f9f7 95 #define __UQSAX __uqsax
<> 144:ef7eb2e8f9f7 96 #define __UHSAX __uhsax
<> 144:ef7eb2e8f9f7 97 #define __USAD8 __usad8
<> 144:ef7eb2e8f9f7 98 #define __USADA8 __usada8
<> 144:ef7eb2e8f9f7 99 #define __SSAT16 __ssat16
<> 144:ef7eb2e8f9f7 100 #define __USAT16 __usat16
<> 144:ef7eb2e8f9f7 101 #define __UXTB16 __uxtb16
<> 144:ef7eb2e8f9f7 102 #define __UXTAB16 __uxtab16
<> 144:ef7eb2e8f9f7 103 #define __SXTB16 __sxtb16
<> 144:ef7eb2e8f9f7 104 #define __SXTAB16 __sxtab16
<> 144:ef7eb2e8f9f7 105 #define __SMUAD __smuad
<> 144:ef7eb2e8f9f7 106 #define __SMUADX __smuadx
<> 144:ef7eb2e8f9f7 107 #define __SMLAD __smlad
<> 144:ef7eb2e8f9f7 108 #define __SMLADX __smladx
<> 144:ef7eb2e8f9f7 109 #define __SMLALD __smlald
<> 144:ef7eb2e8f9f7 110 #define __SMLALDX __smlaldx
<> 144:ef7eb2e8f9f7 111 #define __SMUSD __smusd
<> 144:ef7eb2e8f9f7 112 #define __SMUSDX __smusdx
<> 144:ef7eb2e8f9f7 113 #define __SMLSD __smlsd
<> 144:ef7eb2e8f9f7 114 #define __SMLSDX __smlsdx
<> 144:ef7eb2e8f9f7 115 #define __SMLSLD __smlsld
<> 144:ef7eb2e8f9f7 116 #define __SMLSLDX __smlsldx
<> 144:ef7eb2e8f9f7 117 #define __SEL __sel
<> 144:ef7eb2e8f9f7 118 #define __QADD __qadd
<> 144:ef7eb2e8f9f7 119 #define __QSUB __qsub
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
<> 144:ef7eb2e8f9f7 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
<> 144:ef7eb2e8f9f7 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
<> 144:ef7eb2e8f9f7 128 ((int64_t)(ARG3) << 32) ) >> 32))
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 144:ef7eb2e8f9f7 135 /* IAR iccarm specific functions */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 138 #include <cmsis_iar.h>
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 144:ef7eb2e8f9f7 145 /* TI CCS specific functions */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 148 #include <cmsis_ccs.h>
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 144:ef7eb2e8f9f7 155 /* GNU gcc specific functions */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 159 {
<> 144:ef7eb2e8f9f7 160 uint32_t result;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 163 return(result);
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 uint32_t result;
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 171 return(result);
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 uint32_t result;
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 179 return(result);
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 uint32_t result;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 187 return(result);
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 uint32_t result;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 195 return(result);
<> 144:ef7eb2e8f9f7 196 }
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 199 {
<> 144:ef7eb2e8f9f7 200 uint32_t result;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 203 return(result);
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 208 {
<> 144:ef7eb2e8f9f7 209 uint32_t result;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 212 return(result);
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 uint32_t result;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 220 return(result);
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 uint32_t result;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 228 return(result);
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 uint32_t result;
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 236 return(result);
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 uint32_t result;
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 244 return(result);
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 uint32_t result;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 252 return(result);
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 uint32_t result;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 261 return(result);
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 uint32_t result;
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 269 return(result);
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 uint32_t result;
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 277 return(result);
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 uint32_t result;
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 285 return(result);
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 uint32_t result;
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 293 return(result);
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 uint32_t result;
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 301 return(result);
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 305 {
<> 144:ef7eb2e8f9f7 306 uint32_t result;
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 309 return(result);
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 uint32_t result;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 317 return(result);
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 uint32_t result;
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 325 return(result);
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 uint32_t result;
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 333 return(result);
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 uint32_t result;
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 341 return(result);
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 uint32_t result;
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 349 return(result);
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 uint32_t result;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 357 return(result);
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 uint32_t result;
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 365 return(result);
<> 144:ef7eb2e8f9f7 366 }
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 uint32_t result;
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 373 return(result);
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 377 {
<> 144:ef7eb2e8f9f7 378 uint32_t result;
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 381 return(result);
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 385 {
<> 144:ef7eb2e8f9f7 386 uint32_t result;
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 389 return(result);
<> 144:ef7eb2e8f9f7 390 }
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 uint32_t result;
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 397 return(result);
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 uint32_t result;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 405 return(result);
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 uint32_t result;
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 413 return(result);
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 417 {
<> 144:ef7eb2e8f9f7 418 uint32_t result;
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 421 return(result);
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 uint32_t result;
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 429 return(result);
<> 144:ef7eb2e8f9f7 430 }
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 433 {
<> 144:ef7eb2e8f9f7 434 uint32_t result;
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 437 return(result);
<> 144:ef7eb2e8f9f7 438 }
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 uint32_t result;
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 445 return(result);
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 uint32_t result;
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 453 return(result);
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 uint32_t result;
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 461 return(result);
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 #define __SSAT16(ARG1,ARG2) \
<> 144:ef7eb2e8f9f7 465 ({ \
<> 144:ef7eb2e8f9f7 466 uint32_t __RES, __ARG1 = (ARG1); \
<> 144:ef7eb2e8f9f7 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 144:ef7eb2e8f9f7 468 __RES; \
<> 144:ef7eb2e8f9f7 469 })
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 #define __USAT16(ARG1,ARG2) \
<> 144:ef7eb2e8f9f7 472 ({ \
<> 144:ef7eb2e8f9f7 473 uint32_t __RES, __ARG1 = (ARG1); \
<> 144:ef7eb2e8f9f7 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 144:ef7eb2e8f9f7 475 __RES; \
<> 144:ef7eb2e8f9f7 476 })
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 uint32_t result;
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 144:ef7eb2e8f9f7 483 return(result);
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 487 {
<> 144:ef7eb2e8f9f7 488 uint32_t result;
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 491 return(result);
<> 144:ef7eb2e8f9f7 492 }
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 uint32_t result;
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 144:ef7eb2e8f9f7 499 return(result);
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 uint32_t result;
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 507 return(result);
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 uint32_t result;
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 515 return(result);
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 uint32_t result;
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 523 return(result);
<> 144:ef7eb2e8f9f7 524 }
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 527 {
<> 144:ef7eb2e8f9f7 528 uint32_t result;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 531 return(result);
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 535 {
<> 144:ef7eb2e8f9f7 536 uint32_t result;
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 539 return(result);
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 #define __SMLALD(ARG1,ARG2,ARG3) \
<> 144:ef7eb2e8f9f7 543 ({ \
<> 144:ef7eb2e8f9f7 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
<> 144:ef7eb2e8f9f7 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 144:ef7eb2e8f9f7 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 144:ef7eb2e8f9f7 547 })
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
<> 144:ef7eb2e8f9f7 550 ({ \
<> 144:ef7eb2e8f9f7 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
<> 144:ef7eb2e8f9f7 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 144:ef7eb2e8f9f7 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 144:ef7eb2e8f9f7 554 })
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 uint32_t result;
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 561 return(result);
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 uint32_t result;
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 569 return(result);
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 uint32_t result;
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 577 return(result);
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 uint32_t result;
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 585 return(result);
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
<> 144:ef7eb2e8f9f7 589 ({ \
<> 144:ef7eb2e8f9f7 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
<> 144:ef7eb2e8f9f7 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 144:ef7eb2e8f9f7 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 144:ef7eb2e8f9f7 593 })
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
<> 144:ef7eb2e8f9f7 596 ({ \
<> 144:ef7eb2e8f9f7 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
<> 144:ef7eb2e8f9f7 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
<> 144:ef7eb2e8f9f7 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
<> 144:ef7eb2e8f9f7 600 })
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 uint32_t result;
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 607 return(result);
<> 144:ef7eb2e8f9f7 608 }
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 uint32_t result;
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 615 return(result);
<> 144:ef7eb2e8f9f7 616 }
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 uint32_t result;
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 623 return(result);
<> 144:ef7eb2e8f9f7 624 }
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 #define __PKHBT(ARG1,ARG2,ARG3) \
<> 144:ef7eb2e8f9f7 627 ({ \
<> 144:ef7eb2e8f9f7 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 144:ef7eb2e8f9f7 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 144:ef7eb2e8f9f7 630 __RES; \
<> 144:ef7eb2e8f9f7 631 })
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 #define __PKHTB(ARG1,ARG2,ARG3) \
<> 144:ef7eb2e8f9f7 634 ({ \
<> 144:ef7eb2e8f9f7 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 144:ef7eb2e8f9f7 636 if (ARG3 == 0) \
<> 144:ef7eb2e8f9f7 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
<> 144:ef7eb2e8f9f7 638 else \
<> 144:ef7eb2e8f9f7 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 144:ef7eb2e8f9f7 640 __RES; \
<> 144:ef7eb2e8f9f7 641 })
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 int32_t result;
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 648 return(result);
<> 144:ef7eb2e8f9f7 649 }
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 144:ef7eb2e8f9f7 656 /* TASKING carm specific functions */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 660 /* not yet supported */
<> 144:ef7eb2e8f9f7 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 #endif
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /*@} end of group CMSIS_SIMD_intrinsics */
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 #endif /* __CORE_CM4_SIMD_H */
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673 #endif