mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

Users » JojoS » Code » mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

targets/cmsis/core_cm3.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

Committer:: JojoS
Date:: Sat Sep 10 15:32:04 2016 +0000
Revision:: 147:ba84b7dc41a7
Parent:: 144:ef7eb2e8f9f7

added prescaler for 16 bit timers (solution as in LPC11xx), default prescaler 31 for max 28 ms period time

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/************************************************************************//
<>	144:ef7eb2e8f9f7	2	* @file core_cm3.h
<>	144:ef7eb2e8f9f7	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
<>	144:ef7eb2e8f9f7	4	* @version V4.10
<>	144:ef7eb2e8f9f7	5	* @date 18. March 2015
<>	144:ef7eb2e8f9f7	6	*
<>	144:ef7eb2e8f9f7	7	* @note
<>	144:ef7eb2e8f9f7	8	*
<>	144:ef7eb2e8f9f7	9	******************************************************************************/
<>	144:ef7eb2e8f9f7	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
<>	144:ef7eb2e8f9f7	11
<>	144:ef7eb2e8f9f7	12	All rights reserved.
<>	144:ef7eb2e8f9f7	13	Redistribution and use in source and binary forms, with or without
<>	144:ef7eb2e8f9f7	14	modification, are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	- Redistributions of source code must retain the above copyright
<>	144:ef7eb2e8f9f7	16	notice, this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	- Redistributions in binary form must reproduce the above copyright
<>	144:ef7eb2e8f9f7	18	notice, this list of conditions and the following disclaimer in the
<>	144:ef7eb2e8f9f7	19	documentation and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	- Neither the name of ARM nor the names of its contributors may be used
<>	144:ef7eb2e8f9f7	21	to endorse or promote products derived from this software without
<>	144:ef7eb2e8f9f7	22	specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<>	144:ef7eb2e8f9f7	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<>	144:ef7eb2e8f9f7	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<>	144:ef7eb2e8f9f7	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<>	144:ef7eb2e8f9f7	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<>	144:ef7eb2e8f9f7	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<>	144:ef7eb2e8f9f7	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<>	144:ef7eb2e8f9f7	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<>	144:ef7eb2e8f9f7	34	POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	35	---------------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	36
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	#if defined ( __ICCARM__ )
<>	144:ef7eb2e8f9f7	39	#pragma system_include /* treat file as system include file for MISRA check */
<>	144:ef7eb2e8f9f7	40	#endif
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifndef __CORE_CM3_H_GENERIC
<>	144:ef7eb2e8f9f7	43	#define __CORE_CM3_H_GENERIC
<>	144:ef7eb2e8f9f7	44
<>	144:ef7eb2e8f9f7	45	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	46	extern "C" {
<>	144:ef7eb2e8f9f7	47	#endif
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<>	144:ef7eb2e8f9f7	50	CMSIS violates the following MISRA-C:2004 rules:
<>	144:ef7eb2e8f9f7	51
<>	144:ef7eb2e8f9f7	52	\li Required Rule 8.5, object/function definition in header file.<br>
<>	144:ef7eb2e8f9f7	53	Function definitions in header files are used to allow 'inlining'.
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<>	144:ef7eb2e8f9f7	56	Unions are used for effective representation of core registers.
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
<>	144:ef7eb2e8f9f7	59	Function-like macros are used to allow more efficient code.
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	/*******************************************************************************
<>	144:ef7eb2e8f9f7	64	* CMSIS definitions
<>	144:ef7eb2e8f9f7	65	******************************************************************************/
<>	144:ef7eb2e8f9f7	66	/** \ingroup Cortex_M3
<>	144:ef7eb2e8f9f7	67	@{
<>	144:ef7eb2e8f9f7	68	*/
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	/* CMSIS CM3 definitions */
<>	144:ef7eb2e8f9f7	71	#define __CM3_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
<>	144:ef7eb2e8f9f7	72	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
<>	144:ef7eb2e8f9f7	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
<>	144:ef7eb2e8f9f7	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	#if defined ( __CC_ARM )
<>	144:ef7eb2e8f9f7	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
<>	144:ef7eb2e8f9f7	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
<>	144:ef7eb2e8f9f7	82	#define __STATIC_INLINE static __inline
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84	#elif defined ( __GNUC__ )
<>	144:ef7eb2e8f9f7	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
<>	144:ef7eb2e8f9f7	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
<>	144:ef7eb2e8f9f7	87	#define __STATIC_INLINE static inline
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	#elif defined ( __ICCARM__ )
<>	144:ef7eb2e8f9f7	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
<>	144:ef7eb2e8f9f7	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
<>	144:ef7eb2e8f9f7	92	#define __STATIC_INLINE static inline
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	#elif defined ( __TMS470__ )
<>	144:ef7eb2e8f9f7	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
<>	144:ef7eb2e8f9f7	96	#define __STATIC_INLINE static inline
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	#elif defined ( __TASKING__ )
<>	144:ef7eb2e8f9f7	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
<>	144:ef7eb2e8f9f7	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
<>	144:ef7eb2e8f9f7	101	#define __STATIC_INLINE static inline
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	#elif defined ( __CSMC__ )
<>	144:ef7eb2e8f9f7	104	#define __packed
<>	144:ef7eb2e8f9f7	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
<>	144:ef7eb2e8f9f7	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
<>	144:ef7eb2e8f9f7	107	#define __STATIC_INLINE static inline
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	#endif
<>	144:ef7eb2e8f9f7	110
<>	144:ef7eb2e8f9f7	111	/** __FPU_USED indicates whether an FPU is used or not.
<>	144:ef7eb2e8f9f7	112	This core does not support an FPU at all
<>	144:ef7eb2e8f9f7	113	*/
<>	144:ef7eb2e8f9f7	114	#define __FPU_USED 0
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	#if defined ( __CC_ARM )
<>	144:ef7eb2e8f9f7	117	#if defined __TARGET_FPU_VFP
<>	144:ef7eb2e8f9f7	118	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	144:ef7eb2e8f9f7	119	#endif
<>	144:ef7eb2e8f9f7	120
<>	144:ef7eb2e8f9f7	121	#elif defined ( __GNUC__ )
<>	144:ef7eb2e8f9f7	122	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
<>	144:ef7eb2e8f9f7	123	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	144:ef7eb2e8f9f7	124	#endif
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	#elif defined ( __ICCARM__ )
<>	144:ef7eb2e8f9f7	127	#if defined __ARMVFP__
<>	144:ef7eb2e8f9f7	128	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	144:ef7eb2e8f9f7	129	#endif
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	#elif defined ( __TMS470__ )
<>	144:ef7eb2e8f9f7	132	#if defined __TI__VFP_SUPPORT____
<>	144:ef7eb2e8f9f7	133	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	144:ef7eb2e8f9f7	134	#endif
<>	144:ef7eb2e8f9f7	135
<>	144:ef7eb2e8f9f7	136	#elif defined ( __TASKING__ )
<>	144:ef7eb2e8f9f7	137	#if defined __FPU_VFP__
<>	144:ef7eb2e8f9f7	138	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	144:ef7eb2e8f9f7	139	#endif
<>	144:ef7eb2e8f9f7	140
<>	144:ef7eb2e8f9f7	141	#elif defined ( __CSMC__ ) /* Cosmic */
<>	144:ef7eb2e8f9f7	142	#if ( __CSMC__ & 0x400) // FPU present for parser
<>	144:ef7eb2e8f9f7	143	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<>	144:ef7eb2e8f9f7	144	#endif
<>	144:ef7eb2e8f9f7	145	#endif
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	#include <stdint.h> /* standard types definitions */
<>	144:ef7eb2e8f9f7	148	#include <core_cmInstr.h> /* Core Instruction Access */
<>	144:ef7eb2e8f9f7	149	#include <core_cmFunc.h> /* Core Function Access */
<>	144:ef7eb2e8f9f7	150
<>	144:ef7eb2e8f9f7	151	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	152	}
<>	144:ef7eb2e8f9f7	153	#endif
<>	144:ef7eb2e8f9f7	154
<>	144:ef7eb2e8f9f7	155	#endif /* __CORE_CM3_H_GENERIC */
<>	144:ef7eb2e8f9f7	156
<>	144:ef7eb2e8f9f7	157	#ifndef __CMSIS_GENERIC
<>	144:ef7eb2e8f9f7	158
<>	144:ef7eb2e8f9f7	159	#ifndef __CORE_CM3_H_DEPENDANT
<>	144:ef7eb2e8f9f7	160	#define __CORE_CM3_H_DEPENDANT
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	163	extern "C" {
<>	144:ef7eb2e8f9f7	164	#endif
<>	144:ef7eb2e8f9f7	165
<>	144:ef7eb2e8f9f7	166	/* check device defines and use defaults */
<>	144:ef7eb2e8f9f7	167	#if defined __CHECK_DEVICE_DEFINES
<>	144:ef7eb2e8f9f7	168	#ifndef __CM3_REV
<>	144:ef7eb2e8f9f7	169	#define __CM3_REV 0x0200
<>	144:ef7eb2e8f9f7	170	#warning "__CM3_REV not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	171	#endif
<>	144:ef7eb2e8f9f7	172
<>	144:ef7eb2e8f9f7	173	#ifndef __MPU_PRESENT
<>	144:ef7eb2e8f9f7	174	#define __MPU_PRESENT 0
<>	144:ef7eb2e8f9f7	175	#warning "__MPU_PRESENT not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	176	#endif
<>	144:ef7eb2e8f9f7	177
<>	144:ef7eb2e8f9f7	178	#ifndef __NVIC_PRIO_BITS
<>	144:ef7eb2e8f9f7	179	#define __NVIC_PRIO_BITS 4
<>	144:ef7eb2e8f9f7	180	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	181	#endif
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183	#ifndef __Vendor_SysTickConfig
<>	144:ef7eb2e8f9f7	184	#define __Vendor_SysTickConfig 0
<>	144:ef7eb2e8f9f7	185	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<>	144:ef7eb2e8f9f7	186	#endif
<>	144:ef7eb2e8f9f7	187	#endif
<>	144:ef7eb2e8f9f7	188
<>	144:ef7eb2e8f9f7	189	/* IO definitions (access restrictions to peripheral registers) */
<>	144:ef7eb2e8f9f7	190	/**
<>	144:ef7eb2e8f9f7	191	\defgroup CMSIS_glob_defs CMSIS Global Defines
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	<strong>IO Type Qualifiers</strong> are used
<>	144:ef7eb2e8f9f7	194	\li to specify the access to peripheral variables.
<>	144:ef7eb2e8f9f7	195	\li for automatic generation of peripheral register debug information.
<>	144:ef7eb2e8f9f7	196	*/
<>	144:ef7eb2e8f9f7	197	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	198	#define __I volatile /!< Defines 'read only' permissions /
<>	144:ef7eb2e8f9f7	199	#else
<>	144:ef7eb2e8f9f7	200	#define __I volatile const /!< Defines 'read only' permissions /
<>	144:ef7eb2e8f9f7	201	#endif
<>	144:ef7eb2e8f9f7	202	#define __O volatile /!< Defines 'write only' permissions /
<>	144:ef7eb2e8f9f7	203	#define __IO volatile /!< Defines 'read / write' permissions /
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	/@} end of group Cortex_M3 /
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207
<>	144:ef7eb2e8f9f7	208
<>	144:ef7eb2e8f9f7	209	/*******************************************************************************
<>	144:ef7eb2e8f9f7	210	* Register Abstraction
<>	144:ef7eb2e8f9f7	211	Core Register contain:
<>	144:ef7eb2e8f9f7	212	- Core Register
<>	144:ef7eb2e8f9f7	213	- Core NVIC Register
<>	144:ef7eb2e8f9f7	214	- Core SCB Register
<>	144:ef7eb2e8f9f7	215	- Core SysTick Register
<>	144:ef7eb2e8f9f7	216	- Core Debug Register
<>	144:ef7eb2e8f9f7	217	- Core MPU Register
<>	144:ef7eb2e8f9f7	218	******************************************************************************/
<>	144:ef7eb2e8f9f7	219	/** \defgroup CMSIS_core_register Defines and Type Definitions
<>	144:ef7eb2e8f9f7	220	\brief Type definitions and defines for Cortex-M processor based devices.
<>	144:ef7eb2e8f9f7	221	*/
<>	144:ef7eb2e8f9f7	222
<>	144:ef7eb2e8f9f7	223	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	224	\defgroup CMSIS_CORE Status and Control Registers
<>	144:ef7eb2e8f9f7	225	\brief Core Register type definitions.
<>	144:ef7eb2e8f9f7	226	@{
<>	144:ef7eb2e8f9f7	227	*/
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	/** \brief Union type to access the Application Program Status Register (APSR).
<>	144:ef7eb2e8f9f7	230	*/
<>	144:ef7eb2e8f9f7	231	typedef union
<>	144:ef7eb2e8f9f7	232	{
<>	144:ef7eb2e8f9f7	233	struct
<>	144:ef7eb2e8f9f7	234	{
<>	144:ef7eb2e8f9f7	235	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
<>	144:ef7eb2e8f9f7	236	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
<>	144:ef7eb2e8f9f7	237	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
<>	144:ef7eb2e8f9f7	238	uint32_t C:1; /!< bit: 29 Carry condition code flag /
<>	144:ef7eb2e8f9f7	239	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
<>	144:ef7eb2e8f9f7	240	uint32_t N:1; /!< bit: 31 Negative condition code flag /
<>	144:ef7eb2e8f9f7	241	} b; /!< Structure used for bit access /
<>	144:ef7eb2e8f9f7	242	uint32_t w; /!< Type used for word access /
<>	144:ef7eb2e8f9f7	243	} APSR_Type;
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	/* APSR Register Definitions */
<>	144:ef7eb2e8f9f7	246	#define APSR_N_Pos 31 /!< APSR: N Position /
<>	144:ef7eb2e8f9f7	247	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	#define APSR_Z_Pos 30 /!< APSR: Z Position /
<>	144:ef7eb2e8f9f7	250	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
<>	144:ef7eb2e8f9f7	251
<>	144:ef7eb2e8f9f7	252	#define APSR_C_Pos 29 /!< APSR: C Position /
<>	144:ef7eb2e8f9f7	253	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255	#define APSR_V_Pos 28 /!< APSR: V Position /
<>	144:ef7eb2e8f9f7	256	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	#define APSR_Q_Pos 27 /!< APSR: Q Position /
<>	144:ef7eb2e8f9f7	259	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
<>	144:ef7eb2e8f9f7	260
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
<>	144:ef7eb2e8f9f7	263	*/
<>	144:ef7eb2e8f9f7	264	typedef union
<>	144:ef7eb2e8f9f7	265	{
<>	144:ef7eb2e8f9f7	266	struct
<>	144:ef7eb2e8f9f7	267	{
<>	144:ef7eb2e8f9f7	268	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
<>	144:ef7eb2e8f9f7	269	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
<>	144:ef7eb2e8f9f7	270	} b; /!< Structure used for bit access /
<>	144:ef7eb2e8f9f7	271	uint32_t w; /!< Type used for word access /
<>	144:ef7eb2e8f9f7	272	} IPSR_Type;
<>	144:ef7eb2e8f9f7	273
<>	144:ef7eb2e8f9f7	274	/* IPSR Register Definitions */
<>	144:ef7eb2e8f9f7	275	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
<>	144:ef7eb2e8f9f7	276	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
<>	144:ef7eb2e8f9f7	277
<>	144:ef7eb2e8f9f7	278
<>	144:ef7eb2e8f9f7	279	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<>	144:ef7eb2e8f9f7	280	*/
<>	144:ef7eb2e8f9f7	281	typedef union
<>	144:ef7eb2e8f9f7	282	{
<>	144:ef7eb2e8f9f7	283	struct
<>	144:ef7eb2e8f9f7	284	{
<>	144:ef7eb2e8f9f7	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
<>	144:ef7eb2e8f9f7	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
<>	144:ef7eb2e8f9f7	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
<>	144:ef7eb2e8f9f7	288	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
<>	144:ef7eb2e8f9f7	289	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
<>	144:ef7eb2e8f9f7	290	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
<>	144:ef7eb2e8f9f7	291	uint32_t C:1; /!< bit: 29 Carry condition code flag /
<>	144:ef7eb2e8f9f7	292	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
<>	144:ef7eb2e8f9f7	293	uint32_t N:1; /!< bit: 31 Negative condition code flag /
<>	144:ef7eb2e8f9f7	294	} b; /!< Structure used for bit access /
<>	144:ef7eb2e8f9f7	295	uint32_t w; /!< Type used for word access /
<>	144:ef7eb2e8f9f7	296	} xPSR_Type;
<>	144:ef7eb2e8f9f7	297
<>	144:ef7eb2e8f9f7	298	/* xPSR Register Definitions */
<>	144:ef7eb2e8f9f7	299	#define xPSR_N_Pos 31 /!< xPSR: N Position /
<>	144:ef7eb2e8f9f7	300	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
<>	144:ef7eb2e8f9f7	303	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
<>	144:ef7eb2e8f9f7	304
<>	144:ef7eb2e8f9f7	305	#define xPSR_C_Pos 29 /!< xPSR: C Position /
<>	144:ef7eb2e8f9f7	306	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	#define xPSR_V_Pos 28 /!< xPSR: V Position /
<>	144:ef7eb2e8f9f7	309	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
<>	144:ef7eb2e8f9f7	310
<>	144:ef7eb2e8f9f7	311	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
<>	144:ef7eb2e8f9f7	312	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
<>	144:ef7eb2e8f9f7	315	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	#define xPSR_T_Pos 24 /!< xPSR: T Position /
<>	144:ef7eb2e8f9f7	318	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
<>	144:ef7eb2e8f9f7	321	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
<>	144:ef7eb2e8f9f7	322
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	/** \brief Union type to access the Control Registers (CONTROL).
<>	144:ef7eb2e8f9f7	325	*/
<>	144:ef7eb2e8f9f7	326	typedef union
<>	144:ef7eb2e8f9f7	327	{
<>	144:ef7eb2e8f9f7	328	struct
<>	144:ef7eb2e8f9f7	329	{
<>	144:ef7eb2e8f9f7	330	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
<>	144:ef7eb2e8f9f7	331	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
<>	144:ef7eb2e8f9f7	332	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
<>	144:ef7eb2e8f9f7	333	} b; /!< Structure used for bit access /
<>	144:ef7eb2e8f9f7	334	uint32_t w; /!< Type used for word access /
<>	144:ef7eb2e8f9f7	335	} CONTROL_Type;
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/* CONTROL Register Definitions */
<>	144:ef7eb2e8f9f7	338	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
<>	144:ef7eb2e8f9f7	339	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
<>	144:ef7eb2e8f9f7	340
<>	144:ef7eb2e8f9f7	341	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
<>	144:ef7eb2e8f9f7	342	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
<>	144:ef7eb2e8f9f7	343
<>	144:ef7eb2e8f9f7	344	/@} end of group CMSIS_CORE /
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	348	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<>	144:ef7eb2e8f9f7	349	\brief Type definitions for the NVIC Registers
<>	144:ef7eb2e8f9f7	350	@{
<>	144:ef7eb2e8f9f7	351	*/
<>	144:ef7eb2e8f9f7	352
<>	144:ef7eb2e8f9f7	353	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<>	144:ef7eb2e8f9f7	354	*/
<>	144:ef7eb2e8f9f7	355	typedef struct
<>	144:ef7eb2e8f9f7	356	{
<>	144:ef7eb2e8f9f7	357	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
<>	144:ef7eb2e8f9f7	358	uint32_t RESERVED0[24];
<>	144:ef7eb2e8f9f7	359	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
<>	144:ef7eb2e8f9f7	360	uint32_t RSERVED1[24];
<>	144:ef7eb2e8f9f7	361	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
<>	144:ef7eb2e8f9f7	362	uint32_t RESERVED2[24];
<>	144:ef7eb2e8f9f7	363	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
<>	144:ef7eb2e8f9f7	364	uint32_t RESERVED3[24];
<>	144:ef7eb2e8f9f7	365	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
<>	144:ef7eb2e8f9f7	366	uint32_t RESERVED4[56];
<>	144:ef7eb2e8f9f7	367	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
<>	144:ef7eb2e8f9f7	368	uint32_t RESERVED5[644];
<>	144:ef7eb2e8f9f7	369	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
<>	144:ef7eb2e8f9f7	370	} NVIC_Type;
<>	144:ef7eb2e8f9f7	371
<>	144:ef7eb2e8f9f7	372	/* Software Triggered Interrupt Register Definitions */
<>	144:ef7eb2e8f9f7	373	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
<>	144:ef7eb2e8f9f7	374	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/@} end of group CMSIS_NVIC /
<>	144:ef7eb2e8f9f7	377
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	380	\defgroup CMSIS_SCB System Control Block (SCB)
<>	144:ef7eb2e8f9f7	381	\brief Type definitions for the System Control Block Registers
<>	144:ef7eb2e8f9f7	382	@{
<>	144:ef7eb2e8f9f7	383	*/
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	/** \brief Structure type to access the System Control Block (SCB).
<>	144:ef7eb2e8f9f7	386	*/
<>	144:ef7eb2e8f9f7	387	typedef struct
<>	144:ef7eb2e8f9f7	388	{
<>	144:ef7eb2e8f9f7	389	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
<>	144:ef7eb2e8f9f7	390	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
<>	144:ef7eb2e8f9f7	391	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
<>	144:ef7eb2e8f9f7	392	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
<>	144:ef7eb2e8f9f7	393	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
<>	144:ef7eb2e8f9f7	394	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
<>	144:ef7eb2e8f9f7	395	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
<>	144:ef7eb2e8f9f7	396	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
<>	144:ef7eb2e8f9f7	397	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
<>	144:ef7eb2e8f9f7	398	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
<>	144:ef7eb2e8f9f7	399	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
<>	144:ef7eb2e8f9f7	400	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
<>	144:ef7eb2e8f9f7	401	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
<>	144:ef7eb2e8f9f7	402	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
<>	144:ef7eb2e8f9f7	403	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
<>	144:ef7eb2e8f9f7	404	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
<>	144:ef7eb2e8f9f7	405	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
<>	144:ef7eb2e8f9f7	406	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
<>	144:ef7eb2e8f9f7	407	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
<>	144:ef7eb2e8f9f7	408	uint32_t RESERVED0[5];
<>	144:ef7eb2e8f9f7	409	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
<>	144:ef7eb2e8f9f7	410	} SCB_Type;
<>	144:ef7eb2e8f9f7	411
<>	144:ef7eb2e8f9f7	412	/* SCB CPUID Register Definitions */
<>	144:ef7eb2e8f9f7	413	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
<>	144:ef7eb2e8f9f7	414	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
<>	144:ef7eb2e8f9f7	417	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
<>	144:ef7eb2e8f9f7	420	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
<>	144:ef7eb2e8f9f7	423	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
<>	144:ef7eb2e8f9f7	424
<>	144:ef7eb2e8f9f7	425	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
<>	144:ef7eb2e8f9f7	426	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	/* SCB Interrupt Control State Register Definitions */
<>	144:ef7eb2e8f9f7	429	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
<>	144:ef7eb2e8f9f7	430	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
<>	144:ef7eb2e8f9f7	431
<>	144:ef7eb2e8f9f7	432	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
<>	144:ef7eb2e8f9f7	433	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
<>	144:ef7eb2e8f9f7	434
<>	144:ef7eb2e8f9f7	435	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
<>	144:ef7eb2e8f9f7	436	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
<>	144:ef7eb2e8f9f7	439	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
<>	144:ef7eb2e8f9f7	440
<>	144:ef7eb2e8f9f7	441	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
<>	144:ef7eb2e8f9f7	442	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
<>	144:ef7eb2e8f9f7	445	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
<>	144:ef7eb2e8f9f7	448	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
<>	144:ef7eb2e8f9f7	451	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
<>	144:ef7eb2e8f9f7	452
<>	144:ef7eb2e8f9f7	453	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
<>	144:ef7eb2e8f9f7	454	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
<>	144:ef7eb2e8f9f7	455
<>	144:ef7eb2e8f9f7	456	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
<>	144:ef7eb2e8f9f7	457	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	/* SCB Vector Table Offset Register Definitions */
<>	144:ef7eb2e8f9f7	460	#if (__CM3_REV < 0x0201) /* core r2p1 */
<>	144:ef7eb2e8f9f7	461	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
<>	144:ef7eb2e8f9f7	462	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
<>	144:ef7eb2e8f9f7	463
<>	144:ef7eb2e8f9f7	464	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
<>	144:ef7eb2e8f9f7	465	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
<>	144:ef7eb2e8f9f7	466	#else
<>	144:ef7eb2e8f9f7	467	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
<>	144:ef7eb2e8f9f7	468	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
<>	144:ef7eb2e8f9f7	469	#endif
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	/* SCB Application Interrupt and Reset Control Register Definitions */
<>	144:ef7eb2e8f9f7	472	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
<>	144:ef7eb2e8f9f7	473	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
<>	144:ef7eb2e8f9f7	474
<>	144:ef7eb2e8f9f7	475	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
<>	144:ef7eb2e8f9f7	476	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
<>	144:ef7eb2e8f9f7	479	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
<>	144:ef7eb2e8f9f7	482	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
<>	144:ef7eb2e8f9f7	483
<>	144:ef7eb2e8f9f7	484	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
<>	144:ef7eb2e8f9f7	485	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
<>	144:ef7eb2e8f9f7	486
<>	144:ef7eb2e8f9f7	487	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
<>	144:ef7eb2e8f9f7	488	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
<>	144:ef7eb2e8f9f7	489
<>	144:ef7eb2e8f9f7	490	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
<>	144:ef7eb2e8f9f7	491	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
<>	144:ef7eb2e8f9f7	492
<>	144:ef7eb2e8f9f7	493	/* SCB System Control Register Definitions */
<>	144:ef7eb2e8f9f7	494	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
<>	144:ef7eb2e8f9f7	495	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
<>	144:ef7eb2e8f9f7	496
<>	144:ef7eb2e8f9f7	497	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
<>	144:ef7eb2e8f9f7	498	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
<>	144:ef7eb2e8f9f7	499
<>	144:ef7eb2e8f9f7	500	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
<>	144:ef7eb2e8f9f7	501	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/* SCB Configuration Control Register Definitions */
<>	144:ef7eb2e8f9f7	504	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
<>	144:ef7eb2e8f9f7	505	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
<>	144:ef7eb2e8f9f7	508	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
<>	144:ef7eb2e8f9f7	509
<>	144:ef7eb2e8f9f7	510	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
<>	144:ef7eb2e8f9f7	511	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
<>	144:ef7eb2e8f9f7	514	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
<>	144:ef7eb2e8f9f7	515
<>	144:ef7eb2e8f9f7	516	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
<>	144:ef7eb2e8f9f7	517	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
<>	144:ef7eb2e8f9f7	518
<>	144:ef7eb2e8f9f7	519	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
<>	144:ef7eb2e8f9f7	520	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
<>	144:ef7eb2e8f9f7	521
<>	144:ef7eb2e8f9f7	522	/* SCB System Handler Control and State Register Definitions */
<>	144:ef7eb2e8f9f7	523	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
<>	144:ef7eb2e8f9f7	524	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
<>	144:ef7eb2e8f9f7	527	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
<>	144:ef7eb2e8f9f7	528
<>	144:ef7eb2e8f9f7	529	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
<>	144:ef7eb2e8f9f7	530	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
<>	144:ef7eb2e8f9f7	531
<>	144:ef7eb2e8f9f7	532	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
<>	144:ef7eb2e8f9f7	533	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
<>	144:ef7eb2e8f9f7	534
<>	144:ef7eb2e8f9f7	535	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
<>	144:ef7eb2e8f9f7	536	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
<>	144:ef7eb2e8f9f7	537
<>	144:ef7eb2e8f9f7	538	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
<>	144:ef7eb2e8f9f7	539	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
<>	144:ef7eb2e8f9f7	540
<>	144:ef7eb2e8f9f7	541	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
<>	144:ef7eb2e8f9f7	542	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
<>	144:ef7eb2e8f9f7	545	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
<>	144:ef7eb2e8f9f7	546
<>	144:ef7eb2e8f9f7	547	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
<>	144:ef7eb2e8f9f7	548	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
<>	144:ef7eb2e8f9f7	551	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
<>	144:ef7eb2e8f9f7	554	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
<>	144:ef7eb2e8f9f7	555
<>	144:ef7eb2e8f9f7	556	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
<>	144:ef7eb2e8f9f7	557	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
<>	144:ef7eb2e8f9f7	558
<>	144:ef7eb2e8f9f7	559	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
<>	144:ef7eb2e8f9f7	560	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
<>	144:ef7eb2e8f9f7	563	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
<>	144:ef7eb2e8f9f7	564
<>	144:ef7eb2e8f9f7	565	/* SCB Configurable Fault Status Registers Definitions */
<>	144:ef7eb2e8f9f7	566	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
<>	144:ef7eb2e8f9f7	567	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
<>	144:ef7eb2e8f9f7	570	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
<>	144:ef7eb2e8f9f7	571
<>	144:ef7eb2e8f9f7	572	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
<>	144:ef7eb2e8f9f7	573	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/* SCB Hard Fault Status Registers Definitions */
<>	144:ef7eb2e8f9f7	576	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
<>	144:ef7eb2e8f9f7	577	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
<>	144:ef7eb2e8f9f7	578
<>	144:ef7eb2e8f9f7	579	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
<>	144:ef7eb2e8f9f7	580	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
<>	144:ef7eb2e8f9f7	583	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
<>	144:ef7eb2e8f9f7	584
<>	144:ef7eb2e8f9f7	585	/* SCB Debug Fault Status Register Definitions */
<>	144:ef7eb2e8f9f7	586	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
<>	144:ef7eb2e8f9f7	587	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
<>	144:ef7eb2e8f9f7	590	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
<>	144:ef7eb2e8f9f7	591
<>	144:ef7eb2e8f9f7	592	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
<>	144:ef7eb2e8f9f7	593	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
<>	144:ef7eb2e8f9f7	596	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
<>	144:ef7eb2e8f9f7	599	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
<>	144:ef7eb2e8f9f7	600
<>	144:ef7eb2e8f9f7	601	/@} end of group CMSIS_SCB /
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603
<>	144:ef7eb2e8f9f7	604	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	605	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
<>	144:ef7eb2e8f9f7	606	\brief Type definitions for the System Control and ID Register not in the SCB
<>	144:ef7eb2e8f9f7	607	@{
<>	144:ef7eb2e8f9f7	608	*/
<>	144:ef7eb2e8f9f7	609
<>	144:ef7eb2e8f9f7	610	/** \brief Structure type to access the System Control and ID Register not in the SCB.
<>	144:ef7eb2e8f9f7	611	*/
<>	144:ef7eb2e8f9f7	612	typedef struct
<>	144:ef7eb2e8f9f7	613	{
<>	144:ef7eb2e8f9f7	614	uint32_t RESERVED0[1];
<>	144:ef7eb2e8f9f7	615	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
<>	144:ef7eb2e8f9f7	616	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
<>	144:ef7eb2e8f9f7	617	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
<>	144:ef7eb2e8f9f7	618	#else
<>	144:ef7eb2e8f9f7	619	uint32_t RESERVED1[1];
<>	144:ef7eb2e8f9f7	620	#endif
<>	144:ef7eb2e8f9f7	621	} SCnSCB_Type;
<>	144:ef7eb2e8f9f7	622
<>	144:ef7eb2e8f9f7	623	/* Interrupt Controller Type Register Definitions */
<>	144:ef7eb2e8f9f7	624	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
<>	144:ef7eb2e8f9f7	625	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
<>	144:ef7eb2e8f9f7	626
<>	144:ef7eb2e8f9f7	627	/* Auxiliary Control Register Definitions */
<>	144:ef7eb2e8f9f7	628
<>	144:ef7eb2e8f9f7	629	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
<>	144:ef7eb2e8f9f7	630	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
<>	144:ef7eb2e8f9f7	633	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
<>	144:ef7eb2e8f9f7	634
<>	144:ef7eb2e8f9f7	635	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
<>	144:ef7eb2e8f9f7	636	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
<>	144:ef7eb2e8f9f7	637
<>	144:ef7eb2e8f9f7	638	/@} end of group CMSIS_SCnotSCB /
<>	144:ef7eb2e8f9f7	639
<>	144:ef7eb2e8f9f7	640
<>	144:ef7eb2e8f9f7	641	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	642	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
<>	144:ef7eb2e8f9f7	643	\brief Type definitions for the System Timer Registers.
<>	144:ef7eb2e8f9f7	644	@{
<>	144:ef7eb2e8f9f7	645	*/
<>	144:ef7eb2e8f9f7	646
<>	144:ef7eb2e8f9f7	647	/** \brief Structure type to access the System Timer (SysTick).
<>	144:ef7eb2e8f9f7	648	*/
<>	144:ef7eb2e8f9f7	649	typedef struct
<>	144:ef7eb2e8f9f7	650	{
<>	144:ef7eb2e8f9f7	651	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
<>	144:ef7eb2e8f9f7	652	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
<>	144:ef7eb2e8f9f7	653	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
<>	144:ef7eb2e8f9f7	654	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
<>	144:ef7eb2e8f9f7	655	} SysTick_Type;
<>	144:ef7eb2e8f9f7	656
<>	144:ef7eb2e8f9f7	657	/* SysTick Control / Status Register Definitions */
<>	144:ef7eb2e8f9f7	658	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
<>	144:ef7eb2e8f9f7	659	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
<>	144:ef7eb2e8f9f7	662	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
<>	144:ef7eb2e8f9f7	665	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
<>	144:ef7eb2e8f9f7	668	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
<>	144:ef7eb2e8f9f7	669
<>	144:ef7eb2e8f9f7	670	/* SysTick Reload Register Definitions */
<>	144:ef7eb2e8f9f7	671	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
<>	144:ef7eb2e8f9f7	672	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
<>	144:ef7eb2e8f9f7	673
<>	144:ef7eb2e8f9f7	674	/* SysTick Current Register Definitions */
<>	144:ef7eb2e8f9f7	675	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
<>	144:ef7eb2e8f9f7	676	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
<>	144:ef7eb2e8f9f7	677
<>	144:ef7eb2e8f9f7	678	/* SysTick Calibration Register Definitions */
<>	144:ef7eb2e8f9f7	679	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
<>	144:ef7eb2e8f9f7	680	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
<>	144:ef7eb2e8f9f7	683	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
<>	144:ef7eb2e8f9f7	684
<>	144:ef7eb2e8f9f7	685	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
<>	144:ef7eb2e8f9f7	686	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	/@} end of group CMSIS_SysTick /
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	692	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
<>	144:ef7eb2e8f9f7	693	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
<>	144:ef7eb2e8f9f7	694	@{
<>	144:ef7eb2e8f9f7	695	*/
<>	144:ef7eb2e8f9f7	696
<>	144:ef7eb2e8f9f7	697	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
<>	144:ef7eb2e8f9f7	698	*/
<>	144:ef7eb2e8f9f7	699	typedef struct
<>	144:ef7eb2e8f9f7	700	{
<>	144:ef7eb2e8f9f7	701	__O union
<>	144:ef7eb2e8f9f7	702	{
<>	144:ef7eb2e8f9f7	703	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
<>	144:ef7eb2e8f9f7	704	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
<>	144:ef7eb2e8f9f7	705	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
<>	144:ef7eb2e8f9f7	706	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
<>	144:ef7eb2e8f9f7	707	uint32_t RESERVED0[864];
<>	144:ef7eb2e8f9f7	708	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
<>	144:ef7eb2e8f9f7	709	uint32_t RESERVED1[15];
<>	144:ef7eb2e8f9f7	710	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
<>	144:ef7eb2e8f9f7	711	uint32_t RESERVED2[15];
<>	144:ef7eb2e8f9f7	712	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
<>	144:ef7eb2e8f9f7	713	uint32_t RESERVED3[29];
<>	144:ef7eb2e8f9f7	714	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
<>	144:ef7eb2e8f9f7	715	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
<>	144:ef7eb2e8f9f7	716	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
<>	144:ef7eb2e8f9f7	717	uint32_t RESERVED4[43];
<>	144:ef7eb2e8f9f7	718	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
<>	144:ef7eb2e8f9f7	719	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
<>	144:ef7eb2e8f9f7	720	uint32_t RESERVED5[6];
<>	144:ef7eb2e8f9f7	721	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
<>	144:ef7eb2e8f9f7	722	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
<>	144:ef7eb2e8f9f7	723	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
<>	144:ef7eb2e8f9f7	724	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
<>	144:ef7eb2e8f9f7	725	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
<>	144:ef7eb2e8f9f7	726	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
<>	144:ef7eb2e8f9f7	727	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
<>	144:ef7eb2e8f9f7	728	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
<>	144:ef7eb2e8f9f7	729	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
<>	144:ef7eb2e8f9f7	730	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
<>	144:ef7eb2e8f9f7	731	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
<>	144:ef7eb2e8f9f7	732	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
<>	144:ef7eb2e8f9f7	733	} ITM_Type;
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	/* ITM Trace Privilege Register Definitions */
<>	144:ef7eb2e8f9f7	736	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
<>	144:ef7eb2e8f9f7	737	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
<>	144:ef7eb2e8f9f7	738
<>	144:ef7eb2e8f9f7	739	/* ITM Trace Control Register Definitions */
<>	144:ef7eb2e8f9f7	740	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
<>	144:ef7eb2e8f9f7	741	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
<>	144:ef7eb2e8f9f7	744	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
<>	144:ef7eb2e8f9f7	745
<>	144:ef7eb2e8f9f7	746	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
<>	144:ef7eb2e8f9f7	747	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
<>	144:ef7eb2e8f9f7	748
<>	144:ef7eb2e8f9f7	749	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
<>	144:ef7eb2e8f9f7	750	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
<>	144:ef7eb2e8f9f7	751
<>	144:ef7eb2e8f9f7	752	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
<>	144:ef7eb2e8f9f7	753	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
<>	144:ef7eb2e8f9f7	754
<>	144:ef7eb2e8f9f7	755	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
<>	144:ef7eb2e8f9f7	756	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
<>	144:ef7eb2e8f9f7	757
<>	144:ef7eb2e8f9f7	758	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
<>	144:ef7eb2e8f9f7	759	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
<>	144:ef7eb2e8f9f7	760
<>	144:ef7eb2e8f9f7	761	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
<>	144:ef7eb2e8f9f7	762	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
<>	144:ef7eb2e8f9f7	763
<>	144:ef7eb2e8f9f7	764	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
<>	144:ef7eb2e8f9f7	765	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	/* ITM Integration Write Register Definitions */
<>	144:ef7eb2e8f9f7	768	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
<>	144:ef7eb2e8f9f7	769	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
<>	144:ef7eb2e8f9f7	770
<>	144:ef7eb2e8f9f7	771	/* ITM Integration Read Register Definitions */
<>	144:ef7eb2e8f9f7	772	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
<>	144:ef7eb2e8f9f7	773	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
<>	144:ef7eb2e8f9f7	774
<>	144:ef7eb2e8f9f7	775	/* ITM Integration Mode Control Register Definitions */
<>	144:ef7eb2e8f9f7	776	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
<>	144:ef7eb2e8f9f7	777	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
<>	144:ef7eb2e8f9f7	778
<>	144:ef7eb2e8f9f7	779	/* ITM Lock Status Register Definitions */
<>	144:ef7eb2e8f9f7	780	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
<>	144:ef7eb2e8f9f7	781	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
<>	144:ef7eb2e8f9f7	782
<>	144:ef7eb2e8f9f7	783	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
<>	144:ef7eb2e8f9f7	784	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
<>	144:ef7eb2e8f9f7	785
<>	144:ef7eb2e8f9f7	786	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
<>	144:ef7eb2e8f9f7	787	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
<>	144:ef7eb2e8f9f7	788
<>	144:ef7eb2e8f9f7	789	/@}/ /* end of group CMSIS_ITM */
<>	144:ef7eb2e8f9f7	790
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	793	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
<>	144:ef7eb2e8f9f7	794	\brief Type definitions for the Data Watchpoint and Trace (DWT)
<>	144:ef7eb2e8f9f7	795	@{
<>	144:ef7eb2e8f9f7	796	*/
<>	144:ef7eb2e8f9f7	797
<>	144:ef7eb2e8f9f7	798	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
<>	144:ef7eb2e8f9f7	799	*/
<>	144:ef7eb2e8f9f7	800	typedef struct
<>	144:ef7eb2e8f9f7	801	{
<>	144:ef7eb2e8f9f7	802	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
<>	144:ef7eb2e8f9f7	803	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
<>	144:ef7eb2e8f9f7	804	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
<>	144:ef7eb2e8f9f7	805	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
<>	144:ef7eb2e8f9f7	806	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
<>	144:ef7eb2e8f9f7	807	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
<>	144:ef7eb2e8f9f7	808	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
<>	144:ef7eb2e8f9f7	809	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
<>	144:ef7eb2e8f9f7	810	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
<>	144:ef7eb2e8f9f7	811	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
<>	144:ef7eb2e8f9f7	812	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
<>	144:ef7eb2e8f9f7	813	uint32_t RESERVED0[1];
<>	144:ef7eb2e8f9f7	814	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
<>	144:ef7eb2e8f9f7	815	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
<>	144:ef7eb2e8f9f7	816	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
<>	144:ef7eb2e8f9f7	817	uint32_t RESERVED1[1];
<>	144:ef7eb2e8f9f7	818	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
<>	144:ef7eb2e8f9f7	819	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
<>	144:ef7eb2e8f9f7	820	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
<>	144:ef7eb2e8f9f7	821	uint32_t RESERVED2[1];
<>	144:ef7eb2e8f9f7	822	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
<>	144:ef7eb2e8f9f7	823	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
<>	144:ef7eb2e8f9f7	824	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
<>	144:ef7eb2e8f9f7	825	} DWT_Type;
<>	144:ef7eb2e8f9f7	826
<>	144:ef7eb2e8f9f7	827	/* DWT Control Register Definitions */
<>	144:ef7eb2e8f9f7	828	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
<>	144:ef7eb2e8f9f7	829	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
<>	144:ef7eb2e8f9f7	830
<>	144:ef7eb2e8f9f7	831	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
<>	144:ef7eb2e8f9f7	832	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
<>	144:ef7eb2e8f9f7	833
<>	144:ef7eb2e8f9f7	834	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
<>	144:ef7eb2e8f9f7	835	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
<>	144:ef7eb2e8f9f7	838	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
<>	144:ef7eb2e8f9f7	841	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
<>	144:ef7eb2e8f9f7	842
<>	144:ef7eb2e8f9f7	843	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
<>	144:ef7eb2e8f9f7	844	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
<>	144:ef7eb2e8f9f7	845
<>	144:ef7eb2e8f9f7	846	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
<>	144:ef7eb2e8f9f7	847	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
<>	144:ef7eb2e8f9f7	848
<>	144:ef7eb2e8f9f7	849	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
<>	144:ef7eb2e8f9f7	850	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
<>	144:ef7eb2e8f9f7	851
<>	144:ef7eb2e8f9f7	852	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
<>	144:ef7eb2e8f9f7	853	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
<>	144:ef7eb2e8f9f7	856	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
<>	144:ef7eb2e8f9f7	859	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
<>	144:ef7eb2e8f9f7	862	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
<>	144:ef7eb2e8f9f7	863
<>	144:ef7eb2e8f9f7	864	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
<>	144:ef7eb2e8f9f7	865	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
<>	144:ef7eb2e8f9f7	866
<>	144:ef7eb2e8f9f7	867	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
<>	144:ef7eb2e8f9f7	868	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
<>	144:ef7eb2e8f9f7	869
<>	144:ef7eb2e8f9f7	870	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
<>	144:ef7eb2e8f9f7	871	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
<>	144:ef7eb2e8f9f7	872
<>	144:ef7eb2e8f9f7	873	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
<>	144:ef7eb2e8f9f7	874	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
<>	144:ef7eb2e8f9f7	877	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
<>	144:ef7eb2e8f9f7	878
<>	144:ef7eb2e8f9f7	879	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
<>	144:ef7eb2e8f9f7	880	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	/* DWT CPI Count Register Definitions */
<>	144:ef7eb2e8f9f7	883	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
<>	144:ef7eb2e8f9f7	884	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	/* DWT Exception Overhead Count Register Definitions */
<>	144:ef7eb2e8f9f7	887	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
<>	144:ef7eb2e8f9f7	888	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
<>	144:ef7eb2e8f9f7	889
<>	144:ef7eb2e8f9f7	890	/* DWT Sleep Count Register Definitions */
<>	144:ef7eb2e8f9f7	891	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
<>	144:ef7eb2e8f9f7	892	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
<>	144:ef7eb2e8f9f7	893
<>	144:ef7eb2e8f9f7	894	/* DWT LSU Count Register Definitions */
<>	144:ef7eb2e8f9f7	895	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
<>	144:ef7eb2e8f9f7	896	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
<>	144:ef7eb2e8f9f7	897
<>	144:ef7eb2e8f9f7	898	/* DWT Folded-instruction Count Register Definitions */
<>	144:ef7eb2e8f9f7	899	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
<>	144:ef7eb2e8f9f7	900	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	/* DWT Comparator Mask Register Definitions */
<>	144:ef7eb2e8f9f7	903	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
<>	144:ef7eb2e8f9f7	904	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
<>	144:ef7eb2e8f9f7	905
<>	144:ef7eb2e8f9f7	906	/* DWT Comparator Function Register Definitions */
<>	144:ef7eb2e8f9f7	907	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
<>	144:ef7eb2e8f9f7	908	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
<>	144:ef7eb2e8f9f7	909
<>	144:ef7eb2e8f9f7	910	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
<>	144:ef7eb2e8f9f7	911	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
<>	144:ef7eb2e8f9f7	914	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
<>	144:ef7eb2e8f9f7	917	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
<>	144:ef7eb2e8f9f7	918
<>	144:ef7eb2e8f9f7	919	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
<>	144:ef7eb2e8f9f7	920	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
<>	144:ef7eb2e8f9f7	923	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
<>	144:ef7eb2e8f9f7	926	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
<>	144:ef7eb2e8f9f7	929	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
<>	144:ef7eb2e8f9f7	932	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
<>	144:ef7eb2e8f9f7	933
<>	144:ef7eb2e8f9f7	934	/@}/ /* end of group CMSIS_DWT */
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936
<>	144:ef7eb2e8f9f7	937	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	938	\defgroup CMSIS_TPI Trace Port Interface (TPI)
<>	144:ef7eb2e8f9f7	939	\brief Type definitions for the Trace Port Interface (TPI)
<>	144:ef7eb2e8f9f7	940	@{
<>	144:ef7eb2e8f9f7	941	*/
<>	144:ef7eb2e8f9f7	942
<>	144:ef7eb2e8f9f7	943	/** \brief Structure type to access the Trace Port Interface Register (TPI).
<>	144:ef7eb2e8f9f7	944	*/
<>	144:ef7eb2e8f9f7	945	typedef struct
<>	144:ef7eb2e8f9f7	946	{
<>	144:ef7eb2e8f9f7	947	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
<>	144:ef7eb2e8f9f7	948	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
<>	144:ef7eb2e8f9f7	949	uint32_t RESERVED0[2];
<>	144:ef7eb2e8f9f7	950	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
<>	144:ef7eb2e8f9f7	951	uint32_t RESERVED1[55];
<>	144:ef7eb2e8f9f7	952	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
<>	144:ef7eb2e8f9f7	953	uint32_t RESERVED2[131];
<>	144:ef7eb2e8f9f7	954	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
<>	144:ef7eb2e8f9f7	955	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
<>	144:ef7eb2e8f9f7	956	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
<>	144:ef7eb2e8f9f7	957	uint32_t RESERVED3[759];
<>	144:ef7eb2e8f9f7	958	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
<>	144:ef7eb2e8f9f7	959	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
<>	144:ef7eb2e8f9f7	960	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
<>	144:ef7eb2e8f9f7	961	uint32_t RESERVED4[1];
<>	144:ef7eb2e8f9f7	962	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
<>	144:ef7eb2e8f9f7	963	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
<>	144:ef7eb2e8f9f7	964	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
<>	144:ef7eb2e8f9f7	965	uint32_t RESERVED5[39];
<>	144:ef7eb2e8f9f7	966	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
<>	144:ef7eb2e8f9f7	967	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
<>	144:ef7eb2e8f9f7	968	uint32_t RESERVED7[8];
<>	144:ef7eb2e8f9f7	969	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
<>	144:ef7eb2e8f9f7	970	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
<>	144:ef7eb2e8f9f7	971	} TPI_Type;
<>	144:ef7eb2e8f9f7	972
<>	144:ef7eb2e8f9f7	973	/* TPI Asynchronous Clock Prescaler Register Definitions */
<>	144:ef7eb2e8f9f7	974	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
<>	144:ef7eb2e8f9f7	975	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
<>	144:ef7eb2e8f9f7	976
<>	144:ef7eb2e8f9f7	977	/* TPI Selected Pin Protocol Register Definitions */
<>	144:ef7eb2e8f9f7	978	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
<>	144:ef7eb2e8f9f7	979	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
<>	144:ef7eb2e8f9f7	980
<>	144:ef7eb2e8f9f7	981	/* TPI Formatter and Flush Status Register Definitions */
<>	144:ef7eb2e8f9f7	982	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
<>	144:ef7eb2e8f9f7	983	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
<>	144:ef7eb2e8f9f7	984
<>	144:ef7eb2e8f9f7	985	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
<>	144:ef7eb2e8f9f7	986	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
<>	144:ef7eb2e8f9f7	987
<>	144:ef7eb2e8f9f7	988	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
<>	144:ef7eb2e8f9f7	989	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
<>	144:ef7eb2e8f9f7	990
<>	144:ef7eb2e8f9f7	991	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
<>	144:ef7eb2e8f9f7	992	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
<>	144:ef7eb2e8f9f7	993
<>	144:ef7eb2e8f9f7	994	/* TPI Formatter and Flush Control Register Definitions */
<>	144:ef7eb2e8f9f7	995	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
<>	144:ef7eb2e8f9f7	996	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
<>	144:ef7eb2e8f9f7	997
<>	144:ef7eb2e8f9f7	998	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
<>	144:ef7eb2e8f9f7	999	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
<>	144:ef7eb2e8f9f7	1000
<>	144:ef7eb2e8f9f7	1001	/* TPI TRIGGER Register Definitions */
<>	144:ef7eb2e8f9f7	1002	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
<>	144:ef7eb2e8f9f7	1003	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
<>	144:ef7eb2e8f9f7	1004
<>	144:ef7eb2e8f9f7	1005	/* TPI Integration ETM Data Register Definitions (FIFO0) */
<>	144:ef7eb2e8f9f7	1006	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
<>	144:ef7eb2e8f9f7	1007	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
<>	144:ef7eb2e8f9f7	1008
<>	144:ef7eb2e8f9f7	1009	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
<>	144:ef7eb2e8f9f7	1010	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
<>	144:ef7eb2e8f9f7	1011
<>	144:ef7eb2e8f9f7	1012	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
<>	144:ef7eb2e8f9f7	1013	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
<>	144:ef7eb2e8f9f7	1014
<>	144:ef7eb2e8f9f7	1015	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
<>	144:ef7eb2e8f9f7	1016	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
<>	144:ef7eb2e8f9f7	1017
<>	144:ef7eb2e8f9f7	1018	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
<>	144:ef7eb2e8f9f7	1019	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
<>	144:ef7eb2e8f9f7	1020
<>	144:ef7eb2e8f9f7	1021	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
<>	144:ef7eb2e8f9f7	1022	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
<>	144:ef7eb2e8f9f7	1025	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
<>	144:ef7eb2e8f9f7	1026
<>	144:ef7eb2e8f9f7	1027	/* TPI ITATBCTR2 Register Definitions */
<>	144:ef7eb2e8f9f7	1028	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
<>	144:ef7eb2e8f9f7	1029	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
<>	144:ef7eb2e8f9f7	1030
<>	144:ef7eb2e8f9f7	1031	/* TPI Integration ITM Data Register Definitions (FIFO1) */
<>	144:ef7eb2e8f9f7	1032	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
<>	144:ef7eb2e8f9f7	1033	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
<>	144:ef7eb2e8f9f7	1036	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
<>	144:ef7eb2e8f9f7	1039	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
<>	144:ef7eb2e8f9f7	1042	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
<>	144:ef7eb2e8f9f7	1045	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
<>	144:ef7eb2e8f9f7	1048	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
<>	144:ef7eb2e8f9f7	1049
<>	144:ef7eb2e8f9f7	1050	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
<>	144:ef7eb2e8f9f7	1051	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	/* TPI ITATBCTR0 Register Definitions */
<>	144:ef7eb2e8f9f7	1054	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
<>	144:ef7eb2e8f9f7	1055	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
<>	144:ef7eb2e8f9f7	1056
<>	144:ef7eb2e8f9f7	1057	/* TPI Integration Mode Control Register Definitions */
<>	144:ef7eb2e8f9f7	1058	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
<>	144:ef7eb2e8f9f7	1059	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	/* TPI DEVID Register Definitions */
<>	144:ef7eb2e8f9f7	1062	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
<>	144:ef7eb2e8f9f7	1063	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
<>	144:ef7eb2e8f9f7	1064
<>	144:ef7eb2e8f9f7	1065	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
<>	144:ef7eb2e8f9f7	1066	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
<>	144:ef7eb2e8f9f7	1067
<>	144:ef7eb2e8f9f7	1068	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
<>	144:ef7eb2e8f9f7	1069	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
<>	144:ef7eb2e8f9f7	1070
<>	144:ef7eb2e8f9f7	1071	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
<>	144:ef7eb2e8f9f7	1072	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
<>	144:ef7eb2e8f9f7	1073
<>	144:ef7eb2e8f9f7	1074	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
<>	144:ef7eb2e8f9f7	1075	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
<>	144:ef7eb2e8f9f7	1076
<>	144:ef7eb2e8f9f7	1077	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
<>	144:ef7eb2e8f9f7	1078	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
<>	144:ef7eb2e8f9f7	1079
<>	144:ef7eb2e8f9f7	1080	/* TPI DEVTYPE Register Definitions */
<>	144:ef7eb2e8f9f7	1081	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
<>	144:ef7eb2e8f9f7	1082	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
<>	144:ef7eb2e8f9f7	1083
<>	144:ef7eb2e8f9f7	1084	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
<>	144:ef7eb2e8f9f7	1085	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
<>	144:ef7eb2e8f9f7	1086
<>	144:ef7eb2e8f9f7	1087	/@}/ /* end of group CMSIS_TPI */
<>	144:ef7eb2e8f9f7	1088
<>	144:ef7eb2e8f9f7	1089
<>	144:ef7eb2e8f9f7	1090	#if (__MPU_PRESENT == 1)
<>	144:ef7eb2e8f9f7	1091	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	1092	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
<>	144:ef7eb2e8f9f7	1093	\brief Type definitions for the Memory Protection Unit (MPU)
<>	144:ef7eb2e8f9f7	1094	@{
<>	144:ef7eb2e8f9f7	1095	*/
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	/** \brief Structure type to access the Memory Protection Unit (MPU).
<>	144:ef7eb2e8f9f7	1098	*/
<>	144:ef7eb2e8f9f7	1099	typedef struct
<>	144:ef7eb2e8f9f7	1100	{
<>	144:ef7eb2e8f9f7	1101	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
<>	144:ef7eb2e8f9f7	1102	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
<>	144:ef7eb2e8f9f7	1103	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
<>	144:ef7eb2e8f9f7	1104	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
<>	144:ef7eb2e8f9f7	1105	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
<>	144:ef7eb2e8f9f7	1106	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
<>	144:ef7eb2e8f9f7	1107	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
<>	144:ef7eb2e8f9f7	1108	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
<>	144:ef7eb2e8f9f7	1109	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
<>	144:ef7eb2e8f9f7	1110	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
<>	144:ef7eb2e8f9f7	1111	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
<>	144:ef7eb2e8f9f7	1112	} MPU_Type;
<>	144:ef7eb2e8f9f7	1113
<>	144:ef7eb2e8f9f7	1114	/* MPU Type Register */
<>	144:ef7eb2e8f9f7	1115	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
<>	144:ef7eb2e8f9f7	1116	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
<>	144:ef7eb2e8f9f7	1117
<>	144:ef7eb2e8f9f7	1118	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
<>	144:ef7eb2e8f9f7	1119	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
<>	144:ef7eb2e8f9f7	1120
<>	144:ef7eb2e8f9f7	1121	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
<>	144:ef7eb2e8f9f7	1122	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
<>	144:ef7eb2e8f9f7	1123
<>	144:ef7eb2e8f9f7	1124	/* MPU Control Register */
<>	144:ef7eb2e8f9f7	1125	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
<>	144:ef7eb2e8f9f7	1126	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
<>	144:ef7eb2e8f9f7	1127
<>	144:ef7eb2e8f9f7	1128	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
<>	144:ef7eb2e8f9f7	1129	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
<>	144:ef7eb2e8f9f7	1130
<>	144:ef7eb2e8f9f7	1131	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
<>	144:ef7eb2e8f9f7	1132	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
<>	144:ef7eb2e8f9f7	1133
<>	144:ef7eb2e8f9f7	1134	/* MPU Region Number Register */
<>	144:ef7eb2e8f9f7	1135	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
<>	144:ef7eb2e8f9f7	1136	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
<>	144:ef7eb2e8f9f7	1137
<>	144:ef7eb2e8f9f7	1138	/* MPU Region Base Address Register */
<>	144:ef7eb2e8f9f7	1139	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
<>	144:ef7eb2e8f9f7	1140	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
<>	144:ef7eb2e8f9f7	1143	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
<>	144:ef7eb2e8f9f7	1146	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	/* MPU Region Attribute and Size Register */
<>	144:ef7eb2e8f9f7	1149	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
<>	144:ef7eb2e8f9f7	1150	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
<>	144:ef7eb2e8f9f7	1151
<>	144:ef7eb2e8f9f7	1152	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
<>	144:ef7eb2e8f9f7	1153	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
<>	144:ef7eb2e8f9f7	1154
<>	144:ef7eb2e8f9f7	1155	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
<>	144:ef7eb2e8f9f7	1156	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
<>	144:ef7eb2e8f9f7	1159	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
<>	144:ef7eb2e8f9f7	1160
<>	144:ef7eb2e8f9f7	1161	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
<>	144:ef7eb2e8f9f7	1162	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
<>	144:ef7eb2e8f9f7	1163
<>	144:ef7eb2e8f9f7	1164	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
<>	144:ef7eb2e8f9f7	1165	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
<>	144:ef7eb2e8f9f7	1166
<>	144:ef7eb2e8f9f7	1167	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
<>	144:ef7eb2e8f9f7	1168	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
<>	144:ef7eb2e8f9f7	1171	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
<>	144:ef7eb2e8f9f7	1172
<>	144:ef7eb2e8f9f7	1173	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
<>	144:ef7eb2e8f9f7	1174	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
<>	144:ef7eb2e8f9f7	1175
<>	144:ef7eb2e8f9f7	1176	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
<>	144:ef7eb2e8f9f7	1177	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	/@} end of group CMSIS_MPU /
<>	144:ef7eb2e8f9f7	1180	#endif
<>	144:ef7eb2e8f9f7	1181
<>	144:ef7eb2e8f9f7	1182
<>	144:ef7eb2e8f9f7	1183	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	1184	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<>	144:ef7eb2e8f9f7	1185	\brief Type definitions for the Core Debug Registers
<>	144:ef7eb2e8f9f7	1186	@{
<>	144:ef7eb2e8f9f7	1187	*/
<>	144:ef7eb2e8f9f7	1188
<>	144:ef7eb2e8f9f7	1189	/** \brief Structure type to access the Core Debug Register (CoreDebug).
<>	144:ef7eb2e8f9f7	1190	*/
<>	144:ef7eb2e8f9f7	1191	typedef struct
<>	144:ef7eb2e8f9f7	1192	{
<>	144:ef7eb2e8f9f7	1193	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
<>	144:ef7eb2e8f9f7	1194	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
<>	144:ef7eb2e8f9f7	1195	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
<>	144:ef7eb2e8f9f7	1196	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
<>	144:ef7eb2e8f9f7	1197	} CoreDebug_Type;
<>	144:ef7eb2e8f9f7	1198
<>	144:ef7eb2e8f9f7	1199	/* Debug Halting Control and Status Register */
<>	144:ef7eb2e8f9f7	1200	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
<>	144:ef7eb2e8f9f7	1201	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
<>	144:ef7eb2e8f9f7	1202
<>	144:ef7eb2e8f9f7	1203	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
<>	144:ef7eb2e8f9f7	1204	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
<>	144:ef7eb2e8f9f7	1205
<>	144:ef7eb2e8f9f7	1206	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
<>	144:ef7eb2e8f9f7	1207	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
<>	144:ef7eb2e8f9f7	1208
<>	144:ef7eb2e8f9f7	1209	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
<>	144:ef7eb2e8f9f7	1210	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
<>	144:ef7eb2e8f9f7	1213	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
<>	144:ef7eb2e8f9f7	1214
<>	144:ef7eb2e8f9f7	1215	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
<>	144:ef7eb2e8f9f7	1216	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
<>	144:ef7eb2e8f9f7	1219	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
<>	144:ef7eb2e8f9f7	1220
<>	144:ef7eb2e8f9f7	1221	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
<>	144:ef7eb2e8f9f7	1222	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
<>	144:ef7eb2e8f9f7	1223
<>	144:ef7eb2e8f9f7	1224	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
<>	144:ef7eb2e8f9f7	1225	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
<>	144:ef7eb2e8f9f7	1226
<>	144:ef7eb2e8f9f7	1227	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
<>	144:ef7eb2e8f9f7	1228	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
<>	144:ef7eb2e8f9f7	1231	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
<>	144:ef7eb2e8f9f7	1232
<>	144:ef7eb2e8f9f7	1233	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
<>	144:ef7eb2e8f9f7	1234	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
<>	144:ef7eb2e8f9f7	1235
<>	144:ef7eb2e8f9f7	1236	/* Debug Core Register Selector Register */
<>	144:ef7eb2e8f9f7	1237	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
<>	144:ef7eb2e8f9f7	1238	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
<>	144:ef7eb2e8f9f7	1239
<>	144:ef7eb2e8f9f7	1240	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
<>	144:ef7eb2e8f9f7	1241	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
<>	144:ef7eb2e8f9f7	1242
<>	144:ef7eb2e8f9f7	1243	/* Debug Exception and Monitor Control Register */
<>	144:ef7eb2e8f9f7	1244	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
<>	144:ef7eb2e8f9f7	1245	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
<>	144:ef7eb2e8f9f7	1246
<>	144:ef7eb2e8f9f7	1247	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
<>	144:ef7eb2e8f9f7	1248	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
<>	144:ef7eb2e8f9f7	1249
<>	144:ef7eb2e8f9f7	1250	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
<>	144:ef7eb2e8f9f7	1251	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
<>	144:ef7eb2e8f9f7	1254	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
<>	144:ef7eb2e8f9f7	1255
<>	144:ef7eb2e8f9f7	1256	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
<>	144:ef7eb2e8f9f7	1257	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
<>	144:ef7eb2e8f9f7	1258
<>	144:ef7eb2e8f9f7	1259	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
<>	144:ef7eb2e8f9f7	1260	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
<>	144:ef7eb2e8f9f7	1261
<>	144:ef7eb2e8f9f7	1262	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
<>	144:ef7eb2e8f9f7	1263	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
<>	144:ef7eb2e8f9f7	1264
<>	144:ef7eb2e8f9f7	1265	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
<>	144:ef7eb2e8f9f7	1266	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
<>	144:ef7eb2e8f9f7	1267
<>	144:ef7eb2e8f9f7	1268	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
<>	144:ef7eb2e8f9f7	1269	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
<>	144:ef7eb2e8f9f7	1270
<>	144:ef7eb2e8f9f7	1271	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
<>	144:ef7eb2e8f9f7	1272	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
<>	144:ef7eb2e8f9f7	1273
<>	144:ef7eb2e8f9f7	1274	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
<>	144:ef7eb2e8f9f7	1275	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
<>	144:ef7eb2e8f9f7	1276
<>	144:ef7eb2e8f9f7	1277	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
<>	144:ef7eb2e8f9f7	1278	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
<>	144:ef7eb2e8f9f7	1279
<>	144:ef7eb2e8f9f7	1280	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
<>	144:ef7eb2e8f9f7	1281	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
<>	144:ef7eb2e8f9f7	1282
<>	144:ef7eb2e8f9f7	1283	/@} end of group CMSIS_CoreDebug /
<>	144:ef7eb2e8f9f7	1284
<>	144:ef7eb2e8f9f7	1285
<>	144:ef7eb2e8f9f7	1286	/** \ingroup CMSIS_core_register
<>	144:ef7eb2e8f9f7	1287	\defgroup CMSIS_core_base Core Definitions
<>	144:ef7eb2e8f9f7	1288	\brief Definitions for base addresses, unions, and structures.
<>	144:ef7eb2e8f9f7	1289	@{
<>	144:ef7eb2e8f9f7	1290	*/
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	/* Memory mapping of Cortex-M3 Hardware */
<>	144:ef7eb2e8f9f7	1293	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
<>	144:ef7eb2e8f9f7	1294	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
<>	144:ef7eb2e8f9f7	1295	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
<>	144:ef7eb2e8f9f7	1296	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
<>	144:ef7eb2e8f9f7	1297	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
<>	144:ef7eb2e8f9f7	1298	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
<>	144:ef7eb2e8f9f7	1299	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
<>	144:ef7eb2e8f9f7	1300	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
<>	144:ef7eb2e8f9f7	1301
<>	144:ef7eb2e8f9f7	1302	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
<>	144:ef7eb2e8f9f7	1303	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
<>	144:ef7eb2e8f9f7	1304	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
<>	144:ef7eb2e8f9f7	1305	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
<>	144:ef7eb2e8f9f7	1306	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
<>	144:ef7eb2e8f9f7	1307	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
<>	144:ef7eb2e8f9f7	1308	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
<>	144:ef7eb2e8f9f7	1309	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	#if (__MPU_PRESENT == 1)
<>	144:ef7eb2e8f9f7	1312	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
<>	144:ef7eb2e8f9f7	1313	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
<>	144:ef7eb2e8f9f7	1314	#endif
<>	144:ef7eb2e8f9f7	1315
<>	144:ef7eb2e8f9f7	1316	/@} /
<>	144:ef7eb2e8f9f7	1317
<>	144:ef7eb2e8f9f7	1318
<>	144:ef7eb2e8f9f7	1319
<>	144:ef7eb2e8f9f7	1320	/*******************************************************************************
<>	144:ef7eb2e8f9f7	1321	* Hardware Abstraction Layer
<>	144:ef7eb2e8f9f7	1322	Core Function Interface contains:
<>	144:ef7eb2e8f9f7	1323	- Core NVIC Functions
<>	144:ef7eb2e8f9f7	1324	- Core SysTick Functions
<>	144:ef7eb2e8f9f7	1325	- Core Debug Functions
<>	144:ef7eb2e8f9f7	1326	- Core Register Access Functions
<>	144:ef7eb2e8f9f7	1327	******************************************************************************/
<>	144:ef7eb2e8f9f7	1328	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<>	144:ef7eb2e8f9f7	1329	*/
<>	144:ef7eb2e8f9f7	1330
<>	144:ef7eb2e8f9f7	1331
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333	/* ########################## NVIC functions #################################### */
<>	144:ef7eb2e8f9f7	1334	/** \ingroup CMSIS_Core_FunctionInterface
<>	144:ef7eb2e8f9f7	1335	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
<>	144:ef7eb2e8f9f7	1336	\brief Functions that manage interrupts and exceptions via the NVIC.
<>	144:ef7eb2e8f9f7	1337	@{
<>	144:ef7eb2e8f9f7	1338	*/
<>	144:ef7eb2e8f9f7	1339
<>	144:ef7eb2e8f9f7	1340	/** \brief Set Priority Grouping
<>	144:ef7eb2e8f9f7	1341
<>	144:ef7eb2e8f9f7	1342	The function sets the priority grouping field using the required unlock sequence.
<>	144:ef7eb2e8f9f7	1343	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
<>	144:ef7eb2e8f9f7	1344	Only values from 0..7 are used.
<>	144:ef7eb2e8f9f7	1345	In case of a conflict between priority grouping and available
<>	144:ef7eb2e8f9f7	1346	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	\param [in] PriorityGroup Priority grouping field.
<>	144:ef7eb2e8f9f7	1349	*/
<>	144:ef7eb2e8f9f7	1350	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<>	144:ef7eb2e8f9f7	1351	{
<>	144:ef7eb2e8f9f7	1352	uint32_t reg_value;
<>	144:ef7eb2e8f9f7	1353	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	144:ef7eb2e8f9f7	1354
<>	144:ef7eb2e8f9f7	1355	reg_value = SCB->AIRCR; /* read old register configuration */
<>	144:ef7eb2e8f9f7	1356	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
<>	144:ef7eb2e8f9f7	1357	reg_value = (reg_value \|
<>	144:ef7eb2e8f9f7	1358	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
<>	144:ef7eb2e8f9f7	1359	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
<>	144:ef7eb2e8f9f7	1360	SCB->AIRCR = reg_value;
<>	144:ef7eb2e8f9f7	1361	}
<>	144:ef7eb2e8f9f7	1362
<>	144:ef7eb2e8f9f7	1363
<>	144:ef7eb2e8f9f7	1364	/** \brief Get Priority Grouping
<>	144:ef7eb2e8f9f7	1365
<>	144:ef7eb2e8f9f7	1366	The function reads the priority grouping field from the NVIC Interrupt Controller.
<>	144:ef7eb2e8f9f7	1367
<>	144:ef7eb2e8f9f7	1368	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
<>	144:ef7eb2e8f9f7	1369	*/
<>	144:ef7eb2e8f9f7	1370	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
<>	144:ef7eb2e8f9f7	1371	{
<>	144:ef7eb2e8f9f7	1372	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
<>	144:ef7eb2e8f9f7	1373	}
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375
<>	144:ef7eb2e8f9f7	1376	/** \brief Enable External Interrupt
<>	144:ef7eb2e8f9f7	1377
<>	144:ef7eb2e8f9f7	1378	The function enables a device-specific interrupt in the NVIC interrupt controller.
<>	144:ef7eb2e8f9f7	1379
<>	144:ef7eb2e8f9f7	1380	\param [in] IRQn External interrupt number. Value cannot be negative.
<>	144:ef7eb2e8f9f7	1381	*/
<>	144:ef7eb2e8f9f7	1382	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1383	{
<>	144:ef7eb2e8f9f7	1384	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	144:ef7eb2e8f9f7	1385	}
<>	144:ef7eb2e8f9f7	1386
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/** \brief Disable External Interrupt
<>	144:ef7eb2e8f9f7	1389
<>	144:ef7eb2e8f9f7	1390	The function disables a device-specific interrupt in the NVIC interrupt controller.
<>	144:ef7eb2e8f9f7	1391
<>	144:ef7eb2e8f9f7	1392	\param [in] IRQn External interrupt number. Value cannot be negative.
<>	144:ef7eb2e8f9f7	1393	*/
<>	144:ef7eb2e8f9f7	1394	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1395	{
<>	144:ef7eb2e8f9f7	1396	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	144:ef7eb2e8f9f7	1397	}
<>	144:ef7eb2e8f9f7	1398
<>	144:ef7eb2e8f9f7	1399
<>	144:ef7eb2e8f9f7	1400	/** \brief Get Pending Interrupt
<>	144:ef7eb2e8f9f7	1401
<>	144:ef7eb2e8f9f7	1402	The function reads the pending register in the NVIC and returns the pending bit
<>	144:ef7eb2e8f9f7	1403	for the specified interrupt.
<>	144:ef7eb2e8f9f7	1404
<>	144:ef7eb2e8f9f7	1405	\param [in] IRQn Interrupt number.
<>	144:ef7eb2e8f9f7	1406
<>	144:ef7eb2e8f9f7	1407	\return 0 Interrupt status is not pending.
<>	144:ef7eb2e8f9f7	1408	\return 1 Interrupt status is pending.
<>	144:ef7eb2e8f9f7	1409	*/
<>	144:ef7eb2e8f9f7	1410	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1411	{
<>	144:ef7eb2e8f9f7	1412	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<>	144:ef7eb2e8f9f7	1413	}
<>	144:ef7eb2e8f9f7	1414
<>	144:ef7eb2e8f9f7	1415
<>	144:ef7eb2e8f9f7	1416	/** \brief Set Pending Interrupt
<>	144:ef7eb2e8f9f7	1417
<>	144:ef7eb2e8f9f7	1418	The function sets the pending bit of an external interrupt.
<>	144:ef7eb2e8f9f7	1419
<>	144:ef7eb2e8f9f7	1420	\param [in] IRQn Interrupt number. Value cannot be negative.
<>	144:ef7eb2e8f9f7	1421	*/
<>	144:ef7eb2e8f9f7	1422	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1423	{
<>	144:ef7eb2e8f9f7	1424	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	144:ef7eb2e8f9f7	1425	}
<>	144:ef7eb2e8f9f7	1426
<>	144:ef7eb2e8f9f7	1427
<>	144:ef7eb2e8f9f7	1428	/** \brief Clear Pending Interrupt
<>	144:ef7eb2e8f9f7	1429
<>	144:ef7eb2e8f9f7	1430	The function clears the pending bit of an external interrupt.
<>	144:ef7eb2e8f9f7	1431
<>	144:ef7eb2e8f9f7	1432	\param [in] IRQn External interrupt number. Value cannot be negative.
<>	144:ef7eb2e8f9f7	1433	*/
<>	144:ef7eb2e8f9f7	1434	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1435	{
<>	144:ef7eb2e8f9f7	1436	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<>	144:ef7eb2e8f9f7	1437	}
<>	144:ef7eb2e8f9f7	1438
<>	144:ef7eb2e8f9f7	1439
<>	144:ef7eb2e8f9f7	1440	/** \brief Get Active Interrupt
<>	144:ef7eb2e8f9f7	1441
<>	144:ef7eb2e8f9f7	1442	The function reads the active register in NVIC and returns the active bit.
<>	144:ef7eb2e8f9f7	1443
<>	144:ef7eb2e8f9f7	1444	\param [in] IRQn Interrupt number.
<>	144:ef7eb2e8f9f7	1445
<>	144:ef7eb2e8f9f7	1446	\return 0 Interrupt status is not active.
<>	144:ef7eb2e8f9f7	1447	\return 1 Interrupt status is active.
<>	144:ef7eb2e8f9f7	1448	*/
<>	144:ef7eb2e8f9f7	1449	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1450	{
<>	144:ef7eb2e8f9f7	1451	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<>	144:ef7eb2e8f9f7	1452	}
<>	144:ef7eb2e8f9f7	1453
<>	144:ef7eb2e8f9f7	1454
<>	144:ef7eb2e8f9f7	1455	/** \brief Set Interrupt Priority
<>	144:ef7eb2e8f9f7	1456
<>	144:ef7eb2e8f9f7	1457	The function sets the priority of an interrupt.
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	\note The priority cannot be set for every core interrupt.
<>	144:ef7eb2e8f9f7	1460
<>	144:ef7eb2e8f9f7	1461	\param [in] IRQn Interrupt number.
<>	144:ef7eb2e8f9f7	1462	\param [in] priority Priority to set.
<>	144:ef7eb2e8f9f7	1463	*/
<>	144:ef7eb2e8f9f7	1464	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<>	144:ef7eb2e8f9f7	1465	{
<>	144:ef7eb2e8f9f7	1466	if((int32_t)IRQn < 0) {
<>	144:ef7eb2e8f9f7	1467	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<>	144:ef7eb2e8f9f7	1468	}
<>	144:ef7eb2e8f9f7	1469	else {
<>	144:ef7eb2e8f9f7	1470	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
<>	144:ef7eb2e8f9f7	1471	}
<>	144:ef7eb2e8f9f7	1472	}
<>	144:ef7eb2e8f9f7	1473
<>	144:ef7eb2e8f9f7	1474
<>	144:ef7eb2e8f9f7	1475	/** \brief Get Interrupt Priority
<>	144:ef7eb2e8f9f7	1476
<>	144:ef7eb2e8f9f7	1477	The function reads the priority of an interrupt. The interrupt
<>	144:ef7eb2e8f9f7	1478	number can be positive to specify an external (device specific)
<>	144:ef7eb2e8f9f7	1479	interrupt, or negative to specify an internal (core) interrupt.
<>	144:ef7eb2e8f9f7	1480
<>	144:ef7eb2e8f9f7	1481
<>	144:ef7eb2e8f9f7	1482	\param [in] IRQn Interrupt number.
<>	144:ef7eb2e8f9f7	1483	\return Interrupt Priority. Value is aligned automatically to the implemented
<>	144:ef7eb2e8f9f7	1484	priority bits of the microcontroller.
<>	144:ef7eb2e8f9f7	1485	*/
<>	144:ef7eb2e8f9f7	1486	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<>	144:ef7eb2e8f9f7	1487	{
<>	144:ef7eb2e8f9f7	1488
<>	144:ef7eb2e8f9f7	1489	if((int32_t)IRQn < 0) {
<>	144:ef7eb2e8f9f7	1490	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
<>	144:ef7eb2e8f9f7	1491	}
<>	144:ef7eb2e8f9f7	1492	else {
<>	144:ef7eb2e8f9f7	1493	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
<>	144:ef7eb2e8f9f7	1494	}
<>	144:ef7eb2e8f9f7	1495	}
<>	144:ef7eb2e8f9f7	1496
<>	144:ef7eb2e8f9f7	1497
<>	144:ef7eb2e8f9f7	1498	/** \brief Encode Priority
<>	144:ef7eb2e8f9f7	1499
<>	144:ef7eb2e8f9f7	1500	The function encodes the priority for an interrupt with the given priority group,
<>	144:ef7eb2e8f9f7	1501	preemptive priority value, and subpriority value.
<>	144:ef7eb2e8f9f7	1502	In case of a conflict between priority grouping and available
<>	144:ef7eb2e8f9f7	1503	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
<>	144:ef7eb2e8f9f7	1504
<>	144:ef7eb2e8f9f7	1505	\param [in] PriorityGroup Used priority group.
<>	144:ef7eb2e8f9f7	1506	\param [in] PreemptPriority Preemptive priority value (starting from 0).
<>	144:ef7eb2e8f9f7	1507	\param [in] SubPriority Subpriority value (starting from 0).
<>	144:ef7eb2e8f9f7	1508	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
<>	144:ef7eb2e8f9f7	1509	*/
<>	144:ef7eb2e8f9f7	1510	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
<>	144:ef7eb2e8f9f7	1511	{
<>	144:ef7eb2e8f9f7	1512	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	144:ef7eb2e8f9f7	1513	uint32_t PreemptPriorityBits;
<>	144:ef7eb2e8f9f7	1514	uint32_t SubPriorityBits;
<>	144:ef7eb2e8f9f7	1515
<>	144:ef7eb2e8f9f7	1516	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	144:ef7eb2e8f9f7	1517	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	144:ef7eb2e8f9f7	1518
<>	144:ef7eb2e8f9f7	1519	return (
<>	144:ef7eb2e8f9f7	1520	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
<>	144:ef7eb2e8f9f7	1521	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
<>	144:ef7eb2e8f9f7	1522	);
<>	144:ef7eb2e8f9f7	1523	}
<>	144:ef7eb2e8f9f7	1524
<>	144:ef7eb2e8f9f7	1525
<>	144:ef7eb2e8f9f7	1526	/** \brief Decode Priority
<>	144:ef7eb2e8f9f7	1527
<>	144:ef7eb2e8f9f7	1528	The function decodes an interrupt priority value with a given priority group to
<>	144:ef7eb2e8f9f7	1529	preemptive priority value and subpriority value.
<>	144:ef7eb2e8f9f7	1530	In case of a conflict between priority grouping and available
<>	144:ef7eb2e8f9f7	1531	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
<>	144:ef7eb2e8f9f7	1532
<>	144:ef7eb2e8f9f7	1533	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
<>	144:ef7eb2e8f9f7	1534	\param [in] PriorityGroup Used priority group.
<>	144:ef7eb2e8f9f7	1535	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
<>	144:ef7eb2e8f9f7	1536	\param [out] pSubPriority Subpriority value (starting from 0).
<>	144:ef7eb2e8f9f7	1537	*/
<>	144:ef7eb2e8f9f7	1538	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<>	144:ef7eb2e8f9f7	1539	{
<>	144:ef7eb2e8f9f7	1540	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
<>	144:ef7eb2e8f9f7	1541	uint32_t PreemptPriorityBits;
<>	144:ef7eb2e8f9f7	1542	uint32_t SubPriorityBits;
<>	144:ef7eb2e8f9f7	1543
<>	144:ef7eb2e8f9f7	1544	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
<>	144:ef7eb2e8f9f7	1545	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
<>	144:ef7eb2e8f9f7	1546
<>	144:ef7eb2e8f9f7	1547	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
<>	144:ef7eb2e8f9f7	1548	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
<>	144:ef7eb2e8f9f7	1549	}
<>	144:ef7eb2e8f9f7	1550
<>	144:ef7eb2e8f9f7	1551
<>	144:ef7eb2e8f9f7	1552	/** \brief System Reset
<>	144:ef7eb2e8f9f7	1553
<>	144:ef7eb2e8f9f7	1554	The function initiates a system reset request to reset the MCU.
<>	144:ef7eb2e8f9f7	1555	*/
<>	144:ef7eb2e8f9f7	1556	__STATIC_INLINE void NVIC_SystemReset(void)
<>	144:ef7eb2e8f9f7	1557	{
<>	144:ef7eb2e8f9f7	1558	__DSB(); /* Ensure all outstanding memory accesses included
<>	144:ef7eb2e8f9f7	1559	buffered write are completed before reset */
<>	144:ef7eb2e8f9f7	1560	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
<>	144:ef7eb2e8f9f7	1561	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
<>	144:ef7eb2e8f9f7	1562	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
<>	144:ef7eb2e8f9f7	1563	__DSB(); /* Ensure completion of memory access */
<>	144:ef7eb2e8f9f7	1564	while(1) { __NOP(); } /* wait until reset */
<>	144:ef7eb2e8f9f7	1565	}
<>	144:ef7eb2e8f9f7	1566
<>	144:ef7eb2e8f9f7	1567	/@} end of CMSIS_Core_NVICFunctions /
<>	144:ef7eb2e8f9f7	1568
<>	144:ef7eb2e8f9f7	1569
<>	144:ef7eb2e8f9f7	1570
<>	144:ef7eb2e8f9f7	1571	/* ################################## SysTick function ############################################ */
<>	144:ef7eb2e8f9f7	1572	/** \ingroup CMSIS_Core_FunctionInterface
<>	144:ef7eb2e8f9f7	1573	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<>	144:ef7eb2e8f9f7	1574	\brief Functions that configure the System.
<>	144:ef7eb2e8f9f7	1575	@{
<>	144:ef7eb2e8f9f7	1576	*/
<>	144:ef7eb2e8f9f7	1577
<>	144:ef7eb2e8f9f7	1578	#if (__Vendor_SysTickConfig == 0)
<>	144:ef7eb2e8f9f7	1579
<>	144:ef7eb2e8f9f7	1580	/** \brief System Tick Configuration
<>	144:ef7eb2e8f9f7	1581
<>	144:ef7eb2e8f9f7	1582	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<>	144:ef7eb2e8f9f7	1583	Counter is in free running mode to generate periodic interrupts.
<>	144:ef7eb2e8f9f7	1584
<>	144:ef7eb2e8f9f7	1585	\param [in] ticks Number of ticks between two interrupts.
<>	144:ef7eb2e8f9f7	1586
<>	144:ef7eb2e8f9f7	1587	\return 0 Function succeeded.
<>	144:ef7eb2e8f9f7	1588	\return 1 Function failed.
<>	144:ef7eb2e8f9f7	1589
<>	144:ef7eb2e8f9f7	1590	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<>	144:ef7eb2e8f9f7	1591	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<>	144:ef7eb2e8f9f7	1592	must contain a vendor-specific implementation of this function.
<>	144:ef7eb2e8f9f7	1593
<>	144:ef7eb2e8f9f7	1594	*/
<>	144:ef7eb2e8f9f7	1595	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<>	144:ef7eb2e8f9f7	1596	{
<>	144:ef7eb2e8f9f7	1597	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
<>	144:ef7eb2e8f9f7	1598
<>	144:ef7eb2e8f9f7	1599	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<>	144:ef7eb2e8f9f7	1600	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<>	144:ef7eb2e8f9f7	1601	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<>	144:ef7eb2e8f9f7	1602	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
<>	144:ef7eb2e8f9f7	1603	SysTick_CTRL_TICKINT_Msk \|
<>	144:ef7eb2e8f9f7	1604	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<>	144:ef7eb2e8f9f7	1605	return (0UL); /* Function successful */
<>	144:ef7eb2e8f9f7	1606	}
<>	144:ef7eb2e8f9f7	1607
<>	144:ef7eb2e8f9f7	1608	#endif
<>	144:ef7eb2e8f9f7	1609
<>	144:ef7eb2e8f9f7	1610	/@} end of CMSIS_Core_SysTickFunctions /
<>	144:ef7eb2e8f9f7	1611
<>	144:ef7eb2e8f9f7	1612
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/* ##################################### Debug In/Output function ########################################### */
<>	144:ef7eb2e8f9f7	1615	/** \ingroup CMSIS_Core_FunctionInterface
<>	144:ef7eb2e8f9f7	1616	\defgroup CMSIS_core_DebugFunctions ITM Functions
<>	144:ef7eb2e8f9f7	1617	\brief Functions that access the ITM debug interface.
<>	144:ef7eb2e8f9f7	1618	@{
<>	144:ef7eb2e8f9f7	1619	*/
<>	144:ef7eb2e8f9f7	1620
<>	144:ef7eb2e8f9f7	1621	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
<>	144:ef7eb2e8f9f7	1622	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
<>	144:ef7eb2e8f9f7	1623
<>	144:ef7eb2e8f9f7	1624
<>	144:ef7eb2e8f9f7	1625	/** \brief ITM Send Character
<>	144:ef7eb2e8f9f7	1626
<>	144:ef7eb2e8f9f7	1627	The function transmits a character via the ITM channel 0, and
<>	144:ef7eb2e8f9f7	1628	\li Just returns when no debugger is connected that has booked the output.
<>	144:ef7eb2e8f9f7	1629	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
<>	144:ef7eb2e8f9f7	1630
<>	144:ef7eb2e8f9f7	1631	\param [in] ch Character to transmit.
<>	144:ef7eb2e8f9f7	1632
<>	144:ef7eb2e8f9f7	1633	\returns Character to transmit.
<>	144:ef7eb2e8f9f7	1634	*/
<>	144:ef7eb2e8f9f7	1635	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
<>	144:ef7eb2e8f9f7	1636	{
<>	144:ef7eb2e8f9f7	1637	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
<>	144:ef7eb2e8f9f7	1638	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
<>	144:ef7eb2e8f9f7	1639	{
<>	144:ef7eb2e8f9f7	1640	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
<>	144:ef7eb2e8f9f7	1641	ITM->PORT[0].u8 = (uint8_t)ch;
<>	144:ef7eb2e8f9f7	1642	}
<>	144:ef7eb2e8f9f7	1643	return (ch);
<>	144:ef7eb2e8f9f7	1644	}
<>	144:ef7eb2e8f9f7	1645
<>	144:ef7eb2e8f9f7	1646
<>	144:ef7eb2e8f9f7	1647	/** \brief ITM Receive Character
<>	144:ef7eb2e8f9f7	1648
<>	144:ef7eb2e8f9f7	1649	The function inputs a character via the external variable \ref ITM_RxBuffer.
<>	144:ef7eb2e8f9f7	1650
<>	144:ef7eb2e8f9f7	1651	\return Received character.
<>	144:ef7eb2e8f9f7	1652	\return -1 No character pending.
<>	144:ef7eb2e8f9f7	1653	*/
<>	144:ef7eb2e8f9f7	1654	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
<>	144:ef7eb2e8f9f7	1655	int32_t ch = -1; /* no character available */
<>	144:ef7eb2e8f9f7	1656
<>	144:ef7eb2e8f9f7	1657	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
<>	144:ef7eb2e8f9f7	1658	ch = ITM_RxBuffer;
<>	144:ef7eb2e8f9f7	1659	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
<>	144:ef7eb2e8f9f7	1660	}
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662	return (ch);
<>	144:ef7eb2e8f9f7	1663	}
<>	144:ef7eb2e8f9f7	1664
<>	144:ef7eb2e8f9f7	1665
<>	144:ef7eb2e8f9f7	1666	/** \brief ITM Check Character
<>	144:ef7eb2e8f9f7	1667
<>	144:ef7eb2e8f9f7	1668	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
<>	144:ef7eb2e8f9f7	1669
<>	144:ef7eb2e8f9f7	1670	\return 0 No character available.
<>	144:ef7eb2e8f9f7	1671	\return 1 Character available.
<>	144:ef7eb2e8f9f7	1672	*/
<>	144:ef7eb2e8f9f7	1673	__STATIC_INLINE int32_t ITM_CheckChar (void) {
<>	144:ef7eb2e8f9f7	1674
<>	144:ef7eb2e8f9f7	1675	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
<>	144:ef7eb2e8f9f7	1676	return (0); /* no character available */
<>	144:ef7eb2e8f9f7	1677	} else {
<>	144:ef7eb2e8f9f7	1678	return (1); /* character available */
<>	144:ef7eb2e8f9f7	1679	}
<>	144:ef7eb2e8f9f7	1680	}
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	/@} end of CMSIS_core_DebugFunctions /
<>	144:ef7eb2e8f9f7	1683
<>	144:ef7eb2e8f9f7	1684
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686
<>	144:ef7eb2e8f9f7	1687	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1688	}
<>	144:ef7eb2e8f9f7	1689	#endif
<>	144:ef7eb2e8f9f7	1690
<>	144:ef7eb2e8f9f7	1691	#endif /* __CORE_CM3_H_DEPENDANT */
<>	144:ef7eb2e8f9f7	1692
<>	144:ef7eb2e8f9f7	1693	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
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targets/cmsis/core_cm3.h@147:ba84b7dc41a7, 2016-09-10 (annotated)

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