Helmut Tschemernjak
SX1276GenericLib to support sx1276 bassed LoRa modules, including HopeRF RFM95, Murata CMWX1ZZABZ and Semtech SX1276MB1MAS/SX1276MB1LAS modules
Dependents: DISCO-L072CZ-LRWAN1_LoRa_PingPong DISCO-L072CZ-LRWAN1_LoRa_PingPong DISCO-L072CZ-LRWAN1_LoRa_PingPong DISCO-L072CZ-LRWAN1_LoRa_USB_Rx ... more
registers/sx1276Regs-LoRa.h@85:93832cc77534, 2017-08-12 (annotated)
- Committer:
- Helmut Tschemernjak
- Date:
- Sat Aug 12 19:16:08 2017 +0200
- Revision:
- 85:93832cc77534
- Parent:
- 54:0d8ea87fbab9
The deepsleep does not need to disable the SysTick, it is off
already in suspend mode. It looks like out D21 MCU does not
need to keep the flash on during sleep, we got a newer chip
revision.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| GregCr | 0:e6ceb13d2d05 | 1 | /* |
| GregCr | 0:e6ceb13d2d05 | 2 | / _____) _ | | |
| GregCr | 0:e6ceb13d2d05 | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
| GregCr | 0:e6ceb13d2d05 | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
| GregCr | 0:e6ceb13d2d05 | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
| GregCr | 0:e6ceb13d2d05 | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
| mluis | 22:7f3aab69cca9 | 7 | (C) 2014 Semtech |
| GregCr | 0:e6ceb13d2d05 | 8 | |
| GregCr | 0:e6ceb13d2d05 | 9 | Description: SX1276 LoRa modem registers and bits definitions |
| GregCr | 0:e6ceb13d2d05 | 10 | |
| GregCr | 0:e6ceb13d2d05 | 11 | License: Revised BSD License, see LICENSE.TXT file include in the project |
| GregCr | 0:e6ceb13d2d05 | 12 | |
| GregCr | 0:e6ceb13d2d05 | 13 | Maintainer: Miguel Luis and Gregory Cristian |
| GregCr | 0:e6ceb13d2d05 | 14 | */ |
| GregCr | 0:e6ceb13d2d05 | 15 | #ifndef __SX1276_REGS_LORA_H__ |
| GregCr | 0:e6ceb13d2d05 | 16 | #define __SX1276_REGS_LORA_H__ |
| GregCr | 0:e6ceb13d2d05 | 17 | |
| GregCr | 0:e6ceb13d2d05 | 18 | /*! |
| GregCr | 0:e6ceb13d2d05 | 19 | * ============================================================================ |
| GregCr | 0:e6ceb13d2d05 | 20 | * SX1276 Internal registers Address |
| GregCr | 0:e6ceb13d2d05 | 21 | * ============================================================================ |
| GregCr | 0:e6ceb13d2d05 | 22 | */ |
| GregCr | 0:e6ceb13d2d05 | 23 | #define REG_LR_FIFO 0x00 |
| GregCr | 0:e6ceb13d2d05 | 24 | // Common settings |
| GregCr | 0:e6ceb13d2d05 | 25 | #define REG_LR_OPMODE 0x01 |
| GregCr | 0:e6ceb13d2d05 | 26 | #define REG_LR_FRFMSB 0x06 |
| GregCr | 0:e6ceb13d2d05 | 27 | #define REG_LR_FRFMID 0x07 |
| GregCr | 0:e6ceb13d2d05 | 28 | #define REG_LR_FRFLSB 0x08 |
| GregCr | 0:e6ceb13d2d05 | 29 | // Tx settings |
| GregCr | 0:e6ceb13d2d05 | 30 | #define REG_LR_PACONFIG 0x09 |
| GregCr | 0:e6ceb13d2d05 | 31 | #define REG_LR_PARAMP 0x0A |
| GregCr | 0:e6ceb13d2d05 | 32 | #define REG_LR_OCP 0x0B |
| GregCr | 0:e6ceb13d2d05 | 33 | // Rx settings |
| GregCr | 0:e6ceb13d2d05 | 34 | #define REG_LR_LNA 0x0C |
| GregCr | 0:e6ceb13d2d05 | 35 | // LoRa registers |
| GregCr | 0:e6ceb13d2d05 | 36 | #define REG_LR_FIFOADDRPTR 0x0D |
| GregCr | 0:e6ceb13d2d05 | 37 | #define REG_LR_FIFOTXBASEADDR 0x0E |
| GregCr | 0:e6ceb13d2d05 | 38 | #define REG_LR_FIFORXBASEADDR 0x0F |
| GregCr | 0:e6ceb13d2d05 | 39 | #define REG_LR_FIFORXCURRENTADDR 0x10 |
| GregCr | 0:e6ceb13d2d05 | 40 | #define REG_LR_IRQFLAGSMASK 0x11 |
| GregCr | 0:e6ceb13d2d05 | 41 | #define REG_LR_IRQFLAGS 0x12 |
| GregCr | 0:e6ceb13d2d05 | 42 | #define REG_LR_RXNBBYTES 0x13 |
| GregCr | 0:e6ceb13d2d05 | 43 | #define REG_LR_RXHEADERCNTVALUEMSB 0x14 |
| GregCr | 0:e6ceb13d2d05 | 44 | #define REG_LR_RXHEADERCNTVALUELSB 0x15 |
| GregCr | 0:e6ceb13d2d05 | 45 | #define REG_LR_RXPACKETCNTVALUEMSB 0x16 |
| GregCr | 0:e6ceb13d2d05 | 46 | #define REG_LR_RXPACKETCNTVALUELSB 0x17 |
| GregCr | 0:e6ceb13d2d05 | 47 | #define REG_LR_MODEMSTAT 0x18 |
| GregCr | 0:e6ceb13d2d05 | 48 | #define REG_LR_PKTSNRVALUE 0x19 |
| GregCr | 0:e6ceb13d2d05 | 49 | #define REG_LR_PKTRSSIVALUE 0x1A |
| GregCr | 0:e6ceb13d2d05 | 50 | #define REG_LR_RSSIVALUE 0x1B |
| GregCr | 0:e6ceb13d2d05 | 51 | #define REG_LR_HOPCHANNEL 0x1C |
| GregCr | 0:e6ceb13d2d05 | 52 | #define REG_LR_MODEMCONFIG1 0x1D |
| GregCr | 0:e6ceb13d2d05 | 53 | #define REG_LR_MODEMCONFIG2 0x1E |
| GregCr | 0:e6ceb13d2d05 | 54 | #define REG_LR_SYMBTIMEOUTLSB 0x1F |
| GregCr | 0:e6ceb13d2d05 | 55 | #define REG_LR_PREAMBLEMSB 0x20 |
| GregCr | 0:e6ceb13d2d05 | 56 | #define REG_LR_PREAMBLELSB 0x21 |
| GregCr | 0:e6ceb13d2d05 | 57 | #define REG_LR_PAYLOADLENGTH 0x22 |
| GregCr | 0:e6ceb13d2d05 | 58 | #define REG_LR_PAYLOADMAXLENGTH 0x23 |
| GregCr | 0:e6ceb13d2d05 | 59 | #define REG_LR_HOPPERIOD 0x24 |
| GregCr | 0:e6ceb13d2d05 | 60 | #define REG_LR_FIFORXBYTEADDR 0x25 |
| GregCr | 0:e6ceb13d2d05 | 61 | #define REG_LR_MODEMCONFIG3 0x26 |
| GregCr | 0:e6ceb13d2d05 | 62 | #define REG_LR_FEIMSB 0x28 |
| GregCr | 0:e6ceb13d2d05 | 63 | #define REG_LR_FEIMID 0x29 |
| GregCr | 0:e6ceb13d2d05 | 64 | #define REG_LR_FEILSB 0x2A |
| GregCr | 0:e6ceb13d2d05 | 65 | #define REG_LR_RSSIWIDEBAND 0x2C |
| mluis | 22:7f3aab69cca9 | 66 | #define REG_LR_TEST2F 0x2F |
| mluis | 22:7f3aab69cca9 | 67 | #define REG_LR_TEST30 0x30 |
| GregCr | 0:e6ceb13d2d05 | 68 | #define REG_LR_DETECTOPTIMIZE 0x31 |
| GregCr | 0:e6ceb13d2d05 | 69 | #define REG_LR_INVERTIQ 0x33 |
| mluis | 22:7f3aab69cca9 | 70 | #define REG_LR_TEST36 0x36 |
| GregCr | 0:e6ceb13d2d05 | 71 | #define REG_LR_DETECTIONTHRESHOLD 0x37 |
| mluis | 13:618826a997e2 | 72 | #define REG_LR_SYNCWORD 0x39 |
| mluis | 22:7f3aab69cca9 | 73 | #define REG_LR_TEST3A 0x3A |
| mluis | 22:7f3aab69cca9 | 74 | #define REG_LR_INVERTIQ2 0x3B |
| mluis | 13:618826a997e2 | 75 | |
| GregCr | 0:e6ceb13d2d05 | 76 | // end of documented register in datasheet |
| GregCr | 0:e6ceb13d2d05 | 77 | // I/O settings |
| GregCr | 0:e6ceb13d2d05 | 78 | #define REG_LR_DIOMAPPING1 0x40 |
| GregCr | 0:e6ceb13d2d05 | 79 | #define REG_LR_DIOMAPPING2 0x41 |
| GregCr | 0:e6ceb13d2d05 | 80 | // Version |
| GregCr | 0:e6ceb13d2d05 | 81 | #define REG_LR_VERSION 0x42 |
| GregCr | 0:e6ceb13d2d05 | 82 | // Additional settings |
| GregCr | 0:e6ceb13d2d05 | 83 | #define REG_LR_PLLHOP 0x44 |
| GregCr | 0:e6ceb13d2d05 | 84 | #define REG_LR_TCXO 0x4B |
| GregCr | 0:e6ceb13d2d05 | 85 | #define REG_LR_PADAC 0x4D |
| GregCr | 0:e6ceb13d2d05 | 86 | #define REG_LR_FORMERTEMP 0x5B |
| GregCr | 0:e6ceb13d2d05 | 87 | #define REG_LR_BITRATEFRAC 0x5D |
| GregCr | 0:e6ceb13d2d05 | 88 | #define REG_LR_AGCREF 0x61 |
| GregCr | 0:e6ceb13d2d05 | 89 | #define REG_LR_AGCTHRESH1 0x62 |
| GregCr | 0:e6ceb13d2d05 | 90 | #define REG_LR_AGCTHRESH2 0x63 |
| GregCr | 0:e6ceb13d2d05 | 91 | #define REG_LR_AGCTHRESH3 0x64 |
| GregCr | 0:e6ceb13d2d05 | 92 | #define REG_LR_PLL 0x70 |
| GregCr | 0:e6ceb13d2d05 | 93 | |
| GregCr | 0:e6ceb13d2d05 | 94 | /*! |
| GregCr | 0:e6ceb13d2d05 | 95 | * ============================================================================ |
| GregCr | 0:e6ceb13d2d05 | 96 | * SX1276 LoRa bits control definition |
| GregCr | 0:e6ceb13d2d05 | 97 | * ============================================================================ |
| GregCr | 0:e6ceb13d2d05 | 98 | */ |
| GregCr | 0:e6ceb13d2d05 | 99 | |
| GregCr | 0:e6ceb13d2d05 | 100 | /*! |
| GregCr | 0:e6ceb13d2d05 | 101 | * RegFifo |
| GregCr | 0:e6ceb13d2d05 | 102 | */ |
| GregCr | 0:e6ceb13d2d05 | 103 | |
| GregCr | 0:e6ceb13d2d05 | 104 | /*! |
| GregCr | 0:e6ceb13d2d05 | 105 | * RegOpMode |
| GregCr | 0:e6ceb13d2d05 | 106 | */ |
| GregCr | 0:e6ceb13d2d05 | 107 | #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F |
| GregCr | 0:e6ceb13d2d05 | 108 | #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 109 | #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 |
| GregCr | 0:e6ceb13d2d05 | 110 | |
| GregCr | 0:e6ceb13d2d05 | 111 | #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF |
| GregCr | 0:e6ceb13d2d05 | 112 | #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 |
| GregCr | 0:e6ceb13d2d05 | 113 | #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 114 | |
| GregCr | 0:e6ceb13d2d05 | 115 | #define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 |
| GregCr | 0:e6ceb13d2d05 | 116 | #define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default |
| GregCr | 0:e6ceb13d2d05 | 117 | #define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 |
| GregCr | 0:e6ceb13d2d05 | 118 | |
| GregCr | 0:e6ceb13d2d05 | 119 | #define RFLR_OPMODE_MASK 0xF8 |
| GregCr | 0:e6ceb13d2d05 | 120 | #define RFLR_OPMODE_SLEEP 0x00 |
| GregCr | 0:e6ceb13d2d05 | 121 | #define RFLR_OPMODE_STANDBY 0x01 // Default |
| GregCr | 0:e6ceb13d2d05 | 122 | #define RFLR_OPMODE_SYNTHESIZER_TX 0x02 |
| GregCr | 0:e6ceb13d2d05 | 123 | #define RFLR_OPMODE_TRANSMITTER 0x03 |
| GregCr | 0:e6ceb13d2d05 | 124 | #define RFLR_OPMODE_SYNTHESIZER_RX 0x04 |
| GregCr | 0:e6ceb13d2d05 | 125 | #define RFLR_OPMODE_RECEIVER 0x05 |
| GregCr | 0:e6ceb13d2d05 | 126 | // LoRa specific modes |
| GregCr | 0:e6ceb13d2d05 | 127 | #define RFLR_OPMODE_RECEIVER_SINGLE 0x06 |
| GregCr | 0:e6ceb13d2d05 | 128 | #define RFLR_OPMODE_CAD 0x07 |
| GregCr | 0:e6ceb13d2d05 | 129 | |
| GregCr | 0:e6ceb13d2d05 | 130 | /*! |
| mluis | 22:7f3aab69cca9 | 131 | * RegFrf (MHz) |
| GregCr | 0:e6ceb13d2d05 | 132 | */ |
| GregCr | 0:e6ceb13d2d05 | 133 | #define RFLR_FRFMSB_434_MHZ 0x6C // Default |
| GregCr | 0:e6ceb13d2d05 | 134 | #define RFLR_FRFMID_434_MHZ 0x80 // Default |
| GregCr | 0:e6ceb13d2d05 | 135 | #define RFLR_FRFLSB_434_MHZ 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 136 | |
| GregCr | 0:e6ceb13d2d05 | 137 | /*! |
| GregCr | 0:e6ceb13d2d05 | 138 | * RegPaConfig |
| GregCr | 0:e6ceb13d2d05 | 139 | */ |
| GregCr | 0:e6ceb13d2d05 | 140 | #define RFLR_PACONFIG_PASELECT_MASK 0x7F |
| GregCr | 0:e6ceb13d2d05 | 141 | #define RFLR_PACONFIG_PASELECT_PABOOST 0x80 |
| GregCr | 0:e6ceb13d2d05 | 142 | #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 143 | |
| GregCr | 0:e6ceb13d2d05 | 144 | #define RFLR_PACONFIG_MAX_POWER_MASK 0x8F |
| GregCr | 0:e6ceb13d2d05 | 145 | |
| GregCr | 0:e6ceb13d2d05 | 146 | #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 |
| GregCr | 0:e6ceb13d2d05 | 147 | |
| GregCr | 0:e6ceb13d2d05 | 148 | /*! |
| GregCr | 0:e6ceb13d2d05 | 149 | * RegPaRamp |
| GregCr | 0:e6ceb13d2d05 | 150 | */ |
| GregCr | 0:e6ceb13d2d05 | 151 | #define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF |
| GregCr | 0:e6ceb13d2d05 | 152 | #define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 |
| GregCr | 0:e6ceb13d2d05 | 153 | #define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 154 | |
| GregCr | 0:e6ceb13d2d05 | 155 | #define RFLR_PARAMP_MASK 0xF0 |
| GregCr | 0:e6ceb13d2d05 | 156 | #define RFLR_PARAMP_3400_US 0x00 |
| GregCr | 0:e6ceb13d2d05 | 157 | #define RFLR_PARAMP_2000_US 0x01 |
| GregCr | 0:e6ceb13d2d05 | 158 | #define RFLR_PARAMP_1000_US 0x02 |
| GregCr | 0:e6ceb13d2d05 | 159 | #define RFLR_PARAMP_0500_US 0x03 |
| GregCr | 0:e6ceb13d2d05 | 160 | #define RFLR_PARAMP_0250_US 0x04 |
| GregCr | 0:e6ceb13d2d05 | 161 | #define RFLR_PARAMP_0125_US 0x05 |
| GregCr | 0:e6ceb13d2d05 | 162 | #define RFLR_PARAMP_0100_US 0x06 |
| GregCr | 0:e6ceb13d2d05 | 163 | #define RFLR_PARAMP_0062_US 0x07 |
| GregCr | 0:e6ceb13d2d05 | 164 | #define RFLR_PARAMP_0050_US 0x08 |
| GregCr | 0:e6ceb13d2d05 | 165 | #define RFLR_PARAMP_0040_US 0x09 // Default |
| GregCr | 0:e6ceb13d2d05 | 166 | #define RFLR_PARAMP_0031_US 0x0A |
| GregCr | 0:e6ceb13d2d05 | 167 | #define RFLR_PARAMP_0025_US 0x0B |
| GregCr | 0:e6ceb13d2d05 | 168 | #define RFLR_PARAMP_0020_US 0x0C |
| GregCr | 0:e6ceb13d2d05 | 169 | #define RFLR_PARAMP_0015_US 0x0D |
| GregCr | 0:e6ceb13d2d05 | 170 | #define RFLR_PARAMP_0012_US 0x0E |
| GregCr | 0:e6ceb13d2d05 | 171 | #define RFLR_PARAMP_0010_US 0x0F |
| GregCr | 0:e6ceb13d2d05 | 172 | |
| GregCr | 0:e6ceb13d2d05 | 173 | /*! |
| GregCr | 0:e6ceb13d2d05 | 174 | * RegOcp |
| GregCr | 0:e6ceb13d2d05 | 175 | */ |
| GregCr | 0:e6ceb13d2d05 | 176 | #define RFLR_OCP_MASK 0xDF |
| GregCr | 0:e6ceb13d2d05 | 177 | #define RFLR_OCP_ON 0x20 // Default |
| GregCr | 0:e6ceb13d2d05 | 178 | #define RFLR_OCP_OFF 0x00 |
| GregCr | 0:e6ceb13d2d05 | 179 | |
| GregCr | 0:e6ceb13d2d05 | 180 | #define RFLR_OCP_TRIM_MASK 0xE0 |
| GregCr | 0:e6ceb13d2d05 | 181 | #define RFLR_OCP_TRIM_045_MA 0x00 |
| GregCr | 0:e6ceb13d2d05 | 182 | #define RFLR_OCP_TRIM_050_MA 0x01 |
| GregCr | 0:e6ceb13d2d05 | 183 | #define RFLR_OCP_TRIM_055_MA 0x02 |
| GregCr | 0:e6ceb13d2d05 | 184 | #define RFLR_OCP_TRIM_060_MA 0x03 |
| GregCr | 0:e6ceb13d2d05 | 185 | #define RFLR_OCP_TRIM_065_MA 0x04 |
| GregCr | 0:e6ceb13d2d05 | 186 | #define RFLR_OCP_TRIM_070_MA 0x05 |
| GregCr | 0:e6ceb13d2d05 | 187 | #define RFLR_OCP_TRIM_075_MA 0x06 |
| GregCr | 0:e6ceb13d2d05 | 188 | #define RFLR_OCP_TRIM_080_MA 0x07 |
| GregCr | 0:e6ceb13d2d05 | 189 | #define RFLR_OCP_TRIM_085_MA 0x08 |
| GregCr | 0:e6ceb13d2d05 | 190 | #define RFLR_OCP_TRIM_090_MA 0x09 |
| GregCr | 0:e6ceb13d2d05 | 191 | #define RFLR_OCP_TRIM_095_MA 0x0A |
| GregCr | 0:e6ceb13d2d05 | 192 | #define RFLR_OCP_TRIM_100_MA 0x0B // Default |
| GregCr | 0:e6ceb13d2d05 | 193 | #define RFLR_OCP_TRIM_105_MA 0x0C |
| GregCr | 0:e6ceb13d2d05 | 194 | #define RFLR_OCP_TRIM_110_MA 0x0D |
| GregCr | 0:e6ceb13d2d05 | 195 | #define RFLR_OCP_TRIM_115_MA 0x0E |
| GregCr | 0:e6ceb13d2d05 | 196 | #define RFLR_OCP_TRIM_120_MA 0x0F |
| GregCr | 0:e6ceb13d2d05 | 197 | #define RFLR_OCP_TRIM_130_MA 0x10 |
| GregCr | 0:e6ceb13d2d05 | 198 | #define RFLR_OCP_TRIM_140_MA 0x11 |
| GregCr | 0:e6ceb13d2d05 | 199 | #define RFLR_OCP_TRIM_150_MA 0x12 |
| GregCr | 0:e6ceb13d2d05 | 200 | #define RFLR_OCP_TRIM_160_MA 0x13 |
| GregCr | 0:e6ceb13d2d05 | 201 | #define RFLR_OCP_TRIM_170_MA 0x14 |
| GregCr | 0:e6ceb13d2d05 | 202 | #define RFLR_OCP_TRIM_180_MA 0x15 |
| GregCr | 0:e6ceb13d2d05 | 203 | #define RFLR_OCP_TRIM_190_MA 0x16 |
| GregCr | 0:e6ceb13d2d05 | 204 | #define RFLR_OCP_TRIM_200_MA 0x17 |
| GregCr | 0:e6ceb13d2d05 | 205 | #define RFLR_OCP_TRIM_210_MA 0x18 |
| GregCr | 0:e6ceb13d2d05 | 206 | #define RFLR_OCP_TRIM_220_MA 0x19 |
| GregCr | 0:e6ceb13d2d05 | 207 | #define RFLR_OCP_TRIM_230_MA 0x1A |
| GregCr | 0:e6ceb13d2d05 | 208 | #define RFLR_OCP_TRIM_240_MA 0x1B |
| GregCr | 0:e6ceb13d2d05 | 209 | |
| GregCr | 0:e6ceb13d2d05 | 210 | /*! |
| GregCr | 0:e6ceb13d2d05 | 211 | * RegLna |
| GregCr | 0:e6ceb13d2d05 | 212 | */ |
| GregCr | 0:e6ceb13d2d05 | 213 | #define RFLR_LNA_GAIN_MASK 0x1F |
| GregCr | 0:e6ceb13d2d05 | 214 | #define RFLR_LNA_GAIN_G1 0x20 // Default |
| GregCr | 0:e6ceb13d2d05 | 215 | #define RFLR_LNA_GAIN_G2 0x40 |
| GregCr | 0:e6ceb13d2d05 | 216 | #define RFLR_LNA_GAIN_G3 0x60 |
| GregCr | 0:e6ceb13d2d05 | 217 | #define RFLR_LNA_GAIN_G4 0x80 |
| GregCr | 0:e6ceb13d2d05 | 218 | #define RFLR_LNA_GAIN_G5 0xA0 |
| GregCr | 0:e6ceb13d2d05 | 219 | #define RFLR_LNA_GAIN_G6 0xC0 |
| GregCr | 0:e6ceb13d2d05 | 220 | |
| GregCr | 0:e6ceb13d2d05 | 221 | #define RFLR_LNA_BOOST_LF_MASK 0xE7 |
| GregCr | 0:e6ceb13d2d05 | 222 | #define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 223 | |
| GregCr | 0:e6ceb13d2d05 | 224 | #define RFLR_LNA_BOOST_HF_MASK 0xFC |
| GregCr | 0:e6ceb13d2d05 | 225 | #define RFLR_LNA_BOOST_HF_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 226 | #define RFLR_LNA_BOOST_HF_ON 0x03 |
| GregCr | 0:e6ceb13d2d05 | 227 | |
| GregCr | 0:e6ceb13d2d05 | 228 | /*! |
| GregCr | 0:e6ceb13d2d05 | 229 | * RegFifoAddrPtr |
| GregCr | 0:e6ceb13d2d05 | 230 | */ |
| GregCr | 0:e6ceb13d2d05 | 231 | #define RFLR_FIFOADDRPTR 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 232 | |
| GregCr | 0:e6ceb13d2d05 | 233 | /*! |
| GregCr | 0:e6ceb13d2d05 | 234 | * RegFifoTxBaseAddr |
| GregCr | 0:e6ceb13d2d05 | 235 | */ |
| GregCr | 0:e6ceb13d2d05 | 236 | #define RFLR_FIFOTXBASEADDR 0x80 // Default |
| GregCr | 0:e6ceb13d2d05 | 237 | |
| GregCr | 0:e6ceb13d2d05 | 238 | /*! |
| GregCr | 0:e6ceb13d2d05 | 239 | * RegFifoTxBaseAddr |
| GregCr | 0:e6ceb13d2d05 | 240 | */ |
| GregCr | 0:e6ceb13d2d05 | 241 | #define RFLR_FIFORXBASEADDR 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 242 | |
| GregCr | 0:e6ceb13d2d05 | 243 | /*! |
| mluis | 22:7f3aab69cca9 | 244 | * RegFifoRxCurrentAddr (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 245 | */ |
| GregCr | 0:e6ceb13d2d05 | 246 | |
| GregCr | 0:e6ceb13d2d05 | 247 | /*! |
| GregCr | 0:e6ceb13d2d05 | 248 | * RegIrqFlagsMask |
| GregCr | 0:e6ceb13d2d05 | 249 | */ |
| GregCr | 0:e6ceb13d2d05 | 250 | #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 |
| GregCr | 0:e6ceb13d2d05 | 251 | #define RFLR_IRQFLAGS_RXDONE_MASK 0x40 |
| GregCr | 0:e6ceb13d2d05 | 252 | #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 |
| GregCr | 0:e6ceb13d2d05 | 253 | #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 |
| GregCr | 0:e6ceb13d2d05 | 254 | #define RFLR_IRQFLAGS_TXDONE_MASK 0x08 |
| GregCr | 0:e6ceb13d2d05 | 255 | #define RFLR_IRQFLAGS_CADDONE_MASK 0x04 |
| GregCr | 0:e6ceb13d2d05 | 256 | #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 |
| GregCr | 0:e6ceb13d2d05 | 257 | #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 |
| GregCr | 0:e6ceb13d2d05 | 258 | |
| GregCr | 0:e6ceb13d2d05 | 259 | /*! |
| GregCr | 0:e6ceb13d2d05 | 260 | * RegIrqFlags |
| GregCr | 0:e6ceb13d2d05 | 261 | */ |
| GregCr | 0:e6ceb13d2d05 | 262 | #define RFLR_IRQFLAGS_RXTIMEOUT 0x80 |
| GregCr | 0:e6ceb13d2d05 | 263 | #define RFLR_IRQFLAGS_RXDONE 0x40 |
| GregCr | 0:e6ceb13d2d05 | 264 | #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 |
| GregCr | 0:e6ceb13d2d05 | 265 | #define RFLR_IRQFLAGS_VALIDHEADER 0x10 |
| GregCr | 0:e6ceb13d2d05 | 266 | #define RFLR_IRQFLAGS_TXDONE 0x08 |
| GregCr | 0:e6ceb13d2d05 | 267 | #define RFLR_IRQFLAGS_CADDONE 0x04 |
| GregCr | 0:e6ceb13d2d05 | 268 | #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 |
| GregCr | 0:e6ceb13d2d05 | 269 | #define RFLR_IRQFLAGS_CADDETECTED 0x01 |
| GregCr | 0:e6ceb13d2d05 | 270 | |
| GregCr | 0:e6ceb13d2d05 | 271 | /*! |
| mluis | 22:7f3aab69cca9 | 272 | * RegFifoRxNbBytes (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 273 | */ |
| mluis | 22:7f3aab69cca9 | 274 | |
| GregCr | 0:e6ceb13d2d05 | 275 | /*! |
| mluis | 22:7f3aab69cca9 | 276 | * RegRxHeaderCntValueMsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 277 | */ |
| mluis | 22:7f3aab69cca9 | 278 | |
| GregCr | 0:e6ceb13d2d05 | 279 | /*! |
| mluis | 22:7f3aab69cca9 | 280 | * RegRxHeaderCntValueLsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 281 | */ |
| mluis | 22:7f3aab69cca9 | 282 | |
| GregCr | 0:e6ceb13d2d05 | 283 | /*! |
| mluis | 22:7f3aab69cca9 | 284 | * RegRxPacketCntValueMsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 285 | */ |
| mluis | 22:7f3aab69cca9 | 286 | |
| GregCr | 0:e6ceb13d2d05 | 287 | /*! |
| mluis | 22:7f3aab69cca9 | 288 | * RegRxPacketCntValueLsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 289 | */ |
| mluis | 22:7f3aab69cca9 | 290 | |
| GregCr | 0:e6ceb13d2d05 | 291 | /*! |
| mluis | 22:7f3aab69cca9 | 292 | * RegModemStat (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 293 | */ |
| Helmut Tschemernjak | 54:0d8ea87fbab9 | 294 | #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F |
| GregCr | 0:e6ceb13d2d05 | 295 | #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 |
| Helmut Tschemernjak | 54:0d8ea87fbab9 | 296 | |
| Helmut Tschemernjak | 54:0d8ea87fbab9 | 297 | #define RFLR_MODEMSTAT_MODEM_CLEAR 0x10 |
| Helmut Tschemernjak | 54:0d8ea87fbab9 | 298 | #define RFLR_MODEMSTAT_HEADERINFO_VALID 0x08 |
| Helmut Tschemernjak | 54:0d8ea87fbab9 | 299 | #define RFLR_MODEMSTAT_RX_ONGOING 0x04 |
| Helmut Tschemernjak | 54:0d8ea87fbab9 | 300 | #define RFLR_MODEMSTAT_SIGNAL_SYNCRONIZED 0x02 |
| Helmut Tschemernjak | 54:0d8ea87fbab9 | 301 | #define RFLR_MODEMSTAT_SIGNAL_DETECTED 0x01 |
| Helmut Tschemernjak | 54:0d8ea87fbab9 | 302 | |
| GregCr | 0:e6ceb13d2d05 | 303 | /*! |
| mluis | 22:7f3aab69cca9 | 304 | * RegPktSnrValue (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 305 | */ |
| GregCr | 0:e6ceb13d2d05 | 306 | |
| GregCr | 0:e6ceb13d2d05 | 307 | /*! |
| mluis | 22:7f3aab69cca9 | 308 | * RegPktRssiValue (Read Only) |
| mluis | 22:7f3aab69cca9 | 309 | */ |
| mluis | 22:7f3aab69cca9 | 310 | |
| mluis | 22:7f3aab69cca9 | 311 | /*! |
| mluis | 22:7f3aab69cca9 | 312 | * RegRssiValue (Read Only) |
| mluis | 22:7f3aab69cca9 | 313 | */ |
| mluis | 22:7f3aab69cca9 | 314 | |
| mluis | 22:7f3aab69cca9 | 315 | /*! |
| mluis | 22:7f3aab69cca9 | 316 | * RegHopChannel (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 317 | */ |
| GregCr | 0:e6ceb13d2d05 | 318 | #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F |
| GregCr | 0:e6ceb13d2d05 | 319 | #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 |
| GregCr | 0:e6ceb13d2d05 | 320 | #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 321 | |
| GregCr | 0:e6ceb13d2d05 | 322 | #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF |
| GregCr | 0:e6ceb13d2d05 | 323 | #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 |
| GregCr | 0:e6ceb13d2d05 | 324 | #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 325 | |
| GregCr | 0:e6ceb13d2d05 | 326 | #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F |
| mluis | 22:7f3aab69cca9 | 327 | |
| GregCr | 0:e6ceb13d2d05 | 328 | /*! |
| GregCr | 0:e6ceb13d2d05 | 329 | * RegModemConfig1 |
| GregCr | 0:e6ceb13d2d05 | 330 | */ |
| GregCr | 0:e6ceb13d2d05 | 331 | #define RFLR_MODEMCONFIG1_BW_MASK 0x0F |
| GregCr | 0:e6ceb13d2d05 | 332 | #define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 |
| GregCr | 0:e6ceb13d2d05 | 333 | #define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 |
| GregCr | 0:e6ceb13d2d05 | 334 | #define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 |
| GregCr | 0:e6ceb13d2d05 | 335 | #define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 |
| GregCr | 0:e6ceb13d2d05 | 336 | #define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 |
| GregCr | 0:e6ceb13d2d05 | 337 | #define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 |
| GregCr | 0:e6ceb13d2d05 | 338 | #define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 |
| GregCr | 0:e6ceb13d2d05 | 339 | #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default |
| GregCr | 0:e6ceb13d2d05 | 340 | #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 |
| GregCr | 0:e6ceb13d2d05 | 341 | #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 |
| GregCr | 0:e6ceb13d2d05 | 342 | |
| GregCr | 0:e6ceb13d2d05 | 343 | #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 |
| GregCr | 0:e6ceb13d2d05 | 344 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 |
| GregCr | 0:e6ceb13d2d05 | 345 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default |
| GregCr | 0:e6ceb13d2d05 | 346 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 |
| GregCr | 0:e6ceb13d2d05 | 347 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 |
| GregCr | 0:e6ceb13d2d05 | 348 | |
| GregCr | 0:e6ceb13d2d05 | 349 | #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE |
| GregCr | 0:e6ceb13d2d05 | 350 | #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 |
| GregCr | 0:e6ceb13d2d05 | 351 | #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 352 | |
| GregCr | 0:e6ceb13d2d05 | 353 | /*! |
| GregCr | 0:e6ceb13d2d05 | 354 | * RegModemConfig2 |
| GregCr | 0:e6ceb13d2d05 | 355 | */ |
| GregCr | 0:e6ceb13d2d05 | 356 | #define RFLR_MODEMCONFIG2_SF_MASK 0x0F |
| GregCr | 0:e6ceb13d2d05 | 357 | #define RFLR_MODEMCONFIG2_SF_6 0x60 |
| GregCr | 0:e6ceb13d2d05 | 358 | #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default |
| GregCr | 0:e6ceb13d2d05 | 359 | #define RFLR_MODEMCONFIG2_SF_8 0x80 |
| GregCr | 0:e6ceb13d2d05 | 360 | #define RFLR_MODEMCONFIG2_SF_9 0x90 |
| GregCr | 0:e6ceb13d2d05 | 361 | #define RFLR_MODEMCONFIG2_SF_10 0xA0 |
| GregCr | 0:e6ceb13d2d05 | 362 | #define RFLR_MODEMCONFIG2_SF_11 0xB0 |
| GregCr | 0:e6ceb13d2d05 | 363 | #define RFLR_MODEMCONFIG2_SF_12 0xC0 |
| GregCr | 0:e6ceb13d2d05 | 364 | |
| GregCr | 0:e6ceb13d2d05 | 365 | #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 |
| GregCr | 0:e6ceb13d2d05 | 366 | #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 |
| GregCr | 0:e6ceb13d2d05 | 367 | #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 |
| GregCr | 0:e6ceb13d2d05 | 368 | |
| GregCr | 0:e6ceb13d2d05 | 369 | #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB |
| GregCr | 0:e6ceb13d2d05 | 370 | #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 |
| GregCr | 0:e6ceb13d2d05 | 371 | #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 372 | |
| GregCr | 0:e6ceb13d2d05 | 373 | #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC |
| mluis | 22:7f3aab69cca9 | 374 | #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 375 | |
| GregCr | 0:e6ceb13d2d05 | 376 | /*! |
| GregCr | 0:e6ceb13d2d05 | 377 | * RegSymbTimeoutLsb |
| GregCr | 0:e6ceb13d2d05 | 378 | */ |
| GregCr | 0:e6ceb13d2d05 | 379 | #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default |
| GregCr | 0:e6ceb13d2d05 | 380 | |
| GregCr | 0:e6ceb13d2d05 | 381 | /*! |
| GregCr | 0:e6ceb13d2d05 | 382 | * RegPreambleLengthMsb |
| GregCr | 0:e6ceb13d2d05 | 383 | */ |
| GregCr | 0:e6ceb13d2d05 | 384 | #define RFLR_PREAMBLELENGTHMSB 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 385 | |
| GregCr | 0:e6ceb13d2d05 | 386 | /*! |
| GregCr | 0:e6ceb13d2d05 | 387 | * RegPreambleLengthLsb |
| GregCr | 0:e6ceb13d2d05 | 388 | */ |
| GregCr | 0:e6ceb13d2d05 | 389 | #define RFLR_PREAMBLELENGTHLSB 0x08 // Default |
| GregCr | 0:e6ceb13d2d05 | 390 | |
| GregCr | 0:e6ceb13d2d05 | 391 | /*! |
| GregCr | 0:e6ceb13d2d05 | 392 | * RegPayloadLength |
| GregCr | 0:e6ceb13d2d05 | 393 | */ |
| GregCr | 0:e6ceb13d2d05 | 394 | #define RFLR_PAYLOADLENGTH 0x0E // Default |
| GregCr | 0:e6ceb13d2d05 | 395 | |
| GregCr | 0:e6ceb13d2d05 | 396 | /*! |
| GregCr | 0:e6ceb13d2d05 | 397 | * RegPayloadMaxLength |
| GregCr | 0:e6ceb13d2d05 | 398 | */ |
| GregCr | 0:e6ceb13d2d05 | 399 | #define RFLR_PAYLOADMAXLENGTH 0xFF // Default |
| GregCr | 0:e6ceb13d2d05 | 400 | |
| GregCr | 0:e6ceb13d2d05 | 401 | /*! |
| GregCr | 0:e6ceb13d2d05 | 402 | * RegHopPeriod |
| GregCr | 0:e6ceb13d2d05 | 403 | */ |
| GregCr | 0:e6ceb13d2d05 | 404 | #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 405 | |
| GregCr | 0:e6ceb13d2d05 | 406 | /*! |
| mluis | 22:7f3aab69cca9 | 407 | * RegFifoRxByteAddr (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 408 | */ |
| GregCr | 0:e6ceb13d2d05 | 409 | |
| GregCr | 0:e6ceb13d2d05 | 410 | /*! |
| GregCr | 0:e6ceb13d2d05 | 411 | * RegModemConfig3 |
| GregCr | 0:e6ceb13d2d05 | 412 | */ |
| GregCr | 0:e6ceb13d2d05 | 413 | #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 |
| GregCr | 0:e6ceb13d2d05 | 414 | #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 |
| GregCr | 0:e6ceb13d2d05 | 415 | #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 416 | |
| GregCr | 0:e6ceb13d2d05 | 417 | #define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB |
| GregCr | 0:e6ceb13d2d05 | 418 | #define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default |
| GregCr | 0:e6ceb13d2d05 | 419 | #define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 |
| GregCr | 0:e6ceb13d2d05 | 420 | |
| GregCr | 0:e6ceb13d2d05 | 421 | /*! |
| mluis | 22:7f3aab69cca9 | 422 | * RegFeiMsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 423 | */ |
| GregCr | 0:e6ceb13d2d05 | 424 | |
| GregCr | 0:e6ceb13d2d05 | 425 | /*! |
| mluis | 22:7f3aab69cca9 | 426 | * RegFeiMid (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 427 | */ |
| GregCr | 0:e6ceb13d2d05 | 428 | |
| GregCr | 0:e6ceb13d2d05 | 429 | /*! |
| mluis | 22:7f3aab69cca9 | 430 | * RegFeiLsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 431 | */ |
| GregCr | 0:e6ceb13d2d05 | 432 | |
| GregCr | 0:e6ceb13d2d05 | 433 | /*! |
| mluis | 22:7f3aab69cca9 | 434 | * RegRssiWideband (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 435 | */ |
| GregCr | 0:e6ceb13d2d05 | 436 | |
| GregCr | 0:e6ceb13d2d05 | 437 | /*! |
| GregCr | 0:e6ceb13d2d05 | 438 | * RegDetectOptimize |
| GregCr | 0:e6ceb13d2d05 | 439 | */ |
| GregCr | 0:e6ceb13d2d05 | 440 | #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 |
| GregCr | 0:e6ceb13d2d05 | 441 | #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default |
| GregCr | 0:e6ceb13d2d05 | 442 | #define RFLR_DETECTIONOPTIMIZE_SF6 0x05 |
| GregCr | 0:e6ceb13d2d05 | 443 | |
| GregCr | 0:e6ceb13d2d05 | 444 | /*! |
| GregCr | 0:e6ceb13d2d05 | 445 | * RegInvertIQ |
| GregCr | 0:e6ceb13d2d05 | 446 | */ |
| GregCr | 0:e6ceb13d2d05 | 447 | #define RFLR_INVERTIQ_RX_MASK 0xBF |
| GregCr | 0:e6ceb13d2d05 | 448 | #define RFLR_INVERTIQ_RX_OFF 0x00 |
| GregCr | 0:e6ceb13d2d05 | 449 | #define RFLR_INVERTIQ_RX_ON 0x40 |
| GregCr | 0:e6ceb13d2d05 | 450 | #define RFLR_INVERTIQ_TX_MASK 0xFE |
| GregCr | 0:e6ceb13d2d05 | 451 | #define RFLR_INVERTIQ_TX_OFF 0x01 |
| GregCr | 0:e6ceb13d2d05 | 452 | #define RFLR_INVERTIQ_TX_ON 0x00 |
| GregCr | 0:e6ceb13d2d05 | 453 | |
| GregCr | 0:e6ceb13d2d05 | 454 | /*! |
| GregCr | 0:e6ceb13d2d05 | 455 | * RegDetectionThreshold |
| GregCr | 0:e6ceb13d2d05 | 456 | */ |
| GregCr | 0:e6ceb13d2d05 | 457 | #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default |
| GregCr | 0:e6ceb13d2d05 | 458 | #define RFLR_DETECTIONTHRESH_SF6 0x0C |
| GregCr | 0:e6ceb13d2d05 | 459 | |
| GregCr | 0:e6ceb13d2d05 | 460 | /*! |
| mluis | 22:7f3aab69cca9 | 461 | * RegInvertIQ2 |
| mluis | 22:7f3aab69cca9 | 462 | */ |
| mluis | 22:7f3aab69cca9 | 463 | #define RFLR_INVERTIQ2_ON 0x19 |
| mluis | 22:7f3aab69cca9 | 464 | #define RFLR_INVERTIQ2_OFF 0x1D |
| mluis | 22:7f3aab69cca9 | 465 | |
| mluis | 22:7f3aab69cca9 | 466 | /*! |
| GregCr | 0:e6ceb13d2d05 | 467 | * RegDioMapping1 |
| GregCr | 0:e6ceb13d2d05 | 468 | */ |
| GregCr | 0:e6ceb13d2d05 | 469 | #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F |
| GregCr | 0:e6ceb13d2d05 | 470 | #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 471 | #define RFLR_DIOMAPPING1_DIO0_01 0x40 |
| GregCr | 0:e6ceb13d2d05 | 472 | #define RFLR_DIOMAPPING1_DIO0_10 0x80 |
| GregCr | 0:e6ceb13d2d05 | 473 | #define RFLR_DIOMAPPING1_DIO0_11 0xC0 |
| GregCr | 0:e6ceb13d2d05 | 474 | |
| GregCr | 0:e6ceb13d2d05 | 475 | #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF |
| GregCr | 0:e6ceb13d2d05 | 476 | #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 477 | #define RFLR_DIOMAPPING1_DIO1_01 0x10 |
| GregCr | 0:e6ceb13d2d05 | 478 | #define RFLR_DIOMAPPING1_DIO1_10 0x20 |
| GregCr | 0:e6ceb13d2d05 | 479 | #define RFLR_DIOMAPPING1_DIO1_11 0x30 |
| GregCr | 0:e6ceb13d2d05 | 480 | |
| GregCr | 0:e6ceb13d2d05 | 481 | #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 |
| GregCr | 0:e6ceb13d2d05 | 482 | #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 483 | #define RFLR_DIOMAPPING1_DIO2_01 0x04 |
| GregCr | 0:e6ceb13d2d05 | 484 | #define RFLR_DIOMAPPING1_DIO2_10 0x08 |
| GregCr | 0:e6ceb13d2d05 | 485 | #define RFLR_DIOMAPPING1_DIO2_11 0x0C |
| GregCr | 0:e6ceb13d2d05 | 486 | |
| GregCr | 0:e6ceb13d2d05 | 487 | #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC |
| GregCr | 0:e6ceb13d2d05 | 488 | #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 489 | #define RFLR_DIOMAPPING1_DIO3_01 0x01 |
| GregCr | 0:e6ceb13d2d05 | 490 | #define RFLR_DIOMAPPING1_DIO3_10 0x02 |
| GregCr | 0:e6ceb13d2d05 | 491 | #define RFLR_DIOMAPPING1_DIO3_11 0x03 |
| GregCr | 0:e6ceb13d2d05 | 492 | |
| GregCr | 0:e6ceb13d2d05 | 493 | /*! |
| GregCr | 0:e6ceb13d2d05 | 494 | * RegDioMapping2 |
| GregCr | 0:e6ceb13d2d05 | 495 | */ |
| GregCr | 0:e6ceb13d2d05 | 496 | #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F |
| GregCr | 0:e6ceb13d2d05 | 497 | #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 498 | #define RFLR_DIOMAPPING2_DIO4_01 0x40 |
| GregCr | 0:e6ceb13d2d05 | 499 | #define RFLR_DIOMAPPING2_DIO4_10 0x80 |
| GregCr | 0:e6ceb13d2d05 | 500 | #define RFLR_DIOMAPPING2_DIO4_11 0xC0 |
| GregCr | 0:e6ceb13d2d05 | 501 | |
| GregCr | 0:e6ceb13d2d05 | 502 | #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF |
| GregCr | 0:e6ceb13d2d05 | 503 | #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 504 | #define RFLR_DIOMAPPING2_DIO5_01 0x10 |
| GregCr | 0:e6ceb13d2d05 | 505 | #define RFLR_DIOMAPPING2_DIO5_10 0x20 |
| GregCr | 0:e6ceb13d2d05 | 506 | #define RFLR_DIOMAPPING2_DIO5_11 0x30 |
| GregCr | 0:e6ceb13d2d05 | 507 | |
| GregCr | 0:e6ceb13d2d05 | 508 | #define RFLR_DIOMAPPING2_MAP_MASK 0xFE |
| GregCr | 0:e6ceb13d2d05 | 509 | #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 |
| GregCr | 0:e6ceb13d2d05 | 510 | #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 511 | |
| GregCr | 0:e6ceb13d2d05 | 512 | /*! |
| mluis | 22:7f3aab69cca9 | 513 | * RegVersion (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 514 | */ |
| GregCr | 0:e6ceb13d2d05 | 515 | |
| GregCr | 0:e6ceb13d2d05 | 516 | /*! |
| GregCr | 0:e6ceb13d2d05 | 517 | * RegPllHop |
| GregCr | 0:e6ceb13d2d05 | 518 | */ |
| GregCr | 0:e6ceb13d2d05 | 519 | #define RFLR_PLLHOP_FASTHOP_MASK 0x7F |
| GregCr | 0:e6ceb13d2d05 | 520 | #define RFLR_PLLHOP_FASTHOP_ON 0x80 |
| GregCr | 0:e6ceb13d2d05 | 521 | #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 522 | |
| GregCr | 0:e6ceb13d2d05 | 523 | /*! |
| GregCr | 0:e6ceb13d2d05 | 524 | * RegTcxo |
| GregCr | 0:e6ceb13d2d05 | 525 | */ |
| GregCr | 0:e6ceb13d2d05 | 526 | #define RFLR_TCXO_TCXOINPUT_MASK 0xEF |
| GregCr | 0:e6ceb13d2d05 | 527 | #define RFLR_TCXO_TCXOINPUT_ON 0x10 |
| GregCr | 0:e6ceb13d2d05 | 528 | #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 529 | |
| GregCr | 0:e6ceb13d2d05 | 530 | /*! |
| GregCr | 0:e6ceb13d2d05 | 531 | * RegPaDac |
| GregCr | 0:e6ceb13d2d05 | 532 | */ |
| GregCr | 0:e6ceb13d2d05 | 533 | #define RFLR_PADAC_20DBM_MASK 0xF8 |
| GregCr | 0:e6ceb13d2d05 | 534 | #define RFLR_PADAC_20DBM_ON 0x07 |
| GregCr | 0:e6ceb13d2d05 | 535 | #define RFLR_PADAC_20DBM_OFF 0x04 // Default |
| GregCr | 0:e6ceb13d2d05 | 536 | |
| GregCr | 0:e6ceb13d2d05 | 537 | /*! |
| GregCr | 0:e6ceb13d2d05 | 538 | * RegFormerTemp |
| GregCr | 0:e6ceb13d2d05 | 539 | */ |
| GregCr | 0:e6ceb13d2d05 | 540 | |
| GregCr | 0:e6ceb13d2d05 | 541 | /*! |
| GregCr | 0:e6ceb13d2d05 | 542 | * RegBitrateFrac |
| GregCr | 0:e6ceb13d2d05 | 543 | */ |
| GregCr | 0:e6ceb13d2d05 | 544 | #define RF_BITRATEFRAC_MASK 0xF0 |
| GregCr | 0:e6ceb13d2d05 | 545 | |
| GregCr | 0:e6ceb13d2d05 | 546 | /*! |
| GregCr | 0:e6ceb13d2d05 | 547 | * RegAgcRef |
| GregCr | 0:e6ceb13d2d05 | 548 | */ |
| GregCr | 0:e6ceb13d2d05 | 549 | |
| GregCr | 0:e6ceb13d2d05 | 550 | /*! |
| GregCr | 0:e6ceb13d2d05 | 551 | * RegAgcThresh1 |
| GregCr | 0:e6ceb13d2d05 | 552 | */ |
| GregCr | 0:e6ceb13d2d05 | 553 | |
| GregCr | 0:e6ceb13d2d05 | 554 | /*! |
| GregCr | 0:e6ceb13d2d05 | 555 | * RegAgcThresh2 |
| GregCr | 0:e6ceb13d2d05 | 556 | */ |
| GregCr | 0:e6ceb13d2d05 | 557 | |
| GregCr | 0:e6ceb13d2d05 | 558 | /*! |
| GregCr | 0:e6ceb13d2d05 | 559 | * RegAgcThresh3 |
| GregCr | 0:e6ceb13d2d05 | 560 | */ |
| GregCr | 0:e6ceb13d2d05 | 561 | |
| GregCr | 0:e6ceb13d2d05 | 562 | /*! |
| GregCr | 0:e6ceb13d2d05 | 563 | * RegPll |
| GregCr | 0:e6ceb13d2d05 | 564 | */ |
| GregCr | 0:e6ceb13d2d05 | 565 | #define RF_PLL_BANDWIDTH_MASK 0x3F |
| GregCr | 0:e6ceb13d2d05 | 566 | #define RF_PLL_BANDWIDTH_75 0x00 |
| GregCr | 0:e6ceb13d2d05 | 567 | #define RF_PLL_BANDWIDTH_150 0x40 |
| GregCr | 0:e6ceb13d2d05 | 568 | #define RF_PLL_BANDWIDTH_225 0x80 |
| GregCr | 0:e6ceb13d2d05 | 569 | #define RF_PLL_BANDWIDTH_300 0xC0 // Default |
| GregCr | 0:e6ceb13d2d05 | 570 | |
| GregCr | 0:e6ceb13d2d05 | 571 | #endif // __SX1276_REGS_LORA_H__ |
