kris gjika / Mbed 2 deprecated Si4703

Si4703 sample code ECE 4180 Georgia Tech

Dependencies:   TextLCD mbed

Fork of Si4735 by Brett Wilson

parkFun-Si4703.cpp@1:563a11fe39e0, 2015-10-20 (annotated)

Committer:
Gjika
Date:
Tue Oct 20 14:58:05 2015 +0000
Revision:
1:563a11fe39e0
Sample Code for Si4703 Digital FM Radio Receiver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Gjika 1:563a11fe39e0 1 #include "mbed.h"
Gjika 1:563a11fe39e0 2 #include "SparkFun-Si4703.h"
Gjika 1:563a11fe39e0 3
Gjika 1:563a11fe39e0 4 Si4703_Breakout::Si4703_Breakout(PinName sdioPin, PinName sclkPin, PinName resetPin, Serial *pc)
Gjika 1:563a11fe39e0 5 {
Gjika 1:563a11fe39e0 6 _resetPin = resetPin;
Gjika 1:563a11fe39e0 7 _sdioPin = sdioPin;
Gjika 1:563a11fe39e0 8 _sclkPin = sclkPin;
Gjika 1:563a11fe39e0 9
Gjika 1:563a11fe39e0 10 this->pc = pc;
Gjika 1:563a11fe39e0 11 }
Gjika 1:563a11fe39e0 12
Gjika 1:563a11fe39e0 13 void Si4703_Breakout::powerOn()
Gjika 1:563a11fe39e0 14 {
Gjika 1:563a11fe39e0 15 si4703_init();
Gjika 1:563a11fe39e0 16 }
Gjika 1:563a11fe39e0 17
Gjika 1:563a11fe39e0 18 void Si4703_Breakout::powerOff()
Gjika 1:563a11fe39e0 19 {
Gjika 1:563a11fe39e0 20 // a Minimal Power-Down Sequence - According To SI AN230 (rev. 0.9), p.13 - Table 4
Gjika 1:563a11fe39e0 21
Gjika 1:563a11fe39e0 22 readRegisters();
Gjika 1:563a11fe39e0 23
Gjika 1:563a11fe39e0 24 si4703_registers[POWERCFG] &= ~(1<<DMUTE); // 'Enable Mute'
Gjika 1:563a11fe39e0 25 si4703_registers[POWERCFG] |= (1<<ENABLE); // 'Enable IC'
Gjika 1:563a11fe39e0 26 si4703_registers[POWERCFG] |= (1<<DISABLE); // & 'Disable IC'
Gjika 1:563a11fe39e0 27 // To Init. Power-Down Sequence
Gjika 1:563a11fe39e0 28
Gjika 1:563a11fe39e0 29 updateRegisters();
Gjika 1:563a11fe39e0 30 // Notice : This Does NOT Perform a Reset of The IC.
Gjika 1:563a11fe39e0 31 }
Gjika 1:563a11fe39e0 32
Gjika 1:563a11fe39e0 33 void Si4703_Breakout::setChannel(int channel)
Gjika 1:563a11fe39e0 34 {
Gjika 1:563a11fe39e0 35 uint8_t ack;
Gjika 1:563a11fe39e0 36 //Freq(MHz) = 0.1 (in Europe) * Channel + 87.5MHz
Gjika 1:563a11fe39e0 37 //97.3 = 0.1 * Chan + 87.5
Gjika 1:563a11fe39e0 38 //9.8 / 0.1 = 98
Gjika 1:563a11fe39e0 39 int newChannel = channel * 10; //973 * 10 = 9730
Gjika 1:563a11fe39e0 40 newChannel -= 8750; //9730 - 8750 = 980
Gjika 1:563a11fe39e0 41 newChannel /= 10; //980 / 10 = 98
Gjika 1:563a11fe39e0 42
Gjika 1:563a11fe39e0 43 //These steps come from AN230 page 20 rev 0.5
Gjika 1:563a11fe39e0 44 readRegisters();
Gjika 1:563a11fe39e0 45 si4703_registers[CHANNEL] &= 0xFE00; //Clear out the channel bits
Gjika 1:563a11fe39e0 46 si4703_registers[CHANNEL] |= newChannel; //Mask in the new channel
Gjika 1:563a11fe39e0 47 si4703_registers[CHANNEL] |= (1<<TUNE); //Set the TUNE bit to start
Gjika 1:563a11fe39e0 48 updateRegisters();
Gjika 1:563a11fe39e0 49
Gjika 1:563a11fe39e0 50 wait_ms(60); //Wait 60ms - you can use or skip this delay
Gjika 1:563a11fe39e0 51
Gjika 1:563a11fe39e0 52 //Poll to see if STC is set
Gjika 1:563a11fe39e0 53 while(1) {
Gjika 1:563a11fe39e0 54 ack = readRegisters();
Gjika 1:563a11fe39e0 55 wait_ms(1); // Just In Case...
Gjika 1:563a11fe39e0 56 if (( (si4703_registers[STATUSRSSI] & (1<<STC)) != 0) || (ack != SUCCESS)) break; //Tuning complete! (or FAILED)
Gjika 1:563a11fe39e0 57 }
Gjika 1:563a11fe39e0 58
Gjika 1:563a11fe39e0 59 readRegisters();
Gjika 1:563a11fe39e0 60 si4703_registers[CHANNEL] &= ~(1<<TUNE); //Clear the tune after a tune has completed
Gjika 1:563a11fe39e0 61 updateRegisters();
Gjika 1:563a11fe39e0 62
Gjika 1:563a11fe39e0 63 //Wait for the si4703 to clear the STC as well
Gjika 1:563a11fe39e0 64 while(1) {
Gjika 1:563a11fe39e0 65 ack = readRegisters();
Gjika 1:563a11fe39e0 66 wait_ms(1); // Just In Case...
Gjika 1:563a11fe39e0 67 if (( (si4703_registers[STATUSRSSI] & (1<<STC)) == 0) || (ack != SUCCESS)) break; //Tuning complete! (or FAILED)
Gjika 1:563a11fe39e0 68 }
Gjika 1:563a11fe39e0 69 }
Gjika 1:563a11fe39e0 70
Gjika 1:563a11fe39e0 71 int Si4703_Breakout::seekUp()
Gjika 1:563a11fe39e0 72 {
Gjika 1:563a11fe39e0 73 return seek(SEEK_UP);
Gjika 1:563a11fe39e0 74 }
Gjika 1:563a11fe39e0 75
Gjika 1:563a11fe39e0 76 int Si4703_Breakout::seekDown()
Gjika 1:563a11fe39e0 77 {
Gjika 1:563a11fe39e0 78 return seek(SEEK_DOWN);
Gjika 1:563a11fe39e0 79 }
Gjika 1:563a11fe39e0 80
Gjika 1:563a11fe39e0 81 void Si4703_Breakout::setVolume(int volume)
Gjika 1:563a11fe39e0 82 {
Gjika 1:563a11fe39e0 83 readRegisters(); //Read the current register set
Gjika 1:563a11fe39e0 84 if(volume < 0) volume = 0;
Gjika 1:563a11fe39e0 85 if (volume > 15) volume = 15;
Gjika 1:563a11fe39e0 86 si4703_registers[SYSCONFIG2] &= 0xFFF0; //Clear volume bits
Gjika 1:563a11fe39e0 87 si4703_registers[SYSCONFIG2] |= volume; //Set new volume
Gjika 1:563a11fe39e0 88 updateRegisters(); //Update
Gjika 1:563a11fe39e0 89 }
Gjika 1:563a11fe39e0 90
Gjika 1:563a11fe39e0 91 uint8_t Si4703_Breakout::getVolume()
Gjika 1:563a11fe39e0 92 {
Gjika 1:563a11fe39e0 93 readRegisters(); //Read the current register set
Gjika 1:563a11fe39e0 94
Gjika 1:563a11fe39e0 95 return (si4703_registers[SYSCONFIG2] & 0x000F);
Gjika 1:563a11fe39e0 96 }
Gjika 1:563a11fe39e0 97
Gjika 1:563a11fe39e0 98 /*
Gjika 1:563a11fe39e0 99 void Si4703_Breakout::readRDS(char* buffer, long timeout)
Gjika 1:563a11fe39e0 100 {
Gjika 1:563a11fe39e0 101 long endTime = millis() + timeout;
Gjika 1:563a11fe39e0 102 boolean completed[] = {false, false, false, false};
Gjika 1:563a11fe39e0 103 int completedCount = 0;
Gjika 1:563a11fe39e0 104 while(completedCount < 4 && millis() < endTime) {
Gjika 1:563a11fe39e0 105 readRegisters();
Gjika 1:563a11fe39e0 106 if(si4703_registers[STATUSRSSI] & (1<<RDSR)){
Gjika 1:563a11fe39e0 107 // ls 2 bits of B determine the 4 letter pairs
Gjika 1:563a11fe39e0 108 // once we have a full set return
Gjika 1:563a11fe39e0 109 // if you get nothing after 20 readings return with empty string
Gjika 1:563a11fe39e0 110 uint16_t b = si4703_registers[RDSB];
Gjika 1:563a11fe39e0 111 int index = b & 0x03;
Gjika 1:563a11fe39e0 112 if (! completed[index] && b < 500)
Gjika 1:563a11fe39e0 113 {
Gjika 1:563a11fe39e0 114 completed[index] = true;
Gjika 1:563a11fe39e0 115 completedCount ++;
Gjika 1:563a11fe39e0 116 char Dh = (si4703_registers[RDSD] & 0xFF00) >> 8;
Gjika 1:563a11fe39e0 117 char Dl = (si4703_registers[RDSD] & 0x00FF);
Gjika 1:563a11fe39e0 118 buffer[index * 2] = Dh;
Gjika 1:563a11fe39e0 119 buffer[index * 2 +1] = Dl;
Gjika 1:563a11fe39e0 120 // Serial.print(si4703_registers[RDSD]); Serial.print(" ");
Gjika 1:563a11fe39e0 121 // Serial.print(index);Serial.print(" ");
Gjika 1:563a11fe39e0 122 // Serial.write(Dh);
Gjika 1:563a11fe39e0 123 // Serial.write(Dl);
Gjika 1:563a11fe39e0 124 // Serial.println();
Gjika 1:563a11fe39e0 125 }
Gjika 1:563a11fe39e0 126 delay(40); //Wait for the RDS bit to clear
Gjika 1:563a11fe39e0 127 }
Gjika 1:563a11fe39e0 128 else {
Gjika 1:563a11fe39e0 129 delay(30); //From AN230, using the polling method 40ms should be sufficient amount of time between checks
Gjika 1:563a11fe39e0 130 }
Gjika 1:563a11fe39e0 131 }
Gjika 1:563a11fe39e0 132 if (millis() >= endTime) {
Gjika 1:563a11fe39e0 133 buffer[0] ='\0';
Gjika 1:563a11fe39e0 134 return;
Gjika 1:563a11fe39e0 135 }
Gjika 1:563a11fe39e0 136
Gjika 1:563a11fe39e0 137 buffer[8] = '\0';
Gjika 1:563a11fe39e0 138 }
Gjika 1:563a11fe39e0 139 */
Gjika 1:563a11fe39e0 140
Gjika 1:563a11fe39e0 141
Gjika 1:563a11fe39e0 142
Gjika 1:563a11fe39e0 143 //To get the Si4703 inito 2-wire mode, SEN needs to be high and SDIO needs to be low after a reset
Gjika 1:563a11fe39e0 144 //The breakout board has SEN pulled high, but also has SDIO pulled high. Therefore, after a normal power up
Gjika 1:563a11fe39e0 145 //The Si4703 will be in an unknown state. RST must be controlled
Gjika 1:563a11fe39e0 146 void Si4703_Breakout::si4703_init()
Gjika 1:563a11fe39e0 147 {
Gjika 1:563a11fe39e0 148 _reset_ = new DigitalOut(_resetPin);
Gjika 1:563a11fe39e0 149 _sdio_ = new DigitalOut(_sdioPin);
Gjika 1:563a11fe39e0 150
Gjika 1:563a11fe39e0 151 _sdio_->write(0); //A low SDIO indicates a 2-wire interface
Gjika 1:563a11fe39e0 152 _reset_->write(0); //Put Si4703 into reset
Gjika 1:563a11fe39e0 153 wait_ms(1); //Some delays while we allow pins to settle
Gjika 1:563a11fe39e0 154 _reset_->write(1); //Bring Si4703 out of reset with SDIO set to low and SEN pulled high with on-board resistor
Gjika 1:563a11fe39e0 155 wait_ms(1); //Allow Si4703 to come out of reset
Gjika 1:563a11fe39e0 156
Gjika 1:563a11fe39e0 157 //Now that the unit is reset and I2C inteface mode, we need to begin I2C
Gjika 1:563a11fe39e0 158 i2c_ = new I2C(_sdioPin, _sclkPin);
Gjika 1:563a11fe39e0 159 i2c_->frequency(100000);
Gjika 1:563a11fe39e0 160 ///
Gjika 1:563a11fe39e0 161
Gjika 1:563a11fe39e0 162 readRegisters(); //Read the current register set
Gjika 1:563a11fe39e0 163 si4703_registers[0x07] = 0x8100; //Enable the oscillator, from AN230 page 9, rev 0.61 (works)
Gjika 1:563a11fe39e0 164 updateRegisters(); //Update
Gjika 1:563a11fe39e0 165
Gjika 1:563a11fe39e0 166 wait_ms(500); //Wait for clock to settle - from AN230 page 9
Gjika 1:563a11fe39e0 167
Gjika 1:563a11fe39e0 168 readRegisters(); //Read the current register set
Gjika 1:563a11fe39e0 169 si4703_registers[POWERCFG] = 0x4001; //Enable the IC
Gjika 1:563a11fe39e0 170 // si4703_registers[POWERCFG] |= (1<<SMUTE) | (1<<DMUTE); //Disable Mute, disable softmute
Gjika 1:563a11fe39e0 171 si4703_registers[SYSCONFIG1] |= (1<<RDS); //Enable RDS
Gjika 1:563a11fe39e0 172
Gjika 1:563a11fe39e0 173 si4703_registers[SYSCONFIG1] |= (1<<DE); //50μS Europe setup
Gjika 1:563a11fe39e0 174 si4703_registers[SYSCONFIG2] |= (1<<SPACE0); //100kHz channel spacing for Europe
Gjika 1:563a11fe39e0 175
Gjika 1:563a11fe39e0 176 si4703_registers[SYSCONFIG2] &= 0xFFF0; //Clear volume bits
Gjika 1:563a11fe39e0 177 si4703_registers[SYSCONFIG2] |= 0x0001; //Set volume to lowest
Gjika 1:563a11fe39e0 178
Gjika 1:563a11fe39e0 179 // SI AN230 page 40 - Table 23 ('Good Quality Stations Only' Settings)
Gjika 1:563a11fe39e0 180 si4703_registers[SYSCONFIG2] |= (0xC<<SEEKTH);
Gjika 1:563a11fe39e0 181 si4703_registers[SYSCONFIG3] |= (0x7<<SKSNR);
Gjika 1:563a11fe39e0 182 si4703_registers[SYSCONFIG3] |= (0xF<<SKCNT);
Gjika 1:563a11fe39e0 183 ///
Gjika 1:563a11fe39e0 184 updateRegisters(); //Update
Gjika 1:563a11fe39e0 185
Gjika 1:563a11fe39e0 186 wait_ms(110); //Max powerup time, from datasheet page 13
Gjika 1:563a11fe39e0 187
Gjika 1:563a11fe39e0 188 }
Gjika 1:563a11fe39e0 189
Gjika 1:563a11fe39e0 190 //Read the entire register control set from 0x00 to 0x0F
Gjika 1:563a11fe39e0 191 uint8_t Si4703_Breakout::readRegisters(){
Gjika 1:563a11fe39e0 192
Gjika 1:563a11fe39e0 193 //Si4703 begins reading from register upper register of 0x0A and reads to 0x0F, then loops to 0x00.
Gjika 1:563a11fe39e0 194 // Wire.requestFrom(SI4703, 32); //We want to read the entire register set from 0x0A to 0x09 = 32 uint8_ts.
Gjika 1:563a11fe39e0 195 char data[32];
Gjika 1:563a11fe39e0 196 uint8_t ack = i2c_->read(SI4703, data, 32); //Read in these 32 uint8_ts
Gjika 1:563a11fe39e0 197
Gjika 1:563a11fe39e0 198 if (ack != 0) { //We have a problem!
Gjika 1:563a11fe39e0 199 return(FAIL);
Gjika 1:563a11fe39e0 200 }
Gjika 1:563a11fe39e0 201
Gjika 1:563a11fe39e0 202 //Remember, register 0x0A comes in first so we have to shuffle the array around a bit
Gjika 1:563a11fe39e0 203 for (int y=0; y<6; y++)
Gjika 1:563a11fe39e0 204 {
Gjika 1:563a11fe39e0 205 si4703_registers[0x0A+y] = 0;
Gjika 1:563a11fe39e0 206 si4703_registers[0x0A+y] = data[(y*2)+1];
Gjika 1:563a11fe39e0 207 si4703_registers[0x0A+y] |= (data[(y*2)] << 8);
Gjika 1:563a11fe39e0 208 }
Gjika 1:563a11fe39e0 209
Gjika 1:563a11fe39e0 210 for (int y=0; y<10; y++)
Gjika 1:563a11fe39e0 211 {
Gjika 1:563a11fe39e0 212 si4703_registers[y] = 0;
Gjika 1:563a11fe39e0 213 si4703_registers[y] = data[(12)+(y*2)+1];
Gjika 1:563a11fe39e0 214 si4703_registers[y] |= (data[(12)+(y*2)] << 8);
Gjika 1:563a11fe39e0 215 }
Gjika 1:563a11fe39e0 216 //We're done!
Gjika 1:563a11fe39e0 217 ///
Gjika 1:563a11fe39e0 218 return(SUCCESS);
Gjika 1:563a11fe39e0 219 }
Gjika 1:563a11fe39e0 220
Gjika 1:563a11fe39e0 221 //Write the current 9 control registers (0x02 to 0x07) to the Si4703
Gjika 1:563a11fe39e0 222 //It's a little weird, you don't write an I2C address
Gjika 1:563a11fe39e0 223 //The Si4703 assumes you are writing to 0x02 first, then increments
Gjika 1:563a11fe39e0 224 uint8_t Si4703_Breakout::updateRegisters() {
Gjika 1:563a11fe39e0 225
Gjika 1:563a11fe39e0 226 char data[12];
Gjika 1:563a11fe39e0 227
Gjika 1:563a11fe39e0 228 //First we send the 0x02 to 0x07 control registers
Gjika 1:563a11fe39e0 229 //In general, we should not write to registers 0x08 and 0x09
Gjika 1:563a11fe39e0 230 for(int regSpot = 0x02 ; regSpot < 0x08 ; regSpot++) {
Gjika 1:563a11fe39e0 231 data[(regSpot-2)*2] = si4703_registers[regSpot] >> 8;
Gjika 1:563a11fe39e0 232 data[((regSpot-2)*2)+1] = si4703_registers[regSpot] & 0x00FF;
Gjika 1:563a11fe39e0 233 }
Gjika 1:563a11fe39e0 234
Gjika 1:563a11fe39e0 235 uint8_t ack = i2c_->write(SI4703, data, 12); // a write command automatically begins with register 0x02 so no need to send a write-to address
Gjika 1:563a11fe39e0 236
Gjika 1:563a11fe39e0 237 if(ack != 0) { //We have a problem!
Gjika 1:563a11fe39e0 238 return(FAIL);
Gjika 1:563a11fe39e0 239 }
Gjika 1:563a11fe39e0 240
Gjika 1:563a11fe39e0 241 return(SUCCESS);
Gjika 1:563a11fe39e0 242 }
Gjika 1:563a11fe39e0 243
Gjika 1:563a11fe39e0 244 //Returns The Value of a Register
Gjika 1:563a11fe39e0 245 uint16_t Si4703_Breakout::getRegister(uint8_t regNum)
Gjika 1:563a11fe39e0 246 {
Gjika 1:563a11fe39e0 247 readRegisters();
Gjika 1:563a11fe39e0 248 return si4703_registers[regNum];
Gjika 1:563a11fe39e0 249 // No Error Status Checking
Gjika 1:563a11fe39e0 250 }
Gjika 1:563a11fe39e0 251
Gjika 1:563a11fe39e0 252 //Seeks out the next available station
Gjika 1:563a11fe39e0 253 //Returns the freq if it made it
Gjika 1:563a11fe39e0 254 //Returns zero if failed
Gjika 1:563a11fe39e0 255 int Si4703_Breakout::seek(bool seekDirection){
Gjika 1:563a11fe39e0 256 uint8_t ack;
Gjika 1:563a11fe39e0 257 readRegisters();
Gjika 1:563a11fe39e0 258 //Set seek mode wrap bit
Gjika 1:563a11fe39e0 259 si4703_registers[POWERCFG] |= (1<<SKMODE); //Disallow wrap - if you disallow wrap, you may want to tune to 87.5 first
Gjika 1:563a11fe39e0 260 //si4703_registers[POWERCFG] &= ~(1<<SKMODE); //Allow wrap
Gjika 1:563a11fe39e0 261 if(seekDirection == SEEK_DOWN) si4703_registers[POWERCFG] &= ~(1<<SEEKUP); //Seek down is the default upon reset
Gjika 1:563a11fe39e0 262 else si4703_registers[POWERCFG] |= 1<<SEEKUP; //Set the bit to seek up
Gjika 1:563a11fe39e0 263
Gjika 1:563a11fe39e0 264 si4703_registers[POWERCFG] |= (1<<SEEK); //Start seek
Gjika 1:563a11fe39e0 265 updateRegisters(); //Seeking will now start
Gjika 1:563a11fe39e0 266
Gjika 1:563a11fe39e0 267 //Poll to see if STC is set
Gjika 1:563a11fe39e0 268 while(1) {
Gjika 1:563a11fe39e0 269 ack = readRegisters();
Gjika 1:563a11fe39e0 270 wait_ms(1); // Just In Case...
Gjika 1:563a11fe39e0 271 if (((si4703_registers[STATUSRSSI] & (1<<STC)) != 0) || (ack != SUCCESS)) break; //Tuning complete! (or FAILED)
Gjika 1:563a11fe39e0 272 }
Gjika 1:563a11fe39e0 273
Gjika 1:563a11fe39e0 274 readRegisters();
Gjika 1:563a11fe39e0 275 int valueSFBL = si4703_registers[STATUSRSSI] & (1<<SFBL); //Store the value of SFBL
Gjika 1:563a11fe39e0 276 si4703_registers[POWERCFG] &= ~(1<<SEEK); //Clear the seek bit after seek has completed
Gjika 1:563a11fe39e0 277 updateRegisters();
Gjika 1:563a11fe39e0 278
Gjika 1:563a11fe39e0 279 //Wait for the si4703 to clear the STC as well
Gjika 1:563a11fe39e0 280 while(1) {
Gjika 1:563a11fe39e0 281 ack = readRegisters();
Gjika 1:563a11fe39e0 282 wait_ms(1); // Just In Case...
Gjika 1:563a11fe39e0 283 if (((si4703_registers[STATUSRSSI] & (1<<STC)) == 0) || (ack != SUCCESS)) break; //Tuning complete! (or FAILED)
Gjika 1:563a11fe39e0 284 }
Gjika 1:563a11fe39e0 285
Gjika 1:563a11fe39e0 286 if(valueSFBL) { //The bit was set indicating we hit a band limit or failed to find a station
Gjika 1:563a11fe39e0 287 return(0);
Gjika 1:563a11fe39e0 288 }
Gjika 1:563a11fe39e0 289 return getChannel();
Gjika 1:563a11fe39e0 290 }
Gjika 1:563a11fe39e0 291
Gjika 1:563a11fe39e0 292 //Reads the current channel from READCHAN
Gjika 1:563a11fe39e0 293 //Returns a number like 973 for 97.3MHz
Gjika 1:563a11fe39e0 294 int Si4703_Breakout::getChannel() {
Gjika 1:563a11fe39e0 295 readRegisters();
Gjika 1:563a11fe39e0 296 int channel = (si4703_registers[READCHAN] & 0x03FF); //Mask out everything but the lower 10 bits
Gjika 1:563a11fe39e0 297 //Freq(MHz) = 0.100(in Europe) * Channel + 87.5MHz
Gjika 1:563a11fe39e0 298 //X = 0.1 * Chan + 87.5
Gjika 1:563a11fe39e0 299 channel += 875; //98 + 875 = 973 ( for 97.3 MHz )
Gjika 1:563a11fe39e0 300 return(channel);
Gjika 1:563a11fe39e0 301 }
Gjika 1:563a11fe39e0 302
Gjika 1:563a11fe39e0 303 void Si4703_Breakout::printRegs() {
Gjika 1:563a11fe39e0 304 readRegisters();
Gjika 1:563a11fe39e0 305 for (int x=0; x<16; x++) { pc->printf("Reg# 0x%X = 0x%X\r\n",x,si4703_registers[x]); wait_ms(1); }
Gjika 1:563a11fe39e0 306 }