Hal Drivers for L4
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stm32l4xx_ll_fmc.c File Reference
FMC Low Layer HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible Memory Controller (FMC) peripheral memories: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions. More...
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Functions | |
HAL_StatusTypeDef | FMC_NORSRAM_Init (FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init) |
Initialize the FMC_NORSRAM device according to the specified control parameters in the FMC_NORSRAM_InitTypeDef. | |
HAL_StatusTypeDef | FMC_NORSRAM_DeInit (FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
DeInitialize the FMC_NORSRAM peripheral. | |
HAL_StatusTypeDef | FMC_NORSRAM_Timing_Init (FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
Initialize the FMC_NORSRAM Timing according to the specified parameters in the FMC_NORSRAM_TimingTypeDef. | |
HAL_StatusTypeDef | FMC_NORSRAM_Extended_Timing_Init (FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
Initialize the FMC_NORSRAM Extended mode Timing according to the specified parameters in the FMC_NORSRAM_TimingTypeDef. | |
HAL_StatusTypeDef | FMC_NORSRAM_WriteOperation_Enable (FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
Enables dynamically FMC_NORSRAM write operation. | |
HAL_StatusTypeDef | FMC_NORSRAM_WriteOperation_Disable (FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
Disables dynamically FMC_NORSRAM write operation. | |
HAL_StatusTypeDef | FMC_NAND_Init (FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
Initializes the FMC_NAND device according to the specified control parameters in the FMC_NAND_HandleTypeDef. | |
HAL_StatusTypeDef | FMC_NAND_CommonSpace_Timing_Init (FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
Initializes the FMC_NAND Common space Timing according to the specified parameters in the FMC_NAND_PCC_TimingTypeDef. | |
HAL_StatusTypeDef | FMC_NAND_AttributeSpace_Timing_Init (FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
Initializes the FMC_NAND Attribute space Timing according to the specified parameters in the FMC_NAND_PCC_TimingTypeDef. | |
HAL_StatusTypeDef | FMC_NAND_DeInit (FMC_NAND_TypeDef *Device, uint32_t Bank) |
DeInitialize the FMC_NAND device. | |
HAL_StatusTypeDef | FMC_NAND_ECC_Enable (FMC_NAND_TypeDef *Device, uint32_t Bank) |
Enables dynamically FMC_NAND ECC feature. | |
HAL_StatusTypeDef | FMC_NAND_ECC_Disable (FMC_NAND_TypeDef *Device, uint32_t Bank) |
Disables dynamically FMC_NAND ECC feature. | |
HAL_StatusTypeDef | FMC_NAND_GetECC (FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
Disables dynamically FMC_NAND ECC feature. |
Detailed Description
FMC Low Layer HAL module driver. This file provides firmware functions to manage the following functionalities of the Flexible Memory Controller (FMC) peripheral memories: + Initialization/de-initialization functions + Peripheral Control functions + Peripheral State functions.
- Version:
- V1.1.0
- Date:
- 16-September-2015
============================================================================== ##### FMC peripheral features ##### ============================================================================== [..] The Flexible memory controller (FMC) includes following memory controllers: (+) The NOR/PSRAM memory controller (+) The NAND memory controller [..] The FMC functional block makes the interface with synchronous and asynchronous static memories and 16-bit PC memory cards. Its main purposes are: (+) to translate AHB transactions into the appropriate external device protocol. (+) to meet the access time requirements of the external memory devices. [..] All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique Chip Select. The FMC performs only one access at a time to an external device. The main features of the FMC controller are the following: (+) Interface with static-memory mapped devices including: (++) Static random access memory (SRAM). (++) NOR Flash memory. (++) PSRAM (4 memory banks). (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of data (+) Independent Chip Select control for each memory bank (+) Independent configuration for each memory bank
- Attention:
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Definition in file stm32l4xx_ll_fmc.c.
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