Configuration of ADC hierarchical scope: group regular
[ADC Exported Functions]

Get ADC continuous conversion mode on ADC group regular: whether ADC conversions are performed: * single mode: one conversion per trigger * continuous mode: after the first trigger, following conversions launched successively automatically.

CFGR CONT LL_ADC_REG_GetContinuousMode

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_CONV_SINGLE LL_ADC_REG_CONV_CONTINUOUS

Definition at line 2681 of file stm32l4xx_ll_adc.h.

Get ADC group regular conversion data transfer: no transfer or transfer by DMA.

If transfer by DMA selected, specifies the DMA requests mode: * Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. * Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

Note:

If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).

For devices with several ADC instances: ADC multimode DMA settings are available using function LL_ADC_GetMultiDMATransfer().

To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr(). CFGR DMAEN LL_ADC_REG_GetDMATransfer
CFGR DMACFG LL_ADC_REG_GetDMATransfer

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_DMA_TRANSFER_NONE LL_ADC_REG_DMA_TRANSFER_LIMITED LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Definition at line 2754 of file stm32l4xx_ll_adc.h.

Get ADC group regular behaviour in case of overrun: data preserved or overwritten.

CFGR OVRMOD LL_ADC_REG_GetOverrun

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_OVR_DATA_PRESERVED LL_ADC_REG_OVR_DATA_OVERWRITTEN

Definition at line 2793 of file stm32l4xx_ll_adc.h.

Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

CFGR DISCEN LL_ADC_REG_GetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_SEQ_DISCONT_DISABLE LL_ADC_REG_SEQ_DISCONT_1RANK LL_ADC_REG_SEQ_DISCONT_2RANKS LL_ADC_REG_SEQ_DISCONT_3RANKS LL_ADC_REG_SEQ_DISCONT_4RANKS LL_ADC_REG_SEQ_DISCONT_5RANKS LL_ADC_REG_SEQ_DISCONT_6RANKS LL_ADC_REG_SEQ_DISCONT_7RANKS LL_ADC_REG_SEQ_DISCONT_8RANKS

Definition at line 2959 of file stm32l4xx_ll_adc.h.

Get ADC group regular sequencer length and scan direction.

* For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs:

• Sequence length: Set number of ranks in the scan sequence.
• Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()". * For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs:
• Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
• Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".

  Note:

  Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel. SQR1 L LL_ADC_REG_GetSequencerLength

  Parameters:

  ADCx	ADC instance

  Return values:

  Returned

  value can be one of the following values: LL_ADC_REG_SEQ_SCAN_DISABLE LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Definition at line 2904 of file stm32l4xx_ll_adc.h.

Get ADC group regular sequence: channel on the selected scan sequence rank.

Note:

On this STM32 family, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().

Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.

Usage of the returned channel number:

• To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with literals LL_ADC_CHANNEL_x, then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
• To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). SQR1 SQ1 LL_ADC_REG_GetSequencerRanks
  SQR1 SQ2 LL_ADC_REG_GetSequencerRanks
  SQR1 SQ3 LL_ADC_REG_GetSequencerRanks
  SQR1 SQ4 LL_ADC_REG_GetSequencerRanks
  SQR2 SQ5 LL_ADC_REG_GetSequencerRanks
  SQR2 SQ6 LL_ADC_REG_GetSequencerRanks
  SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
  SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
  SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
  SQR3 SQ10 LL_ADC_REG_GetSequencerRanks
  SQR3 SQ11 LL_ADC_REG_GetSequencerRanks
  SQR3 SQ12 LL_ADC_REG_GetSequencerRanks
  SQR3 SQ13 LL_ADC_REG_GetSequencerRanks
  SQR3 SQ14 LL_ADC_REG_GetSequencerRanks
  SQR4 SQ15 LL_ADC_REG_GetSequencerRanks
  SQR4 SQ16 LL_ADC_REG_GetSequencerRanks

Parameters:

ADCx	ADC instance
Rank	This parameter can be one of the following values: LL_ADC_REG_RANK_1 LL_ADC_REG_RANK_2 LL_ADC_REG_RANK_3 LL_ADC_REG_RANK_4 LL_ADC_REG_RANK_5 LL_ADC_REG_RANK_6 LL_ADC_REG_RANK_7 LL_ADC_REG_RANK_8 LL_ADC_REG_RANK_9 LL_ADC_REG_RANK_10 LL_ADC_REG_RANK_11 LL_ADC_REG_RANK_12 LL_ADC_REG_RANK_13 LL_ADC_REG_RANK_14 LL_ADC_REG_RANK_15 LL_ADC_REG_RANK_16

Return values:

Returned

value can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 (5) LL_ADC_CHANNEL_2 (5) LL_ADC_CHANNEL_3 (5) LL_ADC_CHANNEL_4 (5) LL_ADC_CHANNEL_5 (5) LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_18 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (4) LL_ADC_CHANNEL_VBAT (4) LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) LL_ADC_CHANNEL_DAC1CH1_ADC3 (3) LL_ADC_CHANNEL_DAC1CH2_ADC3 (3) (1) On STM32L4, parameter available only on ADC instance: ADC1. (2) On STM32L4, parameter available only on ADC instance: ADC2. (3) On STM32L4, parameter available only on ADC instance: ADC3. (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). (1, 2, 3, 4) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 3156 of file stm32l4xx_ll_adc.h.

Get ADC group regular conversion trigger polarity.

Applicable only for trigger source set to external trigger. CFGR EXTEN LL_ADC_REG_GetTrigEdge

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_TRIG_EXT_RISING LL_ADC_REG_TRIG_EXT_FALLING LL_ADC_REG_TRIG_EXT_RISINGFALLING

Definition at line 2640 of file stm32l4xx_ll_adc.h.

Get ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.

Note:

To determine whether group regular trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to " if(LL_ADC_REG_GetTrigSource(ADC1) == LL_ADC_REG_TRIG_SW_START) ") use function LL_ADC_REG_IsTrigSourceSWStart. CFGR EXTSEL LL_ADC_REG_GetTrigSource
CFGR EXTEN LL_ADC_REG_GetTrigSource

Parameters:

ADCx	ADC instance

Return values:

Returned

value can be one of the following values: LL_ADC_REG_TRIG_SW_START LL_ADC_REG_TRIG_EXT_TIM1_TRGO LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 LL_ADC_REG_TRIG_EXT_TIM1_CC1 LL_ADC_REG_TRIG_EXT_TIM1_CC2 LL_ADC_REG_TRIG_EXT_TIM1_CC3 LL_ADC_REG_TRIG_EXT_TIM2_TRGO LL_ADC_REG_TRIG_EXT_TIM2_CC2 LL_ADC_REG_TRIG_EXT_TIM3_TRGO LL_ADC_REG_TRIG_EXT_TIM3_CC4 LL_ADC_REG_TRIG_EXT_TIM4_TRGO LL_ADC_REG_TRIG_EXT_TIM4_CC4 LL_ADC_REG_TRIG_EXT_TIM6_TRGO LL_ADC_REG_TRIG_EXT_TIM8_TRGO LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 LL_ADC_REG_TRIG_EXT_TIM15_TRGO LL_ADC_REG_TRIG_EXT_EXTI_LINE11

Definition at line 2579 of file stm32l4xx_ll_adc.h.

Get ADC group regular conversion trigger source: (0: trigger source external trigger, 1: trigger source SW start).

Note:

In case of group regular trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_REG_GetTrigSource(). CFGR EXTEN LL_ADC_REG_IsTrigSourceSWStart

Parameters:

ADCx	ADC instance

Return values:

State

of bit (1 or 0).

Definition at line 2605 of file stm32l4xx_ll_adc.h.

Set ADC continuous conversion mode on ADC group regular: whether ADC conversions are performed: * single mode: one conversion per trigger * continuous mode: after the first trigger, following conversions launched successively automatically.

Note:

It is not possible to enable both ADC continuous mode and ADC group regular discontinuous mode.

On this STM32 family, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular. CFGR CONT LL_ADC_REG_SetContinuousMode

Parameters:

ADCx	ADC instance
Continuous	This parameter can be one of the following values: LL_ADC_REG_CONV_SINGLE LL_ADC_REG_CONV_CONTINUOUS

Return values:

None

Definition at line 2664 of file stm32l4xx_ll_adc.h.

Set ADC group regular conversion data transfer: no transfer or transfer by DMA.

If transfer by DMA selected, specifies the DMA requests mode: * Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. * Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

Note:

If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).

For devices with several ADC instances: ADC multimode DMA settings are available using function LL_ADC_SetMultiDMATransfer().

To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().

On this STM32 family, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on either groups regular or injected. CFGR DMAEN LL_ADC_REG_SetDMATransfer
CFGR DMACFG LL_ADC_REG_SetDMATransfer

Parameters:

ADCx	ADC instance
DMATransfer	This parameter can be one of the following values: LL_ADC_REG_DMA_TRANSFER_NONE LL_ADC_REG_DMA_TRANSFER_LIMITED LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Return values:

None

Definition at line 2720 of file stm32l4xx_ll_adc.h.

Set ADC group regular behaviour in case of overrun: data preserved or overwritten.

Note:

Compatibility with devices without feature overrun: other devices without this feature have a behaviour equivalent to data overwritten. The default setting of overrun is data preserved. Therefore, for compatibility with all devices, parameter overrun should be set to data overwritten.

On this STM32 family, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular. CFGR OVRMOD LL_ADC_REG_SetOverrun

Parameters:

ADCx	ADC instance
Overrun	This parameter can be one of the following values: LL_ADC_REG_OVR_DATA_PRESERVED LL_ADC_REG_OVR_DATA_OVERWRITTEN

Return values:

None

Definition at line 2779 of file stm32l4xx_ll_adc.h.

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:

It is not possible to enable both ADC continuous mode and ADC group regular discontinuous mode.

It is not possible to enable both ADC auto-injected mode and ADC group regular discontinuous mode.

On this STM32 family, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular. CFGR DISCEN LL_ADC_REG_SetSequencerDiscont
CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont

Parameters:

ADCx	ADC instance
SeqDiscont	This parameter can be one of the following values: LL_ADC_REG_SEQ_DISCONT_DISABLE LL_ADC_REG_SEQ_DISCONT_1RANK LL_ADC_REG_SEQ_DISCONT_2RANKS LL_ADC_REG_SEQ_DISCONT_3RANKS LL_ADC_REG_SEQ_DISCONT_4RANKS LL_ADC_REG_SEQ_DISCONT_5RANKS LL_ADC_REG_SEQ_DISCONT_6RANKS LL_ADC_REG_SEQ_DISCONT_7RANKS LL_ADC_REG_SEQ_DISCONT_8RANKS

Return values:

None

Definition at line 2936 of file stm32l4xx_ll_adc.h.

Set ADC group regular sequencer length and scan direction.

* For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs:

• Sequence length: Set number of ranks in the scan sequence.
• Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()". * For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs:
• Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
• Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".

  Note:

  Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.

  On this STM32 family, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular. SQR1 L LL_ADC_REG_SetSequencerLength

  Parameters:

  ADCx

  ADC instance

  SequencerNbRanks

  This parameter can be one of the following values: LL_ADC_REG_SEQ_SCAN_DISABLE LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

  Return values:

  None

Definition at line 2851 of file stm32l4xx_ll_adc.h.

Set ADC group regular sequence: channel on the selected scan sequence rank.

This function performs:

• Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.

  Note:

  On this STM32 family, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().

  Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.

  On this STM32 family, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().

  On this STM32 family, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular. SQR1 SQ1 LL_ADC_REG_SetSequencerRanks
  SQR1 SQ2 LL_ADC_REG_SetSequencerRanks
  SQR1 SQ3 LL_ADC_REG_SetSequencerRanks
  SQR1 SQ4 LL_ADC_REG_SetSequencerRanks
  SQR2 SQ5 LL_ADC_REG_SetSequencerRanks
  SQR2 SQ6 LL_ADC_REG_SetSequencerRanks
  SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
  SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
  SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
  SQR3 SQ10 LL_ADC_REG_SetSequencerRanks
  SQR3 SQ11 LL_ADC_REG_SetSequencerRanks
  SQR3 SQ12 LL_ADC_REG_SetSequencerRanks
  SQR3 SQ13 LL_ADC_REG_SetSequencerRanks
  SQR3 SQ14 LL_ADC_REG_SetSequencerRanks
  SQR4 SQ15 LL_ADC_REG_SetSequencerRanks
  SQR4 SQ16 LL_ADC_REG_SetSequencerRanks

  Parameters:

  ADCx	ADC instance
  Rank	This parameter can be one of the following values: LL_ADC_REG_RANK_1 LL_ADC_REG_RANK_2 LL_ADC_REG_RANK_3 LL_ADC_REG_RANK_4 LL_ADC_REG_RANK_5 LL_ADC_REG_RANK_6 LL_ADC_REG_RANK_7 LL_ADC_REG_RANK_8 LL_ADC_REG_RANK_9 LL_ADC_REG_RANK_10 LL_ADC_REG_RANK_11 LL_ADC_REG_RANK_12 LL_ADC_REG_RANK_13 LL_ADC_REG_RANK_14 LL_ADC_REG_RANK_15 LL_ADC_REG_RANK_16
  Channel	This parameter can be one of the following values: LL_ADC_CHANNEL_0 LL_ADC_CHANNEL_1 (5) LL_ADC_CHANNEL_2 (5) LL_ADC_CHANNEL_3 (5) LL_ADC_CHANNEL_4 (5) LL_ADC_CHANNEL_5 (5) LL_ADC_CHANNEL_6 LL_ADC_CHANNEL_7 LL_ADC_CHANNEL_8 LL_ADC_CHANNEL_9 LL_ADC_CHANNEL_10 LL_ADC_CHANNEL_11 LL_ADC_CHANNEL_12 LL_ADC_CHANNEL_13 LL_ADC_CHANNEL_14 LL_ADC_CHANNEL_15 LL_ADC_CHANNEL_16 LL_ADC_CHANNEL_17 LL_ADC_CHANNEL_18 LL_ADC_CHANNEL_VREFINT (1) LL_ADC_CHANNEL_TEMPSENSOR (4) LL_ADC_CHANNEL_VBAT (4) LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) LL_ADC_CHANNEL_DAC1CH1_ADC3 (3) LL_ADC_CHANNEL_DAC1CH2_ADC3 (3) (1) On STM32L4, parameter available only on ADC instance: ADC1. (2) On STM32L4, parameter available only on ADC instance: ADC2. (3) On STM32L4, parameter available only on ADC instance: ADC3. (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3. (5) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).

  Return values:

  None

Definition at line 3053 of file stm32l4xx_ll_adc.h.

Set ADC group regular conversion trigger polarity.

Applicable only for trigger source set to external trigger.

Note:

On this STM32 family, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular. CFGR EXTEN LL_ADC_REG_SetTrigEdge

Parameters:

ADCx	ADC instance
ExternalTriggerEdge	This parameter can be one of the following values: LL_ADC_REG_TRIG_EXT_RISING LL_ADC_REG_TRIG_EXT_FALLING LL_ADC_REG_TRIG_EXT_RISINGFALLING

Return values:

None

Definition at line 2625 of file stm32l4xx_ll_adc.h.

Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.

Note:

Setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function LL_ADC_REG_SetTrigEdge().

On this STM32 family, setting of this feature is conditioned to ADC state: ADC must be disabled or enabled without conversion on going on group regular. CFGR EXTSEL LL_ADC_REG_SetTrigSource
CFGR EXTEN LL_ADC_REG_SetTrigSource

Parameters:

ADCx

ADC instance

TriggerSource

This parameter can be one of the following values: LL_ADC_REG_TRIG_SW_START LL_ADC_REG_TRIG_EXT_TIM1_TRGO LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 LL_ADC_REG_TRIG_EXT_TIM1_CC1 LL_ADC_REG_TRIG_EXT_TIM1_CC2 LL_ADC_REG_TRIG_EXT_TIM1_CC3 LL_ADC_REG_TRIG_EXT_TIM2_TRGO LL_ADC_REG_TRIG_EXT_TIM2_CC2 LL_ADC_REG_TRIG_EXT_TIM3_TRGO LL_ADC_REG_TRIG_EXT_TIM3_CC4 LL_ADC_REG_TRIG_EXT_TIM4_TRGO LL_ADC_REG_TRIG_EXT_TIM4_CC4 LL_ADC_REG_TRIG_EXT_TIM6_TRGO LL_ADC_REG_TRIG_EXT_TIM8_TRGO LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 LL_ADC_REG_TRIG_EXT_TIM15_TRGO LL_ADC_REG_TRIG_EXT_EXTI_LINE11

Return values:

None

Definition at line 2543 of file stm32l4xx_ll_adc.h.