Eric Lewiston / STM32L4xx_HAL_Driver

Hal Drivers for L4

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Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Src/stm32l4xx_hal_sram.c@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:
EricLew
Date:
Wed Nov 25 17:30:43 2015 +0000
Revision:
2:7aef7655b0a8
Parent:
0:80ee8f3b695e 
commit;

Who changed what in which revision?

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EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_hal_sram.c
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief SRAM HAL module driver.
EricLew 0:80ee8f3b695e 8 * This file provides a generic firmware to drive SRAM memories
EricLew 0:80ee8f3b695e 9 * mounted as external device.
EricLew 0:80ee8f3b695e 10 *
EricLew 0:80ee8f3b695e 11 @verbatim
EricLew 0:80ee8f3b695e 12 ==============================================================================
EricLew 0:80ee8f3b695e 13 ##### How to use this driver #####
EricLew 0:80ee8f3b695e 14 ==============================================================================
EricLew 0:80ee8f3b695e 15 [..]
EricLew 0:80ee8f3b695e 16 This driver is a generic layered driver which contains a set of APIs used to
EricLew 0:80ee8f3b695e 17 control SRAM memories. It uses the FMC layer functions to interface
EricLew 0:80ee8f3b695e 18 with SRAM devices.
EricLew 0:80ee8f3b695e 19 The following sequence should be followed to configure the FMC to interface
EricLew 0:80ee8f3b695e 20 with SRAM/PSRAM memories:
EricLew 0:80ee8f3b695e 21
EricLew 0:80ee8f3b695e 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
EricLew 0:80ee8f3b695e 23 SRAM_HandleTypeDef hsram; and:
EricLew 0:80ee8f3b695e 24
EricLew 0:80ee8f3b695e 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
EricLew 0:80ee8f3b695e 26 values of the structure member.
EricLew 0:80ee8f3b695e 27
EricLew 0:80ee8f3b695e 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
EricLew 0:80ee8f3b695e 29 base register instance for NOR or SRAM device
EricLew 0:80ee8f3b695e 30
EricLew 0:80ee8f3b695e 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
EricLew 0:80ee8f3b695e 32 base register instance for NOR or SRAM extended mode
EricLew 0:80ee8f3b695e 33
EricLew 0:80ee8f3b695e 34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
EricLew 0:80ee8f3b695e 35 mode timings; for example:
EricLew 0:80ee8f3b695e 36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
EricLew 0:80ee8f3b695e 37 and fill its fields with the allowed values of the structure member.
EricLew 0:80ee8f3b695e 38
EricLew 0:80ee8f3b695e 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
EricLew 0:80ee8f3b695e 40 performs the following sequence:
EricLew 0:80ee8f3b695e 41
EricLew 0:80ee8f3b695e 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
EricLew 0:80ee8f3b695e 43 (##) Control register configuration using the FMC NORSRAM interface function
EricLew 0:80ee8f3b695e 44 FMC_NORSRAM_Init()
EricLew 0:80ee8f3b695e 45 (##) Timing register configuration using the FMC NORSRAM interface function
EricLew 0:80ee8f3b695e 46 FMC_NORSRAM_Timing_Init()
EricLew 0:80ee8f3b695e 47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
EricLew 0:80ee8f3b695e 48 FMC_NORSRAM_Extended_Timing_Init()
EricLew 0:80ee8f3b695e 49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
EricLew 0:80ee8f3b695e 50
EricLew 0:80ee8f3b695e 51 (#) At this stage you can perform read/write accesses from/to the memory connected
EricLew 0:80ee8f3b695e 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
EricLew 0:80ee8f3b695e 53 following APIs:
EricLew 0:80ee8f3b695e 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
EricLew 0:80ee8f3b695e 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
EricLew 0:80ee8f3b695e 56
EricLew 0:80ee8f3b695e 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
EricLew 0:80ee8f3b695e 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
EricLew 0:80ee8f3b695e 59
EricLew 0:80ee8f3b695e 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
EricLew 0:80ee8f3b695e 61 HAL_SRAM_GetState()
EricLew 0:80ee8f3b695e 62
EricLew 0:80ee8f3b695e 63 @endverbatim
EricLew 0:80ee8f3b695e 64 ******************************************************************************
EricLew 0:80ee8f3b695e 65 * @attention
EricLew 0:80ee8f3b695e 66 *
EricLew 0:80ee8f3b695e 67 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 68 *
EricLew 0:80ee8f3b695e 69 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 70 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 71 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 72 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 74 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 75 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 77 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 78 * without specific prior written permission.
EricLew 0:80ee8f3b695e 79 *
EricLew 0:80ee8f3b695e 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 90 *
EricLew 0:80ee8f3b695e 91 ******************************************************************************
EricLew 0:80ee8f3b695e 92 */
EricLew 0:80ee8f3b695e 93
EricLew 0:80ee8f3b695e 94 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 95 #include "stm32l4xx_hal.h"
EricLew 0:80ee8f3b695e 96
EricLew 0:80ee8f3b695e 97 /** @addtogroup STM32L4xx_HAL_Driver
EricLew 0:80ee8f3b695e 98 * @{
EricLew 0:80ee8f3b695e 99 */
EricLew 0:80ee8f3b695e 100
EricLew 0:80ee8f3b695e 101 #ifdef HAL_SRAM_MODULE_ENABLED
EricLew 0:80ee8f3b695e 102
EricLew 0:80ee8f3b695e 103 /** @defgroup SRAM SRAM
EricLew 0:80ee8f3b695e 104 * @brief SRAM HAL module driver.
EricLew 0:80ee8f3b695e 105 * @{
EricLew 0:80ee8f3b695e 106 */
EricLew 0:80ee8f3b695e 107 /* Private typedef -----------------------------------------------------------*/
EricLew 0:80ee8f3b695e 108 /* Private define ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 109 /* Private macro -------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 110 /* Private variables ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 111 /* Private function prototypes -----------------------------------------------*/
EricLew 0:80ee8f3b695e 112 /* Exported functions --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 113
EricLew 0:80ee8f3b695e 114 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
EricLew 0:80ee8f3b695e 115 * @{
EricLew 0:80ee8f3b695e 116 */
EricLew 0:80ee8f3b695e 117
EricLew 0:80ee8f3b695e 118 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 119 * @brief Initialization and Configuration functions.
EricLew 0:80ee8f3b695e 120 *
EricLew 0:80ee8f3b695e 121 @verbatim
EricLew 0:80ee8f3b695e 122 ==============================================================================
EricLew 0:80ee8f3b695e 123 ##### SRAM Initialization and de-initialization functions #####
EricLew 0:80ee8f3b695e 124 ==============================================================================
EricLew 0:80ee8f3b695e 125 [..] This section provides functions allowing to initialize/de-initialize
EricLew 0:80ee8f3b695e 126 the SRAM memory.
EricLew 0:80ee8f3b695e 127
EricLew 0:80ee8f3b695e 128 @endverbatim
EricLew 0:80ee8f3b695e 129 * @{
EricLew 0:80ee8f3b695e 130 */
EricLew 0:80ee8f3b695e 131
EricLew 0:80ee8f3b695e 132 /**
EricLew 0:80ee8f3b695e 133 * @brief Perform the SRAM device initialization sequence.
EricLew 0:80ee8f3b695e 134 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 135 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 136 * @param Timing: Pointer to SRAM control timing structure
EricLew 0:80ee8f3b695e 137 * @param ExtTiming: Pointer to SRAM extended mode timing structure
EricLew 0:80ee8f3b695e 138 * @retval HAL status
EricLew 0:80ee8f3b695e 139 */
EricLew 0:80ee8f3b695e 140 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
EricLew 0:80ee8f3b695e 141 {
EricLew 0:80ee8f3b695e 142 /* Check the SRAM handle parameter */
EricLew 0:80ee8f3b695e 143 if(hsram == NULL)
EricLew 0:80ee8f3b695e 144 {
EricLew 0:80ee8f3b695e 145 return HAL_ERROR;
EricLew 0:80ee8f3b695e 146 }
EricLew 0:80ee8f3b695e 147
EricLew 0:80ee8f3b695e 148 if(hsram->State == HAL_SRAM_STATE_RESET)
EricLew 0:80ee8f3b695e 149 {
EricLew 0:80ee8f3b695e 150 /* Allocate lock resource and initialize it */
EricLew 0:80ee8f3b695e 151 hsram->Lock = HAL_UNLOCKED;
EricLew 0:80ee8f3b695e 152
EricLew 0:80ee8f3b695e 153 /* Initialize the low level hardware (MSP) */
EricLew 0:80ee8f3b695e 154 HAL_SRAM_MspInit(hsram);
EricLew 0:80ee8f3b695e 155 }
EricLew 0:80ee8f3b695e 156
EricLew 0:80ee8f3b695e 157 /* Initialize SRAM control Interface */
EricLew 0:80ee8f3b695e 158 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
EricLew 0:80ee8f3b695e 159
EricLew 0:80ee8f3b695e 160 /* Initialize SRAM timing Interface */
EricLew 0:80ee8f3b695e 161 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
EricLew 0:80ee8f3b695e 162
EricLew 0:80ee8f3b695e 163 /* Initialize SRAM extended mode timing Interface */
EricLew 0:80ee8f3b695e 164 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
EricLew 0:80ee8f3b695e 165
EricLew 0:80ee8f3b695e 166 /* Enable the NORSRAM device */
EricLew 0:80ee8f3b695e 167 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
EricLew 0:80ee8f3b695e 168
EricLew 0:80ee8f3b695e 169 return HAL_OK;
EricLew 0:80ee8f3b695e 170 }
EricLew 0:80ee8f3b695e 171
EricLew 0:80ee8f3b695e 172 /**
EricLew 0:80ee8f3b695e 173 * @brief Perform the SRAM device de-initialization sequence.
EricLew 0:80ee8f3b695e 174 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 175 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 176 * @retval HAL status
EricLew 0:80ee8f3b695e 177 */
EricLew 0:80ee8f3b695e 178 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
EricLew 0:80ee8f3b695e 179 {
EricLew 0:80ee8f3b695e 180 /* De-Initialize the low level hardware (MSP) */
EricLew 0:80ee8f3b695e 181 HAL_SRAM_MspDeInit(hsram);
EricLew 0:80ee8f3b695e 182
EricLew 0:80ee8f3b695e 183 /* Configure the SRAM registers with their reset values */
EricLew 0:80ee8f3b695e 184 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
EricLew 0:80ee8f3b695e 185
EricLew 0:80ee8f3b695e 186 hsram->State = HAL_SRAM_STATE_RESET;
EricLew 0:80ee8f3b695e 187
EricLew 0:80ee8f3b695e 188 /* Release Lock */
EricLew 0:80ee8f3b695e 189 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 190
EricLew 0:80ee8f3b695e 191 return HAL_OK;
EricLew 0:80ee8f3b695e 192 }
EricLew 0:80ee8f3b695e 193
EricLew 0:80ee8f3b695e 194 /**
EricLew 0:80ee8f3b695e 195 * @brief Initialize the SRAM MSP.
EricLew 0:80ee8f3b695e 196 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 197 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 198 * @retval None
EricLew 0:80ee8f3b695e 199 */
EricLew 0:80ee8f3b695e 200 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
EricLew 0:80ee8f3b695e 201 {
EricLew 0:80ee8f3b695e 202 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 203 the HAL_SRAM_MspInit could be implemented in the user file
EricLew 0:80ee8f3b695e 204 */
EricLew 0:80ee8f3b695e 205 }
EricLew 0:80ee8f3b695e 206
EricLew 0:80ee8f3b695e 207 /**
EricLew 0:80ee8f3b695e 208 * @brief DeInitialize the SRAM MSP.
EricLew 0:80ee8f3b695e 209 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 210 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 211 * @retval None
EricLew 0:80ee8f3b695e 212 */
EricLew 0:80ee8f3b695e 213 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
EricLew 0:80ee8f3b695e 214 {
EricLew 0:80ee8f3b695e 215 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 216 the HAL_SRAM_MspDeInit could be implemented in the user file
EricLew 0:80ee8f3b695e 217 */
EricLew 0:80ee8f3b695e 218 }
EricLew 0:80ee8f3b695e 219
EricLew 0:80ee8f3b695e 220 /**
EricLew 0:80ee8f3b695e 221 * @brief DMA transfer complete callback.
EricLew 0:80ee8f3b695e 222 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 223 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 224 * @retval None
EricLew 0:80ee8f3b695e 225 */
EricLew 0:80ee8f3b695e 226 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
EricLew 0:80ee8f3b695e 227 {
EricLew 0:80ee8f3b695e 228 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 229 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
EricLew 0:80ee8f3b695e 230 */
EricLew 0:80ee8f3b695e 231 }
EricLew 0:80ee8f3b695e 232
EricLew 0:80ee8f3b695e 233 /**
EricLew 0:80ee8f3b695e 234 * @brief DMA transfer complete error callback.
EricLew 0:80ee8f3b695e 235 * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 236 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 237 * @retval None
EricLew 0:80ee8f3b695e 238 */
EricLew 0:80ee8f3b695e 239 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
EricLew 0:80ee8f3b695e 240 {
EricLew 0:80ee8f3b695e 241 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 242 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
EricLew 0:80ee8f3b695e 243 */
EricLew 0:80ee8f3b695e 244 }
EricLew 0:80ee8f3b695e 245
EricLew 0:80ee8f3b695e 246 /**
EricLew 0:80ee8f3b695e 247 * @}
EricLew 0:80ee8f3b695e 248 */
EricLew 0:80ee8f3b695e 249
EricLew 0:80ee8f3b695e 250 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
EricLew 0:80ee8f3b695e 251 * @brief Input Output and memory control functions
EricLew 0:80ee8f3b695e 252 *
EricLew 0:80ee8f3b695e 253 @verbatim
EricLew 0:80ee8f3b695e 254 ==============================================================================
EricLew 0:80ee8f3b695e 255 ##### SRAM Input and Output functions #####
EricLew 0:80ee8f3b695e 256 ==============================================================================
EricLew 0:80ee8f3b695e 257 [..]
EricLew 0:80ee8f3b695e 258 This section provides functions allowing to use and control the SRAM memory
EricLew 0:80ee8f3b695e 259
EricLew 0:80ee8f3b695e 260 @endverbatim
EricLew 0:80ee8f3b695e 261 * @{
EricLew 0:80ee8f3b695e 262 */
EricLew 0:80ee8f3b695e 263
EricLew 0:80ee8f3b695e 264 /**
EricLew 0:80ee8f3b695e 265 * @brief Read 8-bit buffer from SRAM memory.
EricLew 0:80ee8f3b695e 266 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 267 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 268 * @param pAddress: Pointer to read start address
EricLew 0:80ee8f3b695e 269 * @param pDstBuffer: Pointer to destination buffer
EricLew 0:80ee8f3b695e 270 * @param BufferSize: Size of the buffer to read from memory
EricLew 0:80ee8f3b695e 271 * @retval HAL status
EricLew 0:80ee8f3b695e 272 */
EricLew 0:80ee8f3b695e 273 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
EricLew 0:80ee8f3b695e 274 {
EricLew 0:80ee8f3b695e 275 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
EricLew 0:80ee8f3b695e 276
EricLew 0:80ee8f3b695e 277 /* Process Locked */
EricLew 0:80ee8f3b695e 278 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 279
EricLew 0:80ee8f3b695e 280 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 281 hsram->State = HAL_SRAM_STATE_BUSY;
EricLew 0:80ee8f3b695e 282
EricLew 0:80ee8f3b695e 283 /* Read data from memory */
EricLew 0:80ee8f3b695e 284 for(; BufferSize != 0; BufferSize--)
EricLew 0:80ee8f3b695e 285 {
EricLew 0:80ee8f3b695e 286 *pDstBuffer = *(__IO uint8_t *)psramaddress;
EricLew 0:80ee8f3b695e 287 pDstBuffer++;
EricLew 0:80ee8f3b695e 288 psramaddress++;
EricLew 0:80ee8f3b695e 289 }
EricLew 0:80ee8f3b695e 290
EricLew 0:80ee8f3b695e 291 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 292 hsram->State = HAL_SRAM_STATE_READY;
EricLew 0:80ee8f3b695e 293
EricLew 0:80ee8f3b695e 294 /* Process unlocked */
EricLew 0:80ee8f3b695e 295 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 296
EricLew 0:80ee8f3b695e 297 return HAL_OK;
EricLew 0:80ee8f3b695e 298 }
EricLew 0:80ee8f3b695e 299
EricLew 0:80ee8f3b695e 300 /**
EricLew 0:80ee8f3b695e 301 * @brief Write 8-bit buffer to SRAM memory.
EricLew 0:80ee8f3b695e 302 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 303 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 304 * @param pAddress: Pointer to write start address
EricLew 0:80ee8f3b695e 305 * @param pSrcBuffer: Pointer to source buffer to write
EricLew 0:80ee8f3b695e 306 * @param BufferSize: Size of the buffer to write to memory
EricLew 0:80ee8f3b695e 307 * @retval HAL status
EricLew 0:80ee8f3b695e 308 */
EricLew 0:80ee8f3b695e 309 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
EricLew 0:80ee8f3b695e 310 {
EricLew 0:80ee8f3b695e 311 __IO uint8_t * psramaddress = (uint8_t *)pAddress;
EricLew 0:80ee8f3b695e 312
EricLew 0:80ee8f3b695e 313 /* Check the SRAM controller state */
EricLew 0:80ee8f3b695e 314 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
EricLew 0:80ee8f3b695e 315 {
EricLew 0:80ee8f3b695e 316 return HAL_ERROR;
EricLew 0:80ee8f3b695e 317 }
EricLew 0:80ee8f3b695e 318
EricLew 0:80ee8f3b695e 319 /* Process Locked */
EricLew 0:80ee8f3b695e 320 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 321
EricLew 0:80ee8f3b695e 322 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 323 hsram->State = HAL_SRAM_STATE_BUSY;
EricLew 0:80ee8f3b695e 324
EricLew 0:80ee8f3b695e 325 /* Write data to memory */
EricLew 0:80ee8f3b695e 326 for(; BufferSize != 0; BufferSize--)
EricLew 0:80ee8f3b695e 327 {
EricLew 0:80ee8f3b695e 328 *(__IO uint8_t *)psramaddress = *pSrcBuffer;
EricLew 0:80ee8f3b695e 329 pSrcBuffer++;
EricLew 0:80ee8f3b695e 330 psramaddress++;
EricLew 0:80ee8f3b695e 331 }
EricLew 0:80ee8f3b695e 332
EricLew 0:80ee8f3b695e 333 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 334 hsram->State = HAL_SRAM_STATE_READY;
EricLew 0:80ee8f3b695e 335
EricLew 0:80ee8f3b695e 336 /* Process unlocked */
EricLew 0:80ee8f3b695e 337 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 338
EricLew 0:80ee8f3b695e 339 return HAL_OK;
EricLew 0:80ee8f3b695e 340 }
EricLew 0:80ee8f3b695e 341
EricLew 0:80ee8f3b695e 342 /**
EricLew 0:80ee8f3b695e 343 * @brief Read 16-bit buffer from SRAM memory.
EricLew 0:80ee8f3b695e 344 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 345 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 346 * @param pAddress: Pointer to read start address
EricLew 0:80ee8f3b695e 347 * @param pDstBuffer: Pointer to destination buffer
EricLew 0:80ee8f3b695e 348 * @param BufferSize: Size of the buffer to read from memory
EricLew 0:80ee8f3b695e 349 * @retval HAL status
EricLew 0:80ee8f3b695e 350 */
EricLew 0:80ee8f3b695e 351 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
EricLew 0:80ee8f3b695e 352 {
EricLew 0:80ee8f3b695e 353 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
EricLew 0:80ee8f3b695e 354
EricLew 0:80ee8f3b695e 355 /* Process Locked */
EricLew 0:80ee8f3b695e 356 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 357
EricLew 0:80ee8f3b695e 358 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 359 hsram->State = HAL_SRAM_STATE_BUSY;
EricLew 0:80ee8f3b695e 360
EricLew 0:80ee8f3b695e 361 /* Read data from memory */
EricLew 0:80ee8f3b695e 362 for(; BufferSize != 0; BufferSize--)
EricLew 0:80ee8f3b695e 363 {
EricLew 0:80ee8f3b695e 364 *pDstBuffer = *(__IO uint16_t *)psramaddress;
EricLew 0:80ee8f3b695e 365 pDstBuffer++;
EricLew 0:80ee8f3b695e 366 psramaddress++;
EricLew 0:80ee8f3b695e 367 }
EricLew 0:80ee8f3b695e 368
EricLew 0:80ee8f3b695e 369 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 370 hsram->State = HAL_SRAM_STATE_READY;
EricLew 0:80ee8f3b695e 371
EricLew 0:80ee8f3b695e 372 /* Process unlocked */
EricLew 0:80ee8f3b695e 373 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 374
EricLew 0:80ee8f3b695e 375 return HAL_OK;
EricLew 0:80ee8f3b695e 376 }
EricLew 0:80ee8f3b695e 377
EricLew 0:80ee8f3b695e 378 /**
EricLew 0:80ee8f3b695e 379 * @brief Write 16-bit buffer to SRAM memory.
EricLew 0:80ee8f3b695e 380 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 381 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 382 * @param pAddress: Pointer to write start address
EricLew 0:80ee8f3b695e 383 * @param pSrcBuffer: Pointer to source buffer to write
EricLew 0:80ee8f3b695e 384 * @param BufferSize: Size of the buffer to write to memory
EricLew 0:80ee8f3b695e 385 * @retval HAL status
EricLew 0:80ee8f3b695e 386 */
EricLew 0:80ee8f3b695e 387 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
EricLew 0:80ee8f3b695e 388 {
EricLew 0:80ee8f3b695e 389 __IO uint16_t * psramaddress = (uint16_t *)pAddress;
EricLew 0:80ee8f3b695e 390
EricLew 0:80ee8f3b695e 391 /* Check the SRAM controller state */
EricLew 0:80ee8f3b695e 392 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
EricLew 0:80ee8f3b695e 393 {
EricLew 0:80ee8f3b695e 394 return HAL_ERROR;
EricLew 0:80ee8f3b695e 395 }
EricLew 0:80ee8f3b695e 396
EricLew 0:80ee8f3b695e 397 /* Process Locked */
EricLew 0:80ee8f3b695e 398 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 399
EricLew 0:80ee8f3b695e 400 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 401 hsram->State = HAL_SRAM_STATE_BUSY;
EricLew 0:80ee8f3b695e 402
EricLew 0:80ee8f3b695e 403 /* Write data to memory */
EricLew 0:80ee8f3b695e 404 for(; BufferSize != 0; BufferSize--)
EricLew 0:80ee8f3b695e 405 {
EricLew 0:80ee8f3b695e 406 *(__IO uint16_t *)psramaddress = *pSrcBuffer;
EricLew 0:80ee8f3b695e 407 pSrcBuffer++;
EricLew 0:80ee8f3b695e 408 psramaddress++;
EricLew 0:80ee8f3b695e 409 }
EricLew 0:80ee8f3b695e 410
EricLew 0:80ee8f3b695e 411 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 412 hsram->State = HAL_SRAM_STATE_READY;
EricLew 0:80ee8f3b695e 413
EricLew 0:80ee8f3b695e 414 /* Process unlocked */
EricLew 0:80ee8f3b695e 415 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 416
EricLew 0:80ee8f3b695e 417 return HAL_OK;
EricLew 0:80ee8f3b695e 418 }
EricLew 0:80ee8f3b695e 419
EricLew 0:80ee8f3b695e 420 /**
EricLew 0:80ee8f3b695e 421 * @brief Read 32-bit buffer from SRAM memory.
EricLew 0:80ee8f3b695e 422 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 423 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 424 * @param pAddress: Pointer to read start address
EricLew 0:80ee8f3b695e 425 * @param pDstBuffer: Pointer to destination buffer
EricLew 0:80ee8f3b695e 426 * @param BufferSize: Size of the buffer to read from memory
EricLew 0:80ee8f3b695e 427 * @retval HAL status
EricLew 0:80ee8f3b695e 428 */
EricLew 0:80ee8f3b695e 429 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
EricLew 0:80ee8f3b695e 430 {
EricLew 0:80ee8f3b695e 431 /* Process Locked */
EricLew 0:80ee8f3b695e 432 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 433
EricLew 0:80ee8f3b695e 434 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 435 hsram->State = HAL_SRAM_STATE_BUSY;
EricLew 0:80ee8f3b695e 436
EricLew 0:80ee8f3b695e 437 /* Read data from memory */
EricLew 0:80ee8f3b695e 438 for(; BufferSize != 0; BufferSize--)
EricLew 0:80ee8f3b695e 439 {
EricLew 0:80ee8f3b695e 440 *pDstBuffer = *(__IO uint32_t *)pAddress;
EricLew 0:80ee8f3b695e 441 pDstBuffer++;
EricLew 0:80ee8f3b695e 442 pAddress++;
EricLew 0:80ee8f3b695e 443 }
EricLew 0:80ee8f3b695e 444
EricLew 0:80ee8f3b695e 445 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 446 hsram->State = HAL_SRAM_STATE_READY;
EricLew 0:80ee8f3b695e 447
EricLew 0:80ee8f3b695e 448 /* Process unlocked */
EricLew 0:80ee8f3b695e 449 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 450
EricLew 0:80ee8f3b695e 451 return HAL_OK;
EricLew 0:80ee8f3b695e 452 }
EricLew 0:80ee8f3b695e 453
EricLew 0:80ee8f3b695e 454 /**
EricLew 0:80ee8f3b695e 455 * @brief Write 32-bit buffer to SRAM memory.
EricLew 0:80ee8f3b695e 456 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 457 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 458 * @param pAddress: Pointer to write start address
EricLew 0:80ee8f3b695e 459 * @param pSrcBuffer: Pointer to source buffer to write
EricLew 0:80ee8f3b695e 460 * @param BufferSize: Size of the buffer to write to memory
EricLew 0:80ee8f3b695e 461 * @retval HAL status
EricLew 0:80ee8f3b695e 462 */
EricLew 0:80ee8f3b695e 463 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
EricLew 0:80ee8f3b695e 464 {
EricLew 0:80ee8f3b695e 465 /* Check the SRAM controller state */
EricLew 0:80ee8f3b695e 466 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
EricLew 0:80ee8f3b695e 467 {
EricLew 0:80ee8f3b695e 468 return HAL_ERROR;
EricLew 0:80ee8f3b695e 469 }
EricLew 0:80ee8f3b695e 470
EricLew 0:80ee8f3b695e 471 /* Process Locked */
EricLew 0:80ee8f3b695e 472 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 473
EricLew 0:80ee8f3b695e 474 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 475 hsram->State = HAL_SRAM_STATE_BUSY;
EricLew 0:80ee8f3b695e 476
EricLew 0:80ee8f3b695e 477 /* Write data to memory */
EricLew 0:80ee8f3b695e 478 for(; BufferSize != 0; BufferSize--)
EricLew 0:80ee8f3b695e 479 {
EricLew 0:80ee8f3b695e 480 *(__IO uint32_t *)pAddress = *pSrcBuffer;
EricLew 0:80ee8f3b695e 481 pSrcBuffer++;
EricLew 0:80ee8f3b695e 482 pAddress++;
EricLew 0:80ee8f3b695e 483 }
EricLew 0:80ee8f3b695e 484
EricLew 0:80ee8f3b695e 485 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 486 hsram->State = HAL_SRAM_STATE_READY;
EricLew 0:80ee8f3b695e 487
EricLew 0:80ee8f3b695e 488 /* Process unlocked */
EricLew 0:80ee8f3b695e 489 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 490
EricLew 0:80ee8f3b695e 491 return HAL_OK;
EricLew 0:80ee8f3b695e 492 }
EricLew 0:80ee8f3b695e 493
EricLew 0:80ee8f3b695e 494 /**
EricLew 0:80ee8f3b695e 495 * @brief Read a Word data buffer from the SRAM memory using DMA transfer.
EricLew 0:80ee8f3b695e 496 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 497 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 498 * @param pAddress: Pointer to read start address
EricLew 0:80ee8f3b695e 499 * @param pDstBuffer: Pointer to destination buffer
EricLew 0:80ee8f3b695e 500 * @param BufferSize: Size of the buffer to read from memory
EricLew 0:80ee8f3b695e 501 * @retval HAL status
EricLew 0:80ee8f3b695e 502 */
EricLew 0:80ee8f3b695e 503 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
EricLew 0:80ee8f3b695e 504 {
EricLew 0:80ee8f3b695e 505 /* Process Locked */
EricLew 0:80ee8f3b695e 506 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 507
EricLew 0:80ee8f3b695e 508 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 509 hsram->State = HAL_SRAM_STATE_BUSY;
EricLew 0:80ee8f3b695e 510
EricLew 0:80ee8f3b695e 511 /* Configure DMA user callbacks */
EricLew 0:80ee8f3b695e 512 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
EricLew 0:80ee8f3b695e 513 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
EricLew 0:80ee8f3b695e 514
EricLew 0:80ee8f3b695e 515 /* Enable the DMA Channel */
EricLew 0:80ee8f3b695e 516 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
EricLew 0:80ee8f3b695e 517
EricLew 0:80ee8f3b695e 518 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 519 hsram->State = HAL_SRAM_STATE_READY;
EricLew 0:80ee8f3b695e 520
EricLew 0:80ee8f3b695e 521 /* Process unlocked */
EricLew 0:80ee8f3b695e 522 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 523
EricLew 0:80ee8f3b695e 524 return HAL_OK;
EricLew 0:80ee8f3b695e 525 }
EricLew 0:80ee8f3b695e 526
EricLew 0:80ee8f3b695e 527 /**
EricLew 0:80ee8f3b695e 528 * @brief Write a Word data buffer to SRAM memory using DMA transfer.
EricLew 0:80ee8f3b695e 529 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 530 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 531 * @param pAddress: Pointer to write start address
EricLew 0:80ee8f3b695e 532 * @param pSrcBuffer: Pointer to source buffer to write
EricLew 0:80ee8f3b695e 533 * @param BufferSize: Size of the buffer to write to memory
EricLew 0:80ee8f3b695e 534 * @retval HAL status
EricLew 0:80ee8f3b695e 535 */
EricLew 0:80ee8f3b695e 536 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
EricLew 0:80ee8f3b695e 537 {
EricLew 0:80ee8f3b695e 538 /* Check the SRAM controller state */
EricLew 0:80ee8f3b695e 539 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
EricLew 0:80ee8f3b695e 540 {
EricLew 0:80ee8f3b695e 541 return HAL_ERROR;
EricLew 0:80ee8f3b695e 542 }
EricLew 0:80ee8f3b695e 543
EricLew 0:80ee8f3b695e 544 /* Process Locked */
EricLew 0:80ee8f3b695e 545 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 546
EricLew 0:80ee8f3b695e 547 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 548 hsram->State = HAL_SRAM_STATE_BUSY;
EricLew 0:80ee8f3b695e 549
EricLew 0:80ee8f3b695e 550 /* Configure DMA user callbacks */
EricLew 0:80ee8f3b695e 551 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
EricLew 0:80ee8f3b695e 552 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
EricLew 0:80ee8f3b695e 553
EricLew 0:80ee8f3b695e 554 /* Enable the DMA Channel */
EricLew 0:80ee8f3b695e 555 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
EricLew 0:80ee8f3b695e 556
EricLew 0:80ee8f3b695e 557 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 558 hsram->State = HAL_SRAM_STATE_READY;
EricLew 0:80ee8f3b695e 559
EricLew 0:80ee8f3b695e 560 /* Process unlocked */
EricLew 0:80ee8f3b695e 561 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 562
EricLew 0:80ee8f3b695e 563 return HAL_OK;
EricLew 0:80ee8f3b695e 564 }
EricLew 0:80ee8f3b695e 565
EricLew 0:80ee8f3b695e 566 /**
EricLew 0:80ee8f3b695e 567 * @}
EricLew 0:80ee8f3b695e 568 */
EricLew 0:80ee8f3b695e 569
EricLew 0:80ee8f3b695e 570 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
EricLew 0:80ee8f3b695e 571 * @brief Control functions
EricLew 0:80ee8f3b695e 572 *
EricLew 0:80ee8f3b695e 573 @verbatim
EricLew 0:80ee8f3b695e 574 ==============================================================================
EricLew 0:80ee8f3b695e 575 ##### SRAM Control functions #####
EricLew 0:80ee8f3b695e 576 ==============================================================================
EricLew 0:80ee8f3b695e 577 [..]
EricLew 0:80ee8f3b695e 578 This subsection provides a set of functions allowing to control dynamically
EricLew 0:80ee8f3b695e 579 the SRAM interface.
EricLew 0:80ee8f3b695e 580
EricLew 0:80ee8f3b695e 581 @endverbatim
EricLew 0:80ee8f3b695e 582 * @{
EricLew 0:80ee8f3b695e 583 */
EricLew 0:80ee8f3b695e 584
EricLew 0:80ee8f3b695e 585 /**
EricLew 0:80ee8f3b695e 586 * @brief Enable dynamically SRAM write operation.
EricLew 0:80ee8f3b695e 587 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 588 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 589 * @retval HAL status
EricLew 0:80ee8f3b695e 590 */
EricLew 0:80ee8f3b695e 591 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
EricLew 0:80ee8f3b695e 592 {
EricLew 0:80ee8f3b695e 593 /* Process Locked */
EricLew 0:80ee8f3b695e 594 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 595
EricLew 0:80ee8f3b695e 596 /* Enable write operation */
EricLew 0:80ee8f3b695e 597 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
EricLew 0:80ee8f3b695e 598
EricLew 0:80ee8f3b695e 599 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 600 hsram->State = HAL_SRAM_STATE_READY;
EricLew 0:80ee8f3b695e 601
EricLew 0:80ee8f3b695e 602 /* Process unlocked */
EricLew 0:80ee8f3b695e 603 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 604
EricLew 0:80ee8f3b695e 605 return HAL_OK;
EricLew 0:80ee8f3b695e 606 }
EricLew 0:80ee8f3b695e 607
EricLew 0:80ee8f3b695e 608 /**
EricLew 0:80ee8f3b695e 609 * @brief Disable dynamically SRAM write operation.
EricLew 0:80ee8f3b695e 610 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 611 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 612 * @retval HAL status
EricLew 0:80ee8f3b695e 613 */
EricLew 0:80ee8f3b695e 614 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
EricLew 0:80ee8f3b695e 615 {
EricLew 0:80ee8f3b695e 616 /* Process Locked */
EricLew 0:80ee8f3b695e 617 __HAL_LOCK(hsram);
EricLew 0:80ee8f3b695e 618
EricLew 0:80ee8f3b695e 619 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 620 hsram->State = HAL_SRAM_STATE_BUSY;
EricLew 0:80ee8f3b695e 621
EricLew 0:80ee8f3b695e 622 /* Disable write operation */
EricLew 0:80ee8f3b695e 623 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
EricLew 0:80ee8f3b695e 624
EricLew 0:80ee8f3b695e 625 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 626 hsram->State = HAL_SRAM_STATE_PROTECTED;
EricLew 0:80ee8f3b695e 627
EricLew 0:80ee8f3b695e 628 /* Process unlocked */
EricLew 0:80ee8f3b695e 629 __HAL_UNLOCK(hsram);
EricLew 0:80ee8f3b695e 630
EricLew 0:80ee8f3b695e 631 return HAL_OK;
EricLew 0:80ee8f3b695e 632 }
EricLew 0:80ee8f3b695e 633
EricLew 0:80ee8f3b695e 634 /**
EricLew 0:80ee8f3b695e 635 * @}
EricLew 0:80ee8f3b695e 636 */
EricLew 0:80ee8f3b695e 637
EricLew 0:80ee8f3b695e 638 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
EricLew 0:80ee8f3b695e 639 * @brief Peripheral State functions
EricLew 0:80ee8f3b695e 640 *
EricLew 0:80ee8f3b695e 641 @verbatim
EricLew 0:80ee8f3b695e 642 ==============================================================================
EricLew 0:80ee8f3b695e 643 ##### SRAM State functions #####
EricLew 0:80ee8f3b695e 644 ==============================================================================
EricLew 0:80ee8f3b695e 645 [..]
EricLew 0:80ee8f3b695e 646 This subsection permits to get in run-time the status of the SRAM controller
EricLew 0:80ee8f3b695e 647 and the data flow.
EricLew 0:80ee8f3b695e 648
EricLew 0:80ee8f3b695e 649 @endverbatim
EricLew 0:80ee8f3b695e 650 * @{
EricLew 0:80ee8f3b695e 651 */
EricLew 0:80ee8f3b695e 652
EricLew 0:80ee8f3b695e 653 /**
EricLew 0:80ee8f3b695e 654 * @brief Return the SRAM controller handle state.
EricLew 0:80ee8f3b695e 655 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 656 * the configuration information for SRAM module.
EricLew 0:80ee8f3b695e 657 * @retval HAL state
EricLew 0:80ee8f3b695e 658 */
EricLew 0:80ee8f3b695e 659 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
EricLew 0:80ee8f3b695e 660 {
EricLew 0:80ee8f3b695e 661 /* Return SRAM handle state */
EricLew 0:80ee8f3b695e 662 return hsram->State;
EricLew 0:80ee8f3b695e 663 }
EricLew 0:80ee8f3b695e 664
EricLew 0:80ee8f3b695e 665 /**
EricLew 0:80ee8f3b695e 666 * @}
EricLew 0:80ee8f3b695e 667 */
EricLew 0:80ee8f3b695e 668
EricLew 0:80ee8f3b695e 669 /**
EricLew 0:80ee8f3b695e 670 * @}
EricLew 0:80ee8f3b695e 671 */
EricLew 0:80ee8f3b695e 672 /**
EricLew 0:80ee8f3b695e 673 * @}
EricLew 0:80ee8f3b695e 674 */
EricLew 0:80ee8f3b695e 675 #endif /* HAL_SRAM_MODULE_ENABLED */
EricLew 0:80ee8f3b695e 676
EricLew 0:80ee8f3b695e 677 /**
EricLew 0:80ee8f3b695e 678 * @}
EricLew 0:80ee8f3b695e 679 */
EricLew 0:80ee8f3b695e 680
EricLew 0:80ee8f3b695e 681 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 682