Kamil Krężołek / Mbed 2 deprecated DISCO-F746NG_AUDIO_demo

orang plz

Dependencies:   AUDIO_DISCO_F746NG BSP_DISCO_F746NG SDRAM_DISCO_F746NG mbed

main.cpp@0:3fc742cc8331, 2018-04-20 (annotated)

Committer:
AproxingMan
Date:
Fri Apr 20 19:13:59 2018 +0000
Revision:
0:3fc742cc8331
hejka

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AproxingMan 0:3fc742cc8331 1 #include "mbed.h"
AproxingMan 0:3fc742cc8331 2 #include "AUDIO_DISCO_F746NG.h"
AproxingMan 0:3fc742cc8331 3 #include "SDRAM_DISCO_F746NG.h"
AproxingMan 0:3fc742cc8331 4
AproxingMan 0:3fc742cc8331 5 AUDIO_DISCO_F746NG audio;
AproxingMan 0:3fc742cc8331 6 // audio IN_OUT buffer is stored in the SDRAM, SDRAM needs to be initialized and FMC enabled
AproxingMan 0:3fc742cc8331 7 SDRAM_DISCO_F746NG sdram;
AproxingMan 0:3fc742cc8331 8
AproxingMan 0:3fc742cc8331 9 DigitalOut led_green(LED1);
AproxingMan 0:3fc742cc8331 10 DigitalOut led_red(LED2);
AproxingMan 0:3fc742cc8331 11 Serial pc(USBTX, USBRX);
AproxingMan 0:3fc742cc8331 12
AproxingMan 0:3fc742cc8331 13 typedef enum
AproxingMan 0:3fc742cc8331 14 {
AproxingMan 0:3fc742cc8331 15 BUFFER_OFFSET_NONE = 0,
AproxingMan 0:3fc742cc8331 16 BUFFER_OFFSET_HALF = 1,
AproxingMan 0:3fc742cc8331 17 BUFFER_OFFSET_FULL = 2,
AproxingMan 0:3fc742cc8331 18 }BUFFER_StateTypeDef;
AproxingMan 0:3fc742cc8331 19
AproxingMan 0:3fc742cc8331 20 #define AUDIO_BLOCK_SIZE ((uint32_t)512)
AproxingMan 0:3fc742cc8331 21 #define AUDIO_BUFFER_IN SDRAM_DEVICE_ADDR /* In SDRAM */
AproxingMan 0:3fc742cc8331 22 #define AUDIO_BUFFER_OUT (SDRAM_DEVICE_ADDR + (AUDIO_BLOCK_SIZE * 2)) /* In SDRAM */
AproxingMan 0:3fc742cc8331 23 __IO uint32_t audio_rec_buffer_state = BUFFER_OFFSET_NONE;
AproxingMan 0:3fc742cc8331 24 static uint8_t SetSysClock_PLL_HSE_200MHz();
AproxingMan 0:3fc742cc8331 25 int main()
AproxingMan 0:3fc742cc8331 26 {
AproxingMan 0:3fc742cc8331 27 SetSysClock_PLL_HSE_200MHz();
AproxingMan 0:3fc742cc8331 28 pc.baud(9600);
AproxingMan 0:3fc742cc8331 29
AproxingMan 0:3fc742cc8331 30 pc.printf("\n\nAUDIO LOOPBACK EXAMPLE START:\n");
AproxingMan 0:3fc742cc8331 31 led_red = 0;
AproxingMan 0:3fc742cc8331 32
AproxingMan 0:3fc742cc8331 33 pc.printf("\nAUDIO RECORD INIT OK\n");
AproxingMan 0:3fc742cc8331 34 pc.printf("Microphones sound streamed to headphones\n");
AproxingMan 0:3fc742cc8331 35
AproxingMan 0:3fc742cc8331 36 /* Initialize SDRAM buffers */
AproxingMan 0:3fc742cc8331 37 memset((uint16_t*)AUDIO_BUFFER_IN, 0, AUDIO_BLOCK_SIZE*2);
AproxingMan 0:3fc742cc8331 38 memset((uint16_t*)AUDIO_BUFFER_OUT, 0, AUDIO_BLOCK_SIZE*2);
AproxingMan 0:3fc742cc8331 39 audio_rec_buffer_state = BUFFER_OFFSET_NONE;
AproxingMan 0:3fc742cc8331 40
AproxingMan 0:3fc742cc8331 41 /* Start Recording */
AproxingMan 0:3fc742cc8331 42 audio.IN_Record((uint16_t*)AUDIO_BUFFER_IN, AUDIO_BLOCK_SIZE);
AproxingMan 0:3fc742cc8331 43
AproxingMan 0:3fc742cc8331 44 /* Start Playback */
AproxingMan 0:3fc742cc8331 45 audio.OUT_SetAudioFrameSlot(CODEC_AUDIOFRAME_SLOT_02);
AproxingMan 0:3fc742cc8331 46 audio.OUT_Play((uint16_t*)AUDIO_BUFFER_OUT, AUDIO_BLOCK_SIZE * 2);
AproxingMan 0:3fc742cc8331 47
AproxingMan 0:3fc742cc8331 48
AproxingMan 0:3fc742cc8331 49 while (1) {
AproxingMan 0:3fc742cc8331 50 /* Wait end of half block recording */
AproxingMan 0:3fc742cc8331 51 while(audio_rec_buffer_state == BUFFER_OFFSET_HALF) {
AproxingMan 0:3fc742cc8331 52 }
AproxingMan 0:3fc742cc8331 53 audio_rec_buffer_state = BUFFER_OFFSET_NONE;
AproxingMan 0:3fc742cc8331 54 /* Copy recorded 1st half block */
AproxingMan 0:3fc742cc8331 55 memcpy((uint16_t *)(AUDIO_BUFFER_OUT), (uint16_t *)(AUDIO_BUFFER_IN), AUDIO_BLOCK_SIZE);
AproxingMan 0:3fc742cc8331 56 /* Wait end of one block recording */
AproxingMan 0:3fc742cc8331 57 while(audio_rec_buffer_state == BUFFER_OFFSET_FULL) {
AproxingMan 0:3fc742cc8331 58 }
AproxingMan 0:3fc742cc8331 59 audio_rec_buffer_state = BUFFER_OFFSET_NONE;
AproxingMan 0:3fc742cc8331 60 /* Copy recorded 2nd half block */
AproxingMan 0:3fc742cc8331 61 memcpy((uint16_t *)(AUDIO_BUFFER_OUT + (AUDIO_BLOCK_SIZE)), (uint16_t *)(AUDIO_BUFFER_IN + (AUDIO_BLOCK_SIZE)), AUDIO_BLOCK_SIZE);
AproxingMan 0:3fc742cc8331 62 }
AproxingMan 0:3fc742cc8331 63 }
AproxingMan 0:3fc742cc8331 64 /*-------------------------------------------------------------------------------------
AproxingMan 0:3fc742cc8331 65 Callbacks implementation:
AproxingMan 0:3fc742cc8331 66 the callbacks API are defined __weak in the stm32746g_discovery_audio.c file
AproxingMan 0:3fc742cc8331 67 and their implementation should be done in the user code if they are needed.
AproxingMan 0:3fc742cc8331 68 Below some examples of callback implementations.
AproxingMan 0:3fc742cc8331 69 -------------------------------------------------------------------------------------*/
AproxingMan 0:3fc742cc8331 70 /**
AproxingMan 0:3fc742cc8331 71 * @brief Manages the DMA Transfer complete interrupt.
AproxingMan 0:3fc742cc8331 72 * @param None
AproxingMan 0:3fc742cc8331 73 * @retval None
AproxingMan 0:3fc742cc8331 74 */
AproxingMan 0:3fc742cc8331 75 void BSP_AUDIO_IN_TransferComplete_CallBack(void)
AproxingMan 0:3fc742cc8331 76 {
AproxingMan 0:3fc742cc8331 77 audio_rec_buffer_state = BUFFER_OFFSET_FULL;
AproxingMan 0:3fc742cc8331 78 return;
AproxingMan 0:3fc742cc8331 79 }
AproxingMan 0:3fc742cc8331 80
AproxingMan 0:3fc742cc8331 81 /**
AproxingMan 0:3fc742cc8331 82 * @brief Manages the DMA Half Transfer complete interrupt.
AproxingMan 0:3fc742cc8331 83 * @param None
AproxingMan 0:3fc742cc8331 84 * @retval None
AproxingMan 0:3fc742cc8331 85 */
AproxingMan 0:3fc742cc8331 86 void BSP_AUDIO_IN_HalfTransfer_CallBack(void)
AproxingMan 0:3fc742cc8331 87 {
AproxingMan 0:3fc742cc8331 88 audio_rec_buffer_state = BUFFER_OFFSET_HALF;
AproxingMan 0:3fc742cc8331 89 return;
AproxingMan 0:3fc742cc8331 90 }
AproxingMan 0:3fc742cc8331 91
AproxingMan 0:3fc742cc8331 92 static uint8_t SetSysClock_PLL_HSE_200MHz()
AproxingMan 0:3fc742cc8331 93 {
AproxingMan 0:3fc742cc8331 94 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AproxingMan 0:3fc742cc8331 95 RCC_OscInitTypeDef RCC_OscInitStruct;
AproxingMan 0:3fc742cc8331 96
AproxingMan 0:3fc742cc8331 97 // Enable power clock
AproxingMan 0:3fc742cc8331 98 __PWR_CLK_ENABLE();
AproxingMan 0:3fc742cc8331 99
AproxingMan 0:3fc742cc8331 100 // Enable HSE oscillator and activate PLL with HSE as source
AproxingMan 0:3fc742cc8331 101 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
AproxingMan 0:3fc742cc8331 102 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
AproxingMan 0:3fc742cc8331 103
AproxingMan 0:3fc742cc8331 104 // Warning: this configuration is for a 25 MHz xtal clock only
AproxingMan 0:3fc742cc8331 105 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AproxingMan 0:3fc742cc8331 106 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AproxingMan 0:3fc742cc8331 107 RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
AproxingMan 0:3fc742cc8331 108 RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
AproxingMan 0:3fc742cc8331 109 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 200 MHz (400 MHz / 2)
AproxingMan 0:3fc742cc8331 110 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 50 MHz (400 MHz / 8)
AproxingMan 0:3fc742cc8331 111
AproxingMan 0:3fc742cc8331 112 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
AproxingMan 0:3fc742cc8331 113 {
AproxingMan 0:3fc742cc8331 114 return 0; // FAIL
AproxingMan 0:3fc742cc8331 115 }
AproxingMan 0:3fc742cc8331 116
AproxingMan 0:3fc742cc8331 117 // Activate the OverDrive to reach the 216 MHz Frequency
AproxingMan 0:3fc742cc8331 118 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
AproxingMan 0:3fc742cc8331 119 {
AproxingMan 0:3fc742cc8331 120 return 0; // FAIL
AproxingMan 0:3fc742cc8331 121 }
AproxingMan 0:3fc742cc8331 122
AproxingMan 0:3fc742cc8331 123 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AproxingMan 0:3fc742cc8331 124 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AproxingMan 0:3fc742cc8331 125 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 200 MHz
AproxingMan 0:3fc742cc8331 126 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 200 MHz
AproxingMan 0:3fc742cc8331 127 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 50 MHz
AproxingMan 0:3fc742cc8331 128 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 100 MHz
AproxingMan 0:3fc742cc8331 129
AproxingMan 0:3fc742cc8331 130 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
AproxingMan 0:3fc742cc8331 131 {
AproxingMan 0:3fc742cc8331 132 return 0; // FAIL
AproxingMan 0:3fc742cc8331 133 }
AproxingMan 0:3fc742cc8331 134 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_4);
AproxingMan 0:3fc742cc8331 135 return 1; // OK
AproxingMan 0:3fc742cc8331 136 }