Diff: i2c.h

Revision:

357:f3d48d62e00e

Parent:

356:197c93dc2012

--- a/i2c.h	Sat Feb 10 09:06:26 2018 +0000
+++ b/i2c.h	Sun Apr 03 15:35:53 2022 +0000
@@ -18,18 +18,19 @@
 
 void I2C_busreset()
 {
-    PORTE->PCR[1] &= 0xfffffffb;    //Enabling high slew rates for SDA and SCL lines
-    PORTE->PCR[0] &= 0xfffffffb;    //Enabling high slew rates for SDA and SCL lines
+    PORTE->PCR[24] &= 0xfffffffb;    //Enabling high slew rates for SDA and SCL lines
+    PORTE->PCR[25] &= 0xfffffffb;    //Enabling high slew rates for SDA and SCL lines
     I2C0->C1 &= 0x7f;               //Disabling I2C module
     SIM->SCGC4 &= 0xffffffbf;       //Disabling clock to I2C module
     SIM->SCGC4 |= 0x00000040;       //Enabling clock to I2C module
     I2C0->C1 |= 0x80;               //Enabling I2C module
-    PORTE->PCR[1] |= 0x00000004;    //Disabling high slew rates for SDA and SCL lines
-    PORTE->PCR[0] |= 0x00000004;    //Disabling high slew rates for SDA and SCL lines
+    PORTE->PCR[24] |= 0x00000004;    //Disabling high slew rates for SDA and SCL lines
+    PORTE->PCR[25] |= 0x00000004;    //Disabling high slew rates for SDA and SCL lines
     Thread::wait(1);                //Wait for all I2C registers to be updates to their their values
 }
 bool FCTN_I2C_READ_PL(char *data,int length)       // Returns 0 for success
 {    
+    master.frequency(400000);
     PL_I2C_GPIO = 1;
     read_ack = master.read(addr_pl|1,data,length);
     Thread::wait(1);        //as per tests Thread::wait not required on master side. But its safe to give 1ms 
@@ -67,7 +68,8 @@
 }
 bool FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2)       // Returns 0 for success
 {
-    write_ack = master.write(addr_pl|0x00,data2,tc_len2+1);//address to be defined in payload    
+    master.frequency(400000);
+    write_ack = master.write(addr_pl|0x00,data2,tc_len2);//address to be defined in payload    
     Thread::wait(1);    //As per the tests Thread::wait is not required on master side but its safe to give 1ms
     pdirw1=PTE->PDIR;
     uint8_t i2c_count = 0;
@@ -100,8 +102,9 @@
 bool FCTN_I2C_READ(char *data,int length)       // Returns 0 for success
 {   
  //   gPC.printf("i2C_rd\r\n");
+    master.frequency(400000);
     CDMS_I2C_GPIO = 1;
-    read_ack = master.read(addr_bae|1,data,length);
+    read_ack = master.read(addr_bae|1,data,length); 
     Thread::wait(1);        //as per tests Thread::wait not required on master side. But its safe to give 1ms 
     pdirr1=PTE->PDIR;
     uint8_t i2c_count = 0;    
@@ -123,11 +126,10 @@
             read_ack = 1;
         }
     }
-    else if (read_ack == 1)
+    if (read_ack == 1)
     {
         I2C_busreset();
-        CDMS_I2C_ERR_BAE_COUNTER++;
-        
+        CDMS_I2C_ERR_BAE_COUNTER++;     
     }
  //  gPC.printf("end_12c_RD_\r\n");
     CDMS_I2C_GPIO = 0;
@@ -138,8 +140,9 @@
 bool FCTN_I2C_WRITE(char *data,int tc_len2)       // Returns 0 for success
 {    
    //  gPC.printf("i2C_wr\r\n");
+    master.frequency(400000);
     CDMS_I2C_GPIO = 1;
-    write_ack = master.write(addr_bae|0x00,data,tc_len2);    
+    write_ack = master.write(addr_bae|0x00,data,tc_len2); 
     Thread::wait(1);   //As per the tests Thread::wait is not required on master side but its safe to give 1ms
     pdirw1=PTE->PDIR;
     uint8_t i2c_count = 0;