stm32l4xx_ll_rcc.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_rcc.h
00004   * @author  MCD Application Team
00005   * @version V1.1.0
00006   * @date    16-September-2015
00007   * @brief   Header file of RCC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_RCC_H
00040 #define __STM32L4xx_LL_RCC_H
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048 
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 
00053 #if defined(RCC)
00054 
00055 /** @defgroup RCC_LL RCC
00056   * @{
00057   */
00058 
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
00062   * @{
00063   */
00064 
00065 static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
00066 
00067 /**
00068   * @}
00069   */
00070 
00071 /* Private constants ---------------------------------------------------------*/
00072 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
00073   * @{
00074   */
00075 
00076 /* Defines used for the bit position in the register and perform offsets*/
00077 #define RCC_POSITION_HPRE       (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
00078 #define RCC_POSITION_PPRE1      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
00079 #define RCC_POSITION_PPRE2      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
00080 #define RCC_POSITION_HSICAL     (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL)
00081 #define RCC_POSITION_HSITRIM    (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM)
00082 #define RCC_POSITION_MSICAL     (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)
00083 #define RCC_POSITION_MSITRIM    (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM)
00084 #define RCC_POSITION_PLLN       (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLN)
00085 #define RCC_POSITION_PLLSAI1N   (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)
00086 #define RCC_POSITION_PLLSAI2N   (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)
00087 
00088 /**
00089   * @}
00090   */
00091 
00092 /* Private macros ------------------------------------------------------------*/
00093 
00094 /* Exported types ------------------------------------------------------------*/
00095 /* Exported constants --------------------------------------------------------*/
00096 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
00097   * @{
00098   */
00099 
00100 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
00101   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
00102   * @{
00103   */
00104 #define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC
00105 #define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC
00106 #define LL_RCC_CICR_MSIRDYC                RCC_CICR_MSIRDYC
00107 #define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC
00108 #define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC
00109 #define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC
00110 #define LL_RCC_CICR_PLLSAI1RDYC            RCC_CICR_PLLSAI1RDYC
00111 #define LL_RCC_CICR_PLLSAI2RDYC            RCC_CICR_PLLSAI2RDYC
00112 #define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC
00113 #define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC
00114 /**
00115   * @}
00116   */
00117 
00118 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
00119   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
00120   * @{
00121   */
00122 #define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF
00123 #define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF
00124 #define LL_RCC_CIFR_MSIRDYF                RCC_CIFR_MSIRDYF
00125 #define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF
00126 #define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF
00127 #define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF
00128 #define LL_RCC_CIFR_PLLSAI1RDYF            RCC_CIFR_PLLSAI1RDYF
00129 #define LL_RCC_CIFR_PLLSAI2RDYF            RCC_CIFR_PLLSAI2RDYF
00130 #define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF
00131 #define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF
00132 #define LL_RCC_CSR_FWRSTF                  RCC_CSR_FWRSTF
00133 #define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF
00134 #define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF
00135 #define LL_RCC_CSR_OBLRSTF                 RCC_CSR_OBLRSTF
00136 #define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF
00137 #define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF
00138 #define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF
00139 #define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF
00140 /**
00141   * @}
00142   */
00143 
00144 /** @defgroup RCC_LL_EC_IT IT Defines
00145   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
00146   * @{
00147   */
00148 #define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE
00149 #define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE
00150 #define LL_RCC_CIER_MSIRDYIE               RCC_CIER_MSIRDYIE
00151 #define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE
00152 #define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE
00153 #define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE
00154 #define LL_RCC_CIER_PLLSAI1RDYIE           RCC_CIER_PLLSAI1RDYIE
00155 #define LL_RCC_CIER_PLLSAI2RDYIE           RCC_CIER_PLLSAI2RDYIE
00156 #define LL_RCC_CIER_LSECSSIE               RCC_CIER_LSECSSIE
00157 /**
00158   * @}
00159   */
00160 
00161 /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
00162   * @{
00163   */
00164 #define LL_RCC_LSEDRIVE_LOW                ((uint32_t)0x00000000)  /*!< Xtal mode lower driving capability */
00165 #define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium low driving capability */
00166 #define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium high driving capability */
00167 #define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */
00168 /**
00169   * @}
00170   */
00171 
00172 /** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges
00173   * @{
00174   */
00175 #define LL_RCC_MSIRANGE_0                  RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */
00176 #define LL_RCC_MSIRANGE_1                  RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */
00177 #define LL_RCC_MSIRANGE_2                  RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */
00178 #define LL_RCC_MSIRANGE_3                  RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */
00179 #define LL_RCC_MSIRANGE_4                  RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */
00180 #define LL_RCC_MSIRANGE_5                  RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */
00181 #define LL_RCC_MSIRANGE_6                  RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */
00182 #define LL_RCC_MSIRANGE_7                  RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */
00183 #define LL_RCC_MSIRANGE_8                  RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */
00184 #define LL_RCC_MSIRANGE_9                  RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */
00185 #define LL_RCC_MSIRANGE_10                 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */
00186 #define LL_RCC_MSIRANGE_11                 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */
00187 /**
00188   * @}
00189   */
00190 
00191 /** @defgroup RCC_LL_EC_MSISRANGE  MSI range after Standby mode
00192   * @{
00193   */
00194 #define LL_RCC_MSISRANGE_4                 RCC_CSR_MSISRANGE_1  /*!< MSI = 1 MHz    */
00195 #define LL_RCC_MSISRANGE_5                 RCC_CSR_MSISRANGE_2  /*!< MSI = 2 MHz    */
00196 #define LL_RCC_MSISRANGE_6                 RCC_CSR_MSISRANGE_4  /*!< MSI = 4 MHz    */
00197 #define LL_RCC_MSISRANGE_7                 RCC_CSR_MSISRANGE_8  /*!< MSI = 8 MHz    */
00198 /**
00199   * @}
00200   */
00201 
00202 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE  LSCO Selection
00203   * @{
00204   */
00205 #define LL_RCC_LSCO_CLKSOURCE_LSI          (uint32_t)0x00000000  /*!< LSI selection for low speed clock  */
00206 #define LL_RCC_LSCO_CLKSOURCE_LSE          RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock  */
00207 /**
00208   * @}
00209   */
00210 
00211 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
00212   * @{
00213   */
00214 #define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */
00215 #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
00216 #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
00217 #define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
00218 /**
00219   * @}
00220   */
00221 
00222 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
00223   * @{
00224   */
00225 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */
00226 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00227 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00228 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
00229 /**
00230   * @}
00231   */
00232 
00233 /** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
00234   * @{
00235   */
00236 #define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
00237 #define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
00238 #define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
00239 #define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
00240 #define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
00241 #define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
00242 #define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
00243 #define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
00244 #define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
00245 /**
00246   * @}
00247   */
00248 
00249 /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
00250   * @{
00251   */
00252 #define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
00253 #define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
00254 #define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
00255 #define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
00256 #define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
00257 /**
00258   * @}
00259   */
00260 
00261 /** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
00262   * @{
00263   */
00264 #define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
00265 #define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
00266 #define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
00267 #define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
00268 #define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
00269 /**
00270   * @}
00271   */
00272 
00273 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK  Wakeup from Stop and CSS backup clock selection
00274   * @{
00275   */
00276 #define LL_RCC_STOP_WAKEUPCLOCK_MSI        ((uint32_t)0x00000000)  /*!< MSI selection after wake-up from STOP */
00277 #define LL_RCC_STOP_WAKEUPCLOCK_HSI        RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */
00278 /**
00279   * @}
00280   */
00281 
00282 /** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
00283   * @{
00284   */
00285 #define LL_RCC_MCO1SOURCE_NOCLOCK          ((uint32_t)0x00000000)                 /*!< MCO output disabled, no clock on MCO */
00286 #define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */
00287 #define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_1                      /*!< MSI selection as MCO1 source */
00288 #define LL_RCC_MCO1SOURCE_HSI              (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
00289 #define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */
00290 #define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< PLLCLK selection as MCO1 source */
00291 #define LL_RCC_MCO1SOURCE_LSI              (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */
00292 #define LL_RCC_MCO1SOURCE_LSE              RCC_CFGR_MCOSEL                        /*!< LSE selection as MCO1 source */
00293 /**
00294   * @}
00295   */
00296 
00297 /** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
00298   * @{
00299   */
00300 #define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCO_PRE_1       /*!< MCO not divided */
00301 #define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCO_PRE_2       /*!< MCO divided by 2 */
00302 #define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCO_PRE_4       /*!< MCO divided by 4 */
00303 #define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCO_PRE_8       /*!< MCO divided by 8 */
00304 #define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCO_PRE_16      /*!< MCO divided by 16 */
00305 /**
00306   * @}
00307   */
00308 
00309 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE  Peripheral USART clock source selection
00310   * @{
00311   */
00312 #define LL_RCC_USART1_CLKSOURCE_PCLK2      (uint32_t)((RCC_CCIPR_USART1SEL << 16) | 0x00000000)
00313 #define LL_RCC_USART1_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_0)
00314 #define LL_RCC_USART1_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL_1)
00315 #define LL_RCC_USART1_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART1SEL << 16) | RCC_CCIPR_USART1SEL)
00316 #define LL_RCC_USART2_CLKSOURCE_PCLK1      (uint32_t)((RCC_CCIPR_USART2SEL << 16) | 0x00000000)
00317 #define LL_RCC_USART2_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_0)
00318 #define LL_RCC_USART2_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL_1)
00319 #define LL_RCC_USART2_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART2SEL << 16) | RCC_CCIPR_USART2SEL)
00320 #define LL_RCC_USART3_CLKSOURCE_PCLK1      (uint32_t)((RCC_CCIPR_USART3SEL << 16) | 0x00000000)
00321 #define LL_RCC_USART3_CLKSOURCE_SYSCLK     (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_0)
00322 #define LL_RCC_USART3_CLKSOURCE_HSI        (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL_1)
00323 #define LL_RCC_USART3_CLKSOURCE_LSE        (uint32_t)((RCC_CCIPR_USART3SEL << 16) | RCC_CCIPR_USART3SEL)
00324 /**
00325   * @}
00326   */
00327 
00328 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE  Peripheral UART clock source selection
00329   * @{
00330   */
00331 #define LL_RCC_UART4_CLKSOURCE_PCLK1       (uint32_t)((RCC_CCIPR_UART4SEL << 16) | 0x00000000)
00332 #define LL_RCC_UART4_CLKSOURCE_SYSCLK      (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_0)
00333 #define LL_RCC_UART4_CLKSOURCE_HSI         (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL_1)
00334 #define LL_RCC_UART4_CLKSOURCE_LSE         (uint32_t)((RCC_CCIPR_UART4SEL << 16) | RCC_CCIPR_UART4SEL)
00335 #define LL_RCC_UART5_CLKSOURCE_PCLK1       (uint32_t)((RCC_CCIPR_UART5SEL << 16) | 0x00000000)
00336 #define LL_RCC_UART5_CLKSOURCE_SYSCLK      (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_0)
00337 #define LL_RCC_UART5_CLKSOURCE_HSI         (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL_1)
00338 #define LL_RCC_UART5_CLKSOURCE_LSE         (uint32_t)((RCC_CCIPR_UART5SEL << 16) | RCC_CCIPR_UART5SEL)
00339 /**
00340   * @}
00341   */
00342 
00343 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE  Peripheral LPUART clock source selection
00344   * @{
00345   */
00346 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1     (uint32_t)0x00000000
00347 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0
00348 #define LL_RCC_LPUART1_CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1
00349 #define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR_LPUART1SEL
00350 /**
00351   * @}
00352   */
00353 
00354 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE  Peripheral I2C clock source selection
00355   * @{
00356   */
00357 #define LL_RCC_I2C1_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000 >> 4))
00358 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4))
00359 #define LL_RCC_I2C1_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4))
00360 #define LL_RCC_I2C2_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (0x00000000 >> 4))
00361 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_0 >> 4))
00362 #define LL_RCC_I2C2_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_1 >> 4))
00363 #define LL_RCC_I2C3_CLKSOURCE_PCLK1        (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000 >> 4))
00364 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK       (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4))
00365 #define LL_RCC_I2C3_CLKSOURCE_HSI          (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4))
00366 /**
00367   * @}
00368   */
00369 
00370 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
00371   * @{
00372   */
00373 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000 >> 16))
00374 #define LL_RCC_LPTIM1_CLKSOURCE_LSI        (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16))
00375 #define LL_RCC_LPTIM1_CLKSOURCE_HSI        (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16))
00376 #define LL_RCC_LPTIM1_CLKSOURCE_LSE        (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16))
00377 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1      (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000 >> 16))
00378 #define LL_RCC_LPTIM2_CLKSOURCE_LSI        (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16))
00379 #define LL_RCC_LPTIM2_CLKSOURCE_HSI        (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16))
00380 #define LL_RCC_LPTIM2_CLKSOURCE_LSE        (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16))
00381 /**
00382   * @}
00383   */
00384 
00385 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE  Peripheral SAI clock source selection
00386   * @{
00387   */
00388 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI1      (uint32_t)(RCC_CCIPR_SAI1SEL | (0x00000000 >> 16))
00389 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI2      (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16))
00390 #define LL_RCC_SAI1_CLKSOURCE_PLL          (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16))
00391 #define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16))
00392 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI1      (uint32_t)(RCC_CCIPR_SAI2SEL | (0x00000000 >> 16))
00393 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI2      (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16))
00394 #define LL_RCC_SAI2_CLKSOURCE_PLL          (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16))
00395 #define LL_RCC_SAI2_CLKSOURCE_PIN          (uint32_t)(RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16))
00396 /**
00397   * @}
00398   */
00399 
00400 /** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE  Peripheral SDMMC clock source selection
00401   * @{
00402   */
00403 #define LL_RCC_SDMMC1_CLKSOURCE_NONE       (uint32_t)(0x00000000)
00404 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1    (uint32_t)(RCC_CCIPR_CLK48SEL_0)
00405 #define LL_RCC_SDMMC1_CLKSOURCE_PLL        (uint32_t)(RCC_CCIPR_CLK48SEL_1)
00406 #define LL_RCC_SDMMC1_CLKSOURCE_MSI        (uint32_t)(RCC_CCIPR_CLK48SEL)
00407 /**
00408   * @}
00409   */
00410 
00411 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
00412   * @{
00413   */
00414 #define LL_RCC_RNG_CLKSOURCE_NONE          (uint32_t)(0x00000000)
00415 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1       (uint32_t)(RCC_CCIPR_CLK48SEL_0)
00416 #define LL_RCC_RNG_CLKSOURCE_PLL           (uint32_t)(RCC_CCIPR_CLK48SEL_1)
00417 #define LL_RCC_RNG_CLKSOURCE_MSI           (uint32_t)(RCC_CCIPR_CLK48SEL)
00418 /**
00419   * @}
00420   */
00421 
00422 #if defined(USB_OTG_FS)
00423 /** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
00424   * @{
00425   */
00426 #define LL_RCC_USB_CLKSOURCE_NONE          (uint32_t)(0x00000000)
00427 #define LL_RCC_USB_CLKSOURCE_PLLSAI1       (uint32_t)(RCC_CCIPR_CLK48SEL_0)
00428 #define LL_RCC_USB_CLKSOURCE_PLL           (uint32_t)(RCC_CCIPR_CLK48SEL_1)
00429 #define LL_RCC_USB_CLKSOURCE_MSI           (uint32_t)(RCC_CCIPR_CLK48SEL)
00430 /**
00431   * @}
00432   */
00433 
00434 #endif /* USB_OTG_FS */
00435 
00436 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
00437   * @{
00438   */
00439 #define LL_RCC_ADC_CLKSOURCE_NONE          (uint32_t)(0x00000000)
00440 #define LL_RCC_ADC_CLKSOURCE_PLLSAI1       (uint32_t)(RCC_CCIPR_ADCSEL_0)
00441 #define LL_RCC_ADC_CLKSOURCE_PLLSAI2       (uint32_t)(RCC_CCIPR_ADCSEL_1)
00442 #define LL_RCC_ADC_CLKSOURCE_SYSCLK        (uint32_t)(RCC_CCIPR_ADCSEL)
00443 /**
00444   * @}
00445   */
00446 
00447 /** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE  Peripheral SWPMI clock source selection
00448   * @{
00449   */
00450 #define LL_RCC_SWPMI1_CLKSOURCE_PCLK       (uint32_t)(0x00000000)
00451 #define LL_RCC_SWPMI1_CLKSOURCE_HSI        (uint32_t)(RCC_CCIPR_SWPMI1SEL)
00452 /**
00453   * @}
00454   */
00455 
00456 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM clock source selection
00457   * @{
00458   */
00459 #define LL_RCC_DFSDM_CLKSOURCE_PCLK        (uint32_t)(0x00000000)
00460 #define LL_RCC_DFSDM_CLKSOURCE_SYSCLK      (uint32_t)(RCC_CCIPR_DFSDMSEL)
00461 /**
00462   * @}
00463   */
00464 
00465 /** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
00466   * @{
00467   */
00468 #define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL
00469 #define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL
00470 #define LL_RCC_USART3_CLKSOURCE            RCC_CCIPR_USART3SEL
00471 /**
00472   * @}
00473   */
00474 
00475 /** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
00476   * @{
00477   */
00478 #define LL_RCC_UART4_CLKSOURCE             RCC_CCIPR_UART4SEL
00479 #define LL_RCC_UART5_CLKSOURCE             RCC_CCIPR_UART5SEL
00480 /**
00481   * @}
00482   */
00483 
00484 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
00485   * @{
00486   */
00487 #define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL
00488 /**
00489   * @}
00490   */
00491 
00492 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
00493   * @{
00494   */
00495 #define LL_RCC_I2C1_CLKSOURCE              RCC_CCIPR_I2C1SEL
00496 #define LL_RCC_I2C2_CLKSOURCE              RCC_CCIPR_I2C2SEL
00497 #define LL_RCC_I2C3_CLKSOURCE              RCC_CCIPR_I2C3SEL
00498 /**
00499   * @}
00500   */
00501 
00502 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
00503   * @{
00504   */
00505 #define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL
00506 /**
00507   * @}
00508   */
00509 
00510 /** @defgroup RCC_LL_EC_SAI1  Peripheral SAI get clock source
00511   * @{
00512   */
00513 #define LL_RCC_SAI1_CLKSOURCE              RCC_CCIPR_SAI1SEL
00514 #define LL_RCC_SAI2_CLKSOURCE              RCC_CCIPR_SAI2SEL
00515 /**
00516   * @}
00517   */
00518 
00519 /** @defgroup RCC_LL_EC_SDMMC1  Peripheral SDMMC get clock source
00520   * @{
00521   */
00522 #define LL_RCC_SDMMC1_CLKSOURCE            RCC_CCIPR_CLK48SEL
00523 /**
00524   * @}
00525   */
00526 
00527 /** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
00528   * @{
00529   */
00530 #define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_CLK48SEL
00531 /**
00532   * @}
00533   */
00534 
00535 #if defined(USB_OTG_FS)
00536 /** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
00537   * @{
00538   */
00539 #define LL_RCC_USB_CLKSOURCE               RCC_CCIPR_CLK48SEL
00540 /**
00541   * @}
00542   */
00543 
00544 #endif /* USB_OTG_FS */
00545 
00546 /** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source
00547   * @{
00548   */
00549 #define LL_RCC_ADC_CLKSOURCE               RCC_CCIPR_ADCSEL
00550 /**
00551   * @}
00552   */
00553 
00554 /** @defgroup RCC_LL_EC_SWPMI1  Peripheral SWPMI get clock source
00555   * @{
00556   */
00557 #define LL_RCC_SWPMI1_CLKSOURCE            RCC_CCIPR_SWPMI1SEL
00558 /**
00559   * @}
00560   */
00561 
00562 /** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
00563   * @{
00564   */
00565 #define LL_RCC_DFSDM_CLKSOURCE             RCC_CCIPR_DFSDMSEL
00566 /**
00567   * @}
00568   */
00569 
00570 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
00571   * @{
00572   */
00573 #define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000)  /*!< No clock used as RTC clock */
00574 #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
00575 #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
00576 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */
00577 /**
00578   * @}
00579   */
00580 
00581 /** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLSAI1 and PLLSAI2 entry clock source
00582   * @{
00583   */
00584 #define LL_RCC_PLLSOURCE_NONE              (uint32_t)0x00000000    /*!< No clock */
00585 #define LL_RCC_PLLSOURCE_MSI               RCC_PLLCFGR_PLLSRC_MSI  /*!< MSI clock selected as PLL entry clock source */
00586 #define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI clock selected as PLL entry clock source */
00587 #define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
00588 /**
00589   * @}
00590   */
00591 
00592 /** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLSAI1 and PLLSAI2 division factor
00593   * @{
00594   */
00595 #define LL_RCC_PLLM_DIV_1                  ((uint32_t)0x00000000)
00596 #define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_0)
00597 #define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1)
00598 #define LL_RCC_PLLM_DIV_4                  ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0))
00599 #define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2)
00600 #define LL_RCC_PLLM_DIV_6                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0))
00601 #define LL_RCC_PLLM_DIV_7                  ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1))
00602 #define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM)
00603 /**
00604   * @}
00605   */
00606 
00607 /** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
00608   * @{
00609   */
00610 #define LL_RCC_PLLR_DIV_2                  ((uint32_t)0x00000000)
00611 #define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_0)
00612 #define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_1)
00613 #define LL_RCC_PLLR_DIV_8                  (RCC_PLLCFGR_PLLR)
00614 /**
00615   * @}
00616   */
00617 
00618 /** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
00619   * @{
00620   */
00621 #define LL_RCC_PLLP_DIV_7                  ((uint32_t)0x00000000)
00622 #define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLP)
00623 /**
00624   * @}
00625   */
00626 
00627 /** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
00628   * @{
00629   */
00630 #define LL_RCC_PLLQ_DIV_2                  ((uint32_t)0x00000000)
00631 #define LL_RCC_PLLQ_DIV_4                  (RCC_PLLCFGR_PLLQ_0)
00632 #define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_1)
00633 #define LL_RCC_PLLQ_DIV_8                  (RCC_PLLCFGR_PLLQ)
00634 /**
00635   * @}
00636   */
00637 
00638 /** @defgroup RCC_LL_EC_PLLSAI1Q  PLLSAI1 division factor (PLLSAI1Q)
00639   * @{
00640   */
00641 #define LL_RCC_PLLSAI1Q_DIV2               ((uint32_t)0x00000000)
00642 #define LL_RCC_PLLSAI1Q_DIV4               ((uint32_t)0x00200000)
00643 #define LL_RCC_PLLSAI1Q_DIV6               ((uint32_t)0x00400000)
00644 #define LL_RCC_PLLSAI1Q_DIV8               (RCC_PLLSAI1CFGR_PLLSAI1Q)
00645 /**
00646   * @}
00647   */
00648 
00649 /** @defgroup RCC_LL_EC_PLLSAI1P  PLLSAI1 division factor (PLLSAI1P)
00650   * @{
00651   */
00652 #define LL_RCC_PLLSAI1P_DIV7               ((uint32_t)0x00000000)
00653 #define LL_RCC_PLLSAI1P_DIV17              (RCC_PLLSAI1CFGR_PLLSAI1P)
00654 /**
00655   * @}
00656   */
00657 
00658 /** @defgroup RCC_LL_EC_PLLSAI1R  PLLSAI1 division factor (PLLSAI1R)
00659   * @{
00660   */
00661 #define LL_RCC_PLLSAI1R_DIV2               ((uint32_t)0x00000000)
00662 #define LL_RCC_PLLSAI1R_DIV4               ((uint32_t)0x02000000)
00663 #define LL_RCC_PLLSAI1R_DIV6               ((uint32_t)0x04000000)
00664 #define LL_RCC_PLLSAI1R_DIV8               (RCC_PLLSAI1CFGR_PLLSAI1R)
00665 /**
00666   * @}
00667   */
00668 
00669 /** @defgroup RCC_LL_EC_PLLSAI2P  PLLSAI2 division factor (PLLSAI2P)
00670   * @{
00671   */
00672 #define LL_RCC_PLLSAI2P_DIV7               ((uint32_t)0x00000000)
00673 #define LL_RCC_PLLSAI2P_DIV17              (RCC_PLLSAI2CFGR_PLLSAI2P)
00674 /**
00675   * @}
00676   */
00677 
00678 /** @defgroup RCC_LL_EC_PLLSAI2R  PLLSAI2 division factor (PLLSAI2R)
00679   * @{
00680   */
00681 #define LL_RCC_PLLSAI2R_DIV2               ((uint32_t)0x00000000)
00682 #define LL_RCC_PLLSAI2R_DIV4               (((uint32_t)0x02000000))
00683 #define LL_RCC_PLLSAI2R_DIV6               (((uint32_t)0x04000000))
00684 #define LL_RCC_PLLSAI2R_DIV8               (RCC_PLLSAI2CFGR_PLLSAI2R)
00685 /**
00686   * @}
00687   */
00688 
00689 /** @defgroup RCC_LL_EC_MSIRANGESEL  MSI clock range selection
00690   * @{
00691   */
00692 #define LL_RCC_MSIRANGESEL_STANDBY         (uint32_t)0 /*!< MSI Range is provided by MSISRANGE */
00693 #define LL_RCC_MSIRANGESEL_RUN             (uint32_t)1 /*!< MSI Range is provided by MSIRANGE */
00694 /**
00695   * @}
00696   */
00697 
00698 /**
00699   * @}
00700   */
00701 
00702 /* Exported macro ------------------------------------------------------------*/
00703 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
00704   * @{
00705   */
00706 
00707 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
00708   * @{
00709   */
00710 
00711 /**
00712   * @brief  Write a value in RCC register
00713   * @param  __REG__ Register to be written
00714   * @param  __VALUE__ Value to be written in the register
00715   * @retval None
00716   */
00717 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
00718 
00719 /**
00720   * @brief  Read a value in RCC register
00721   * @param  __REG__ Register to be read
00722   * @retval Register value
00723   */
00724 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
00725 /**
00726   * @}
00727   */
00728 
00729 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
00730   * @{
00731   */
00732 
00733 /**
00734   * @brief  Helper macro to calculate the PLLCLK frequency
00735   * @note ex: __LL_RCC_CALC_PLLCLK_FREQ(HSE_VALUE,LL_RCC_PLL_GetDivider(),
00736   *             LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
00737   * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
00738   * @param  __PLLM__: This parameter can be one of the following values:
00739   *         @arg @ref LL_RCC_PLLM_DIV_1
00740   *         @arg @ref LL_RCC_PLLM_DIV_2
00741   *         @arg @ref LL_RCC_PLLM_DIV_3
00742   *         @arg @ref LL_RCC_PLLM_DIV_4
00743   *         @arg @ref LL_RCC_PLLM_DIV_5
00744   *         @arg @ref LL_RCC_PLLM_DIV_6
00745   *         @arg @ref LL_RCC_PLLM_DIV_7
00746   *         @arg @ref LL_RCC_PLLM_DIV_8
00747   * @param  __PLLN__ Between 8 and 86
00748   * @param  __PLLR__: This parameter can be one of the following values:
00749   *         @arg @ref LL_RCC_PLLR_DIV_2
00750   *         @arg @ref LL_RCC_PLLR_DIV_4
00751   *         @arg @ref LL_RCC_PLLR_DIV_6
00752   *         @arg @ref LL_RCC_PLLR_DIV_8
00753   * @retval PLL clock frequency (in Hz)
00754   */
00755 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> 4) + 1)) * (__PLLN__) / \
00756                    ((((__PLLR__) >> 25 ) + 1 ) * 2))
00757 
00758 /**
00759   * @brief  Helper macro to calculate the HCLK frequency
00760   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
00761   * @param  __AHBPRESCALER__: This parameter can be one of the following values:
00762   *         @arg @ref LL_RCC_SYSCLK_DIV_1
00763   *         @arg @ref LL_RCC_SYSCLK_DIV_2
00764   *         @arg @ref LL_RCC_SYSCLK_DIV_4
00765   *         @arg @ref LL_RCC_SYSCLK_DIV_8
00766   *         @arg @ref LL_RCC_SYSCLK_DIV_16
00767   *         @arg @ref LL_RCC_SYSCLK_DIV_64
00768   *         @arg @ref LL_RCC_SYSCLK_DIV_128
00769   *         @arg @ref LL_RCC_SYSCLK_DIV_256
00770   *         @arg @ref LL_RCC_SYSCLK_DIV_512
00771   * @retval HCLK clock frequency (in Hz)
00772   */
00773 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[(__AHBPRESCALER__) >>  RCC_POSITION_HPRE])
00774 
00775 /**
00776   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
00777   * @param  __HCLKFREQ__ HCLK frequency
00778   * @param  __APB1PRESCALER__: This parameter can be one of the following values:
00779   *         @arg @ref LL_RCC_APB1_DIV_1
00780   *         @arg @ref LL_RCC_APB1_DIV_2
00781   *         @arg @ref LL_RCC_APB1_DIV_4
00782   *         @arg @ref LL_RCC_APB1_DIV_8
00783   *         @arg @ref LL_RCC_APB1_DIV_16
00784   * @retval PCLK1 clock frequency (in Hz)
00785   */
00786 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >>  RCC_POSITION_PPRE1])
00787 
00788 /**
00789   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
00790   * @param  __HCLKFREQ__ HCLK frequency
00791   * @param  __APB2PRESCALER__: This parameter can be one of the following values:
00792   *         @arg @ref LL_RCC_APB2_DIV_1
00793   *         @arg @ref LL_RCC_APB2_DIV_2
00794   *         @arg @ref LL_RCC_APB2_DIV_4
00795   *         @arg @ref LL_RCC_APB2_DIV_8
00796   *         @arg @ref LL_RCC_APB2_DIV_16
00797   * @retval PCLK2 clock frequency (in Hz)
00798   */
00799 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >>  RCC_POSITION_PPRE2])
00800 
00801 /**
00802   * @brief  Helper macro to calculate the MSI frequency (in Hz)
00803   * @note: __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect
00804   * @note: if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
00805   *        __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby
00806   *        else by LL_RCC_MSI_GetRange
00807   *        ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
00808   *              (LL_RCC_MSI_IsEnabledRangeSelect()?
00809   *               LL_RCC_MSI_GetRange():
00810   *               LL_RCC_MSI_GetRangeAfterStandby())
00811   * @param  __MSISEL__: This parameter can be one of the following values:
00812   *         @arg @ref LL_RCC_MSIRANGESEL_STANDBY
00813   *         @arg @ref LL_RCC_MSIRANGESEL_RUN
00814   * @param  __MSIRANGE__: This parameter can be one of the following values:
00815   *         @arg @ref LL_RCC_MSIRANGE_0
00816   *         @arg @ref LL_RCC_MSIRANGE_1
00817   *         @arg @ref LL_RCC_MSIRANGE_2
00818   *         @arg @ref LL_RCC_MSIRANGE_3
00819   *         @arg @ref LL_RCC_MSIRANGE_4
00820   *         @arg @ref LL_RCC_MSIRANGE_5
00821   *         @arg @ref LL_RCC_MSIRANGE_6
00822   *         @arg @ref LL_RCC_MSIRANGE_7
00823   *         @arg @ref LL_RCC_MSIRANGE_8
00824   *         @arg @ref LL_RCC_MSIRANGE_9
00825   *         @arg @ref LL_RCC_MSIRANGE_10
00826   *         @arg @ref LL_RCC_MSIRANGE_11
00827   *         @arg @ref LL_RCC_MSISRANGE_4
00828   *         @arg @ref LL_RCC_MSISRANGE_5
00829   *         @arg @ref LL_RCC_MSISRANGE_6
00830   *         @arg @ref LL_RCC_MSISRANGE_7
00831   * @retval MSI clock frequency (in Hz)
00832   */
00833 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__)   (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
00834                            (MSIRangeTable[(__MSIRANGE__) >> 8]) : \
00835                            (MSIRangeTable[(__MSIRANGE__) >> 4]))
00836 
00837 /**
00838   * @}
00839   */
00840 
00841 /**
00842   * @}
00843   */
00844 
00845 /* Exported functions --------------------------------------------------------*/
00846 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
00847   * @{
00848   */
00849 /** @defgroup RCC_LL_EF_HSE HSE
00850   * @{
00851   */
00852 
00853 /**
00854   * @brief  Enable the Clock Security System.
00855   * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
00856   * @retval None
00857   */
00858 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
00859 {
00860   SET_BIT(RCC->CR, RCC_CR_CSSON);
00861 }
00862 
00863 /**
00864   * @brief  Enable HSE external oscillator (HSE Bypass)
00865   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
00866   * @retval None
00867   */
00868 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
00869 {
00870   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
00871 }
00872 
00873 /**
00874   * @brief  Disable HSE external oscillator (HSE Bypass)
00875   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
00876   * @retval None
00877   */
00878 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
00879 {
00880   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00881 }
00882 
00883 /**
00884   * @brief  Enable HSE crystal oscillator (HSE ON)
00885   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
00886   * @retval None
00887   */
00888 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
00889 {
00890   SET_BIT(RCC->CR, RCC_CR_HSEON);
00891 }
00892 
00893 /**
00894   * @brief  Disable HSE crystal oscillator (HSE ON)
00895   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
00896   * @retval None
00897   */
00898 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
00899 {
00900   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
00901 }
00902 
00903 /**
00904   * @brief  Check if HSE oscillator Ready
00905   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
00906   * @retval State of bit (1 or 0).
00907   */
00908 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
00909 {
00910   return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
00911 }
00912 
00913 /**
00914   * @}
00915   */
00916 
00917 /** @defgroup RCC_LL_EF_HSI HSI
00918   * @{
00919   */
00920 
00921 /**
00922   * @brief  Enable HSI even in stop mode
00923   * @note HSI oscillator is forced ON even in Stop mode
00924   * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode
00925   * @retval None
00926   */
00927 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
00928 {
00929   SET_BIT(RCC->CR, RCC_CR_HSIKERON);
00930 }
00931 
00932 /**
00933   * @brief  Disable HSI in stop mode
00934   * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode
00935   * @retval None
00936   */
00937 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
00938 {
00939   CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
00940 }
00941 
00942 /**
00943   * @brief  Enable HSI oscillator
00944   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
00945   * @retval None
00946   */
00947 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
00948 {
00949   SET_BIT(RCC->CR, RCC_CR_HSION);
00950 }
00951 
00952 /**
00953   * @brief  Disable HSI oscillator
00954   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
00955   * @retval None
00956   */
00957 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
00958 {
00959   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
00960 }
00961 
00962 /**
00963   * @brief  Check if HSI clock divided by 4
00964   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
00965   * @retval State of bit (1 or 0).
00966   */
00967 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
00968 {
00969   return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
00970 }
00971 
00972 /**
00973   * @brief  Enable HSI Automatic from stop mode
00974   * @rmtoll CR           HSIASFS       LL_RCC_HSI_EnableAutoFromStop
00975   * @retval None
00976   */
00977 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
00978 {
00979   SET_BIT(RCC->CR, RCC_CR_HSIASFS);
00980 }
00981 
00982 /**
00983   * @brief  Disable HSI Automatic from stop mode
00984   * @rmtoll CR           HSIASFS       LL_RCC_HSI_DisableAutoFromStop
00985   * @retval None
00986   */
00987 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
00988 {
00989   CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
00990 }
00991 
00992 /**
00993   * @brief  Get HSI Calibration value
00994   * @note When HSITRIM is written, HSICAL is updated with the sum of
00995   *       HSITRIM and the factory trim value
00996   * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration
00997   * @retval Between 0x00 and 0xFF
00998   */
00999 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
01000 {
01001   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL);
01002 }
01003 
01004 /**
01005   * @brief  Set HSI Calibration trimming
01006   * @note user-programmable trimming value that is added to the HSICAL
01007   * @note Default value is 16, which, when added to the HSICAL value,
01008   *       should trim the HSI to 16 MHz +/- 1 %
01009   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
01010   * @param  Value Between 0 and 31
01011   * @retval None
01012   */
01013 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
01014 {
01015   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM);
01016 }
01017 
01018 /**
01019   * @brief  Get HSI Calibration trimming
01020   * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
01021   * @retval Between 0 and 31
01022   */
01023 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
01024 {
01025   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM);
01026 }
01027 
01028 /**
01029   * @}
01030   */
01031 
01032 /** @defgroup RCC_LL_EF_LSE LSE
01033   * @{
01034   */
01035 
01036 /**
01037   * @brief  Enable  Low Speed External (LSE) crystal.
01038   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
01039   * @retval None
01040   */
01041 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
01042 {
01043   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01044 }
01045 
01046 /**
01047   * @brief  Disable  Low Speed External (LSE) crystal.
01048   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
01049   * @retval None
01050   */
01051 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
01052 {
01053   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
01054 }
01055 
01056 /**
01057   * @brief  Enable external clock source (LSE bypass).
01058   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
01059   * @retval None
01060   */
01061 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
01062 {
01063   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01064 }
01065 
01066 /**
01067   * @brief  Disable external clock source (LSE bypass).
01068   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
01069   * @retval None
01070   */
01071 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
01072 {
01073   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
01074 }
01075 
01076 /**
01077   * @brief  Set LSE oscillator drive capability
01078   * @note The oscillator is in Xtal mode when it is not in bypass mode.
01079   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
01080   * @param  LSEDrive This parameter can be one of the following values:
01081   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01082   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01083   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01084   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01085   * @retval None
01086   */
01087 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
01088 {
01089   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
01090 }
01091 
01092 /**
01093   * @brief  Get LSE oscillator drive capability
01094   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
01095   * @retval Returned value can be one of the following values:
01096   *         @arg @ref LL_RCC_LSEDRIVE_LOW
01097   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
01098   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
01099   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
01100   */
01101 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
01102 {
01103   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
01104 }
01105 
01106 /**
01107   * @brief  Enable Clock security system on LSE.
01108   * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS
01109   * @retval None
01110   */
01111 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
01112 {
01113   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
01114 }
01115 
01116 /**
01117   * @brief  Check if LSE oscillator Ready
01118   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
01119   * @retval State of bit (1 or 0).
01120   */
01121 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
01122 {
01123   return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
01124 }
01125 
01126 /**
01127   * @brief  Check if CSS on LSE failure Detection
01128   * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected
01129   * @retval State of bit (1 or 0).
01130   */
01131 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
01132 {
01133   return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
01134 }
01135 
01136 /**
01137   * @}
01138   */
01139 
01140 /** @defgroup RCC_LL_EF_LSI LSI
01141   * @{
01142   */
01143 
01144 /**
01145   * @brief  Enable LSI Oscillator
01146   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
01147   * @retval None
01148   */
01149 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
01150 {
01151   SET_BIT(RCC->CSR, RCC_CSR_LSION);
01152 }
01153 
01154 /**
01155   * @brief  Disable LSI Oscillator
01156   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
01157   * @retval None
01158   */
01159 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
01160 {
01161   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
01162 }
01163 
01164 /**
01165   * @brief  Check if LSI is Ready
01166   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
01167   * @retval State of bit (1 or 0).
01168   */
01169 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
01170 {
01171   return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
01172 }
01173 
01174 /**
01175   * @}
01176   */
01177 
01178 /** @defgroup RCC_LL_EF_MSI MSI
01179   * @{
01180   */
01181 
01182 /**
01183   * @brief  Enable MSI oscillator
01184   * @rmtoll CR           MSION         LL_RCC_MSI_Enable
01185   * @retval None
01186   */
01187 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
01188 {
01189   SET_BIT(RCC->CR, RCC_CR_MSION);
01190 }
01191 
01192 /**
01193   * @brief  Disable MSI oscillator
01194   * @rmtoll CR           MSION         LL_RCC_MSI_Disable
01195   * @retval None
01196   */
01197 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
01198 {
01199   CLEAR_BIT(RCC->CR, RCC_CR_MSION);
01200 }
01201 
01202 /**
01203   * @brief  Check if MSI oscillator Ready
01204   * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady
01205   * @retval State of bit (1 or 0).
01206   */
01207 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
01208 {
01209   return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
01210 }
01211 
01212 /**
01213   * @brief  Enable MSI PLL-mode (Hardware auto calibration with LSE)
01214   * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
01215   *       and ready (LSERDY set by hardware)
01216   * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
01217   *       ready
01218   * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_EnablePLLMode
01219   * @retval None
01220   */
01221 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
01222 {
01223   SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
01224 }
01225 
01226 /**
01227   * @brief  Disable MSI-PLL mode
01228   * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
01229   *       the Clock Security System on LSE detects a LSE failure
01230   * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_DisablePLLMode
01231   * @retval None
01232   */
01233 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
01234 {
01235   CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
01236 }
01237 
01238 /**
01239   * @brief  Enable MSI clock range selection with MSIRANGE register
01240   * @note Write 0 has no effect. After a standby or a reset
01241   *       MSIRGSEL is at 0 and the MSI range value is provided by
01242   *       MSISRANGE
01243   * @rmtoll CR           MSIRGSEL      LL_RCC_MSI_EnableRangeSelection
01244   * @retval None
01245   */
01246 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
01247 {
01248   SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
01249 }
01250 
01251 /**
01252   * @brief  Check if MSI clock range is selected with MSIRANGE register
01253   * @rmtoll CR           MSIRGSEL      LL_RCC_MSI_IsEnabledRangeSelect
01254   * @retval State of bit (1 or 0).
01255   */
01256 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
01257 {
01258   return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
01259 }
01260 
01261 /**
01262   * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
01263   * @rmtoll CR           MSIRANGE      LL_RCC_MSI_SetRange
01264   * @param  Range This parameter can be one of the following values:
01265   *         @arg @ref LL_RCC_MSIRANGE_0
01266   *         @arg @ref LL_RCC_MSIRANGE_1
01267   *         @arg @ref LL_RCC_MSIRANGE_2
01268   *         @arg @ref LL_RCC_MSIRANGE_3
01269   *         @arg @ref LL_RCC_MSIRANGE_4
01270   *         @arg @ref LL_RCC_MSIRANGE_5
01271   *         @arg @ref LL_RCC_MSIRANGE_6
01272   *         @arg @ref LL_RCC_MSIRANGE_7
01273   *         @arg @ref LL_RCC_MSIRANGE_8
01274   *         @arg @ref LL_RCC_MSIRANGE_9
01275   *         @arg @ref LL_RCC_MSIRANGE_10
01276   *         @arg @ref LL_RCC_MSIRANGE_11
01277   * @retval None
01278   */
01279 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
01280 {
01281   MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
01282 }
01283 
01284 /**
01285   * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
01286   * @rmtoll CR           MSIRANGE      LL_RCC_MSI_GetRange
01287   * @retval Returned value can be one of the following values:
01288   *         @arg @ref LL_RCC_MSIRANGE_0
01289   *         @arg @ref LL_RCC_MSIRANGE_1
01290   *         @arg @ref LL_RCC_MSIRANGE_2
01291   *         @arg @ref LL_RCC_MSIRANGE_3
01292   *         @arg @ref LL_RCC_MSIRANGE_4
01293   *         @arg @ref LL_RCC_MSIRANGE_5
01294   *         @arg @ref LL_RCC_MSIRANGE_6
01295   *         @arg @ref LL_RCC_MSIRANGE_7
01296   *         @arg @ref LL_RCC_MSIRANGE_8
01297   *         @arg @ref LL_RCC_MSIRANGE_9
01298   *         @arg @ref LL_RCC_MSIRANGE_10
01299   *         @arg @ref LL_RCC_MSIRANGE_11
01300   */
01301 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
01302 {
01303   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
01304 }
01305 
01306 /**
01307   * @brief  Configure MSI range used after standby
01308   * @rmtoll CSR          MSISRANGE     LL_RCC_MSI_SetRangeAfterStandby
01309   * @param  Range This parameter can be one of the following values:
01310   *         @arg @ref LL_RCC_MSISRANGE_4
01311   *         @arg @ref LL_RCC_MSISRANGE_5
01312   *         @arg @ref LL_RCC_MSISRANGE_6
01313   *         @arg @ref LL_RCC_MSISRANGE_7
01314   * @retval None
01315   */
01316 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
01317 {
01318   MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
01319 }
01320 
01321 /**
01322   * @brief  Get MSI range used after standby
01323   * @rmtoll CSR          MSISRANGE     LL_RCC_MSI_GetRangeAfterStandby
01324   * @retval Returned value can be one of the following values:
01325   *         @arg @ref LL_RCC_MSISRANGE_4
01326   *         @arg @ref LL_RCC_MSISRANGE_5
01327   *         @arg @ref LL_RCC_MSISRANGE_6
01328   *         @arg @ref LL_RCC_MSISRANGE_7
01329   */
01330 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
01331 {
01332   return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
01333 }
01334 
01335 /**
01336   * @brief  Get MSI Calibration value
01337   * @note When MSITRIM is written, MSICAL is updated with the sum of
01338   *       MSITRIM and the factory trim value
01339   * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration
01340   * @retval Between 0 and 255
01341   */
01342 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
01343 {
01344   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL);
01345 }
01346 
01347 /**
01348   * @brief  Set MSI Calibration trimming
01349   * @note user-programmable trimming value that is added to the MSICAL
01350   * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming
01351   * @param  Value Between 0 and 255
01352   * @retval None
01353   */
01354 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
01355 {
01356   MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM);
01357 }
01358 
01359 /**
01360   * @brief  Get MSI Calibration trimming
01361   * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming
01362   * @retval Between 0 and 255
01363   */
01364 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
01365 {
01366   return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM);
01367 }
01368 
01369 /**
01370   * @}
01371   */
01372 
01373 /** @defgroup RCC_LL_EF_LSCO LSCO
01374   * @{
01375   */
01376 
01377 /**
01378   * @brief  Enable Low speed clock
01379   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Enable
01380   * @retval None
01381   */
01382 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
01383 {
01384   SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01385 }
01386 
01387 /**
01388   * @brief  Disable Low speed clock
01389   * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Disable
01390   * @retval None
01391   */
01392 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
01393 {
01394   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
01395 }
01396 
01397 /**
01398   * @brief  Configure Low speed clock  selection
01399   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_SetSource
01400   * @param  Source This parameter can be one of the following values:
01401   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
01402   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
01403   * @retval None
01404   */
01405 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
01406 {
01407   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
01408 }
01409 
01410 /**
01411   * @brief  Get Low speed clock  selection
01412   * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_GetSource
01413   * @retval Returned value can be one of the following values:
01414   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
01415   *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
01416   */
01417 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
01418 {
01419   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
01420 }
01421 
01422 /**
01423   * @}
01424   */
01425 
01426 /** @defgroup RCC_LL_EF_System System
01427   * @{
01428   */
01429 
01430 /**
01431   * @brief  Configure the system clock source
01432   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
01433   * @param  Source This parameter can be one of the following values:
01434   *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
01435   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
01436   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
01437   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
01438   * @retval None
01439   */
01440 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
01441 {
01442   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
01443 }
01444 
01445 /**
01446   * @brief  Get the system clock source
01447   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
01448   * @retval Returned value can be one of the following values:
01449   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
01450   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
01451   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
01452   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
01453   */
01454 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
01455 {
01456   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
01457 }
01458 
01459 /**
01460   * @brief  Set AHB prescaler
01461   * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
01462   * @param  Prescaler This parameter can be one of the following values:
01463   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01464   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01465   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01466   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01467   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01468   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01469   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01470   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01471   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01472   * @retval None
01473   */
01474 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
01475 {
01476   MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
01477 }
01478 
01479 /**
01480   * @brief  Set APB1 prescaler
01481   * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
01482   * @param  Prescaler This parameter can be one of the following values:
01483   *         @arg @ref LL_RCC_APB1_DIV_1
01484   *         @arg @ref LL_RCC_APB1_DIV_2
01485   *         @arg @ref LL_RCC_APB1_DIV_4
01486   *         @arg @ref LL_RCC_APB1_DIV_8
01487   *         @arg @ref LL_RCC_APB1_DIV_16
01488   * @retval None
01489   */
01490 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
01491 {
01492   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
01493 }
01494 
01495 /**
01496   * @brief  Set APB2 prescaler
01497   * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
01498   * @param  Prescaler This parameter can be one of the following values:
01499   *         @arg @ref LL_RCC_APB2_DIV_1
01500   *         @arg @ref LL_RCC_APB2_DIV_2
01501   *         @arg @ref LL_RCC_APB2_DIV_4
01502   *         @arg @ref LL_RCC_APB2_DIV_8
01503   *         @arg @ref LL_RCC_APB2_DIV_16
01504   * @retval None
01505   */
01506 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
01507 {
01508   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
01509 }
01510 
01511 /**
01512   * @brief  Get AHB prescaler
01513   * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
01514   * @retval Returned value can be one of the following values:
01515   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01516   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01517   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01518   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01519   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01520   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01521   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01522   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01523   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01524   */
01525 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
01526 {
01527   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
01528 }
01529 
01530 /**
01531   * @brief  Get APB1 prescaler
01532   * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
01533   * @retval Returned value can be one of the following values:
01534   *         @arg @ref LL_RCC_APB1_DIV_1
01535   *         @arg @ref LL_RCC_APB1_DIV_2
01536   *         @arg @ref LL_RCC_APB1_DIV_4
01537   *         @arg @ref LL_RCC_APB1_DIV_8
01538   *         @arg @ref LL_RCC_APB1_DIV_16
01539   */
01540 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
01541 {
01542   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
01543 }
01544 
01545 /**
01546   * @brief  Get APB2 prescaler
01547   * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
01548   * @retval Returned value can be one of the following values:
01549   *         @arg @ref LL_RCC_APB2_DIV_1
01550   *         @arg @ref LL_RCC_APB2_DIV_2
01551   *         @arg @ref LL_RCC_APB2_DIV_4
01552   *         @arg @ref LL_RCC_APB2_DIV_8
01553   *         @arg @ref LL_RCC_APB2_DIV_16
01554   */
01555 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
01556 {
01557   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
01558 }
01559 
01560 /**
01561   * @brief  Set Clock After Wake-Up From Stop mode
01562   * @rmtoll CFGR         STOPWUCK      LL_RCC_SetClkAfterWakeFromStop
01563   * @param  Clock This parameter can be one of the following values:
01564   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
01565   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
01566   * @retval None
01567   */
01568 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
01569 {
01570   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
01571 }
01572 
01573 /**
01574   * @brief  Get Clock After Wake-Up From Stop mode
01575   * @rmtoll CFGR         STOPWUCK      LL_RCC_GetClkAfterWakeFromStop
01576   * @retval Returned value can be one of the following values:
01577   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
01578   *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
01579   */
01580 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
01581 {
01582   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
01583 }
01584 
01585 /**
01586   * @}
01587   */
01588 
01589 /** @defgroup RCC_LL_EF_MCO MCO
01590   * @{
01591   */
01592 
01593 /**
01594   * @brief  Configure MCOx
01595   * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\n
01596   *         CFGR         MCO_PRE       LL_RCC_ConfigMCO
01597   * @param  MCOxSource This parameter can be one of the following values:
01598   *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
01599   *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
01600   *         @arg @ref LL_RCC_MCO1SOURCE_MSI
01601   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
01602   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
01603   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
01604   *         @arg @ref LL_RCC_MCO1SOURCE_LSI
01605   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
01606   * @param  MCOxPrescaler This parameter can be one of the following values:
01607   *         @arg @ref LL_RCC_MCO1_DIV_1
01608   *         @arg @ref LL_RCC_MCO1_DIV_2
01609   *         @arg @ref LL_RCC_MCO1_DIV_4
01610   *         @arg @ref LL_RCC_MCO1_DIV_8
01611   *         @arg @ref LL_RCC_MCO1_DIV_16
01612   * @retval None
01613   */
01614 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
01615 {
01616   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE, MCOxSource | MCOxPrescaler);
01617 }
01618 
01619 /**
01620   * @}
01621   */
01622 
01623 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
01624   * @{
01625   */
01626 
01627 /**
01628   * @brief  Configure USARTx clock source
01629   * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource
01630   * @param  USARTxSource This parameter can be one of the following values:
01631   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
01632   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
01633   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
01634   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
01635   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
01636   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
01637   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
01638   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
01639   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
01640   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
01641   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
01642   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
01643   * @retval None
01644   */
01645 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
01646 {
01647   MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
01648 }
01649 
01650 /**
01651   * @brief  Configure UARTx clock source
01652   * @rmtoll CCIPR        UARTxSEL      LL_RCC_SetUARTClockSource
01653   * @param  UARTxSource This parameter can be one of the following values:
01654   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
01655   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
01656   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
01657   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
01658   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
01659   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
01660   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
01661   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
01662   * @retval None
01663   */
01664 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
01665 {
01666   MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
01667 }
01668 
01669 /**
01670   * @brief  Configure LPUART1x clock source
01671   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource
01672   * @param  LPUARTxSource This parameter can be one of the following values:
01673   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
01674   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
01675   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
01676   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
01677   * @retval None
01678   */
01679 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
01680 {
01681   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
01682 }
01683 
01684 /**
01685   * @brief  Configure I2Cx clock source
01686   * @rmtoll CCIPR        I2CxSEL       LL_RCC_SetI2CClockSource
01687   * @param  I2CxSource This parameter can be one of the following values:
01688   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
01689   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
01690   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
01691   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
01692   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
01693   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
01694   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
01695   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
01696   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
01697   * @retval None
01698   */
01699 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
01700 {
01701   MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000), ((I2CxSource << 4) & 0x000FF000));
01702 }
01703 
01704 /**
01705   * @brief  Configure LPTIMx clock source
01706   * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_SetLPTIMClockSource
01707   * @param  LPTIMxSource This parameter can be one of the following values:
01708   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
01709   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
01710   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
01711   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
01712   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
01713   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
01714   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
01715   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
01716   * @retval None
01717   */
01718 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
01719 {
01720   MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000), (LPTIMxSource << 16));
01721 }
01722 
01723 /**
01724   * @brief  Configure SAIx clock source
01725   * @rmtoll CCIPR        SAIxSEL       LL_RCC_SetSAIClockSource
01726   * @param  SAIxSource This parameter can be one of the following values:
01727   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
01728   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2
01729   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
01730   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
01731   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1
01732   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2
01733   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL
01734   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
01735   * @retval None
01736   */
01737 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
01738 {
01739   MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000), (SAIxSource << 16));
01740 }
01741 
01742 /**
01743   * @brief  Configure SDMMC1 clock source
01744   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetSDMMCClockSource
01745   * @param  SDMMCxSource This parameter can be one of the following values:
01746   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
01747   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
01748   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
01749   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
01750   * @retval None
01751   */
01752 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
01753 {
01754   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
01755 }
01756 
01757 /**
01758   * @brief  Configure RNG clock source
01759   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetRNGClockSource
01760   * @param  RNGxSource This parameter can be one of the following values:
01761   *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
01762   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
01763   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
01764   *         @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
01765   * @retval None
01766   */
01767 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
01768 {
01769   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
01770 }
01771 
01772 #if defined(USB_OTG_FS)
01773 /**
01774   * @brief  Configure USB clock source
01775   * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetUSBClockSource
01776   * @param  USBxSource This parameter can be one of the following values:
01777   *         @arg @ref LL_RCC_USB_CLKSOURCE_NONE
01778   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
01779   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
01780   *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI
01781   * @retval None
01782   */
01783 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
01784 {
01785   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
01786 }
01787 #endif /* USB_OTG_FS */
01788 
01789 /**
01790   * @brief  Configure ADC clock source
01791   * @rmtoll CCIPR        ADCSEL        LL_RCC_SetADCClockSource
01792   * @param  ADCxSource This parameter can be one of the following values:
01793   *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
01794   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
01795   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2
01796   *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
01797   * @retval None
01798   */
01799 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
01800 {
01801   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
01802 }
01803 
01804 /**
01805   * @brief  Configure SWPMI clock source
01806   * @rmtoll CCIPR        SWPMI1SEL     LL_RCC_SetSWPMIClockSource
01807   * @param  SWPMIxSource This parameter can be one of the following values:
01808   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
01809   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
01810   * @retval None
01811   */
01812 __STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
01813 {
01814   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
01815 }
01816 
01817 /**
01818   * @brief  Configure DFSDM clock source
01819   * @rmtoll CCIPR        DFSDMSEL      LL_RCC_SetDFSDMClockSource
01820   * @param  DFSDMxSource This parameter can be one of the following values:
01821   *         @arg @ref LL_RCC_DFSDM_CLKSOURCE_PCLK
01822   *         @arg @ref LL_RCC_DFSDM_CLKSOURCE_SYSCLK
01823   * @retval None
01824   */
01825 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
01826 {
01827   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDMSEL, DFSDMxSource);
01828 }
01829 
01830 /**
01831   * @brief  Get USARTx clock source
01832   * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource
01833   * @param  USARTx This parameter can be one of the following values:
01834   *         @arg @ref LL_RCC_USART1_CLKSOURCE
01835   *         @arg @ref LL_RCC_USART2_CLKSOURCE
01836   *         @arg @ref LL_RCC_USART3_CLKSOURCE
01837   * @retval Returned value can be one of the following values:
01838   *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
01839   *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
01840   *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
01841   *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
01842   *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
01843   *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
01844   *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
01845   *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
01846   *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
01847   *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
01848   *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
01849   *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
01850   */
01851 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
01852 {
01853   return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16));
01854 }
01855 
01856 /**
01857   * @brief  Get UARTx clock source
01858   * @rmtoll CCIPR        UARTxSEL      LL_RCC_GetUARTClockSource
01859   * @param  UARTx This parameter can be one of the following values:
01860   *         @arg @ref LL_RCC_UART4_CLKSOURCE
01861   *         @arg @ref LL_RCC_UART5_CLKSOURCE
01862   * @retval Returned value can be one of the following values:
01863   *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
01864   *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
01865   *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
01866   *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
01867   *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
01868   *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
01869   *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
01870   *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
01871   */
01872 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
01873 {
01874   return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16));
01875 }
01876 
01877 /**
01878   * @brief  Get LPUARTx clock source
01879   * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource
01880   * @param  LPUARTx This parameter can be one of the following values:
01881   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
01882   * @retval Returned value can be one of the following values:
01883   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
01884   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
01885   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
01886   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
01887   */
01888 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
01889 {
01890   return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
01891 }
01892 
01893 /**
01894   * @brief  Get I2Cx clock source
01895   * @rmtoll CCIPR        I2CxSEL       LL_RCC_GetI2CClockSource
01896   * @param  I2Cx This parameter can be one of the following values:
01897   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
01898   *         @arg @ref LL_RCC_I2C2_CLKSOURCE
01899   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
01900   * @retval Returned value can be one of the following values:
01901   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
01902   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
01903   *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
01904   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
01905   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
01906   *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
01907   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
01908   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
01909   *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
01910   */
01911 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
01912 {
01913   return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4));
01914 }
01915 
01916 /**
01917   * @brief  Get LPTIMx clock source
01918   * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_GetLPTIMClockSource
01919   * @param  LPTIMx This parameter can be one of the following values:
01920   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
01921   * @retval Returned value can be one of the following values:
01922   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
01923   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
01924   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
01925   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
01926   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
01927   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
01928   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
01929   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
01930   */
01931 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
01932 {
01933   return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16 | LPTIMx);
01934 }
01935 
01936 /**
01937   * @brief  Get SAIx clock source
01938   * @rmtoll CCIPR        SAIxSEL       LL_RCC_GetSAIClockSource
01939   * @param  SAIx This parameter can be one of the following values:
01940   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
01941   *         @arg @ref LL_RCC_SAI2_CLKSOURCE
01942   * @retval Returned value can be one of the following values:
01943   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
01944   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2
01945   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
01946   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
01947   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1
01948   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2
01949   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL
01950   *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
01951   */
01952 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
01953 {
01954   return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16 | SAIx);
01955 }
01956 
01957 /**
01958   * @brief  Get SDMMCx clock source
01959   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetSDMMCClockSource
01960   * @param  SDMMCx This parameter can be one of the following values:
01961   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE
01962   * @retval Returned value can be one of the following values:
01963   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
01964   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
01965   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
01966   *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
01967   */
01968 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
01969 {
01970   return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
01971 }
01972 
01973 /**
01974   * @brief  Get RNGx clock source
01975   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetRNGClockSource
01976   * @param  RNGx This parameter can be one of the following values:
01977   *         @arg @ref LL_RCC_RNG_CLKSOURCE
01978   * @retval Returned value can be one of the following values:
01979   *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
01980   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
01981   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
01982   *         @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
01983   */
01984 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
01985 {
01986   return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
01987 }
01988 
01989 #if defined(USB_OTG_FS)
01990 /**
01991   * @brief  Get USBx clock source
01992   * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetUSBClockSource
01993   * @param  USBx This parameter can be one of the following values:
01994   *         @arg @ref LL_RCC_USB_CLKSOURCE
01995   * @retval Returned value can be one of the following values:
01996   *         @arg @ref LL_RCC_USB_CLKSOURCE_NONE
01997   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
01998   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
01999   *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI
02000   */
02001 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
02002 {
02003   return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
02004 }
02005 #endif /* USB_OTG_FS */
02006 
02007 /**
02008   * @brief  Get ADCx clock source
02009   * @rmtoll CCIPR        ADCSEL        LL_RCC_GetADCClockSource
02010   * @param  ADCx This parameter can be one of the following values:
02011   *         @arg @ref LL_RCC_ADC_CLKSOURCE
02012   * @retval Returned value can be one of the following values:
02013   *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
02014   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
02015   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2
02016   *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
02017   */
02018 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
02019 {
02020   return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
02021 }
02022 
02023 /**
02024   * @brief  Get SWPMIx clock source
02025   * @rmtoll CCIPR        SWPMI1SEL     LL_RCC_GetSWPMIClockSource
02026   * @param  SPWMIx This parameter can be one of the following values:
02027   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE
02028   * @retval Returned value can be one of the following values:
02029   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
02030   *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
02031   */
02032 __STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
02033 {
02034   return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
02035 }
02036 
02037 /**
02038   * @brief  Get DFSDMx clock source
02039   * @rmtoll CCIPR        DFSDMSEL      LL_RCC_GetDFSDMClockSource
02040   * @param  DFSDMx This parameter can be one of the following values:
02041   *         @arg @ref LL_RCC_DFSDM_CLKSOURCE
02042   * @retval Returned value can be one of the following values:
02043   *         @arg @ref LL_RCC_DFSDM_CLKSOURCE_PCLK
02044   *         @arg @ref LL_RCC_DFSDM_CLKSOURCE_SYSCLK
02045   */
02046 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
02047 {
02048   return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
02049 }
02050 
02051 /**
02052   * @}
02053   */
02054 
02055 /** @defgroup RCC_LL_EF_RTC RTC
02056   * @{
02057   */
02058 
02059 /**
02060   * @brief  Set RTC Clock Source
02061   * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
02062   *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
02063   *       set). The BDRST bit can be used to reset them.
02064   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
02065   * @param  Source This parameter can be one of the following values:
02066   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02067   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02068   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02069   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02070   * @retval None
02071   */
02072 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
02073 {
02074   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
02075 }
02076 
02077 /**
02078   * @brief  Get RTC Clock Source
02079   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
02080   * @retval Returned value can be one of the following values:
02081   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
02082   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
02083   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
02084   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
02085   */
02086 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
02087 {
02088   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
02089 }
02090 
02091 /**
02092   * @brief  Enable RTC
02093   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
02094   * @retval None
02095   */
02096 __STATIC_INLINE void LL_RCC_EnableRTC(void)
02097 {
02098   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02099 }
02100 
02101 /**
02102   * @brief  Disable RTC
02103   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
02104   * @retval None
02105   */
02106 __STATIC_INLINE void LL_RCC_DisableRTC(void)
02107 {
02108   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
02109 }
02110 
02111 /**
02112   * @brief  Check if RTC has been enabled or not
02113   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
02114   * @retval State of bit (1 or 0).
02115   */
02116 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
02117 {
02118   return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
02119 }
02120 
02121 /**
02122   * @brief  Force the Backup domain reset
02123   * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
02124   * @retval None
02125   */
02126 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
02127 {
02128   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02129 }
02130 
02131 /**
02132   * @brief  Release the Backup domain reset
02133   * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
02134   * @retval None
02135   */
02136 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
02137 {
02138   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
02139 }
02140 
02141 /**
02142   * @}
02143   */
02144 
02145 /** @defgroup RCC_LL_EF_PLL PLL
02146   * @{
02147   */
02148 
02149 /**
02150   * @brief  Enable PLL
02151   * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
02152   * @retval None
02153   */
02154 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
02155 {
02156   SET_BIT(RCC->CR, RCC_CR_PLLON);
02157 }
02158 
02159 /**
02160   * @brief  Disable PLL
02161   * @note Cannot be disabled if the PLL clock is used as the system clock
02162   * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
02163   * @retval None
02164   */
02165 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
02166 {
02167   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
02168 }
02169 
02170 /**
02171   * @brief  Check if PLL Ready
02172   * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
02173   * @retval State of bit (1 or 0).
02174   */
02175 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
02176 {
02177   return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
02178 }
02179 
02180 /**
02181   * @brief  Configure PLL used for SYSCLK Domain
02182   * @note PLL Source and PLLM Divider can be written only when PLL,
02183   *       PLLSAI1 and PLLSAI2 are disabled
02184   * @note PLLN/PLLR can be written only when PLL is disabled
02185   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
02186   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
02187   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
02188   *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS
02189   * @param  Source This parameter can be one of the following values:
02190   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02191   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02192   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02193   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02194   * @param  PLLM This parameter can be one of the following values:
02195   *         @arg @ref LL_RCC_PLLM_DIV_1
02196   *         @arg @ref LL_RCC_PLLM_DIV_2
02197   *         @arg @ref LL_RCC_PLLM_DIV_3
02198   *         @arg @ref LL_RCC_PLLM_DIV_4
02199   *         @arg @ref LL_RCC_PLLM_DIV_5
02200   *         @arg @ref LL_RCC_PLLM_DIV_6
02201   *         @arg @ref LL_RCC_PLLM_DIV_7
02202   *         @arg @ref LL_RCC_PLLM_DIV_8
02203   * @param  PLLN Between 8 and 86
02204   * @param  PLLR This parameter can be one of the following values:
02205   *         @arg @ref LL_RCC_PLLR_DIV_2
02206   *         @arg @ref LL_RCC_PLLR_DIV_4
02207   *         @arg @ref LL_RCC_PLLR_DIV_6
02208   *         @arg @ref LL_RCC_PLLR_DIV_8
02209   * @retval None
02210   */
02211 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
02212 {
02213   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
02214              Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLR);
02215 }
02216 
02217 /**
02218   * @brief  Configure PLL used for SAI domain clock
02219   * @note PLL Source and PLLM Divider can be written only when PLL,
02220   *       PLLSAI1 and PLLSAI2 are disabled
02221   * @note PLLN/PLLP can be written only when PLL is disabled
02222   * @note This  can be selected for SAI1 or SAI2
02223   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\n
02224   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\n
02225   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\n
02226   *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SAI
02227   * @param  Source This parameter can be one of the following values:
02228   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02229   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02230   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02231   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02232   * @param  PLLM This parameter can be one of the following values:
02233   *         @arg @ref LL_RCC_PLLM_DIV_1
02234   *         @arg @ref LL_RCC_PLLM_DIV_2
02235   *         @arg @ref LL_RCC_PLLM_DIV_3
02236   *         @arg @ref LL_RCC_PLLM_DIV_4
02237   *         @arg @ref LL_RCC_PLLM_DIV_5
02238   *         @arg @ref LL_RCC_PLLM_DIV_6
02239   *         @arg @ref LL_RCC_PLLM_DIV_7
02240   *         @arg @ref LL_RCC_PLLM_DIV_8
02241   * @param  PLLN Between 8 and 86
02242   * @param  PLLP This parameter can be one of the following values:
02243   *         @arg @ref LL_RCC_PLLP_DIV_7
02244   *         @arg @ref LL_RCC_PLLP_DIV_17
02245   * @retval None
02246   */
02247 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
02248 {
02249   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
02250              Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLP);
02251 }
02252 
02253 /**
02254   * @brief  Configure PLL used for 48Mhz domain clock
02255   * @note PLL Source and PLLM Divider can be written only when PLL,
02256   *       PLLSAI1 and PLLSAI2 are disabled
02257   * @note PLLN/PLLQ can be written only when PLL is disabled
02258   * @note This  can be selected for USB, RNG, SDMMC
02259   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
02260   *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
02261   *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
02262   *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
02263   * @param  Source This parameter can be one of the following values:
02264   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02265   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02266   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02267   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02268   * @param  PLLM This parameter can be one of the following values:
02269   *         @arg @ref LL_RCC_PLLM_DIV_1
02270   *         @arg @ref LL_RCC_PLLM_DIV_2
02271   *         @arg @ref LL_RCC_PLLM_DIV_3
02272   *         @arg @ref LL_RCC_PLLM_DIV_4
02273   *         @arg @ref LL_RCC_PLLM_DIV_5
02274   *         @arg @ref LL_RCC_PLLM_DIV_6
02275   *         @arg @ref LL_RCC_PLLM_DIV_7
02276   *         @arg @ref LL_RCC_PLLM_DIV_8
02277   * @param  PLLN Between 8 and 86
02278   * @param  PLLQ This parameter can be one of the following values:
02279   *         @arg @ref LL_RCC_PLLQ_DIV_2
02280   *         @arg @ref LL_RCC_PLLQ_DIV_4
02281   *         @arg @ref LL_RCC_PLLQ_DIV_6
02282   *         @arg @ref LL_RCC_PLLQ_DIV_8
02283   * @retval None
02284   */
02285 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
02286 {
02287   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
02288              Source | PLLM | PLLN << RCC_POSITION_PLLN | PLLQ);
02289 }
02290 
02291 /**
02292   * @brief  Get Main PLL multiplication factor for VCO
02293   * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
02294   * @retval Between 8 and 86
02295   */
02296 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
02297 {
02298   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_POSITION_PLLN);
02299 }
02300 
02301 /**
02302   * @brief  Get Main PLL division factor for PLLP
02303   * @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
02304   * @rmtoll PLLCFGR      PLLP          LL_RCC_PLL_GetP
02305   * @retval Returned value can be one of the following values:
02306   *         @arg @ref LL_RCC_PLLP_DIV_7
02307   *         @arg @ref LL_RCC_PLLP_DIV_17
02308   */
02309 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
02310 {
02311   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
02312 }
02313 
02314 /**
02315   * @brief  Get Main PLL division factor for PLLQ
02316   * @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
02317   * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
02318   * @retval Returned value can be one of the following values:
02319   *         @arg @ref LL_RCC_PLLQ_DIV_2
02320   *         @arg @ref LL_RCC_PLLQ_DIV_4
02321   *         @arg @ref LL_RCC_PLLQ_DIV_6
02322   *         @arg @ref LL_RCC_PLLQ_DIV_8
02323   */
02324 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
02325 {
02326   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
02327 }
02328 
02329 /**
02330   * @brief  Get Main PLL division factor for PLLR
02331   * @note used for PLLCLK (system clock)
02332   * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
02333   * @retval Returned value can be one of the following values:
02334   *         @arg @ref LL_RCC_PLLR_DIV_2
02335   *         @arg @ref LL_RCC_PLLR_DIV_4
02336   *         @arg @ref LL_RCC_PLLR_DIV_6
02337   *         @arg @ref LL_RCC_PLLR_DIV_8
02338   */
02339 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
02340 {
02341   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
02342 }
02343 
02344 /**
02345   * @brief  Get the oscillator used as PLL clock source.
02346   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
02347   * @retval Returned value can be one of the following values:
02348   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02349   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02350   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02351   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02352   */
02353 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
02354 {
02355   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
02356 }
02357 
02358 /**
02359   * @brief  Get Division factor for the main PLL and other PLL
02360   * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
02361   * @retval Returned value can be one of the following values:
02362   *         @arg @ref LL_RCC_PLLM_DIV_1
02363   *         @arg @ref LL_RCC_PLLM_DIV_2
02364   *         @arg @ref LL_RCC_PLLM_DIV_3
02365   *         @arg @ref LL_RCC_PLLM_DIV_4
02366   *         @arg @ref LL_RCC_PLLM_DIV_5
02367   *         @arg @ref LL_RCC_PLLM_DIV_6
02368   *         @arg @ref LL_RCC_PLLM_DIV_7
02369   *         @arg @ref LL_RCC_PLLM_DIV_8
02370   */
02371 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
02372 {
02373   return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
02374 }
02375 
02376 /**
02377   * @brief  Enable PLL output mapped on SAI domain clock
02378   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_SAI
02379   * @retval None
02380   */
02381 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
02382 {
02383   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
02384 }
02385 
02386 /**
02387   * @brief  Disable PLL output mapped on SAI domain clock
02388   * @note Cannot be disabled if the PLL clock is used as the system
02389   *       clock
02390   * @note In order to save power, when the PLLCLK  of the PLL is
02391   *       not used,  should be 0
02392   * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_SAI
02393   * @retval None
02394   */
02395 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
02396 {
02397   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
02398 }
02399 
02400 /**
02401   * @brief  Enable PLL output mapped on 48MHz domain clock
02402   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_48M
02403   * @retval None
02404   */
02405 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
02406 {
02407   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
02408 }
02409 
02410 /**
02411   * @brief  Disable PLL output mapped on 48MHz domain clock
02412   * @note Cannot be disabled if the PLL clock is used as the system
02413   *       clock
02414   * @note In order to save power, when the PLLCLK  of the PLL is
02415   *       not used,  should be 0
02416   * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_48M
02417   * @retval None
02418   */
02419 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
02420 {
02421   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
02422 }
02423 
02424 /**
02425   * @brief  Enable PLL output mapped on SYSCLK domain
02426   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS
02427   * @retval None
02428   */
02429 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
02430 {
02431   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
02432 }
02433 
02434 /**
02435   * @brief  Disable PLL output mapped on SYSCLK domain
02436   * @note Cannot be disabled if the PLL clock is used as the system
02437   *       clock
02438   * @note In order to save power, when the PLLCLK  of the PLL is
02439   *       not used, Main PLL  should be 0
02440   * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_DisableDomain_SYS
02441   * @retval None
02442   */
02443 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
02444 {
02445   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
02446 }
02447 
02448 /**
02449   * @}
02450   */
02451 
02452 /** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
02453   * @{
02454   */
02455 
02456 /**
02457   * @brief  Enable PLLSAI1
02458   * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Enable
02459   * @retval None
02460   */
02461 __STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
02462 {
02463   SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
02464 }
02465 
02466 /**
02467   * @brief  Disable PLLSAI1
02468   * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Disable
02469   * @retval None
02470   */
02471 __STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
02472 {
02473   CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
02474 }
02475 
02476 /**
02477   * @brief  Check if PLLSAI1 Ready
02478   * @rmtoll CR           PLLSAI1RDY    LL_RCC_PLLSAI1_IsReady
02479   * @retval State of bit (1 or 0).
02480   */
02481 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
02482 {
02483   return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
02484 }
02485 
02486 /**
02487   * @brief  Configure PLLSAI1 used for 48Mhz domain clock
02488   * @note PLL Source and PLLM Divider can be written only when PLL,
02489   *       PLLSAI1 and PLLSAI2 are disabled
02490   * @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
02491   * @note This  can be selected for USB, RNG, SDMMC
02492   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_48M\n
02493   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_48M\n
02494   *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_48M\n
02495   *         PLLSAI1CFGR  PLLSAI1Q      LL_RCC_PLLSAI1_ConfigDomain_48M
02496   * @param  Source This parameter can be one of the following values:
02497   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02498   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02499   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02500   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02501   * @param  PLLM This parameter can be one of the following values:
02502   *         @arg @ref LL_RCC_PLLM_DIV_1
02503   *         @arg @ref LL_RCC_PLLM_DIV_2
02504   *         @arg @ref LL_RCC_PLLM_DIV_3
02505   *         @arg @ref LL_RCC_PLLM_DIV_4
02506   *         @arg @ref LL_RCC_PLLM_DIV_5
02507   *         @arg @ref LL_RCC_PLLM_DIV_6
02508   *         @arg @ref LL_RCC_PLLM_DIV_7
02509   *         @arg @ref LL_RCC_PLLM_DIV_8
02510   * @param  PLLN Between 8 and 86
02511   * @param  PLLQ This parameter can be one of the following values:
02512   *         @arg @ref LL_RCC_PLLSAI1Q_DIV2
02513   *         @arg @ref LL_RCC_PLLSAI1Q_DIV4
02514   *         @arg @ref LL_RCC_PLLSAI1Q_DIV6
02515   *         @arg @ref LL_RCC_PLLSAI1Q_DIV8
02516   * @retval None
02517   */
02518 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
02519 {
02520   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
02521   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_POSITION_PLLSAI1N | PLLQ);
02522 }
02523 
02524 /**
02525   * @brief  Configure PLLSAI1 used for SAI domain clock
02526   * @note PLL Source and PLLM Divider can be written only when PLL,
02527   *       PLLSAI1 and PLLSAI2 are disabled
02528   * @note PLLN/PLLP can be written only when PLLSAI1 is disabled
02529   * @note This  can be selected for SAI1 or SAI2
02530   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_SAI\n
02531   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_SAI\n
02532   *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_SAI\n
02533   *         PLLSAI1CFGR  PLLSAI1P      LL_RCC_PLLSAI1_ConfigDomain_SAI
02534   * @param  Source This parameter can be one of the following values:
02535   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02536   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02537   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02538   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02539   * @param  PLLM This parameter can be one of the following values:
02540   *         @arg @ref LL_RCC_PLLM_DIV_1
02541   *         @arg @ref LL_RCC_PLLM_DIV_2
02542   *         @arg @ref LL_RCC_PLLM_DIV_3
02543   *         @arg @ref LL_RCC_PLLM_DIV_4
02544   *         @arg @ref LL_RCC_PLLM_DIV_5
02545   *         @arg @ref LL_RCC_PLLM_DIV_6
02546   *         @arg @ref LL_RCC_PLLM_DIV_7
02547   *         @arg @ref LL_RCC_PLLM_DIV_8
02548   * @param  PLLN Between 8 and 86
02549   * @param  PLLP This parameter can be one of the following values:
02550   *         @arg @ref LL_RCC_PLLSAI1P_DIV7
02551   *         @arg @ref LL_RCC_PLLSAI1P_DIV17
02552   * @retval None
02553   */
02554 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
02555 {
02556   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
02557   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_POSITION_PLLSAI1N | PLLP);
02558 }
02559 
02560 /**
02561   * @brief  Configure PLLSAI1 used for ADC domain clock
02562   * @note PLL Source and PLLM Divider can be written only when PLL,
02563   *       PLLSAI1 and PLLSAI2 are disabled
02564   * @note PLLN/PLLR can be written only when PLLSAI1 is disabled
02565   * @note This  can be selected for ADC
02566   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_ADC\n
02567   *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_ADC\n
02568   *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_ADC\n
02569   *         PLLSAI1CFGR  PLLSAI1R      LL_RCC_PLLSAI1_ConfigDomain_ADC
02570   * @param  Source This parameter can be one of the following values:
02571   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02572   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02573   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02574   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02575   * @param  PLLM This parameter can be one of the following values:
02576   *         @arg @ref LL_RCC_PLLM_DIV_1
02577   *         @arg @ref LL_RCC_PLLM_DIV_2
02578   *         @arg @ref LL_RCC_PLLM_DIV_3
02579   *         @arg @ref LL_RCC_PLLM_DIV_4
02580   *         @arg @ref LL_RCC_PLLM_DIV_5
02581   *         @arg @ref LL_RCC_PLLM_DIV_6
02582   *         @arg @ref LL_RCC_PLLM_DIV_7
02583   *         @arg @ref LL_RCC_PLLM_DIV_8
02584   * @param  PLLN Between 8 and 86
02585   * @param  PLLR This parameter can be one of the following values:
02586   *         @arg @ref LL_RCC_PLLSAI1R_DIV2
02587   *         @arg @ref LL_RCC_PLLSAI1R_DIV4
02588   *         @arg @ref LL_RCC_PLLSAI1R_DIV6
02589   *         @arg @ref LL_RCC_PLLSAI1R_DIV8
02590   * @retval None
02591   */
02592 __STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
02593 {
02594   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
02595   MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_POSITION_PLLSAI1N | PLLR);
02596 }
02597 
02598 /**
02599   * @brief  Get SAI1PLL multiplication factor for VCO
02600   * @rmtoll PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_GetN
02601   * @retval Between 8 and 86
02602   */
02603 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
02604 {
02605   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_POSITION_PLLSAI1N);
02606 }
02607 
02608 /**
02609   * @brief  Get SAI1PLL division factor for PLLSAI1P
02610   * @note used for PLLSAI1CLK (SAI1 or SAI2 clock).
02611   * @rmtoll PLLSAI1CFGR  PLLSAI1P      LL_RCC_PLLSAI1_GetP
02612   * @retval Returned value can be one of the following values:
02613   *         @arg @ref LL_RCC_PLLSAI1P_DIV7
02614   *         @arg @ref LL_RCC_PLLSAI1P_DIV17
02615   */
02616 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
02617 {
02618   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
02619 }
02620 
02621 /**
02622   * @brief  Get SAI1PLL division factor for PLLSAI1Q
02623   * @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
02624   * @rmtoll PLLSAI1CFGR  PLLSAI1Q      LL_RCC_PLLSAI1_GetQ
02625   * @retval Returned value can be one of the following values:
02626   *         @arg @ref LL_RCC_PLLSAI1Q_DIV2
02627   *         @arg @ref LL_RCC_PLLSAI1Q_DIV4
02628   *         @arg @ref LL_RCC_PLLSAI1Q_DIV6
02629   *         @arg @ref LL_RCC_PLLSAI1Q_DIV8
02630   */
02631 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
02632 {
02633   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
02634 }
02635 
02636 /**
02637   * @brief  Get PLLSAI1 division factor for PLLSAIR
02638   * @note used for PLLADC1CLK (ADC clock)
02639   * @rmtoll PLLSAI1CFGR  PLLSAI1R      LL_RCC_PLLSAI1_GetR
02640   * @retval Returned value can be one of the following values:
02641   *         @arg @ref LL_RCC_PLLSAI1R_DIV2
02642   *         @arg @ref LL_RCC_PLLSAI1R_DIV4
02643   *         @arg @ref LL_RCC_PLLSAI1R_DIV6
02644   *         @arg @ref LL_RCC_PLLSAI1R_DIV8
02645   */
02646 __STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
02647 {
02648   return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
02649 }
02650 
02651 /**
02652   * @brief  Enable PLLSAI1 output mapped on SAI domain clock
02653   * @rmtoll PLLSAI1CFGR  PLLSAI1PEN    LL_RCC_PLLSAI1_EnableDomain_SAI
02654   * @retval None
02655   */
02656 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
02657 {
02658   SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
02659 }
02660 
02661 /**
02662   * @brief  Disable PLLSAI1 output mapped on SAI domain clock
02663   * @note In order to save power, when  of the PLLSAI1 is
02664   *       not used,  should be 0
02665   * @rmtoll PLLSAI1CFGR  PLLSAI1PEN    LL_RCC_PLLSAI1_DisableDomain_SAI
02666   * @retval None
02667   */
02668 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
02669 {
02670   CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
02671 }
02672 
02673 /**
02674   * @brief  Enable PLLSAI1 output mapped on 48MHz domain clock
02675   * @rmtoll PLLSAI1CFGR  PLLSAI1QEN    LL_RCC_PLLSAI1_EnableDomain_48M
02676   * @retval None
02677   */
02678 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
02679 {
02680   SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
02681 }
02682 
02683 /**
02684   * @brief  Disable PLLSAI1 output mapped on 48MHz domain clock
02685   * @note In order to save power, when  of the PLLSAI1 is
02686   *       not used,  should be 0
02687   * @rmtoll PLLSAI1CFGR  PLLSAI1QEN    LL_RCC_PLLSAI1_DisableDomain_48M
02688   * @retval None
02689   */
02690 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
02691 {
02692   CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
02693 }
02694 
02695 /**
02696   * @brief  Enable PLLSAI1 output mapped on ADC domain clock
02697   * @rmtoll PLLSAI1CFGR  PLLSAI1REN    LL_RCC_PLLSAI1_EnableDomain_ADC
02698   * @retval None
02699   */
02700 __STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
02701 {
02702   SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
02703 }
02704 
02705 /**
02706   * @brief  Disable PLLSAI1 output mapped on ADC domain clock
02707   * @note In order to save power, when  of the PLLSAI1 is
02708   *       not used, Main PLLSAI1  should be 0
02709   * @rmtoll PLLSAI1CFGR  PLLSAI1REN    LL_RCC_PLLSAI1_DisableDomain_ADC
02710   * @retval None
02711   */
02712 __STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
02713 {
02714   CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
02715 }
02716 
02717 /**
02718   * @}
02719   */
02720 
02721 /** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
02722   * @{
02723   */
02724 
02725 /**
02726   * @brief  Enable PLLSAI2
02727   * @rmtoll CR           PLLSAI2ON     LL_RCC_PLLSAI2_Enable
02728   * @retval None
02729   */
02730 __STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
02731 {
02732   SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
02733 }
02734 
02735 /**
02736   * @brief  Disable PLLSAI2
02737   * @rmtoll CR           PLLSAI2ON     LL_RCC_PLLSAI2_Disable
02738   * @retval None
02739   */
02740 __STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
02741 {
02742   CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
02743 }
02744 
02745 /**
02746   * @brief  Check if PLLSAI2 Ready
02747   * @rmtoll CR           PLLSAI2RDY    LL_RCC_PLLSAI2_IsReady
02748   * @retval State of bit (1 or 0).
02749   */
02750 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
02751 {
02752   return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
02753 }
02754 
02755 /**
02756   * @brief  Configure PLLSAI2 used for SAI domain clock
02757   * @note PLL Source and PLLM Divider can be written only when PLL,
02758   *       PLLSAI2 and PLLSAI2 are disabled
02759   * @note PLLN/PLLP can be written only when PLLSAI2 is disabled
02760   * @note This  can be selected for SAI1 or SAI2
02761   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_SAI\n
02762   *         PLLCFGR      PLLM          LL_RCC_PLLSAI2_ConfigDomain_SAI\n
02763   *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_SAI\n
02764   *         PLLSAI2CFGR  PLLSAI2P      LL_RCC_PLLSAI2_ConfigDomain_SAI
02765   * @param  Source This parameter can be one of the following values:
02766   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02767   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02768   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02769   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02770   * @param  PLLM This parameter can be one of the following values:
02771   *         @arg @ref LL_RCC_PLLM_DIV_1
02772   *         @arg @ref LL_RCC_PLLM_DIV_2
02773   *         @arg @ref LL_RCC_PLLM_DIV_3
02774   *         @arg @ref LL_RCC_PLLM_DIV_4
02775   *         @arg @ref LL_RCC_PLLM_DIV_5
02776   *         @arg @ref LL_RCC_PLLM_DIV_6
02777   *         @arg @ref LL_RCC_PLLM_DIV_7
02778   *         @arg @ref LL_RCC_PLLM_DIV_8
02779   * @param  PLLN Between 8 and 86
02780   * @param  PLLP This parameter can be one of the following values:
02781   *         @arg @ref LL_RCC_PLLSAI2P_DIV7
02782   *         @arg @ref LL_RCC_PLLSAI2P_DIV17
02783   * @retval None
02784   */
02785 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
02786 {
02787   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
02788   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_POSITION_PLLSAI2N | PLLP);
02789 }
02790 
02791 /**
02792   * @brief  Configure PLLSAI2 used for ADC domain clock
02793   * @note PLL Source and PLLM Divider can be written only when PLL,
02794   *       PLLSAI2 and PLLSAI2 are disabled
02795   * @note PLLN/PLLR can be written only when PLLSAI2 is disabled
02796   * @note This  can be selected for ADC
02797   * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_ADC\n
02798   *         PLLCFGR      PLLM          LL_RCC_PLLSAI2_ConfigDomain_ADC\n
02799   *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_ADC\n
02800   *         PLLSAI2CFGR  PLLSAI2R      LL_RCC_PLLSAI2_ConfigDomain_ADC
02801   * @param  Source This parameter can be one of the following values:
02802   *         @arg @ref LL_RCC_PLLSOURCE_NONE
02803   *         @arg @ref LL_RCC_PLLSOURCE_MSI
02804   *         @arg @ref LL_RCC_PLLSOURCE_HSI
02805   *         @arg @ref LL_RCC_PLLSOURCE_HSE
02806   * @param  PLLM This parameter can be one of the following values:
02807   *         @arg @ref LL_RCC_PLLM_DIV_1
02808   *         @arg @ref LL_RCC_PLLM_DIV_2
02809   *         @arg @ref LL_RCC_PLLM_DIV_3
02810   *         @arg @ref LL_RCC_PLLM_DIV_4
02811   *         @arg @ref LL_RCC_PLLM_DIV_5
02812   *         @arg @ref LL_RCC_PLLM_DIV_6
02813   *         @arg @ref LL_RCC_PLLM_DIV_7
02814   *         @arg @ref LL_RCC_PLLM_DIV_8
02815   * @param  PLLN Between 8 and 86
02816   * @param  PLLR This parameter can be one of the following values:
02817   *         @arg @ref LL_RCC_PLLSAI2R_DIV2
02818   *         @arg @ref LL_RCC_PLLSAI2R_DIV4
02819   *         @arg @ref LL_RCC_PLLSAI2R_DIV6
02820   *         @arg @ref LL_RCC_PLLSAI2R_DIV8
02821   * @retval None
02822   */
02823 __STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
02824 {
02825   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
02826   MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_POSITION_PLLSAI2N | PLLR);
02827 }
02828 
02829 /**
02830   * @brief  Get SAI2PLL multiplication factor for VCO
02831   * @rmtoll PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_GetN
02832   * @retval Between 8 and 86
02833   */
02834 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
02835 {
02836   return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_POSITION_PLLSAI2N);
02837 }
02838 
02839 /**
02840   * @brief  Get SAI2PLL division factor for PLLSAI2P
02841   * @note used for PLLSAI2CLK (SAI1 or SAI2 clock).
02842   * @rmtoll PLLSAI2CFGR  PLLSAI2P      LL_RCC_PLLSAI2_GetP
02843   * @retval Returned value can be one of the following values:
02844   *         @arg @ref LL_RCC_PLLSAI2P_DIV7
02845   *         @arg @ref LL_RCC_PLLSAI2P_DIV17
02846   */
02847 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
02848 {
02849   return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
02850 }
02851 
02852 /**
02853   * @brief  Get SAI2PLL division factor for PLLSAI2R
02854   * @note used for PLLADC2CLK (ADC clock)
02855   * @rmtoll PLLSAI2CFGR  PLLSAI2R      LL_RCC_PLLSAI2_GetR
02856   * @retval Returned value can be one of the following values:
02857   *         @arg @ref LL_RCC_PLLSAI2R_DIV2
02858   *         @arg @ref LL_RCC_PLLSAI2R_DIV4
02859   *         @arg @ref LL_RCC_PLLSAI2R_DIV6
02860   *         @arg @ref LL_RCC_PLLSAI2R_DIV8
02861   */
02862 __STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
02863 {
02864   return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
02865 }
02866 
02867 /**
02868   * @brief  Enable PLLSAI2 output mapped on SAI domain clock
02869   * @rmtoll PLLSAI2CFGR  PLLSAI2PEN    LL_RCC_PLLSAI2_EnableDomain_SAI
02870   * @retval None
02871   */
02872 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
02873 {
02874   SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
02875 }
02876 
02877 /**
02878   * @brief  Disable PLLSAI2 output mapped on SAI domain clock
02879   * @note In order to save power, when  of the PLLSAI2 is
02880   *       not used,  should be 0
02881   * @rmtoll PLLSAI2CFGR  PLLSAI2PEN    LL_RCC_PLLSAI2_DisableDomain_SAI
02882   * @retval None
02883   */
02884 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
02885 {
02886   CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
02887 }
02888 
02889 /**
02890   * @brief  Enable PLLSAI2 output mapped on ADC domain clock
02891   * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_EnableDomain_ADC
02892   * @retval None
02893   */
02894 __STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
02895 {
02896   SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
02897 }
02898 
02899 /**
02900   * @brief  Disable PLLSAI2 output mapped on ADC domain clock
02901   * @note In order to save power, when  of the PLLSAI2 is
02902   *       not used, Main PLLSAI2  should be 0
02903   * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_DisableDomain_ADC
02904   * @retval None
02905   */
02906 __STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
02907 {
02908   CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
02909 }
02910 
02911 /**
02912   * @}
02913   */
02914 
02915 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
02916   * @{
02917   */
02918 
02919 /**
02920   * @brief  Clear LSI ready interrupt flag
02921   * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
02922   * @retval None
02923   */
02924 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
02925 {
02926   SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
02927 }
02928 
02929 /**
02930   * @brief  Clear LSE ready interrupt flag
02931   * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
02932   * @retval None
02933   */
02934 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
02935 {
02936   SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
02937 }
02938 
02939 /**
02940   * @brief  Clear MSI ready interrupt flag
02941   * @rmtoll CICR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY
02942   * @retval None
02943   */
02944 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
02945 {
02946   SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
02947 }
02948 
02949 /**
02950   * @brief  Clear HSI ready interrupt flag
02951   * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
02952   * @retval None
02953   */
02954 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
02955 {
02956   SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
02957 }
02958 
02959 /**
02960   * @brief  Clear HSE ready interrupt flag
02961   * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
02962   * @retval None
02963   */
02964 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
02965 {
02966   SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
02967 }
02968 
02969 /**
02970   * @brief  Clear PLL ready interrupt flag
02971   * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
02972   * @retval None
02973   */
02974 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
02975 {
02976   SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
02977 }
02978 
02979 /**
02980   * @brief  Clear PLLSAI1 ready interrupt flag
02981   * @rmtoll CICR         PLLSAI1RDYC   LL_RCC_ClearFlag_PLLSAI1RDY
02982   * @retval None
02983   */
02984 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
02985 {
02986   SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
02987 }
02988 
02989 /**
02990   * @brief  Clear PLLSAI1 ready interrupt flag
02991   * @rmtoll CICR         PLLSAI2RDYC   LL_RCC_ClearFlag_PLLSAI2RDY
02992   * @retval None
02993   */
02994 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
02995 {
02996   SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
02997 }
02998 
02999 /**
03000   * @brief  Clear Clock security system interrupt flag
03001   * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS
03002   * @retval None
03003   */
03004 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
03005 {
03006   SET_BIT(RCC->CICR, RCC_CICR_CSSC);
03007 }
03008 
03009 /**
03010   * @brief  Clear LSE Clock security system interrupt flag
03011   * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS
03012   * @retval None
03013   */
03014 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
03015 {
03016   SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
03017 }
03018 
03019 /**
03020   * @brief  Check if LSI ready interrupt occurred or not
03021   * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
03022   * @retval State of bit (1 or 0).
03023   */
03024 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
03025 {
03026   return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
03027 }
03028 
03029 /**
03030   * @brief  Check if LSE ready interrupt occurred or not
03031   * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
03032   * @retval State of bit (1 or 0).
03033   */
03034 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
03035 {
03036   return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
03037 }
03038 
03039 /**
03040   * @brief  Check if MSI ready interrupt occurred or not
03041   * @rmtoll CIFR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY
03042   * @retval State of bit (1 or 0).
03043   */
03044 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
03045 {
03046   return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
03047 }
03048 
03049 /**
03050   * @brief  Check if HSI ready interrupt occurred or not
03051   * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
03052   * @retval State of bit (1 or 0).
03053   */
03054 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
03055 {
03056   return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
03057 }
03058 
03059 /**
03060   * @brief  Check if HSE ready interrupt occurred or not
03061   * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
03062   * @retval State of bit (1 or 0).
03063   */
03064 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
03065 {
03066   return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
03067 }
03068 
03069 /**
03070   * @brief  Check if PLL ready interrupt occurred or not
03071   * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
03072   * @retval State of bit (1 or 0).
03073   */
03074 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
03075 {
03076   return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
03077 }
03078 
03079 /**
03080   * @brief  Check if PLLSAI1 ready interrupt occurred or not
03081   * @rmtoll CIFR         PLLSAI1RDYF   LL_RCC_IsActiveFlag_PLLSAI1RDY
03082   * @retval State of bit (1 or 0).
03083   */
03084 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
03085 {
03086   return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
03087 }
03088 
03089 /**
03090   * @brief  Check if PLLSAI1 ready interrupt occurred or not
03091   * @rmtoll CIFR         PLLSAI2RDYF   LL_RCC_IsActiveFlag_PLLSAI2RDY
03092   * @retval State of bit (1 or 0).
03093   */
03094 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
03095 {
03096   return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
03097 }
03098 
03099 /**
03100   * @brief  Check if Clock security system interrupt occurred or not
03101   * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS
03102   * @retval State of bit (1 or 0).
03103   */
03104 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
03105 {
03106   return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
03107 }
03108 
03109 /**
03110   * @brief  Check if LSE Clock security system interrupt occurred or not
03111   * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS
03112   * @retval State of bit (1 or 0).
03113   */
03114 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
03115 {
03116   return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
03117 }
03118 
03119 /**
03120   * @brief  Check if RCC flag FW reset is set or not.
03121   * @rmtoll CSR          FWRSTF        LL_RCC_IsActiveFlag_FWRST
03122   * @retval State of bit (1 or 0).
03123   */
03124 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
03125 {
03126   return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
03127 }
03128 
03129 /**
03130   * @brief  Check if RCC flag Independent Watchdog reset is set or not.
03131   * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
03132   * @retval State of bit (1 or 0).
03133   */
03134 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
03135 {
03136   return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
03137 }
03138 
03139 /**
03140   * @brief  Check if RCC flag Low Power reset is set or not.
03141   * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
03142   * @retval State of bit (1 or 0).
03143   */
03144 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
03145 {
03146   return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
03147 }
03148 
03149 /**
03150   * @brief  Check if RCC flag is set or not.
03151   * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST
03152   * @retval State of bit (1 or 0).
03153   */
03154 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
03155 {
03156   return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
03157 }
03158 
03159 /**
03160   * @brief  Check if RCC flag Pin reset is set or not.
03161   * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
03162   * @retval State of bit (1 or 0).
03163   */
03164 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
03165 {
03166   return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
03167 }
03168 
03169 /**
03170   * @brief  Check if RCC flag Software reset is set or not.
03171   * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
03172   * @retval State of bit (1 or 0).
03173   */
03174 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
03175 {
03176   return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
03177 }
03178 
03179 /**
03180   * @brief  Check if RCC flag Window Watchdog reset is set or not.
03181   * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
03182   * @retval State of bit (1 or 0).
03183   */
03184 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
03185 {
03186   return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
03187 }
03188 
03189 /**
03190   * @brief  Check if RCC flag BOR reset is set or not.
03191   * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
03192   * @retval State of bit (1 or 0).
03193   */
03194 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
03195 {
03196   return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
03197 }
03198 
03199 /**
03200   * @brief  Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST,
03201   *         RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST,
03202   *         RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST
03203   * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
03204   * @retval None
03205   */
03206 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
03207 {
03208   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
03209 }
03210 
03211 /**
03212   * @}
03213   */
03214 
03215 /** @defgroup RCC_LL_EF_IT_Management IT Management
03216   * @{
03217   */
03218 
03219 /**
03220   * @brief  Enable RCC interrupt
03221   * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
03222   * @retval None
03223   */
03224 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
03225 {
03226   SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
03227 }
03228 
03229 /**
03230   * @brief  Enable RCC interrupt
03231   * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
03232   * @retval None
03233   */
03234 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
03235 {
03236   SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
03237 }
03238 
03239 /**
03240   * @brief  Enable RCC interrupt
03241   * @rmtoll CIER         MSIRDYIE      LL_RCC_EnableIT_MSIRDY
03242   * @retval None
03243   */
03244 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
03245 {
03246   SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
03247 }
03248 
03249 /**
03250   * @brief  Enable RCC interrupt
03251   * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
03252   * @retval None
03253   */
03254 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
03255 {
03256   SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
03257 }
03258 
03259 /**
03260   * @brief  Enable RCC interrupt
03261   * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
03262   * @retval None
03263   */
03264 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
03265 {
03266   SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
03267 }
03268 
03269 /**
03270   * @brief  Enable RCC interrupt
03271   * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
03272   * @retval None
03273   */
03274 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
03275 {
03276   SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
03277 }
03278 
03279 /**
03280   * @brief  Enable RCC interrupt
03281   * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_EnableIT_PLLSAI1RDY
03282   * @retval None
03283   */
03284 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
03285 {
03286   SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
03287 }
03288 
03289 /**
03290   * @brief  Enable RCC interrupt
03291   * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_EnableIT_PLLSAI2RDY
03292   * @retval None
03293   */
03294 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
03295 {
03296   SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
03297 }
03298 
03299 /**
03300   * @brief  Disable RCC interrupt
03301   * @rmtoll CIER         LSECSSIE      LL_RCC_EnableIT_LSECSS
03302   * @retval None
03303   */
03304 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
03305 {
03306   SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
03307 }
03308 
03309 /**
03310   * @brief  Disable RCC interrupt
03311   * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
03312   * @retval None
03313   */
03314 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
03315 {
03316   CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
03317 }
03318 
03319 /**
03320   * @brief  Disable RCC interrupt
03321   * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
03322   * @retval None
03323   */
03324 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
03325 {
03326   CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
03327 }
03328 
03329 /**
03330   * @brief  Disable RCC interrupt
03331   * @rmtoll CIER         MSIRDYIE      LL_RCC_DisableIT_MSIRDY
03332   * @retval None
03333   */
03334 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
03335 {
03336   CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
03337 }
03338 
03339 /**
03340   * @brief  Disable RCC interrupt
03341   * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
03342   * @retval None
03343   */
03344 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
03345 {
03346   CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
03347 }
03348 
03349 /**
03350   * @brief  Disable RCC interrupt
03351   * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
03352   * @retval None
03353   */
03354 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
03355 {
03356   CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
03357 }
03358 
03359 /**
03360   * @brief  Disable RCC interrupt
03361   * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
03362   * @retval None
03363   */
03364 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
03365 {
03366   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
03367 }
03368 
03369 /**
03370   * @brief  Disable RCC interrupt
03371   * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_DisableIT_PLLSAI1RDY
03372   * @retval None
03373   */
03374 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
03375 {
03376   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
03377 }
03378 
03379 /**
03380   * @brief  Disable RCC interrupt
03381   * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_DisableIT_PLLSAI2RDY
03382   * @retval None
03383   */
03384 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
03385 {
03386   CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
03387 }
03388 
03389 /**
03390   * @brief  Disable RCC interrupt
03391   * @rmtoll CIER         LSECSSIE      LL_RCC_DisableIT_LSECSS
03392   * @retval None
03393   */
03394 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
03395 {
03396   CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
03397 }
03398 
03399 /**
03400   * @brief  Checks if the specified RCC interrupt source is enabled or disabled.
03401   * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
03402   * @retval State of bit (1 or 0).
03403   */
03404 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
03405 {
03406   return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
03407 }
03408 
03409 /**
03410   * @brief  Checks if the specified RCC interrupt source is enabled or disabled.
03411   * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
03412   * @retval State of bit (1 or 0).
03413   */
03414 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
03415 {
03416   return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
03417 }
03418 
03419 /**
03420   * @brief  Checks if the specified RCC interrupt source is enabled or disabled.
03421   * @rmtoll CIER         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY
03422   * @retval State of bit (1 or 0).
03423   */
03424 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
03425 {
03426   return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
03427 }
03428 
03429 /**
03430   * @brief  Checks if the specified RCC interrupt source is enabled or disabled.
03431   * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
03432   * @retval State of bit (1 or 0).
03433   */
03434 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
03435 {
03436   return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
03437 }
03438 
03439 /**
03440   * @brief  Checks if the specified RCC interrupt source is enabled or disabled.
03441   * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
03442   * @retval State of bit (1 or 0).
03443   */
03444 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
03445 {
03446   return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
03447 }
03448 
03449 /**
03450   * @brief  Checks if the specified RCC interrupt source is enabled or disabled.
03451   * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
03452   * @retval State of bit (1 or 0).
03453   */
03454 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
03455 {
03456   return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
03457 }
03458 
03459 /**
03460   * @brief  Checks if the specified RCC interrupt source is enabled or disabled.
03461   * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_IsEnabledIT_PLLSAI1RDY
03462   * @retval State of bit (1 or 0).
03463   */
03464 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
03465 {
03466   return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
03467 }
03468 
03469 /**
03470   * @brief  Checks if the specified RCC interrupt source is enabled or disabled.
03471   * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_IsEnabledIT_PLLSAI2RDY
03472   * @retval State of bit (1 or 0).
03473   */
03474 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
03475 {
03476   return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
03477 }
03478 
03479 /**
03480   * @brief  Checks if the specified RCC interrupt source is enabled or disabled.
03481   * @rmtoll CIER         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS
03482   * @retval State of bit (1 or 0).
03483   */
03484 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
03485 {
03486   return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
03487 }
03488 
03489 /**
03490   * @}
03491   */
03492 
03493 
03494 /**
03495   * @}
03496   */
03497 
03498 /**
03499   * @}
03500   */
03501 
03502 #endif /* defined(RCC) */
03503 
03504 /**
03505   * @}
03506   */
03507 
03508 #ifdef __cplusplus
03509 }
03510 #endif
03511 
03512 #endif /* __STM32L4xx_LL_RCC_H */
03513 
03514 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
03515