STM32L4xx_HAL_Driver - L4 HAL Drivers

Senior Design: Sound Monitor » Code » STM32L4xx_HAL_Driver

Senior Design: Sound Monitor / STM32L4xx_HAL_Driver

L4 HAL Drivers

Src/stm32l4xx_hal_tim.c@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:: EricLew
Date:: Mon Nov 02 19:37:23 2015 +0000
Revision:: 0:80ee8f3b695e

Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_hal_tim.c
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief TIM HAL module driver.
EricLew	0:80ee8f3b695e	8	* This file provides firmware functions to manage the following
EricLew	0:80ee8f3b695e	9	* functionalities of the Timer (TIM) peripheral:
EricLew	0:80ee8f3b695e	10	* + Time Base Initialization
EricLew	0:80ee8f3b695e	11	* + Time Base Start
EricLew	0:80ee8f3b695e	12	* + Time Base Start Interruption
EricLew	0:80ee8f3b695e	13	* + Time Base Start DMA
EricLew	0:80ee8f3b695e	14	* + Time Output Compare/PWM Initialization
EricLew	0:80ee8f3b695e	15	* + Time Output Compare/PWM Channel Configuration
EricLew	0:80ee8f3b695e	16	* + Time Output Compare/PWM Start
EricLew	0:80ee8f3b695e	17	* + Time Output Compare/PWM Start Interruption
EricLew	0:80ee8f3b695e	18	* + Time Output Compare/PWM Start DMA
EricLew	0:80ee8f3b695e	19	* + Time Input Capture Initialization
EricLew	0:80ee8f3b695e	20	* + Time Input Capture Channel Configuration
EricLew	0:80ee8f3b695e	21	* + Time Input Capture Start
EricLew	0:80ee8f3b695e	22	* + Time Input Capture Start Interruption
EricLew	0:80ee8f3b695e	23	* + Time Input Capture Start DMA
EricLew	0:80ee8f3b695e	24	* + Time One Pulse Initialization
EricLew	0:80ee8f3b695e	25	* + Time One Pulse Channel Configuration
EricLew	0:80ee8f3b695e	26	* + Time One Pulse Start
EricLew	0:80ee8f3b695e	27	* + Time Encoder Interface Initialization
EricLew	0:80ee8f3b695e	28	* + Time Encoder Interface Start
EricLew	0:80ee8f3b695e	29	* + Time Encoder Interface Start Interruption
EricLew	0:80ee8f3b695e	30	* + Time Encoder Interface Start DMA
EricLew	0:80ee8f3b695e	31	* + Commutation Event configuration with Interruption and DMA
EricLew	0:80ee8f3b695e	32	* + Time OCRef clear configuration
EricLew	0:80ee8f3b695e	33	* + Time External Clock configuration
EricLew	0:80ee8f3b695e	34	@verbatim
EricLew	0:80ee8f3b695e	35	==============================================================================
EricLew	0:80ee8f3b695e	36	##### TIMER Generic features #####
EricLew	0:80ee8f3b695e	37	==============================================================================
EricLew	0:80ee8f3b695e	38	[..] The Timer features include:
EricLew	0:80ee8f3b695e	39	(#) 16-bit up, down, up/down auto-reload counter.
EricLew	0:80ee8f3b695e	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
EricLew	0:80ee8f3b695e	41	counter clock frequency either by any factor between 1 and 65536.
EricLew	0:80ee8f3b695e	42	(#) Up to 4 independent channels for:
EricLew	0:80ee8f3b695e	43	(++) Input Capture
EricLew	0:80ee8f3b695e	44	(++) Output Compare
EricLew	0:80ee8f3b695e	45	(++) PWM generation (Edge and Center-aligned Mode)
EricLew	0:80ee8f3b695e	46	(++) One-pulse mode output
EricLew	0:80ee8f3b695e	47
EricLew	0:80ee8f3b695e	48	##### How to use this driver #####
EricLew	0:80ee8f3b695e	49	==============================================================================
EricLew	0:80ee8f3b695e	50	[..]
EricLew	0:80ee8f3b695e	51	(#) Initialize the TIM low level resources by implementing the following functions
EricLew	0:80ee8f3b695e	52	depending on the selected feature:
EricLew	0:80ee8f3b695e	53	(++) Time Base : HAL_TIM_Base_MspInit()
EricLew	0:80ee8f3b695e	54	(++) Input Capture : HAL_TIM_IC_MspInit()
EricLew	0:80ee8f3b695e	55	(++) Output Compare : HAL_TIM_OC_MspInit()
EricLew	0:80ee8f3b695e	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
EricLew	0:80ee8f3b695e	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
EricLew	0:80ee8f3b695e	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
EricLew	0:80ee8f3b695e	59
EricLew	0:80ee8f3b695e	60	(#) Initialize the TIM low level resources :
EricLew	0:80ee8f3b695e	61	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
EricLew	0:80ee8f3b695e	62	(##) TIM pins configuration
EricLew	0:80ee8f3b695e	63	(+++) Enable the clock for the TIM GPIOs using the following function:
EricLew	0:80ee8f3b695e	64	__HAL_RCC_GPIOx_CLK_ENABLE();
EricLew	0:80ee8f3b695e	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
EricLew	0:80ee8f3b695e	66
EricLew	0:80ee8f3b695e	67	(#) The external Clock can be configured, if needed (the default clock is the
EricLew	0:80ee8f3b695e	68	internal clock from the APBx), using the following function:
EricLew	0:80ee8f3b695e	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
EricLew	0:80ee8f3b695e	70	any start function.
EricLew	0:80ee8f3b695e	71
EricLew	0:80ee8f3b695e	72	(#) Configure the TIM in the desired functioning mode using one of the
EricLew	0:80ee8f3b695e	73	Initialization function of this driver:
EricLew	0:80ee8f3b695e	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
EricLew	0:80ee8f3b695e	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
EricLew	0:80ee8f3b695e	76	Output Compare signal.
EricLew	0:80ee8f3b695e	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
EricLew	0:80ee8f3b695e	78	PWM signal.
EricLew	0:80ee8f3b695e	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
EricLew	0:80ee8f3b695e	80	external signal.
EricLew	0:80ee8f3b695e	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
EricLew	0:80ee8f3b695e	82	in One Pulse Mode.
EricLew	0:80ee8f3b695e	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
EricLew	0:80ee8f3b695e	84
EricLew	0:80ee8f3b695e	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
EricLew	0:80ee8f3b695e	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
EricLew	0:80ee8f3b695e	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
EricLew	0:80ee8f3b695e	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
EricLew	0:80ee8f3b695e	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
EricLew	0:80ee8f3b695e	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
EricLew	0:80ee8f3b695e	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
EricLew	0:80ee8f3b695e	92
EricLew	0:80ee8f3b695e	93	(#) The DMA Burst is managed with the two following functions:
EricLew	0:80ee8f3b695e	94	HAL_TIM_DMABurst_WriteStart()
EricLew	0:80ee8f3b695e	95	HAL_TIM_DMABurst_ReadStart()
EricLew	0:80ee8f3b695e	96
EricLew	0:80ee8f3b695e	97	@endverbatim
EricLew	0:80ee8f3b695e	98	******************************************************************************
EricLew	0:80ee8f3b695e	99	* @attention
EricLew	0:80ee8f3b695e	100	*
EricLew	0:80ee8f3b695e	101	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	102	*
EricLew	0:80ee8f3b695e	103	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	104	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	105	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	106	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	108	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	109	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	111	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	112	* without specific prior written permission.
EricLew	0:80ee8f3b695e	113	*
EricLew	0:80ee8f3b695e	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	124	*
EricLew	0:80ee8f3b695e	125	******************************************************************************
EricLew	0:80ee8f3b695e	126	*/
EricLew	0:80ee8f3b695e	127
EricLew	0:80ee8f3b695e	128	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	129	#include "stm32l4xx_hal.h"
EricLew	0:80ee8f3b695e	130
EricLew	0:80ee8f3b695e	131	/** @addtogroup STM32L4xx_HAL_Driver
EricLew	0:80ee8f3b695e	132	* @{
EricLew	0:80ee8f3b695e	133	*/
EricLew	0:80ee8f3b695e	134
EricLew	0:80ee8f3b695e	135	/** @defgroup TIM TIM
EricLew	0:80ee8f3b695e	136	* @brief TIM HAL module driver
EricLew	0:80ee8f3b695e	137	* @{
EricLew	0:80ee8f3b695e	138	*/
EricLew	0:80ee8f3b695e	139
EricLew	0:80ee8f3b695e	140	#ifdef HAL_TIM_MODULE_ENABLED
EricLew	0:80ee8f3b695e	141
EricLew	0:80ee8f3b695e	142	/* Private typedef -----------------------------------------------------------*/
EricLew	0:80ee8f3b695e	143	/* Private define ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	144	/* Private macro -------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	145	/* Private variables ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	146	/* Private function prototypes -----------------------------------------------*/
EricLew	0:80ee8f3b695e	147	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
EricLew	0:80ee8f3b695e	148	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
EricLew	0:80ee8f3b695e	149	uint32_t TIM_ICFilter);
EricLew	0:80ee8f3b695e	150	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
EricLew	0:80ee8f3b695e	151	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
EricLew	0:80ee8f3b695e	152	uint32_t TIM_ICFilter);
EricLew	0:80ee8f3b695e	153	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
EricLew	0:80ee8f3b695e	154	uint32_t TIM_ICFilter);
EricLew	0:80ee8f3b695e	155	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
EricLew	0:80ee8f3b695e	156	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
EricLew	0:80ee8f3b695e	157	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
EricLew	0:80ee8f3b695e	158	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
EricLew	0:80ee8f3b695e	159	TIM_SlaveConfigTypeDef * sSlaveConfig);
EricLew	0:80ee8f3b695e	160	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	161
EricLew	0:80ee8f3b695e	162	/** @defgroup TIM_Exported_Functions TIM Exported Functions
EricLew	0:80ee8f3b695e	163	* @{
EricLew	0:80ee8f3b695e	164	*/
EricLew	0:80ee8f3b695e	165
EricLew	0:80ee8f3b695e	166	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
EricLew	0:80ee8f3b695e	167	* @brief Time Base functions
EricLew	0:80ee8f3b695e	168	*
EricLew	0:80ee8f3b695e	169	@verbatim
EricLew	0:80ee8f3b695e	170	==============================================================================
EricLew	0:80ee8f3b695e	171	##### Time Base functions #####
EricLew	0:80ee8f3b695e	172	==============================================================================
EricLew	0:80ee8f3b695e	173	[..]
EricLew	0:80ee8f3b695e	174	This section provides functions allowing to:
EricLew	0:80ee8f3b695e	175	(+) Initialize and configure the TIM base.
EricLew	0:80ee8f3b695e	176	(+) De-initialize the TIM base.
EricLew	0:80ee8f3b695e	177	(+) Start the Time Base.
EricLew	0:80ee8f3b695e	178	(+) Stop the Time Base.
EricLew	0:80ee8f3b695e	179	(+) Start the Time Base and enable interrupt.
EricLew	0:80ee8f3b695e	180	(+) Stop the Time Base and disable interrupt.
EricLew	0:80ee8f3b695e	181	(+) Start the Time Base and enable DMA transfer.
EricLew	0:80ee8f3b695e	182	(+) Stop the Time Base and disable DMA transfer.
EricLew	0:80ee8f3b695e	183
EricLew	0:80ee8f3b695e	184	@endverbatim
EricLew	0:80ee8f3b695e	185	* @{
EricLew	0:80ee8f3b695e	186	*/
EricLew	0:80ee8f3b695e	187	/**
EricLew	0:80ee8f3b695e	188	* @brief Initializes the TIM Time base Unit according to the specified
EricLew	0:80ee8f3b695e	189	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
EricLew	0:80ee8f3b695e	190	* @param htim: TIM Base handle
EricLew	0:80ee8f3b695e	191	* @retval HAL status
EricLew	0:80ee8f3b695e	192	*/
EricLew	0:80ee8f3b695e	193	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	194	{
EricLew	0:80ee8f3b695e	195	/* Check the TIM handle allocation */
EricLew	0:80ee8f3b695e	196	if(htim == NULL)
EricLew	0:80ee8f3b695e	197	{
EricLew	0:80ee8f3b695e	198	return HAL_ERROR;
EricLew	0:80ee8f3b695e	199	}
EricLew	0:80ee8f3b695e	200
EricLew	0:80ee8f3b695e	201	/* Check the parameters */
EricLew	0:80ee8f3b695e	202	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	203	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
EricLew	0:80ee8f3b695e	204	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
EricLew	0:80ee8f3b695e	205
EricLew	0:80ee8f3b695e	206	if(htim->State == HAL_TIM_STATE_RESET)
EricLew	0:80ee8f3b695e	207	{
EricLew	0:80ee8f3b695e	208	/* Allocate lock resource and initialize it */
EricLew	0:80ee8f3b695e	209	htim->Lock = HAL_UNLOCKED;
EricLew	0:80ee8f3b695e	210
EricLew	0:80ee8f3b695e	211	/* Init the low level hardware : GPIO, CLOCK, NVIC */
EricLew	0:80ee8f3b695e	212	HAL_TIM_Base_MspInit(htim);
EricLew	0:80ee8f3b695e	213	}
EricLew	0:80ee8f3b695e	214
EricLew	0:80ee8f3b695e	215	/* Set the TIM state */
EricLew	0:80ee8f3b695e	216	htim->State= HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	217
EricLew	0:80ee8f3b695e	218	/* Set the Time Base configuration */
EricLew	0:80ee8f3b695e	219	TIM_Base_SetConfig(htim->Instance, &htim->Init);
EricLew	0:80ee8f3b695e	220
EricLew	0:80ee8f3b695e	221	/* Initialize the TIM state*/
EricLew	0:80ee8f3b695e	222	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	223
EricLew	0:80ee8f3b695e	224	return HAL_OK;
EricLew	0:80ee8f3b695e	225	}
EricLew	0:80ee8f3b695e	226
EricLew	0:80ee8f3b695e	227	/**
EricLew	0:80ee8f3b695e	228	* @brief DeInitialize the TIM Base peripheral
EricLew	0:80ee8f3b695e	229	* @param htim: TIM Base handle
EricLew	0:80ee8f3b695e	230	* @retval HAL status
EricLew	0:80ee8f3b695e	231	*/
EricLew	0:80ee8f3b695e	232	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	233	{
EricLew	0:80ee8f3b695e	234	/* Check the parameters */
EricLew	0:80ee8f3b695e	235	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	236
EricLew	0:80ee8f3b695e	237	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	238
EricLew	0:80ee8f3b695e	239	/* Disable the TIM Peripheral Clock */
EricLew	0:80ee8f3b695e	240	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	241
EricLew	0:80ee8f3b695e	242	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
EricLew	0:80ee8f3b695e	243	HAL_TIM_Base_MspDeInit(htim);
EricLew	0:80ee8f3b695e	244
EricLew	0:80ee8f3b695e	245	/* Change TIM state */
EricLew	0:80ee8f3b695e	246	htim->State = HAL_TIM_STATE_RESET;
EricLew	0:80ee8f3b695e	247
EricLew	0:80ee8f3b695e	248	/* Release Lock */
EricLew	0:80ee8f3b695e	249	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	250
EricLew	0:80ee8f3b695e	251	return HAL_OK;
EricLew	0:80ee8f3b695e	252	}
EricLew	0:80ee8f3b695e	253
EricLew	0:80ee8f3b695e	254	/**
EricLew	0:80ee8f3b695e	255	* @brief Initializes the TIM Base MSP.
EricLew	0:80ee8f3b695e	256	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	257	* @retval None
EricLew	0:80ee8f3b695e	258	*/
EricLew	0:80ee8f3b695e	259	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	260	{
EricLew	0:80ee8f3b695e	261	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	262	the HAL_TIM_Base_MspInit could be implemented in the user file
EricLew	0:80ee8f3b695e	263	*/
EricLew	0:80ee8f3b695e	264	}
EricLew	0:80ee8f3b695e	265
EricLew	0:80ee8f3b695e	266	/**
EricLew	0:80ee8f3b695e	267	* @brief DeInitialize TIM Base MSP.
EricLew	0:80ee8f3b695e	268	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	269	* @retval None
EricLew	0:80ee8f3b695e	270	*/
EricLew	0:80ee8f3b695e	271	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	272	{
EricLew	0:80ee8f3b695e	273	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	274	the HAL_TIM_Base_MspDeInit could be implemented in the user file
EricLew	0:80ee8f3b695e	275	*/
EricLew	0:80ee8f3b695e	276	}
EricLew	0:80ee8f3b695e	277
EricLew	0:80ee8f3b695e	278
EricLew	0:80ee8f3b695e	279	/**
EricLew	0:80ee8f3b695e	280	* @brief Starts the TIM Base generation.
EricLew	0:80ee8f3b695e	281	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	282	* @retval HAL status
EricLew	0:80ee8f3b695e	283	*/
EricLew	0:80ee8f3b695e	284	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	285	{
EricLew	0:80ee8f3b695e	286	/* Check the parameters */
EricLew	0:80ee8f3b695e	287	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	288
EricLew	0:80ee8f3b695e	289	/* Set the TIM state */
EricLew	0:80ee8f3b695e	290	htim->State= HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	291
EricLew	0:80ee8f3b695e	292	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	293	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	294
EricLew	0:80ee8f3b695e	295	/* Change the TIM state*/
EricLew	0:80ee8f3b695e	296	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	297
EricLew	0:80ee8f3b695e	298	/* Return function status */
EricLew	0:80ee8f3b695e	299	return HAL_OK;
EricLew	0:80ee8f3b695e	300	}
EricLew	0:80ee8f3b695e	301
EricLew	0:80ee8f3b695e	302	/**
EricLew	0:80ee8f3b695e	303	* @brief Stops the TIM Base generation.
EricLew	0:80ee8f3b695e	304	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	305	* @retval HAL status
EricLew	0:80ee8f3b695e	306	*/
EricLew	0:80ee8f3b695e	307	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	308	{
EricLew	0:80ee8f3b695e	309	/* Check the parameters */
EricLew	0:80ee8f3b695e	310	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	311
EricLew	0:80ee8f3b695e	312	/* Set the TIM state */
EricLew	0:80ee8f3b695e	313	htim->State= HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	314
EricLew	0:80ee8f3b695e	315	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	316	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	317
EricLew	0:80ee8f3b695e	318	/* Change the TIM state*/
EricLew	0:80ee8f3b695e	319	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	320
EricLew	0:80ee8f3b695e	321	/* Return function status */
EricLew	0:80ee8f3b695e	322	return HAL_OK;
EricLew	0:80ee8f3b695e	323	}
EricLew	0:80ee8f3b695e	324
EricLew	0:80ee8f3b695e	325	/**
EricLew	0:80ee8f3b695e	326	* @brief Starts the TIM Base generation in interrupt mode.
EricLew	0:80ee8f3b695e	327	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	328	* @retval HAL status
EricLew	0:80ee8f3b695e	329	*/
EricLew	0:80ee8f3b695e	330	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	331	{
EricLew	0:80ee8f3b695e	332	/* Check the parameters */
EricLew	0:80ee8f3b695e	333	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	334
EricLew	0:80ee8f3b695e	335	/* Enable the TIM Update interrupt */
EricLew	0:80ee8f3b695e	336	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
EricLew	0:80ee8f3b695e	337
EricLew	0:80ee8f3b695e	338	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	339	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	340
EricLew	0:80ee8f3b695e	341	/* Return function status */
EricLew	0:80ee8f3b695e	342	return HAL_OK;
EricLew	0:80ee8f3b695e	343	}
EricLew	0:80ee8f3b695e	344
EricLew	0:80ee8f3b695e	345	/**
EricLew	0:80ee8f3b695e	346	* @brief Stops the TIM Base generation in interrupt mode.
EricLew	0:80ee8f3b695e	347	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	348	* @retval HAL status
EricLew	0:80ee8f3b695e	349	*/
EricLew	0:80ee8f3b695e	350	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	351	{
EricLew	0:80ee8f3b695e	352	/* Check the parameters */
EricLew	0:80ee8f3b695e	353	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	354	/* Disable the TIM Update interrupt */
EricLew	0:80ee8f3b695e	355	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
EricLew	0:80ee8f3b695e	356
EricLew	0:80ee8f3b695e	357	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	358	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	359
EricLew	0:80ee8f3b695e	360	/* Return function status */
EricLew	0:80ee8f3b695e	361	return HAL_OK;
EricLew	0:80ee8f3b695e	362	}
EricLew	0:80ee8f3b695e	363
EricLew	0:80ee8f3b695e	364	/**
EricLew	0:80ee8f3b695e	365	* @brief Starts the TIM Base generation in DMA mode.
EricLew	0:80ee8f3b695e	366	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	367	* @param pData: The source Buffer address.
EricLew	0:80ee8f3b695e	368	* @param Length: The length of data to be transferred from memory to peripheral.
EricLew	0:80ee8f3b695e	369	* @retval HAL status
EricLew	0:80ee8f3b695e	370	*/
EricLew	0:80ee8f3b695e	371	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
EricLew	0:80ee8f3b695e	372	{
EricLew	0:80ee8f3b695e	373	/* Check the parameters */
EricLew	0:80ee8f3b695e	374	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	375
EricLew	0:80ee8f3b695e	376	if((htim->State == HAL_TIM_STATE_BUSY))
EricLew	0:80ee8f3b695e	377	{
EricLew	0:80ee8f3b695e	378	return HAL_BUSY;
EricLew	0:80ee8f3b695e	379	}
EricLew	0:80ee8f3b695e	380	else if((htim->State == HAL_TIM_STATE_READY))
EricLew	0:80ee8f3b695e	381	{
EricLew	0:80ee8f3b695e	382	if((pData == 0 ) && (Length > 0))
EricLew	0:80ee8f3b695e	383	{
EricLew	0:80ee8f3b695e	384	return HAL_ERROR;
EricLew	0:80ee8f3b695e	385	}
EricLew	0:80ee8f3b695e	386	else
EricLew	0:80ee8f3b695e	387	{
EricLew	0:80ee8f3b695e	388	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	389	}
EricLew	0:80ee8f3b695e	390	}
EricLew	0:80ee8f3b695e	391	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	392	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
EricLew	0:80ee8f3b695e	393
EricLew	0:80ee8f3b695e	394	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	395	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	396
EricLew	0:80ee8f3b695e	397	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	398	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
EricLew	0:80ee8f3b695e	399
EricLew	0:80ee8f3b695e	400	/* Enable the TIM Update DMA request */
EricLew	0:80ee8f3b695e	401	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
EricLew	0:80ee8f3b695e	402
EricLew	0:80ee8f3b695e	403	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	404	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	405
EricLew	0:80ee8f3b695e	406	/* Return function status */
EricLew	0:80ee8f3b695e	407	return HAL_OK;
EricLew	0:80ee8f3b695e	408	}
EricLew	0:80ee8f3b695e	409
EricLew	0:80ee8f3b695e	410	/**
EricLew	0:80ee8f3b695e	411	* @brief Stops the TIM Base generation in DMA mode.
EricLew	0:80ee8f3b695e	412	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	413	* @retval HAL status
EricLew	0:80ee8f3b695e	414	*/
EricLew	0:80ee8f3b695e	415	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	416	{
EricLew	0:80ee8f3b695e	417	/* Check the parameters */
EricLew	0:80ee8f3b695e	418	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	419
EricLew	0:80ee8f3b695e	420	/* Disable the TIM Update DMA request */
EricLew	0:80ee8f3b695e	421	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
EricLew	0:80ee8f3b695e	422
EricLew	0:80ee8f3b695e	423	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	424	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	425
EricLew	0:80ee8f3b695e	426	/* Change the htim state */
EricLew	0:80ee8f3b695e	427	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	428
EricLew	0:80ee8f3b695e	429	/* Return function status */
EricLew	0:80ee8f3b695e	430	return HAL_OK;
EricLew	0:80ee8f3b695e	431	}
EricLew	0:80ee8f3b695e	432
EricLew	0:80ee8f3b695e	433	/**
EricLew	0:80ee8f3b695e	434	* @}
EricLew	0:80ee8f3b695e	435	*/
EricLew	0:80ee8f3b695e	436
EricLew	0:80ee8f3b695e	437	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
EricLew	0:80ee8f3b695e	438	* @brief Time Output Compare functions
EricLew	0:80ee8f3b695e	439	*
EricLew	0:80ee8f3b695e	440	@verbatim
EricLew	0:80ee8f3b695e	441	==============================================================================
EricLew	0:80ee8f3b695e	442	##### Time Output Compare functions #####
EricLew	0:80ee8f3b695e	443	==============================================================================
EricLew	0:80ee8f3b695e	444	[..]
EricLew	0:80ee8f3b695e	445	This section provides functions allowing to:
EricLew	0:80ee8f3b695e	446	(+) Initialize and configure the TIM Output Compare.
EricLew	0:80ee8f3b695e	447	(+) De-initialize the TIM Output Compare.
EricLew	0:80ee8f3b695e	448	(+) Start the Time Output Compare.
EricLew	0:80ee8f3b695e	449	(+) Stop the Time Output Compare.
EricLew	0:80ee8f3b695e	450	(+) Start the Time Output Compare and enable interrupt.
EricLew	0:80ee8f3b695e	451	(+) Stop the Time Output Compare and disable interrupt.
EricLew	0:80ee8f3b695e	452	(+) Start the Time Output Compare and enable DMA transfer.
EricLew	0:80ee8f3b695e	453	(+) Stop the Time Output Compare and disable DMA transfer.
EricLew	0:80ee8f3b695e	454
EricLew	0:80ee8f3b695e	455	@endverbatim
EricLew	0:80ee8f3b695e	456	* @{
EricLew	0:80ee8f3b695e	457	*/
EricLew	0:80ee8f3b695e	458	/**
EricLew	0:80ee8f3b695e	459	* @brief Initializes the TIM Output Compare according to the specified
EricLew	0:80ee8f3b695e	460	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
EricLew	0:80ee8f3b695e	461	* @param htim: TIM Output Compare handle
EricLew	0:80ee8f3b695e	462	* @retval HAL status
EricLew	0:80ee8f3b695e	463	*/
EricLew	0:80ee8f3b695e	464	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
EricLew	0:80ee8f3b695e	465	{
EricLew	0:80ee8f3b695e	466	/* Check the TIM handle allocation */
EricLew	0:80ee8f3b695e	467	if(htim == NULL)
EricLew	0:80ee8f3b695e	468	{
EricLew	0:80ee8f3b695e	469	return HAL_ERROR;
EricLew	0:80ee8f3b695e	470	}
EricLew	0:80ee8f3b695e	471
EricLew	0:80ee8f3b695e	472	/* Check the parameters */
EricLew	0:80ee8f3b695e	473	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	474	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
EricLew	0:80ee8f3b695e	475	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
EricLew	0:80ee8f3b695e	476
EricLew	0:80ee8f3b695e	477	if(htim->State == HAL_TIM_STATE_RESET)
EricLew	0:80ee8f3b695e	478	{
EricLew	0:80ee8f3b695e	479	/* Allocate lock resource and initialize it */
EricLew	0:80ee8f3b695e	480	htim->Lock = HAL_UNLOCKED;
EricLew	0:80ee8f3b695e	481
EricLew	0:80ee8f3b695e	482	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
EricLew	0:80ee8f3b695e	483	HAL_TIM_OC_MspInit(htim);
EricLew	0:80ee8f3b695e	484	}
EricLew	0:80ee8f3b695e	485
EricLew	0:80ee8f3b695e	486	/* Set the TIM state */
EricLew	0:80ee8f3b695e	487	htim->State= HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	488
EricLew	0:80ee8f3b695e	489	/* Init the base time for the Output Compare */
EricLew	0:80ee8f3b695e	490	TIM_Base_SetConfig(htim->Instance, &htim->Init);
EricLew	0:80ee8f3b695e	491
EricLew	0:80ee8f3b695e	492	/* Initialize the TIM state*/
EricLew	0:80ee8f3b695e	493	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	494
EricLew	0:80ee8f3b695e	495	return HAL_OK;
EricLew	0:80ee8f3b695e	496	}
EricLew	0:80ee8f3b695e	497
EricLew	0:80ee8f3b695e	498	/**
EricLew	0:80ee8f3b695e	499	* @brief DeInitialize the TIM peripheral
EricLew	0:80ee8f3b695e	500	* @param htim: TIM Output Compare handle
EricLew	0:80ee8f3b695e	501	* @retval HAL status
EricLew	0:80ee8f3b695e	502	*/
EricLew	0:80ee8f3b695e	503	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	504	{
EricLew	0:80ee8f3b695e	505	/* Check the parameters */
EricLew	0:80ee8f3b695e	506	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	507
EricLew	0:80ee8f3b695e	508	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	509
EricLew	0:80ee8f3b695e	510	/* Disable the TIM Peripheral Clock */
EricLew	0:80ee8f3b695e	511	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	512
EricLew	0:80ee8f3b695e	513	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
EricLew	0:80ee8f3b695e	514	HAL_TIM_OC_MspDeInit(htim);
EricLew	0:80ee8f3b695e	515
EricLew	0:80ee8f3b695e	516	/* Change TIM state */
EricLew	0:80ee8f3b695e	517	htim->State = HAL_TIM_STATE_RESET;
EricLew	0:80ee8f3b695e	518
EricLew	0:80ee8f3b695e	519	/* Release Lock */
EricLew	0:80ee8f3b695e	520	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	521
EricLew	0:80ee8f3b695e	522	return HAL_OK;
EricLew	0:80ee8f3b695e	523	}
EricLew	0:80ee8f3b695e	524
EricLew	0:80ee8f3b695e	525	/**
EricLew	0:80ee8f3b695e	526	* @brief Initializes the TIM Output Compare MSP.
EricLew	0:80ee8f3b695e	527	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	528	* @retval None
EricLew	0:80ee8f3b695e	529	*/
EricLew	0:80ee8f3b695e	530	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	531	{
EricLew	0:80ee8f3b695e	532	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	533	the HAL_TIM_OC_MspInit could be implemented in the user file
EricLew	0:80ee8f3b695e	534	*/
EricLew	0:80ee8f3b695e	535	}
EricLew	0:80ee8f3b695e	536
EricLew	0:80ee8f3b695e	537	/**
EricLew	0:80ee8f3b695e	538	* @brief DeInitialize TIM Output Compare MSP.
EricLew	0:80ee8f3b695e	539	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	540	* @retval None
EricLew	0:80ee8f3b695e	541	*/
EricLew	0:80ee8f3b695e	542	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	543	{
EricLew	0:80ee8f3b695e	544	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	545	the HAL_TIM_OC_MspDeInit could be implemented in the user file
EricLew	0:80ee8f3b695e	546	*/
EricLew	0:80ee8f3b695e	547	}
EricLew	0:80ee8f3b695e	548
EricLew	0:80ee8f3b695e	549	/**
EricLew	0:80ee8f3b695e	550	* @brief Starts the TIM Output Compare signal generation.
EricLew	0:80ee8f3b695e	551	* @param htim : TIM Output Compare handle
EricLew	0:80ee8f3b695e	552	* @param Channel : TIM Channel to be enabled
EricLew	0:80ee8f3b695e	553	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	554	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	555	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	556	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	557	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	558	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
EricLew	0:80ee8f3b695e	559	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
EricLew	0:80ee8f3b695e	560	* @retval HAL status
EricLew	0:80ee8f3b695e	561	*/
EricLew	0:80ee8f3b695e	562	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	563	{
EricLew	0:80ee8f3b695e	564	/* Check the parameters */
EricLew	0:80ee8f3b695e	565	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	566
EricLew	0:80ee8f3b695e	567	/* Enable the Output compare channel */
EricLew	0:80ee8f3b695e	568	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	569
EricLew	0:80ee8f3b695e	570	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	571	{
EricLew	0:80ee8f3b695e	572	/* Enable the main output */
EricLew	0:80ee8f3b695e	573	__HAL_TIM_MOE_ENABLE(htim);
EricLew	0:80ee8f3b695e	574	}
EricLew	0:80ee8f3b695e	575
EricLew	0:80ee8f3b695e	576	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	577	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	578
EricLew	0:80ee8f3b695e	579	/* Return function status */
EricLew	0:80ee8f3b695e	580	return HAL_OK;
EricLew	0:80ee8f3b695e	581	}
EricLew	0:80ee8f3b695e	582
EricLew	0:80ee8f3b695e	583	/**
EricLew	0:80ee8f3b695e	584	* @brief Stops the TIM Output Compare signal generation.
EricLew	0:80ee8f3b695e	585	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	586	* @param Channel : TIM Channel to be disabled
EricLew	0:80ee8f3b695e	587	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	588	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	589	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	590	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	591	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	592	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
EricLew	0:80ee8f3b695e	593	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
EricLew	0:80ee8f3b695e	594	* @retval HAL status
EricLew	0:80ee8f3b695e	595	*/
EricLew	0:80ee8f3b695e	596	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	597	{
EricLew	0:80ee8f3b695e	598	/* Check the parameters */
EricLew	0:80ee8f3b695e	599	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	600
EricLew	0:80ee8f3b695e	601	/* Disable the Output compare channel */
EricLew	0:80ee8f3b695e	602	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	603
EricLew	0:80ee8f3b695e	604	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	605	{
EricLew	0:80ee8f3b695e	606	/* Disable the Main Ouput */
EricLew	0:80ee8f3b695e	607	__HAL_TIM_MOE_DISABLE(htim);
EricLew	0:80ee8f3b695e	608	}
EricLew	0:80ee8f3b695e	609
EricLew	0:80ee8f3b695e	610	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	611	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	612
EricLew	0:80ee8f3b695e	613	/* Return function status */
EricLew	0:80ee8f3b695e	614	return HAL_OK;
EricLew	0:80ee8f3b695e	615	}
EricLew	0:80ee8f3b695e	616
EricLew	0:80ee8f3b695e	617	/**
EricLew	0:80ee8f3b695e	618	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
EricLew	0:80ee8f3b695e	619	* @param htim : TIM OC handle
EricLew	0:80ee8f3b695e	620	* @param Channel : TIM Channel to be enabled
EricLew	0:80ee8f3b695e	621	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	622	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	623	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	624	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	625	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	626	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
EricLew	0:80ee8f3b695e	627	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
EricLew	0:80ee8f3b695e	628	* @retval HAL status
EricLew	0:80ee8f3b695e	629	*/
EricLew	0:80ee8f3b695e	630	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	631	{
EricLew	0:80ee8f3b695e	632	/* Check the parameters */
EricLew	0:80ee8f3b695e	633	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	634
EricLew	0:80ee8f3b695e	635	switch (Channel)
EricLew	0:80ee8f3b695e	636	{
EricLew	0:80ee8f3b695e	637	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	638	{
EricLew	0:80ee8f3b695e	639	/* Enable the TIM Capture/Compare 1 interrupt */
EricLew	0:80ee8f3b695e	640	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	641	}
EricLew	0:80ee8f3b695e	642	break;
EricLew	0:80ee8f3b695e	643
EricLew	0:80ee8f3b695e	644	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	645	{
EricLew	0:80ee8f3b695e	646	/* Enable the TIM Capture/Compare 2 interrupt */
EricLew	0:80ee8f3b695e	647	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	648	}
EricLew	0:80ee8f3b695e	649	break;
EricLew	0:80ee8f3b695e	650
EricLew	0:80ee8f3b695e	651	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	652	{
EricLew	0:80ee8f3b695e	653	/* Enable the TIM Capture/Compare 3 interrupt */
EricLew	0:80ee8f3b695e	654	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
EricLew	0:80ee8f3b695e	655	}
EricLew	0:80ee8f3b695e	656	break;
EricLew	0:80ee8f3b695e	657
EricLew	0:80ee8f3b695e	658	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	659	{
EricLew	0:80ee8f3b695e	660	/* Enable the TIM Capture/Compare 4 interrupt */
EricLew	0:80ee8f3b695e	661	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
EricLew	0:80ee8f3b695e	662	}
EricLew	0:80ee8f3b695e	663	break;
EricLew	0:80ee8f3b695e	664
EricLew	0:80ee8f3b695e	665	default:
EricLew	0:80ee8f3b695e	666	break;
EricLew	0:80ee8f3b695e	667	}
EricLew	0:80ee8f3b695e	668
EricLew	0:80ee8f3b695e	669	/* Enable the Output compare channel */
EricLew	0:80ee8f3b695e	670	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	671
EricLew	0:80ee8f3b695e	672	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	673	{
EricLew	0:80ee8f3b695e	674	/* Enable the main output */
EricLew	0:80ee8f3b695e	675	__HAL_TIM_MOE_ENABLE(htim);
EricLew	0:80ee8f3b695e	676	}
EricLew	0:80ee8f3b695e	677
EricLew	0:80ee8f3b695e	678	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	679	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	680
EricLew	0:80ee8f3b695e	681	/* Return function status */
EricLew	0:80ee8f3b695e	682	return HAL_OK;
EricLew	0:80ee8f3b695e	683	}
EricLew	0:80ee8f3b695e	684
EricLew	0:80ee8f3b695e	685	/**
EricLew	0:80ee8f3b695e	686	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
EricLew	0:80ee8f3b695e	687	* @param htim : TIM Output Compare handle
EricLew	0:80ee8f3b695e	688	* @param Channel : TIM Channel to be disabled
EricLew	0:80ee8f3b695e	689	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	690	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	691	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	692	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	693	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	694	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
EricLew	0:80ee8f3b695e	695	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
EricLew	0:80ee8f3b695e	696	* @retval HAL status
EricLew	0:80ee8f3b695e	697	*/
EricLew	0:80ee8f3b695e	698	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	699	{
EricLew	0:80ee8f3b695e	700	/* Check the parameters */
EricLew	0:80ee8f3b695e	701	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	702
EricLew	0:80ee8f3b695e	703	switch (Channel)
EricLew	0:80ee8f3b695e	704	{
EricLew	0:80ee8f3b695e	705	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	706	{
EricLew	0:80ee8f3b695e	707	/* Disable the TIM Capture/Compare 1 interrupt */
EricLew	0:80ee8f3b695e	708	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	709	}
EricLew	0:80ee8f3b695e	710	break;
EricLew	0:80ee8f3b695e	711
EricLew	0:80ee8f3b695e	712	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	713	{
EricLew	0:80ee8f3b695e	714	/* Disable the TIM Capture/Compare 2 interrupt */
EricLew	0:80ee8f3b695e	715	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	716	}
EricLew	0:80ee8f3b695e	717	break;
EricLew	0:80ee8f3b695e	718
EricLew	0:80ee8f3b695e	719	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	720	{
EricLew	0:80ee8f3b695e	721	/* Disable the TIM Capture/Compare 3 interrupt */
EricLew	0:80ee8f3b695e	722	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
EricLew	0:80ee8f3b695e	723	}
EricLew	0:80ee8f3b695e	724	break;
EricLew	0:80ee8f3b695e	725
EricLew	0:80ee8f3b695e	726	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	727	{
EricLew	0:80ee8f3b695e	728	/* Disable the TIM Capture/Compare 4 interrupt */
EricLew	0:80ee8f3b695e	729	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
EricLew	0:80ee8f3b695e	730	}
EricLew	0:80ee8f3b695e	731	break;
EricLew	0:80ee8f3b695e	732
EricLew	0:80ee8f3b695e	733	default:
EricLew	0:80ee8f3b695e	734	break;
EricLew	0:80ee8f3b695e	735	}
EricLew	0:80ee8f3b695e	736
EricLew	0:80ee8f3b695e	737	/* Disable the Output compare channel */
EricLew	0:80ee8f3b695e	738	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	739
EricLew	0:80ee8f3b695e	740	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	741	{
EricLew	0:80ee8f3b695e	742	/* Disable the Main Ouput */
EricLew	0:80ee8f3b695e	743	__HAL_TIM_MOE_DISABLE(htim);
EricLew	0:80ee8f3b695e	744	}
EricLew	0:80ee8f3b695e	745
EricLew	0:80ee8f3b695e	746	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	747	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	748
EricLew	0:80ee8f3b695e	749	/* Return function status */
EricLew	0:80ee8f3b695e	750	return HAL_OK;
EricLew	0:80ee8f3b695e	751	}
EricLew	0:80ee8f3b695e	752
EricLew	0:80ee8f3b695e	753	/**
EricLew	0:80ee8f3b695e	754	* @brief Starts the TIM Output Compare signal generation in DMA mode.
EricLew	0:80ee8f3b695e	755	* @param htim : TIM Output Compare handle
EricLew	0:80ee8f3b695e	756	* @param Channel : TIM Channel to be enabled
EricLew	0:80ee8f3b695e	757	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	758	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	759	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	760	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	761	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	762	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
EricLew	0:80ee8f3b695e	763	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
EricLew	0:80ee8f3b695e	764	* @param pData: The source Buffer address.
EricLew	0:80ee8f3b695e	765	* @param Length: The length of data to be transferred from memory to TIM peripheral
EricLew	0:80ee8f3b695e	766	* @retval HAL status
EricLew	0:80ee8f3b695e	767	*/
EricLew	0:80ee8f3b695e	768	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
EricLew	0:80ee8f3b695e	769	{
EricLew	0:80ee8f3b695e	770	/* Check the parameters */
EricLew	0:80ee8f3b695e	771	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	772
EricLew	0:80ee8f3b695e	773	if((htim->State == HAL_TIM_STATE_BUSY))
EricLew	0:80ee8f3b695e	774	{
EricLew	0:80ee8f3b695e	775	return HAL_BUSY;
EricLew	0:80ee8f3b695e	776	}
EricLew	0:80ee8f3b695e	777	else if((htim->State == HAL_TIM_STATE_READY))
EricLew	0:80ee8f3b695e	778	{
EricLew	0:80ee8f3b695e	779	if(((uint32_t)pData == 0 ) && (Length > 0))
EricLew	0:80ee8f3b695e	780	{
EricLew	0:80ee8f3b695e	781	return HAL_ERROR;
EricLew	0:80ee8f3b695e	782	}
EricLew	0:80ee8f3b695e	783	else
EricLew	0:80ee8f3b695e	784	{
EricLew	0:80ee8f3b695e	785	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	786	}
EricLew	0:80ee8f3b695e	787	}
EricLew	0:80ee8f3b695e	788	switch (Channel)
EricLew	0:80ee8f3b695e	789	{
EricLew	0:80ee8f3b695e	790	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	791	{
EricLew	0:80ee8f3b695e	792	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	793	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	794
EricLew	0:80ee8f3b695e	795	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	796	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	797
EricLew	0:80ee8f3b695e	798	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	799	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
EricLew	0:80ee8f3b695e	800
EricLew	0:80ee8f3b695e	801	/* Enable the TIM Capture/Compare 1 DMA request */
EricLew	0:80ee8f3b695e	802	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	803	}
EricLew	0:80ee8f3b695e	804	break;
EricLew	0:80ee8f3b695e	805
EricLew	0:80ee8f3b695e	806	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	807	{
EricLew	0:80ee8f3b695e	808	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	809	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	810
EricLew	0:80ee8f3b695e	811	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	812	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	813
EricLew	0:80ee8f3b695e	814	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	815	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
EricLew	0:80ee8f3b695e	816
EricLew	0:80ee8f3b695e	817	/* Enable the TIM Capture/Compare 2 DMA request */
EricLew	0:80ee8f3b695e	818	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	819	}
EricLew	0:80ee8f3b695e	820	break;
EricLew	0:80ee8f3b695e	821
EricLew	0:80ee8f3b695e	822	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	823	{
EricLew	0:80ee8f3b695e	824	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	825	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	826
EricLew	0:80ee8f3b695e	827	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	828	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	829
EricLew	0:80ee8f3b695e	830	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	831	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
EricLew	0:80ee8f3b695e	832
EricLew	0:80ee8f3b695e	833	/* Enable the TIM Capture/Compare 3 DMA request */
EricLew	0:80ee8f3b695e	834	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
EricLew	0:80ee8f3b695e	835	}
EricLew	0:80ee8f3b695e	836	break;
EricLew	0:80ee8f3b695e	837
EricLew	0:80ee8f3b695e	838	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	839	{
EricLew	0:80ee8f3b695e	840	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	841	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	842
EricLew	0:80ee8f3b695e	843	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	844	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	845
EricLew	0:80ee8f3b695e	846	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	847	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
EricLew	0:80ee8f3b695e	848
EricLew	0:80ee8f3b695e	849	/* Enable the TIM Capture/Compare 4 DMA request */
EricLew	0:80ee8f3b695e	850	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
EricLew	0:80ee8f3b695e	851	}
EricLew	0:80ee8f3b695e	852	break;
EricLew	0:80ee8f3b695e	853
EricLew	0:80ee8f3b695e	854	default:
EricLew	0:80ee8f3b695e	855	break;
EricLew	0:80ee8f3b695e	856	}
EricLew	0:80ee8f3b695e	857
EricLew	0:80ee8f3b695e	858	/* Enable the Output compare channel */
EricLew	0:80ee8f3b695e	859	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	860
EricLew	0:80ee8f3b695e	861	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	862	{
EricLew	0:80ee8f3b695e	863	/* Enable the main output */
EricLew	0:80ee8f3b695e	864	__HAL_TIM_MOE_ENABLE(htim);
EricLew	0:80ee8f3b695e	865	}
EricLew	0:80ee8f3b695e	866
EricLew	0:80ee8f3b695e	867	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	868	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	869
EricLew	0:80ee8f3b695e	870	/* Return function status */
EricLew	0:80ee8f3b695e	871	return HAL_OK;
EricLew	0:80ee8f3b695e	872	}
EricLew	0:80ee8f3b695e	873
EricLew	0:80ee8f3b695e	874	/**
EricLew	0:80ee8f3b695e	875	* @brief Stops the TIM Output Compare signal generation in DMA mode.
EricLew	0:80ee8f3b695e	876	* @param htim : TIM Output Compare handle
EricLew	0:80ee8f3b695e	877	* @param Channel : TIM Channel to be disabled
EricLew	0:80ee8f3b695e	878	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	879	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	880	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	881	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	882	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	883	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
EricLew	0:80ee8f3b695e	884	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
EricLew	0:80ee8f3b695e	885	* @retval HAL status
EricLew	0:80ee8f3b695e	886	*/
EricLew	0:80ee8f3b695e	887	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	888	{
EricLew	0:80ee8f3b695e	889	/* Check the parameters */
EricLew	0:80ee8f3b695e	890	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	891
EricLew	0:80ee8f3b695e	892	switch (Channel)
EricLew	0:80ee8f3b695e	893	{
EricLew	0:80ee8f3b695e	894	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	895	{
EricLew	0:80ee8f3b695e	896	/* Disable the TIM Capture/Compare 1 DMA request */
EricLew	0:80ee8f3b695e	897	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	898	}
EricLew	0:80ee8f3b695e	899	break;
EricLew	0:80ee8f3b695e	900
EricLew	0:80ee8f3b695e	901	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	902	{
EricLew	0:80ee8f3b695e	903	/* Disable the TIM Capture/Compare 2 DMA request */
EricLew	0:80ee8f3b695e	904	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	905	}
EricLew	0:80ee8f3b695e	906	break;
EricLew	0:80ee8f3b695e	907
EricLew	0:80ee8f3b695e	908	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	909	{
EricLew	0:80ee8f3b695e	910	/* Disable the TIM Capture/Compare 3 DMA request */
EricLew	0:80ee8f3b695e	911	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
EricLew	0:80ee8f3b695e	912	}
EricLew	0:80ee8f3b695e	913	break;
EricLew	0:80ee8f3b695e	914
EricLew	0:80ee8f3b695e	915	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	916	{
EricLew	0:80ee8f3b695e	917	/* Disable the TIM Capture/Compare 4 interrupt */
EricLew	0:80ee8f3b695e	918	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
EricLew	0:80ee8f3b695e	919	}
EricLew	0:80ee8f3b695e	920	break;
EricLew	0:80ee8f3b695e	921
EricLew	0:80ee8f3b695e	922	default:
EricLew	0:80ee8f3b695e	923	break;
EricLew	0:80ee8f3b695e	924	}
EricLew	0:80ee8f3b695e	925
EricLew	0:80ee8f3b695e	926	/* Disable the Output compare channel */
EricLew	0:80ee8f3b695e	927	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	928
EricLew	0:80ee8f3b695e	929	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	930	{
EricLew	0:80ee8f3b695e	931	/* Disable the Main Ouput */
EricLew	0:80ee8f3b695e	932	__HAL_TIM_MOE_DISABLE(htim);
EricLew	0:80ee8f3b695e	933	}
EricLew	0:80ee8f3b695e	934
EricLew	0:80ee8f3b695e	935	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	936	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	937
EricLew	0:80ee8f3b695e	938	/* Change the htim state */
EricLew	0:80ee8f3b695e	939	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	940
EricLew	0:80ee8f3b695e	941	/* Return function status */
EricLew	0:80ee8f3b695e	942	return HAL_OK;
EricLew	0:80ee8f3b695e	943	}
EricLew	0:80ee8f3b695e	944
EricLew	0:80ee8f3b695e	945	/**
EricLew	0:80ee8f3b695e	946	* @}
EricLew	0:80ee8f3b695e	947	*/
EricLew	0:80ee8f3b695e	948
EricLew	0:80ee8f3b695e	949	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
EricLew	0:80ee8f3b695e	950	* @brief Time PWM functions
EricLew	0:80ee8f3b695e	951	*
EricLew	0:80ee8f3b695e	952	@verbatim
EricLew	0:80ee8f3b695e	953	==============================================================================
EricLew	0:80ee8f3b695e	954	##### Time PWM functions #####
EricLew	0:80ee8f3b695e	955	==============================================================================
EricLew	0:80ee8f3b695e	956	[..]
EricLew	0:80ee8f3b695e	957	This section provides functions allowing to:
EricLew	0:80ee8f3b695e	958	(+) Initialize and configure the TIM OPWM.
EricLew	0:80ee8f3b695e	959	(+) De-initialize the TIM PWM.
EricLew	0:80ee8f3b695e	960	(+) Start the Time PWM.
EricLew	0:80ee8f3b695e	961	(+) Stop the Time PWM.
EricLew	0:80ee8f3b695e	962	(+) Start the Time PWM and enable interrupt.
EricLew	0:80ee8f3b695e	963	(+) Stop the Time PWM and disable interrupt.
EricLew	0:80ee8f3b695e	964	(+) Start the Time PWM and enable DMA transfer.
EricLew	0:80ee8f3b695e	965	(+) Stop the Time PWM and disable DMA transfer.
EricLew	0:80ee8f3b695e	966
EricLew	0:80ee8f3b695e	967	@endverbatim
EricLew	0:80ee8f3b695e	968	* @{
EricLew	0:80ee8f3b695e	969	*/
EricLew	0:80ee8f3b695e	970	/**
EricLew	0:80ee8f3b695e	971	* @brief Initializes the TIM PWM Time Base according to the specified
EricLew	0:80ee8f3b695e	972	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
EricLew	0:80ee8f3b695e	973	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	974	* @retval HAL status
EricLew	0:80ee8f3b695e	975	*/
EricLew	0:80ee8f3b695e	976	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	977	{
EricLew	0:80ee8f3b695e	978	/* Check the TIM handle allocation */
EricLew	0:80ee8f3b695e	979	if(htim == NULL)
EricLew	0:80ee8f3b695e	980	{
EricLew	0:80ee8f3b695e	981	return HAL_ERROR;
EricLew	0:80ee8f3b695e	982	}
EricLew	0:80ee8f3b695e	983
EricLew	0:80ee8f3b695e	984	/* Check the parameters */
EricLew	0:80ee8f3b695e	985	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	986	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
EricLew	0:80ee8f3b695e	987	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
EricLew	0:80ee8f3b695e	988
EricLew	0:80ee8f3b695e	989	if(htim->State == HAL_TIM_STATE_RESET)
EricLew	0:80ee8f3b695e	990	{
EricLew	0:80ee8f3b695e	991	/* Allocate lock resource and initialize it */
EricLew	0:80ee8f3b695e	992	htim->Lock = HAL_UNLOCKED;
EricLew	0:80ee8f3b695e	993
EricLew	0:80ee8f3b695e	994	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
EricLew	0:80ee8f3b695e	995	HAL_TIM_PWM_MspInit(htim);
EricLew	0:80ee8f3b695e	996	}
EricLew	0:80ee8f3b695e	997
EricLew	0:80ee8f3b695e	998	/* Set the TIM state */
EricLew	0:80ee8f3b695e	999	htim->State= HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	1000
EricLew	0:80ee8f3b695e	1001	/* Init the base time for the PWM */
EricLew	0:80ee8f3b695e	1002	TIM_Base_SetConfig(htim->Instance, &htim->Init);
EricLew	0:80ee8f3b695e	1003
EricLew	0:80ee8f3b695e	1004	/* Initialize the TIM state*/
EricLew	0:80ee8f3b695e	1005	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	1006
EricLew	0:80ee8f3b695e	1007	return HAL_OK;
EricLew	0:80ee8f3b695e	1008	}
EricLew	0:80ee8f3b695e	1009
EricLew	0:80ee8f3b695e	1010	/**
EricLew	0:80ee8f3b695e	1011	* @brief DeInitialize the TIM peripheral
EricLew	0:80ee8f3b695e	1012	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	1013	* @retval HAL status
EricLew	0:80ee8f3b695e	1014	*/
EricLew	0:80ee8f3b695e	1015	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	1016	{
EricLew	0:80ee8f3b695e	1017	/* Check the parameters */
EricLew	0:80ee8f3b695e	1018	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	1019
EricLew	0:80ee8f3b695e	1020	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	1021
EricLew	0:80ee8f3b695e	1022	/* Disable the TIM Peripheral Clock */
EricLew	0:80ee8f3b695e	1023	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	1024
EricLew	0:80ee8f3b695e	1025	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
EricLew	0:80ee8f3b695e	1026	HAL_TIM_PWM_MspDeInit(htim);
EricLew	0:80ee8f3b695e	1027
EricLew	0:80ee8f3b695e	1028	/* Change TIM state */
EricLew	0:80ee8f3b695e	1029	htim->State = HAL_TIM_STATE_RESET;
EricLew	0:80ee8f3b695e	1030
EricLew	0:80ee8f3b695e	1031	/* Release Lock */
EricLew	0:80ee8f3b695e	1032	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	1033
EricLew	0:80ee8f3b695e	1034	return HAL_OK;
EricLew	0:80ee8f3b695e	1035	}
EricLew	0:80ee8f3b695e	1036
EricLew	0:80ee8f3b695e	1037	/**
EricLew	0:80ee8f3b695e	1038	* @brief Initializes the TIM PWM MSP.
EricLew	0:80ee8f3b695e	1039	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	1040	* @retval None
EricLew	0:80ee8f3b695e	1041	*/
EricLew	0:80ee8f3b695e	1042	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	1043	{
EricLew	0:80ee8f3b695e	1044	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	1045	the HAL_TIM_PWM_MspInit could be implemented in the user file
EricLew	0:80ee8f3b695e	1046	*/
EricLew	0:80ee8f3b695e	1047	}
EricLew	0:80ee8f3b695e	1048
EricLew	0:80ee8f3b695e	1049	/**
EricLew	0:80ee8f3b695e	1050	* @brief DeInitialize TIM PWM MSP.
EricLew	0:80ee8f3b695e	1051	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	1052	* @retval None
EricLew	0:80ee8f3b695e	1053	*/
EricLew	0:80ee8f3b695e	1054	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	1055	{
EricLew	0:80ee8f3b695e	1056	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	1057	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
EricLew	0:80ee8f3b695e	1058	*/
EricLew	0:80ee8f3b695e	1059	}
EricLew	0:80ee8f3b695e	1060
EricLew	0:80ee8f3b695e	1061	/**
EricLew	0:80ee8f3b695e	1062	* @brief Starts the PWM signal generation.
EricLew	0:80ee8f3b695e	1063	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	1064	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	1065	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1066	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1067	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1068	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1069	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1070	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
EricLew	0:80ee8f3b695e	1071	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
EricLew	0:80ee8f3b695e	1072	* @retval HAL status
EricLew	0:80ee8f3b695e	1073	*/
EricLew	0:80ee8f3b695e	1074	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1075	{
EricLew	0:80ee8f3b695e	1076	/* Check the parameters */
EricLew	0:80ee8f3b695e	1077	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1078
EricLew	0:80ee8f3b695e	1079	/* Enable the Capture compare channel */
EricLew	0:80ee8f3b695e	1080	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	1081
EricLew	0:80ee8f3b695e	1082	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	1083	{
EricLew	0:80ee8f3b695e	1084	/* Enable the main output */
EricLew	0:80ee8f3b695e	1085	__HAL_TIM_MOE_ENABLE(htim);
EricLew	0:80ee8f3b695e	1086	}
EricLew	0:80ee8f3b695e	1087
EricLew	0:80ee8f3b695e	1088	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	1089	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	1090
EricLew	0:80ee8f3b695e	1091	/* Return function status */
EricLew	0:80ee8f3b695e	1092	return HAL_OK;
EricLew	0:80ee8f3b695e	1093	}
EricLew	0:80ee8f3b695e	1094
EricLew	0:80ee8f3b695e	1095	/**
EricLew	0:80ee8f3b695e	1096	* @brief Stops the PWM signal generation.
EricLew	0:80ee8f3b695e	1097	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	1098	* @param Channel : TIM Channels to be disabled
EricLew	0:80ee8f3b695e	1099	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1100	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1101	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1102	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1103	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1104	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
EricLew	0:80ee8f3b695e	1105	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
EricLew	0:80ee8f3b695e	1106	* @retval HAL status
EricLew	0:80ee8f3b695e	1107	*/
EricLew	0:80ee8f3b695e	1108	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1109	{
EricLew	0:80ee8f3b695e	1110	/* Check the parameters */
EricLew	0:80ee8f3b695e	1111	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1112
EricLew	0:80ee8f3b695e	1113	/* Disable the Capture compare channel */
EricLew	0:80ee8f3b695e	1114	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	1115
EricLew	0:80ee8f3b695e	1116	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	1117	{
EricLew	0:80ee8f3b695e	1118	/* Disable the Main Ouput */
EricLew	0:80ee8f3b695e	1119	__HAL_TIM_MOE_DISABLE(htim);
EricLew	0:80ee8f3b695e	1120	}
EricLew	0:80ee8f3b695e	1121
EricLew	0:80ee8f3b695e	1122	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	1123	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	1124
EricLew	0:80ee8f3b695e	1125	/* Change the htim state */
EricLew	0:80ee8f3b695e	1126	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	1127
EricLew	0:80ee8f3b695e	1128	/* Return function status */
EricLew	0:80ee8f3b695e	1129	return HAL_OK;
EricLew	0:80ee8f3b695e	1130	}
EricLew	0:80ee8f3b695e	1131
EricLew	0:80ee8f3b695e	1132	/**
EricLew	0:80ee8f3b695e	1133	* @brief Starts the PWM signal generation in interrupt mode.
EricLew	0:80ee8f3b695e	1134	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	1135	* @param Channel : TIM Channel to be disabled
EricLew	0:80ee8f3b695e	1136	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1137	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1138	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1139	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1140	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1141	* @retval HAL status
EricLew	0:80ee8f3b695e	1142	*/
EricLew	0:80ee8f3b695e	1143	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1144	{
EricLew	0:80ee8f3b695e	1145	/* Check the parameters */
EricLew	0:80ee8f3b695e	1146	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1147
EricLew	0:80ee8f3b695e	1148	switch (Channel)
EricLew	0:80ee8f3b695e	1149	{
EricLew	0:80ee8f3b695e	1150	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	1151	{
EricLew	0:80ee8f3b695e	1152	/* Enable the TIM Capture/Compare 1 interrupt */
EricLew	0:80ee8f3b695e	1153	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	1154	}
EricLew	0:80ee8f3b695e	1155	break;
EricLew	0:80ee8f3b695e	1156
EricLew	0:80ee8f3b695e	1157	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	1158	{
EricLew	0:80ee8f3b695e	1159	/* Enable the TIM Capture/Compare 2 interrupt */
EricLew	0:80ee8f3b695e	1160	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	1161	}
EricLew	0:80ee8f3b695e	1162	break;
EricLew	0:80ee8f3b695e	1163
EricLew	0:80ee8f3b695e	1164	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	1165	{
EricLew	0:80ee8f3b695e	1166	/* Enable the TIM Capture/Compare 3 interrupt */
EricLew	0:80ee8f3b695e	1167	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
EricLew	0:80ee8f3b695e	1168	}
EricLew	0:80ee8f3b695e	1169	break;
EricLew	0:80ee8f3b695e	1170
EricLew	0:80ee8f3b695e	1171	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	1172	{
EricLew	0:80ee8f3b695e	1173	/* Enable the TIM Capture/Compare 4 interrupt */
EricLew	0:80ee8f3b695e	1174	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
EricLew	0:80ee8f3b695e	1175	}
EricLew	0:80ee8f3b695e	1176	break;
EricLew	0:80ee8f3b695e	1177
EricLew	0:80ee8f3b695e	1178	default:
EricLew	0:80ee8f3b695e	1179	break;
EricLew	0:80ee8f3b695e	1180	}
EricLew	0:80ee8f3b695e	1181
EricLew	0:80ee8f3b695e	1182	/* Enable the Capture compare channel */
EricLew	0:80ee8f3b695e	1183	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	1184
EricLew	0:80ee8f3b695e	1185	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	1186	{
EricLew	0:80ee8f3b695e	1187	/* Enable the main output */
EricLew	0:80ee8f3b695e	1188	__HAL_TIM_MOE_ENABLE(htim);
EricLew	0:80ee8f3b695e	1189	}
EricLew	0:80ee8f3b695e	1190
EricLew	0:80ee8f3b695e	1191	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	1192	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	1193
EricLew	0:80ee8f3b695e	1194	/* Return function status */
EricLew	0:80ee8f3b695e	1195	return HAL_OK;
EricLew	0:80ee8f3b695e	1196	}
EricLew	0:80ee8f3b695e	1197
EricLew	0:80ee8f3b695e	1198	/**
EricLew	0:80ee8f3b695e	1199	* @brief Stops the PWM signal generation in interrupt mode.
EricLew	0:80ee8f3b695e	1200	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	1201	* @param Channel : TIM Channels to be disabled
EricLew	0:80ee8f3b695e	1202	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1203	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1204	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1205	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1206	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1207	* @retval HAL status
EricLew	0:80ee8f3b695e	1208	*/
EricLew	0:80ee8f3b695e	1209	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1210	{
EricLew	0:80ee8f3b695e	1211	/* Check the parameters */
EricLew	0:80ee8f3b695e	1212	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1213
EricLew	0:80ee8f3b695e	1214	switch (Channel)
EricLew	0:80ee8f3b695e	1215	{
EricLew	0:80ee8f3b695e	1216	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	1217	{
EricLew	0:80ee8f3b695e	1218	/* Disable the TIM Capture/Compare 1 interrupt */
EricLew	0:80ee8f3b695e	1219	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	1220	}
EricLew	0:80ee8f3b695e	1221	break;
EricLew	0:80ee8f3b695e	1222
EricLew	0:80ee8f3b695e	1223	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	1224	{
EricLew	0:80ee8f3b695e	1225	/* Disable the TIM Capture/Compare 2 interrupt */
EricLew	0:80ee8f3b695e	1226	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	1227	}
EricLew	0:80ee8f3b695e	1228	break;
EricLew	0:80ee8f3b695e	1229
EricLew	0:80ee8f3b695e	1230	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	1231	{
EricLew	0:80ee8f3b695e	1232	/* Disable the TIM Capture/Compare 3 interrupt */
EricLew	0:80ee8f3b695e	1233	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
EricLew	0:80ee8f3b695e	1234	}
EricLew	0:80ee8f3b695e	1235	break;
EricLew	0:80ee8f3b695e	1236
EricLew	0:80ee8f3b695e	1237	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	1238	{
EricLew	0:80ee8f3b695e	1239	/* Disable the TIM Capture/Compare 4 interrupt */
EricLew	0:80ee8f3b695e	1240	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
EricLew	0:80ee8f3b695e	1241	}
EricLew	0:80ee8f3b695e	1242	break;
EricLew	0:80ee8f3b695e	1243
EricLew	0:80ee8f3b695e	1244	default:
EricLew	0:80ee8f3b695e	1245	break;
EricLew	0:80ee8f3b695e	1246	}
EricLew	0:80ee8f3b695e	1247
EricLew	0:80ee8f3b695e	1248	/* Disable the Capture compare channel */
EricLew	0:80ee8f3b695e	1249	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	1250
EricLew	0:80ee8f3b695e	1251	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	1252	{
EricLew	0:80ee8f3b695e	1253	/* Disable the Main Ouput */
EricLew	0:80ee8f3b695e	1254	__HAL_TIM_MOE_DISABLE(htim);
EricLew	0:80ee8f3b695e	1255	}
EricLew	0:80ee8f3b695e	1256
EricLew	0:80ee8f3b695e	1257	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	1258	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	1259
EricLew	0:80ee8f3b695e	1260	/* Return function status */
EricLew	0:80ee8f3b695e	1261	return HAL_OK;
EricLew	0:80ee8f3b695e	1262	}
EricLew	0:80ee8f3b695e	1263
EricLew	0:80ee8f3b695e	1264	/**
EricLew	0:80ee8f3b695e	1265	* @brief Starts the TIM PWM signal generation in DMA mode.
EricLew	0:80ee8f3b695e	1266	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	1267	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	1268	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1269	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1270	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1271	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1272	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1273	* @param pData: The source Buffer address.
EricLew	0:80ee8f3b695e	1274	* @param Length: The length of data to be transferred from memory to TIM peripheral
EricLew	0:80ee8f3b695e	1275	* @retval HAL status
EricLew	0:80ee8f3b695e	1276	*/
EricLew	0:80ee8f3b695e	1277	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
EricLew	0:80ee8f3b695e	1278	{
EricLew	0:80ee8f3b695e	1279	/* Check the parameters */
EricLew	0:80ee8f3b695e	1280	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1281
EricLew	0:80ee8f3b695e	1282	if((htim->State == HAL_TIM_STATE_BUSY))
EricLew	0:80ee8f3b695e	1283	{
EricLew	0:80ee8f3b695e	1284	return HAL_BUSY;
EricLew	0:80ee8f3b695e	1285	}
EricLew	0:80ee8f3b695e	1286	else if((htim->State == HAL_TIM_STATE_READY))
EricLew	0:80ee8f3b695e	1287	{
EricLew	0:80ee8f3b695e	1288	if(((uint32_t)pData == 0 ) && (Length > 0))
EricLew	0:80ee8f3b695e	1289	{
EricLew	0:80ee8f3b695e	1290	return HAL_ERROR;
EricLew	0:80ee8f3b695e	1291	}
EricLew	0:80ee8f3b695e	1292	else
EricLew	0:80ee8f3b695e	1293	{
EricLew	0:80ee8f3b695e	1294	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	1295	}
EricLew	0:80ee8f3b695e	1296	}
EricLew	0:80ee8f3b695e	1297	switch (Channel)
EricLew	0:80ee8f3b695e	1298	{
EricLew	0:80ee8f3b695e	1299	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	1300	{
EricLew	0:80ee8f3b695e	1301	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	1302	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	1303
EricLew	0:80ee8f3b695e	1304	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	1305	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	1306
EricLew	0:80ee8f3b695e	1307	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	1308	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
EricLew	0:80ee8f3b695e	1309
EricLew	0:80ee8f3b695e	1310	/* Enable the TIM Capture/Compare 1 DMA request */
EricLew	0:80ee8f3b695e	1311	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	1312	}
EricLew	0:80ee8f3b695e	1313	break;
EricLew	0:80ee8f3b695e	1314
EricLew	0:80ee8f3b695e	1315	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	1316	{
EricLew	0:80ee8f3b695e	1317	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	1318	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	1319
EricLew	0:80ee8f3b695e	1320	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	1321	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	1322
EricLew	0:80ee8f3b695e	1323	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	1324	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
EricLew	0:80ee8f3b695e	1325
EricLew	0:80ee8f3b695e	1326	/* Enable the TIM Capture/Compare 2 DMA request */
EricLew	0:80ee8f3b695e	1327	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	1328	}
EricLew	0:80ee8f3b695e	1329	break;
EricLew	0:80ee8f3b695e	1330
EricLew	0:80ee8f3b695e	1331	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	1332	{
EricLew	0:80ee8f3b695e	1333	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	1334	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	1335
EricLew	0:80ee8f3b695e	1336	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	1337	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	1338
EricLew	0:80ee8f3b695e	1339	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	1340	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
EricLew	0:80ee8f3b695e	1341
EricLew	0:80ee8f3b695e	1342	/* Enable the TIM Output Capture/Compare 3 request */
EricLew	0:80ee8f3b695e	1343	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
EricLew	0:80ee8f3b695e	1344	}
EricLew	0:80ee8f3b695e	1345	break;
EricLew	0:80ee8f3b695e	1346
EricLew	0:80ee8f3b695e	1347	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	1348	{
EricLew	0:80ee8f3b695e	1349	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	1350	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	1351
EricLew	0:80ee8f3b695e	1352	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	1353	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	1354
EricLew	0:80ee8f3b695e	1355	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	1356	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
EricLew	0:80ee8f3b695e	1357
EricLew	0:80ee8f3b695e	1358	/* Enable the TIM Capture/Compare 4 DMA request */
EricLew	0:80ee8f3b695e	1359	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
EricLew	0:80ee8f3b695e	1360	}
EricLew	0:80ee8f3b695e	1361	break;
EricLew	0:80ee8f3b695e	1362
EricLew	0:80ee8f3b695e	1363	default:
EricLew	0:80ee8f3b695e	1364	break;
EricLew	0:80ee8f3b695e	1365	}
EricLew	0:80ee8f3b695e	1366
EricLew	0:80ee8f3b695e	1367	/* Enable the Capture compare channel */
EricLew	0:80ee8f3b695e	1368	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	1369
EricLew	0:80ee8f3b695e	1370	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	1371	{
EricLew	0:80ee8f3b695e	1372	/* Enable the main output */
EricLew	0:80ee8f3b695e	1373	__HAL_TIM_MOE_ENABLE(htim);
EricLew	0:80ee8f3b695e	1374	}
EricLew	0:80ee8f3b695e	1375
EricLew	0:80ee8f3b695e	1376	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	1377	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	1378
EricLew	0:80ee8f3b695e	1379	/* Return function status */
EricLew	0:80ee8f3b695e	1380	return HAL_OK;
EricLew	0:80ee8f3b695e	1381	}
EricLew	0:80ee8f3b695e	1382
EricLew	0:80ee8f3b695e	1383	/**
EricLew	0:80ee8f3b695e	1384	* @brief Stops the TIM PWM signal generation in DMA mode.
EricLew	0:80ee8f3b695e	1385	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	1386	* @param Channel : TIM Channels to be disabled
EricLew	0:80ee8f3b695e	1387	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1388	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1389	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1390	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1391	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1392	* @retval HAL status
EricLew	0:80ee8f3b695e	1393	*/
EricLew	0:80ee8f3b695e	1394	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1395	{
EricLew	0:80ee8f3b695e	1396	/* Check the parameters */
EricLew	0:80ee8f3b695e	1397	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1398
EricLew	0:80ee8f3b695e	1399	switch (Channel)
EricLew	0:80ee8f3b695e	1400	{
EricLew	0:80ee8f3b695e	1401	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	1402	{
EricLew	0:80ee8f3b695e	1403	/* Disable the TIM Capture/Compare 1 DMA request */
EricLew	0:80ee8f3b695e	1404	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	1405	}
EricLew	0:80ee8f3b695e	1406	break;
EricLew	0:80ee8f3b695e	1407
EricLew	0:80ee8f3b695e	1408	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	1409	{
EricLew	0:80ee8f3b695e	1410	/* Disable the TIM Capture/Compare 2 DMA request */
EricLew	0:80ee8f3b695e	1411	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	1412	}
EricLew	0:80ee8f3b695e	1413	break;
EricLew	0:80ee8f3b695e	1414
EricLew	0:80ee8f3b695e	1415	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	1416	{
EricLew	0:80ee8f3b695e	1417	/* Disable the TIM Capture/Compare 3 DMA request */
EricLew	0:80ee8f3b695e	1418	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
EricLew	0:80ee8f3b695e	1419	}
EricLew	0:80ee8f3b695e	1420	break;
EricLew	0:80ee8f3b695e	1421
EricLew	0:80ee8f3b695e	1422	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	1423	{
EricLew	0:80ee8f3b695e	1424	/* Disable the TIM Capture/Compare 4 interrupt */
EricLew	0:80ee8f3b695e	1425	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
EricLew	0:80ee8f3b695e	1426	}
EricLew	0:80ee8f3b695e	1427	break;
EricLew	0:80ee8f3b695e	1428
EricLew	0:80ee8f3b695e	1429	default:
EricLew	0:80ee8f3b695e	1430	break;
EricLew	0:80ee8f3b695e	1431	}
EricLew	0:80ee8f3b695e	1432
EricLew	0:80ee8f3b695e	1433	/* Disable the Capture compare channel */
EricLew	0:80ee8f3b695e	1434	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	1435
EricLew	0:80ee8f3b695e	1436	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	1437	{
EricLew	0:80ee8f3b695e	1438	/* Disable the Main Ouput */
EricLew	0:80ee8f3b695e	1439	__HAL_TIM_MOE_DISABLE(htim);
EricLew	0:80ee8f3b695e	1440	}
EricLew	0:80ee8f3b695e	1441
EricLew	0:80ee8f3b695e	1442	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	1443	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	1444
EricLew	0:80ee8f3b695e	1445	/* Change the htim state */
EricLew	0:80ee8f3b695e	1446	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	1447
EricLew	0:80ee8f3b695e	1448	/* Return function status */
EricLew	0:80ee8f3b695e	1449	return HAL_OK;
EricLew	0:80ee8f3b695e	1450	}
EricLew	0:80ee8f3b695e	1451
EricLew	0:80ee8f3b695e	1452	/**
EricLew	0:80ee8f3b695e	1453	* @}
EricLew	0:80ee8f3b695e	1454	*/
EricLew	0:80ee8f3b695e	1455
EricLew	0:80ee8f3b695e	1456	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
EricLew	0:80ee8f3b695e	1457	* @brief Time Input Capture functions
EricLew	0:80ee8f3b695e	1458	*
EricLew	0:80ee8f3b695e	1459	@verbatim
EricLew	0:80ee8f3b695e	1460	==============================================================================
EricLew	0:80ee8f3b695e	1461	##### Time Input Capture functions #####
EricLew	0:80ee8f3b695e	1462	==============================================================================
EricLew	0:80ee8f3b695e	1463	[..]
EricLew	0:80ee8f3b695e	1464	This section provides functions allowing to:
EricLew	0:80ee8f3b695e	1465	(+) Initialize and configure the TIM Input Capture.
EricLew	0:80ee8f3b695e	1466	(+) De-initialize the TIM Input Capture.
EricLew	0:80ee8f3b695e	1467	(+) Start the Time Input Capture.
EricLew	0:80ee8f3b695e	1468	(+) Stop the Time Input Capture.
EricLew	0:80ee8f3b695e	1469	(+) Start the Time Input Capture and enable interrupt.
EricLew	0:80ee8f3b695e	1470	(+) Stop the Time Input Capture and disable interrupt.
EricLew	0:80ee8f3b695e	1471	(+) Start the Time Input Capture and enable DMA transfer.
EricLew	0:80ee8f3b695e	1472	(+) Stop the Time Input Capture and disable DMA transfer.
EricLew	0:80ee8f3b695e	1473
EricLew	0:80ee8f3b695e	1474	@endverbatim
EricLew	0:80ee8f3b695e	1475	* @{
EricLew	0:80ee8f3b695e	1476	*/
EricLew	0:80ee8f3b695e	1477	/**
EricLew	0:80ee8f3b695e	1478	* @brief Initializes the TIM Input Capture Time base according to the specified
EricLew	0:80ee8f3b695e	1479	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
EricLew	0:80ee8f3b695e	1480	* @param htim: TIM Input Capture handle
EricLew	0:80ee8f3b695e	1481	* @retval HAL status
EricLew	0:80ee8f3b695e	1482	*/
EricLew	0:80ee8f3b695e	1483	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	1484	{
EricLew	0:80ee8f3b695e	1485	/* Check the TIM handle allocation */
EricLew	0:80ee8f3b695e	1486	if(htim == NULL)
EricLew	0:80ee8f3b695e	1487	{
EricLew	0:80ee8f3b695e	1488	return HAL_ERROR;
EricLew	0:80ee8f3b695e	1489	}
EricLew	0:80ee8f3b695e	1490
EricLew	0:80ee8f3b695e	1491	/* Check the parameters */
EricLew	0:80ee8f3b695e	1492	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	1493	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
EricLew	0:80ee8f3b695e	1494	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
EricLew	0:80ee8f3b695e	1495
EricLew	0:80ee8f3b695e	1496	if(htim->State == HAL_TIM_STATE_RESET)
EricLew	0:80ee8f3b695e	1497	{
EricLew	0:80ee8f3b695e	1498	/* Allocate lock resource and initialize it */
EricLew	0:80ee8f3b695e	1499	htim->Lock = HAL_UNLOCKED;
EricLew	0:80ee8f3b695e	1500
EricLew	0:80ee8f3b695e	1501	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
EricLew	0:80ee8f3b695e	1502	HAL_TIM_IC_MspInit(htim);
EricLew	0:80ee8f3b695e	1503	}
EricLew	0:80ee8f3b695e	1504
EricLew	0:80ee8f3b695e	1505	/* Set the TIM state */
EricLew	0:80ee8f3b695e	1506	htim->State= HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	1507
EricLew	0:80ee8f3b695e	1508	/* Init the base time for the input capture */
EricLew	0:80ee8f3b695e	1509	TIM_Base_SetConfig(htim->Instance, &htim->Init);
EricLew	0:80ee8f3b695e	1510
EricLew	0:80ee8f3b695e	1511	/* Initialize the TIM state*/
EricLew	0:80ee8f3b695e	1512	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	1513
EricLew	0:80ee8f3b695e	1514	return HAL_OK;
EricLew	0:80ee8f3b695e	1515	}
EricLew	0:80ee8f3b695e	1516
EricLew	0:80ee8f3b695e	1517	/**
EricLew	0:80ee8f3b695e	1518	* @brief DeInitialize the TIM peripheral
EricLew	0:80ee8f3b695e	1519	* @param htim: TIM Input Capture handle
EricLew	0:80ee8f3b695e	1520	* @retval HAL status
EricLew	0:80ee8f3b695e	1521	*/
EricLew	0:80ee8f3b695e	1522	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	1523	{
EricLew	0:80ee8f3b695e	1524	/* Check the parameters */
EricLew	0:80ee8f3b695e	1525	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	1526
EricLew	0:80ee8f3b695e	1527	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	1528
EricLew	0:80ee8f3b695e	1529	/* Disable the TIM Peripheral Clock */
EricLew	0:80ee8f3b695e	1530	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	1531
EricLew	0:80ee8f3b695e	1532	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
EricLew	0:80ee8f3b695e	1533	HAL_TIM_IC_MspDeInit(htim);
EricLew	0:80ee8f3b695e	1534
EricLew	0:80ee8f3b695e	1535	/* Change TIM state */
EricLew	0:80ee8f3b695e	1536	htim->State = HAL_TIM_STATE_RESET;
EricLew	0:80ee8f3b695e	1537
EricLew	0:80ee8f3b695e	1538	/* Release Lock */
EricLew	0:80ee8f3b695e	1539	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	1540
EricLew	0:80ee8f3b695e	1541	return HAL_OK;
EricLew	0:80ee8f3b695e	1542	}
EricLew	0:80ee8f3b695e	1543
EricLew	0:80ee8f3b695e	1544	/**
EricLew	0:80ee8f3b695e	1545	* @brief Initializes the TIM INput Capture MSP.
EricLew	0:80ee8f3b695e	1546	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	1547	* @retval None
EricLew	0:80ee8f3b695e	1548	*/
EricLew	0:80ee8f3b695e	1549	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	1550	{
EricLew	0:80ee8f3b695e	1551	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	1552	the HAL_TIM_IC_MspInit could be implemented in the user file
EricLew	0:80ee8f3b695e	1553	*/
EricLew	0:80ee8f3b695e	1554	}
EricLew	0:80ee8f3b695e	1555
EricLew	0:80ee8f3b695e	1556	/**
EricLew	0:80ee8f3b695e	1557	* @brief DeInitialize TIM Input Capture MSP.
EricLew	0:80ee8f3b695e	1558	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	1559	* @retval None
EricLew	0:80ee8f3b695e	1560	*/
EricLew	0:80ee8f3b695e	1561	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	1562	{
EricLew	0:80ee8f3b695e	1563	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	1564	the HAL_TIM_IC_MspDeInit could be implemented in the user file
EricLew	0:80ee8f3b695e	1565	*/
EricLew	0:80ee8f3b695e	1566	}
EricLew	0:80ee8f3b695e	1567
EricLew	0:80ee8f3b695e	1568	/**
EricLew	0:80ee8f3b695e	1569	* @brief Starts the TIM Input Capture measurement.
EricLew	0:80ee8f3b695e	1570	* @param htim : TIM Input Capture handle
EricLew	0:80ee8f3b695e	1571	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	1572	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1573	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1574	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1575	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1576	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1577	* @retval HAL status
EricLew	0:80ee8f3b695e	1578	*/
EricLew	0:80ee8f3b695e	1579	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1580	{
EricLew	0:80ee8f3b695e	1581	/* Check the parameters */
EricLew	0:80ee8f3b695e	1582	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1583
EricLew	0:80ee8f3b695e	1584	/* Enable the Input Capture channel */
EricLew	0:80ee8f3b695e	1585	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	1586
EricLew	0:80ee8f3b695e	1587	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	1588	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	1589
EricLew	0:80ee8f3b695e	1590	/* Return function status */
EricLew	0:80ee8f3b695e	1591	return HAL_OK;
EricLew	0:80ee8f3b695e	1592	}
EricLew	0:80ee8f3b695e	1593
EricLew	0:80ee8f3b695e	1594	/**
EricLew	0:80ee8f3b695e	1595	* @brief Stops the TIM Input Capture measurement.
EricLew	0:80ee8f3b695e	1596	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	1597	* @param Channel : TIM Channels to be disabled
EricLew	0:80ee8f3b695e	1598	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1599	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1600	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1601	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1602	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1603	* @retval HAL status
EricLew	0:80ee8f3b695e	1604	*/
EricLew	0:80ee8f3b695e	1605	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1606	{
EricLew	0:80ee8f3b695e	1607	/* Check the parameters */
EricLew	0:80ee8f3b695e	1608	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1609
EricLew	0:80ee8f3b695e	1610	/* Disable the Input Capture channel */
EricLew	0:80ee8f3b695e	1611	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	1612
EricLew	0:80ee8f3b695e	1613	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	1614	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	1615
EricLew	0:80ee8f3b695e	1616	/* Return function status */
EricLew	0:80ee8f3b695e	1617	return HAL_OK;
EricLew	0:80ee8f3b695e	1618	}
EricLew	0:80ee8f3b695e	1619
EricLew	0:80ee8f3b695e	1620	/**
EricLew	0:80ee8f3b695e	1621	* @brief Starts the TIM Input Capture measurement in interrupt mode.
EricLew	0:80ee8f3b695e	1622	* @param htim : TIM Input Capture handle
EricLew	0:80ee8f3b695e	1623	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	1624	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1625	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1626	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1627	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1628	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1629	* @retval HAL status
EricLew	0:80ee8f3b695e	1630	*/
EricLew	0:80ee8f3b695e	1631	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1632	{
EricLew	0:80ee8f3b695e	1633	/* Check the parameters */
EricLew	0:80ee8f3b695e	1634	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1635
EricLew	0:80ee8f3b695e	1636	switch (Channel)
EricLew	0:80ee8f3b695e	1637	{
EricLew	0:80ee8f3b695e	1638	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	1639	{
EricLew	0:80ee8f3b695e	1640	/* Enable the TIM Capture/Compare 1 interrupt */
EricLew	0:80ee8f3b695e	1641	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	1642	}
EricLew	0:80ee8f3b695e	1643	break;
EricLew	0:80ee8f3b695e	1644
EricLew	0:80ee8f3b695e	1645	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	1646	{
EricLew	0:80ee8f3b695e	1647	/* Enable the TIM Capture/Compare 2 interrupt */
EricLew	0:80ee8f3b695e	1648	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	1649	}
EricLew	0:80ee8f3b695e	1650	break;
EricLew	0:80ee8f3b695e	1651
EricLew	0:80ee8f3b695e	1652	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	1653	{
EricLew	0:80ee8f3b695e	1654	/* Enable the TIM Capture/Compare 3 interrupt */
EricLew	0:80ee8f3b695e	1655	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
EricLew	0:80ee8f3b695e	1656	}
EricLew	0:80ee8f3b695e	1657	break;
EricLew	0:80ee8f3b695e	1658
EricLew	0:80ee8f3b695e	1659	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	1660	{
EricLew	0:80ee8f3b695e	1661	/* Enable the TIM Capture/Compare 4 interrupt */
EricLew	0:80ee8f3b695e	1662	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
EricLew	0:80ee8f3b695e	1663	}
EricLew	0:80ee8f3b695e	1664	break;
EricLew	0:80ee8f3b695e	1665
EricLew	0:80ee8f3b695e	1666	default:
EricLew	0:80ee8f3b695e	1667	break;
EricLew	0:80ee8f3b695e	1668	}
EricLew	0:80ee8f3b695e	1669	/* Enable the Input Capture channel */
EricLew	0:80ee8f3b695e	1670	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	1671
EricLew	0:80ee8f3b695e	1672	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	1673	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	1674
EricLew	0:80ee8f3b695e	1675	/* Return function status */
EricLew	0:80ee8f3b695e	1676	return HAL_OK;
EricLew	0:80ee8f3b695e	1677	}
EricLew	0:80ee8f3b695e	1678
EricLew	0:80ee8f3b695e	1679	/**
EricLew	0:80ee8f3b695e	1680	* @brief Stops the TIM Input Capture measurement in interrupt mode.
EricLew	0:80ee8f3b695e	1681	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	1682	* @param Channel : TIM Channels to be disabled
EricLew	0:80ee8f3b695e	1683	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1684	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1685	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1686	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1687	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1688	* @retval HAL status
EricLew	0:80ee8f3b695e	1689	*/
EricLew	0:80ee8f3b695e	1690	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1691	{
EricLew	0:80ee8f3b695e	1692	/* Check the parameters */
EricLew	0:80ee8f3b695e	1693	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1694
EricLew	0:80ee8f3b695e	1695	switch (Channel)
EricLew	0:80ee8f3b695e	1696	{
EricLew	0:80ee8f3b695e	1697	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	1698	{
EricLew	0:80ee8f3b695e	1699	/* Disable the TIM Capture/Compare 1 interrupt */
EricLew	0:80ee8f3b695e	1700	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	1701	}
EricLew	0:80ee8f3b695e	1702	break;
EricLew	0:80ee8f3b695e	1703
EricLew	0:80ee8f3b695e	1704	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	1705	{
EricLew	0:80ee8f3b695e	1706	/* Disable the TIM Capture/Compare 2 interrupt */
EricLew	0:80ee8f3b695e	1707	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	1708	}
EricLew	0:80ee8f3b695e	1709	break;
EricLew	0:80ee8f3b695e	1710
EricLew	0:80ee8f3b695e	1711	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	1712	{
EricLew	0:80ee8f3b695e	1713	/* Disable the TIM Capture/Compare 3 interrupt */
EricLew	0:80ee8f3b695e	1714	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
EricLew	0:80ee8f3b695e	1715	}
EricLew	0:80ee8f3b695e	1716	break;
EricLew	0:80ee8f3b695e	1717
EricLew	0:80ee8f3b695e	1718	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	1719	{
EricLew	0:80ee8f3b695e	1720	/* Disable the TIM Capture/Compare 4 interrupt */
EricLew	0:80ee8f3b695e	1721	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
EricLew	0:80ee8f3b695e	1722	}
EricLew	0:80ee8f3b695e	1723	break;
EricLew	0:80ee8f3b695e	1724
EricLew	0:80ee8f3b695e	1725	default:
EricLew	0:80ee8f3b695e	1726	break;
EricLew	0:80ee8f3b695e	1727	}
EricLew	0:80ee8f3b695e	1728
EricLew	0:80ee8f3b695e	1729	/* Disable the Input Capture channel */
EricLew	0:80ee8f3b695e	1730	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	1731
EricLew	0:80ee8f3b695e	1732	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	1733	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	1734
EricLew	0:80ee8f3b695e	1735	/* Return function status */
EricLew	0:80ee8f3b695e	1736	return HAL_OK;
EricLew	0:80ee8f3b695e	1737	}
EricLew	0:80ee8f3b695e	1738
EricLew	0:80ee8f3b695e	1739	/**
EricLew	0:80ee8f3b695e	1740	* @brief Starts the TIM Input Capture measurement on in DMA mode.
EricLew	0:80ee8f3b695e	1741	* @param htim : TIM Input Capture handle
EricLew	0:80ee8f3b695e	1742	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	1743	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1744	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1745	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1746	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1747	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1748	* @param pData: The destination Buffer address.
EricLew	0:80ee8f3b695e	1749	* @param Length: The length of data to be transferred from TIM peripheral to memory.
EricLew	0:80ee8f3b695e	1750	* @retval HAL status
EricLew	0:80ee8f3b695e	1751	*/
EricLew	0:80ee8f3b695e	1752	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
EricLew	0:80ee8f3b695e	1753	{
EricLew	0:80ee8f3b695e	1754	/* Check the parameters */
EricLew	0:80ee8f3b695e	1755	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1756	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	1757
EricLew	0:80ee8f3b695e	1758	if((htim->State == HAL_TIM_STATE_BUSY))
EricLew	0:80ee8f3b695e	1759	{
EricLew	0:80ee8f3b695e	1760	return HAL_BUSY;
EricLew	0:80ee8f3b695e	1761	}
EricLew	0:80ee8f3b695e	1762	else if((htim->State == HAL_TIM_STATE_READY))
EricLew	0:80ee8f3b695e	1763	{
EricLew	0:80ee8f3b695e	1764	if((pData == 0 ) && (Length > 0))
EricLew	0:80ee8f3b695e	1765	{
EricLew	0:80ee8f3b695e	1766	return HAL_ERROR;
EricLew	0:80ee8f3b695e	1767	}
EricLew	0:80ee8f3b695e	1768	else
EricLew	0:80ee8f3b695e	1769	{
EricLew	0:80ee8f3b695e	1770	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	1771	}
EricLew	0:80ee8f3b695e	1772	}
EricLew	0:80ee8f3b695e	1773
EricLew	0:80ee8f3b695e	1774	switch (Channel)
EricLew	0:80ee8f3b695e	1775	{
EricLew	0:80ee8f3b695e	1776	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	1777	{
EricLew	0:80ee8f3b695e	1778	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	1779	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	1780
EricLew	0:80ee8f3b695e	1781	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	1782	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	1783
EricLew	0:80ee8f3b695e	1784	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	1785	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
EricLew	0:80ee8f3b695e	1786
EricLew	0:80ee8f3b695e	1787	/* Enable the TIM Capture/Compare 1 DMA request */
EricLew	0:80ee8f3b695e	1788	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	1789	}
EricLew	0:80ee8f3b695e	1790	break;
EricLew	0:80ee8f3b695e	1791
EricLew	0:80ee8f3b695e	1792	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	1793	{
EricLew	0:80ee8f3b695e	1794	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	1795	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	1796
EricLew	0:80ee8f3b695e	1797	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	1798	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	1799
EricLew	0:80ee8f3b695e	1800	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	1801	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
EricLew	0:80ee8f3b695e	1802
EricLew	0:80ee8f3b695e	1803	/* Enable the TIM Capture/Compare 2 DMA request */
EricLew	0:80ee8f3b695e	1804	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	1805	}
EricLew	0:80ee8f3b695e	1806	break;
EricLew	0:80ee8f3b695e	1807
EricLew	0:80ee8f3b695e	1808	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	1809	{
EricLew	0:80ee8f3b695e	1810	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	1811	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	1812
EricLew	0:80ee8f3b695e	1813	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	1814	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	1815
EricLew	0:80ee8f3b695e	1816	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	1817	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
EricLew	0:80ee8f3b695e	1818
EricLew	0:80ee8f3b695e	1819	/* Enable the TIM Capture/Compare 3 DMA request */
EricLew	0:80ee8f3b695e	1820	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
EricLew	0:80ee8f3b695e	1821	}
EricLew	0:80ee8f3b695e	1822	break;
EricLew	0:80ee8f3b695e	1823
EricLew	0:80ee8f3b695e	1824	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	1825	{
EricLew	0:80ee8f3b695e	1826	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	1827	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	1828
EricLew	0:80ee8f3b695e	1829	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	1830	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	1831
EricLew	0:80ee8f3b695e	1832	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	1833	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
EricLew	0:80ee8f3b695e	1834
EricLew	0:80ee8f3b695e	1835	/* Enable the TIM Capture/Compare 4 DMA request */
EricLew	0:80ee8f3b695e	1836	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
EricLew	0:80ee8f3b695e	1837	}
EricLew	0:80ee8f3b695e	1838	break;
EricLew	0:80ee8f3b695e	1839
EricLew	0:80ee8f3b695e	1840	default:
EricLew	0:80ee8f3b695e	1841	break;
EricLew	0:80ee8f3b695e	1842	}
EricLew	0:80ee8f3b695e	1843
EricLew	0:80ee8f3b695e	1844	/* Enable the Input Capture channel */
EricLew	0:80ee8f3b695e	1845	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	1846
EricLew	0:80ee8f3b695e	1847	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	1848	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	1849
EricLew	0:80ee8f3b695e	1850	/* Return function status */
EricLew	0:80ee8f3b695e	1851	return HAL_OK;
EricLew	0:80ee8f3b695e	1852	}
EricLew	0:80ee8f3b695e	1853
EricLew	0:80ee8f3b695e	1854	/**
EricLew	0:80ee8f3b695e	1855	* @brief Stops the TIM Input Capture measurement on in DMA mode.
EricLew	0:80ee8f3b695e	1856	* @param htim : TIM Input Capture handle
EricLew	0:80ee8f3b695e	1857	* @param Channel : TIM Channels to be disabled
EricLew	0:80ee8f3b695e	1858	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1859	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	1860	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	1861	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	1862	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	1863	* @retval HAL status
EricLew	0:80ee8f3b695e	1864	*/
EricLew	0:80ee8f3b695e	1865	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	1866	{
EricLew	0:80ee8f3b695e	1867	/* Check the parameters */
EricLew	0:80ee8f3b695e	1868	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
EricLew	0:80ee8f3b695e	1869	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	1870
EricLew	0:80ee8f3b695e	1871	switch (Channel)
EricLew	0:80ee8f3b695e	1872	{
EricLew	0:80ee8f3b695e	1873	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	1874	{
EricLew	0:80ee8f3b695e	1875	/* Disable the TIM Capture/Compare 1 DMA request */
EricLew	0:80ee8f3b695e	1876	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	1877	}
EricLew	0:80ee8f3b695e	1878	break;
EricLew	0:80ee8f3b695e	1879
EricLew	0:80ee8f3b695e	1880	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	1881	{
EricLew	0:80ee8f3b695e	1882	/* Disable the TIM Capture/Compare 2 DMA request */
EricLew	0:80ee8f3b695e	1883	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	1884	}
EricLew	0:80ee8f3b695e	1885	break;
EricLew	0:80ee8f3b695e	1886
EricLew	0:80ee8f3b695e	1887	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	1888	{
EricLew	0:80ee8f3b695e	1889	/* Disable the TIM Capture/Compare 3 DMA request */
EricLew	0:80ee8f3b695e	1890	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
EricLew	0:80ee8f3b695e	1891	}
EricLew	0:80ee8f3b695e	1892	break;
EricLew	0:80ee8f3b695e	1893
EricLew	0:80ee8f3b695e	1894	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	1895	{
EricLew	0:80ee8f3b695e	1896	/* Disable the TIM Capture/Compare 4 DMA request */
EricLew	0:80ee8f3b695e	1897	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
EricLew	0:80ee8f3b695e	1898	}
EricLew	0:80ee8f3b695e	1899	break;
EricLew	0:80ee8f3b695e	1900
EricLew	0:80ee8f3b695e	1901	default:
EricLew	0:80ee8f3b695e	1902	break;
EricLew	0:80ee8f3b695e	1903	}
EricLew	0:80ee8f3b695e	1904
EricLew	0:80ee8f3b695e	1905	/* Disable the Input Capture channel */
EricLew	0:80ee8f3b695e	1906	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	1907
EricLew	0:80ee8f3b695e	1908	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	1909	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	1910
EricLew	0:80ee8f3b695e	1911	/* Change the htim state */
EricLew	0:80ee8f3b695e	1912	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	1913
EricLew	0:80ee8f3b695e	1914	/* Return function status */
EricLew	0:80ee8f3b695e	1915	return HAL_OK;
EricLew	0:80ee8f3b695e	1916	}
EricLew	0:80ee8f3b695e	1917	/**
EricLew	0:80ee8f3b695e	1918	* @}
EricLew	0:80ee8f3b695e	1919	*/
EricLew	0:80ee8f3b695e	1920
EricLew	0:80ee8f3b695e	1921	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
EricLew	0:80ee8f3b695e	1922	* @brief Time One Pulse functions
EricLew	0:80ee8f3b695e	1923	*
EricLew	0:80ee8f3b695e	1924	@verbatim
EricLew	0:80ee8f3b695e	1925	==============================================================================
EricLew	0:80ee8f3b695e	1926	##### Time One Pulse functions #####
EricLew	0:80ee8f3b695e	1927	==============================================================================
EricLew	0:80ee8f3b695e	1928	[..]
EricLew	0:80ee8f3b695e	1929	This section provides functions allowing to:
EricLew	0:80ee8f3b695e	1930	(+) Initialize and configure the TIM One Pulse.
EricLew	0:80ee8f3b695e	1931	(+) De-initialize the TIM One Pulse.
EricLew	0:80ee8f3b695e	1932	(+) Start the Time One Pulse.
EricLew	0:80ee8f3b695e	1933	(+) Stop the Time One Pulse.
EricLew	0:80ee8f3b695e	1934	(+) Start the Time One Pulse and enable interrupt.
EricLew	0:80ee8f3b695e	1935	(+) Stop the Time One Pulse and disable interrupt.
EricLew	0:80ee8f3b695e	1936	(+) Start the Time One Pulse and enable DMA transfer.
EricLew	0:80ee8f3b695e	1937	(+) Stop the Time One Pulse and disable DMA transfer.
EricLew	0:80ee8f3b695e	1938
EricLew	0:80ee8f3b695e	1939	@endverbatim
EricLew	0:80ee8f3b695e	1940	* @{
EricLew	0:80ee8f3b695e	1941	*/
EricLew	0:80ee8f3b695e	1942	/**
EricLew	0:80ee8f3b695e	1943	* @brief Initializes the TIM One Pulse Time Base according to the specified
EricLew	0:80ee8f3b695e	1944	* parameters in the TIM_HandleTypeDef and initialize the associated handle.
EricLew	0:80ee8f3b695e	1945	* @param htim: TIM OnePulse handle
EricLew	0:80ee8f3b695e	1946	* @param OnePulseMode: Select the One pulse mode.
EricLew	0:80ee8f3b695e	1947	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1948	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
EricLew	0:80ee8f3b695e	1949	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
EricLew	0:80ee8f3b695e	1950	* @retval HAL status
EricLew	0:80ee8f3b695e	1951	*/
EricLew	0:80ee8f3b695e	1952	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
EricLew	0:80ee8f3b695e	1953	{
EricLew	0:80ee8f3b695e	1954	/* Check the TIM handle allocation */
EricLew	0:80ee8f3b695e	1955	if(htim == NULL)
EricLew	0:80ee8f3b695e	1956	{
EricLew	0:80ee8f3b695e	1957	return HAL_ERROR;
EricLew	0:80ee8f3b695e	1958	}
EricLew	0:80ee8f3b695e	1959
EricLew	0:80ee8f3b695e	1960	/* Check the parameters */
EricLew	0:80ee8f3b695e	1961	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	1962	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
EricLew	0:80ee8f3b695e	1963	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
EricLew	0:80ee8f3b695e	1964	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
EricLew	0:80ee8f3b695e	1965
EricLew	0:80ee8f3b695e	1966	if(htim->State == HAL_TIM_STATE_RESET)
EricLew	0:80ee8f3b695e	1967	{
EricLew	0:80ee8f3b695e	1968	/* Allocate lock resource and initialize it */
EricLew	0:80ee8f3b695e	1969	htim->Lock = HAL_UNLOCKED;
EricLew	0:80ee8f3b695e	1970
EricLew	0:80ee8f3b695e	1971	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
EricLew	0:80ee8f3b695e	1972	HAL_TIM_OnePulse_MspInit(htim);
EricLew	0:80ee8f3b695e	1973	}
EricLew	0:80ee8f3b695e	1974
EricLew	0:80ee8f3b695e	1975	/* Set the TIM state */
EricLew	0:80ee8f3b695e	1976	htim->State= HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	1977
EricLew	0:80ee8f3b695e	1978	/* Configure the Time base in the One Pulse Mode */
EricLew	0:80ee8f3b695e	1979	TIM_Base_SetConfig(htim->Instance, &htim->Init);
EricLew	0:80ee8f3b695e	1980
EricLew	0:80ee8f3b695e	1981	/* Reset the OPM Bit */
EricLew	0:80ee8f3b695e	1982	htim->Instance->CR1 &= ~TIM_CR1_OPM;
EricLew	0:80ee8f3b695e	1983
EricLew	0:80ee8f3b695e	1984	/* Configure the OPM Mode */
EricLew	0:80ee8f3b695e	1985	htim->Instance->CR1 \|= OnePulseMode;
EricLew	0:80ee8f3b695e	1986
EricLew	0:80ee8f3b695e	1987	/* Initialize the TIM state*/
EricLew	0:80ee8f3b695e	1988	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	1989
EricLew	0:80ee8f3b695e	1990	return HAL_OK;
EricLew	0:80ee8f3b695e	1991	}
EricLew	0:80ee8f3b695e	1992
EricLew	0:80ee8f3b695e	1993	/**
EricLew	0:80ee8f3b695e	1994	* @brief DeInitialize the TIM One Pulse
EricLew	0:80ee8f3b695e	1995	* @param htim: TIM One Pulse handle
EricLew	0:80ee8f3b695e	1996	* @retval HAL status
EricLew	0:80ee8f3b695e	1997	*/
EricLew	0:80ee8f3b695e	1998	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	1999	{
EricLew	0:80ee8f3b695e	2000	/* Check the parameters */
EricLew	0:80ee8f3b695e	2001	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2002
EricLew	0:80ee8f3b695e	2003	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	2004
EricLew	0:80ee8f3b695e	2005	/* Disable the TIM Peripheral Clock */
EricLew	0:80ee8f3b695e	2006	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	2007
EricLew	0:80ee8f3b695e	2008	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
EricLew	0:80ee8f3b695e	2009	HAL_TIM_OnePulse_MspDeInit(htim);
EricLew	0:80ee8f3b695e	2010
EricLew	0:80ee8f3b695e	2011	/* Change TIM state */
EricLew	0:80ee8f3b695e	2012	htim->State = HAL_TIM_STATE_RESET;
EricLew	0:80ee8f3b695e	2013
EricLew	0:80ee8f3b695e	2014	/* Release Lock */
EricLew	0:80ee8f3b695e	2015	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	2016
EricLew	0:80ee8f3b695e	2017	return HAL_OK;
EricLew	0:80ee8f3b695e	2018	}
EricLew	0:80ee8f3b695e	2019
EricLew	0:80ee8f3b695e	2020	/**
EricLew	0:80ee8f3b695e	2021	* @brief Initializes the TIM One Pulse MSP.
EricLew	0:80ee8f3b695e	2022	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	2023	* @retval None
EricLew	0:80ee8f3b695e	2024	*/
EricLew	0:80ee8f3b695e	2025	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	2026	{
EricLew	0:80ee8f3b695e	2027	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	2028	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
EricLew	0:80ee8f3b695e	2029	*/
EricLew	0:80ee8f3b695e	2030	}
EricLew	0:80ee8f3b695e	2031
EricLew	0:80ee8f3b695e	2032	/**
EricLew	0:80ee8f3b695e	2033	* @brief DeInitialize TIM One Pulse MSP.
EricLew	0:80ee8f3b695e	2034	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	2035	* @retval None
EricLew	0:80ee8f3b695e	2036	*/
EricLew	0:80ee8f3b695e	2037	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	2038	{
EricLew	0:80ee8f3b695e	2039	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	2040	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
EricLew	0:80ee8f3b695e	2041	*/
EricLew	0:80ee8f3b695e	2042	}
EricLew	0:80ee8f3b695e	2043
EricLew	0:80ee8f3b695e	2044	/**
EricLew	0:80ee8f3b695e	2045	* @brief Starts the TIM One Pulse signal generation.
EricLew	0:80ee8f3b695e	2046	* @param htim : TIM One Pulse handle
EricLew	0:80ee8f3b695e	2047	* @param OutputChannel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	2048	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2049	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2050	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2051	* @retval HAL status
EricLew	0:80ee8f3b695e	2052	*/
EricLew	0:80ee8f3b695e	2053	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
EricLew	0:80ee8f3b695e	2054	{
EricLew	0:80ee8f3b695e	2055	/* Enable the Capture compare and the Input Capture channels
EricLew	0:80ee8f3b695e	2056	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
EricLew	0:80ee8f3b695e	2057	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
EricLew	0:80ee8f3b695e	2058	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
EricLew	0:80ee8f3b695e	2059	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
EricLew	0:80ee8f3b695e	2060
EricLew	0:80ee8f3b695e	2061	No need to enable the counter, it's enabled automatically by hardware
EricLew	0:80ee8f3b695e	2062	(the counter starts in response to a stimulus and generate a pulse */
EricLew	0:80ee8f3b695e	2063
EricLew	0:80ee8f3b695e	2064	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2065	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2066
EricLew	0:80ee8f3b695e	2067	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	2068	{
EricLew	0:80ee8f3b695e	2069	/* Enable the main output */
EricLew	0:80ee8f3b695e	2070	__HAL_TIM_MOE_ENABLE(htim);
EricLew	0:80ee8f3b695e	2071	}
EricLew	0:80ee8f3b695e	2072
EricLew	0:80ee8f3b695e	2073	/* Return function status */
EricLew	0:80ee8f3b695e	2074	return HAL_OK;
EricLew	0:80ee8f3b695e	2075	}
EricLew	0:80ee8f3b695e	2076
EricLew	0:80ee8f3b695e	2077	/**
EricLew	0:80ee8f3b695e	2078	* @brief Stops the TIM One Pulse signal generation.
EricLew	0:80ee8f3b695e	2079	* @param htim : TIM One Pulse handle
EricLew	0:80ee8f3b695e	2080	* @param OutputChannel : TIM Channels to be disable
EricLew	0:80ee8f3b695e	2081	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2082	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2083	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2084	* @retval HAL status
EricLew	0:80ee8f3b695e	2085	*/
EricLew	0:80ee8f3b695e	2086	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
EricLew	0:80ee8f3b695e	2087	{
EricLew	0:80ee8f3b695e	2088	/* Disable the Capture compare and the Input Capture channels
EricLew	0:80ee8f3b695e	2089	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
EricLew	0:80ee8f3b695e	2090	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
EricLew	0:80ee8f3b695e	2091	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
EricLew	0:80ee8f3b695e	2092	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
EricLew	0:80ee8f3b695e	2093
EricLew	0:80ee8f3b695e	2094	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2095	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2096
EricLew	0:80ee8f3b695e	2097	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	2098	{
EricLew	0:80ee8f3b695e	2099	/* Disable the Main Ouput */
EricLew	0:80ee8f3b695e	2100	__HAL_TIM_MOE_DISABLE(htim);
EricLew	0:80ee8f3b695e	2101	}
EricLew	0:80ee8f3b695e	2102
EricLew	0:80ee8f3b695e	2103	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	2104	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	2105
EricLew	0:80ee8f3b695e	2106	/* Return function status */
EricLew	0:80ee8f3b695e	2107	return HAL_OK;
EricLew	0:80ee8f3b695e	2108	}
EricLew	0:80ee8f3b695e	2109
EricLew	0:80ee8f3b695e	2110	/**
EricLew	0:80ee8f3b695e	2111	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
EricLew	0:80ee8f3b695e	2112	* @param htim : TIM One Pulse handle
EricLew	0:80ee8f3b695e	2113	* @param OutputChannel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	2114	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2115	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2116	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2117	* @retval HAL status
EricLew	0:80ee8f3b695e	2118	*/
EricLew	0:80ee8f3b695e	2119	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
EricLew	0:80ee8f3b695e	2120	{
EricLew	0:80ee8f3b695e	2121	/* Enable the Capture compare and the Input Capture channels
EricLew	0:80ee8f3b695e	2122	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
EricLew	0:80ee8f3b695e	2123	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
EricLew	0:80ee8f3b695e	2124	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
EricLew	0:80ee8f3b695e	2125	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
EricLew	0:80ee8f3b695e	2126
EricLew	0:80ee8f3b695e	2127	No need to enable the counter, it's enabled automatically by hardware
EricLew	0:80ee8f3b695e	2128	(the counter starts in response to a stimulus and generate a pulse */
EricLew	0:80ee8f3b695e	2129
EricLew	0:80ee8f3b695e	2130	/* Enable the TIM Capture/Compare 1 interrupt */
EricLew	0:80ee8f3b695e	2131	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	2132
EricLew	0:80ee8f3b695e	2133	/* Enable the TIM Capture/Compare 2 interrupt */
EricLew	0:80ee8f3b695e	2134	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	2135
EricLew	0:80ee8f3b695e	2136	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2137	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2138
EricLew	0:80ee8f3b695e	2139	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	2140	{
EricLew	0:80ee8f3b695e	2141	/* Enable the main output */
EricLew	0:80ee8f3b695e	2142	__HAL_TIM_MOE_ENABLE(htim);
EricLew	0:80ee8f3b695e	2143	}
EricLew	0:80ee8f3b695e	2144
EricLew	0:80ee8f3b695e	2145	/* Return function status */
EricLew	0:80ee8f3b695e	2146	return HAL_OK;
EricLew	0:80ee8f3b695e	2147	}
EricLew	0:80ee8f3b695e	2148
EricLew	0:80ee8f3b695e	2149	/**
EricLew	0:80ee8f3b695e	2150	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
EricLew	0:80ee8f3b695e	2151	* @param htim : TIM One Pulse handle
EricLew	0:80ee8f3b695e	2152	* @param OutputChannel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	2153	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2154	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2155	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2156	* @retval HAL status
EricLew	0:80ee8f3b695e	2157	*/
EricLew	0:80ee8f3b695e	2158	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
EricLew	0:80ee8f3b695e	2159	{
EricLew	0:80ee8f3b695e	2160	/* Disable the TIM Capture/Compare 1 interrupt */
EricLew	0:80ee8f3b695e	2161	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	2162
EricLew	0:80ee8f3b695e	2163	/* Disable the TIM Capture/Compare 2 interrupt */
EricLew	0:80ee8f3b695e	2164	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	2165
EricLew	0:80ee8f3b695e	2166	/* Disable the Capture compare and the Input Capture channels
EricLew	0:80ee8f3b695e	2167	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
EricLew	0:80ee8f3b695e	2168	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
EricLew	0:80ee8f3b695e	2169	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
EricLew	0:80ee8f3b695e	2170	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
EricLew	0:80ee8f3b695e	2171	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2172	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2173
EricLew	0:80ee8f3b695e	2174	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
EricLew	0:80ee8f3b695e	2175	{
EricLew	0:80ee8f3b695e	2176	/* Disable the Main Ouput */
EricLew	0:80ee8f3b695e	2177	__HAL_TIM_MOE_DISABLE(htim);
EricLew	0:80ee8f3b695e	2178	}
EricLew	0:80ee8f3b695e	2179
EricLew	0:80ee8f3b695e	2180	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	2181	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	2182
EricLew	0:80ee8f3b695e	2183	/* Return function status */
EricLew	0:80ee8f3b695e	2184	return HAL_OK;
EricLew	0:80ee8f3b695e	2185	}
EricLew	0:80ee8f3b695e	2186
EricLew	0:80ee8f3b695e	2187	/**
EricLew	0:80ee8f3b695e	2188	* @}
EricLew	0:80ee8f3b695e	2189	*/
EricLew	0:80ee8f3b695e	2190
EricLew	0:80ee8f3b695e	2191	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
EricLew	0:80ee8f3b695e	2192	* @brief Time Encoder functions
EricLew	0:80ee8f3b695e	2193	*
EricLew	0:80ee8f3b695e	2194	@verbatim
EricLew	0:80ee8f3b695e	2195	==============================================================================
EricLew	0:80ee8f3b695e	2196	##### Time Encoder functions #####
EricLew	0:80ee8f3b695e	2197	==============================================================================
EricLew	0:80ee8f3b695e	2198	[..]
EricLew	0:80ee8f3b695e	2199	This section provides functions allowing to:
EricLew	0:80ee8f3b695e	2200	(+) Initialize and configure the TIM Encoder.
EricLew	0:80ee8f3b695e	2201	(+) De-initialize the TIM Encoder.
EricLew	0:80ee8f3b695e	2202	(+) Start the Time Encoder.
EricLew	0:80ee8f3b695e	2203	(+) Stop the Time Encoder.
EricLew	0:80ee8f3b695e	2204	(+) Start the Time Encoder and enable interrupt.
EricLew	0:80ee8f3b695e	2205	(+) Stop the Time Encoder and disable interrupt.
EricLew	0:80ee8f3b695e	2206	(+) Start the Time Encoder and enable DMA transfer.
EricLew	0:80ee8f3b695e	2207	(+) Stop the Time Encoder and disable DMA transfer.
EricLew	0:80ee8f3b695e	2208
EricLew	0:80ee8f3b695e	2209	@endverbatim
EricLew	0:80ee8f3b695e	2210	* @{
EricLew	0:80ee8f3b695e	2211	*/
EricLew	0:80ee8f3b695e	2212	/**
EricLew	0:80ee8f3b695e	2213	* @brief Initializes the TIM Encoder Interface and initialize the associated handle.
EricLew	0:80ee8f3b695e	2214	* @param htim: TIM Encoder Interface handle
EricLew	0:80ee8f3b695e	2215	* @param sConfig: TIM Encoder Interface configuration structure
EricLew	0:80ee8f3b695e	2216	* @retval HAL status
EricLew	0:80ee8f3b695e	2217	*/
EricLew	0:80ee8f3b695e	2218	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
EricLew	0:80ee8f3b695e	2219	{
EricLew	0:80ee8f3b695e	2220	uint32_t tmpsmcr = 0;
EricLew	0:80ee8f3b695e	2221	uint32_t tmpccmr1 = 0;
EricLew	0:80ee8f3b695e	2222	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	2223
EricLew	0:80ee8f3b695e	2224	/* Check the TIM handle allocation */
EricLew	0:80ee8f3b695e	2225	if(htim == NULL)
EricLew	0:80ee8f3b695e	2226	{
EricLew	0:80ee8f3b695e	2227	return HAL_ERROR;
EricLew	0:80ee8f3b695e	2228	}
EricLew	0:80ee8f3b695e	2229
EricLew	0:80ee8f3b695e	2230	/* Check the parameters */
EricLew	0:80ee8f3b695e	2231	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2232	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
EricLew	0:80ee8f3b695e	2233	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
EricLew	0:80ee8f3b695e	2234	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
EricLew	0:80ee8f3b695e	2235	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
EricLew	0:80ee8f3b695e	2236	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
EricLew	0:80ee8f3b695e	2237	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
EricLew	0:80ee8f3b695e	2238	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
EricLew	0:80ee8f3b695e	2239	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
EricLew	0:80ee8f3b695e	2240	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
EricLew	0:80ee8f3b695e	2241
EricLew	0:80ee8f3b695e	2242	if(htim->State == HAL_TIM_STATE_RESET)
EricLew	0:80ee8f3b695e	2243	{
EricLew	0:80ee8f3b695e	2244	/* Allocate lock resource and initialize it */
EricLew	0:80ee8f3b695e	2245	htim->Lock = HAL_UNLOCKED;
EricLew	0:80ee8f3b695e	2246
EricLew	0:80ee8f3b695e	2247	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
EricLew	0:80ee8f3b695e	2248	HAL_TIM_Encoder_MspInit(htim);
EricLew	0:80ee8f3b695e	2249	}
EricLew	0:80ee8f3b695e	2250
EricLew	0:80ee8f3b695e	2251	/* Set the TIM state */
EricLew	0:80ee8f3b695e	2252	htim->State= HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	2253
EricLew	0:80ee8f3b695e	2254	/* Reset the SMS bits */
EricLew	0:80ee8f3b695e	2255	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
EricLew	0:80ee8f3b695e	2256
EricLew	0:80ee8f3b695e	2257	/* Configure the Time base in the Encoder Mode */
EricLew	0:80ee8f3b695e	2258	TIM_Base_SetConfig(htim->Instance, &htim->Init);
EricLew	0:80ee8f3b695e	2259
EricLew	0:80ee8f3b695e	2260	/* Get the TIMx SMCR register value */
EricLew	0:80ee8f3b695e	2261	tmpsmcr = htim->Instance->SMCR;
EricLew	0:80ee8f3b695e	2262
EricLew	0:80ee8f3b695e	2263	/* Get the TIMx CCMR1 register value */
EricLew	0:80ee8f3b695e	2264	tmpccmr1 = htim->Instance->CCMR1;
EricLew	0:80ee8f3b695e	2265
EricLew	0:80ee8f3b695e	2266	/* Get the TIMx CCER register value */
EricLew	0:80ee8f3b695e	2267	tmpccer = htim->Instance->CCER;
EricLew	0:80ee8f3b695e	2268
EricLew	0:80ee8f3b695e	2269	/* Set the encoder Mode */
EricLew	0:80ee8f3b695e	2270	tmpsmcr \|= sConfig->EncoderMode;
EricLew	0:80ee8f3b695e	2271
EricLew	0:80ee8f3b695e	2272	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
EricLew	0:80ee8f3b695e	2273	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
EricLew	0:80ee8f3b695e	2274	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
EricLew	0:80ee8f3b695e	2275
EricLew	0:80ee8f3b695e	2276	/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
EricLew	0:80ee8f3b695e	2277	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
EricLew	0:80ee8f3b695e	2278	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
EricLew	0:80ee8f3b695e	2279	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
EricLew	0:80ee8f3b695e	2280	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
EricLew	0:80ee8f3b695e	2281
EricLew	0:80ee8f3b695e	2282	/* Set the TI1 and the TI2 Polarities */
EricLew	0:80ee8f3b695e	2283	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
EricLew	0:80ee8f3b695e	2284	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
EricLew	0:80ee8f3b695e	2285	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
EricLew	0:80ee8f3b695e	2286
EricLew	0:80ee8f3b695e	2287	/* Write to TIMx SMCR */
EricLew	0:80ee8f3b695e	2288	htim->Instance->SMCR = tmpsmcr;
EricLew	0:80ee8f3b695e	2289
EricLew	0:80ee8f3b695e	2290	/* Write to TIMx CCMR1 */
EricLew	0:80ee8f3b695e	2291	htim->Instance->CCMR1 = tmpccmr1;
EricLew	0:80ee8f3b695e	2292
EricLew	0:80ee8f3b695e	2293	/* Write to TIMx CCER */
EricLew	0:80ee8f3b695e	2294	htim->Instance->CCER = tmpccer;
EricLew	0:80ee8f3b695e	2295
EricLew	0:80ee8f3b695e	2296	/* Initialize the TIM state*/
EricLew	0:80ee8f3b695e	2297	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	2298
EricLew	0:80ee8f3b695e	2299	return HAL_OK;
EricLew	0:80ee8f3b695e	2300	}
EricLew	0:80ee8f3b695e	2301
EricLew	0:80ee8f3b695e	2302
EricLew	0:80ee8f3b695e	2303	/**
EricLew	0:80ee8f3b695e	2304	* @brief DeInitialize the TIM Encoder interface
EricLew	0:80ee8f3b695e	2305	* @param htim: TIM Encoder handle
EricLew	0:80ee8f3b695e	2306	* @retval HAL status
EricLew	0:80ee8f3b695e	2307	*/
EricLew	0:80ee8f3b695e	2308	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	2309	{
EricLew	0:80ee8f3b695e	2310	/* Check the parameters */
EricLew	0:80ee8f3b695e	2311	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2312
EricLew	0:80ee8f3b695e	2313	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	2314
EricLew	0:80ee8f3b695e	2315	/* Disable the TIM Peripheral Clock */
EricLew	0:80ee8f3b695e	2316	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	2317
EricLew	0:80ee8f3b695e	2318	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
EricLew	0:80ee8f3b695e	2319	HAL_TIM_Encoder_MspDeInit(htim);
EricLew	0:80ee8f3b695e	2320
EricLew	0:80ee8f3b695e	2321	/* Change TIM state */
EricLew	0:80ee8f3b695e	2322	htim->State = HAL_TIM_STATE_RESET;
EricLew	0:80ee8f3b695e	2323
EricLew	0:80ee8f3b695e	2324	/* Release Lock */
EricLew	0:80ee8f3b695e	2325	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	2326
EricLew	0:80ee8f3b695e	2327	return HAL_OK;
EricLew	0:80ee8f3b695e	2328	}
EricLew	0:80ee8f3b695e	2329
EricLew	0:80ee8f3b695e	2330	/**
EricLew	0:80ee8f3b695e	2331	* @brief Initializes the TIM Encoder Interface MSP.
EricLew	0:80ee8f3b695e	2332	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	2333	* @retval None
EricLew	0:80ee8f3b695e	2334	*/
EricLew	0:80ee8f3b695e	2335	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	2336	{
EricLew	0:80ee8f3b695e	2337	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	2338	the HAL_TIM_Encoder_MspInit could be implemented in the user file
EricLew	0:80ee8f3b695e	2339	*/
EricLew	0:80ee8f3b695e	2340	}
EricLew	0:80ee8f3b695e	2341
EricLew	0:80ee8f3b695e	2342	/**
EricLew	0:80ee8f3b695e	2343	* @brief DeInitialize TIM Encoder Interface MSP.
EricLew	0:80ee8f3b695e	2344	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	2345	* @retval None
EricLew	0:80ee8f3b695e	2346	*/
EricLew	0:80ee8f3b695e	2347	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	2348	{
EricLew	0:80ee8f3b695e	2349	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	2350	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
EricLew	0:80ee8f3b695e	2351	*/
EricLew	0:80ee8f3b695e	2352	}
EricLew	0:80ee8f3b695e	2353
EricLew	0:80ee8f3b695e	2354	/**
EricLew	0:80ee8f3b695e	2355	* @brief Starts the TIM Encoder Interface.
EricLew	0:80ee8f3b695e	2356	* @param htim : TIM Encoder Interface handle
EricLew	0:80ee8f3b695e	2357	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	2358	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2359	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2360	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2361	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
EricLew	0:80ee8f3b695e	2362	* @retval HAL status
EricLew	0:80ee8f3b695e	2363	*/
EricLew	0:80ee8f3b695e	2364	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	2365	{
EricLew	0:80ee8f3b695e	2366	/* Check the parameters */
EricLew	0:80ee8f3b695e	2367	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2368
EricLew	0:80ee8f3b695e	2369	/* Enable the encoder interface channels */
EricLew	0:80ee8f3b695e	2370	switch (Channel)
EricLew	0:80ee8f3b695e	2371	{
EricLew	0:80ee8f3b695e	2372	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	2373	{
EricLew	0:80ee8f3b695e	2374	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2375	break;
EricLew	0:80ee8f3b695e	2376	}
EricLew	0:80ee8f3b695e	2377	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	2378	{
EricLew	0:80ee8f3b695e	2379	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2380	break;
EricLew	0:80ee8f3b695e	2381	}
EricLew	0:80ee8f3b695e	2382	default :
EricLew	0:80ee8f3b695e	2383	{
EricLew	0:80ee8f3b695e	2384	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2385	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2386	break;
EricLew	0:80ee8f3b695e	2387	}
EricLew	0:80ee8f3b695e	2388	}
EricLew	0:80ee8f3b695e	2389	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	2390	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	2391
EricLew	0:80ee8f3b695e	2392	/* Return function status */
EricLew	0:80ee8f3b695e	2393	return HAL_OK;
EricLew	0:80ee8f3b695e	2394	}
EricLew	0:80ee8f3b695e	2395
EricLew	0:80ee8f3b695e	2396	/**
EricLew	0:80ee8f3b695e	2397	* @brief Stops the TIM Encoder Interface.
EricLew	0:80ee8f3b695e	2398	* @param htim : TIM Encoder Interface handle
EricLew	0:80ee8f3b695e	2399	* @param Channel : TIM Channels to be disabled
EricLew	0:80ee8f3b695e	2400	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2401	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2402	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2403	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
EricLew	0:80ee8f3b695e	2404	* @retval HAL status
EricLew	0:80ee8f3b695e	2405	*/
EricLew	0:80ee8f3b695e	2406	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	2407	{
EricLew	0:80ee8f3b695e	2408	/* Check the parameters */
EricLew	0:80ee8f3b695e	2409	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2410
EricLew	0:80ee8f3b695e	2411	/* Disable the Input Capture channels 1 and 2
EricLew	0:80ee8f3b695e	2412	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
EricLew	0:80ee8f3b695e	2413	switch (Channel)
EricLew	0:80ee8f3b695e	2414	{
EricLew	0:80ee8f3b695e	2415	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	2416	{
EricLew	0:80ee8f3b695e	2417	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2418	break;
EricLew	0:80ee8f3b695e	2419	}
EricLew	0:80ee8f3b695e	2420	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	2421	{
EricLew	0:80ee8f3b695e	2422	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2423	break;
EricLew	0:80ee8f3b695e	2424	}
EricLew	0:80ee8f3b695e	2425	default :
EricLew	0:80ee8f3b695e	2426	{
EricLew	0:80ee8f3b695e	2427	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2428	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2429	break;
EricLew	0:80ee8f3b695e	2430	}
EricLew	0:80ee8f3b695e	2431	}
EricLew	0:80ee8f3b695e	2432
EricLew	0:80ee8f3b695e	2433	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	2434	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	2435
EricLew	0:80ee8f3b695e	2436	/* Return function status */
EricLew	0:80ee8f3b695e	2437	return HAL_OK;
EricLew	0:80ee8f3b695e	2438	}
EricLew	0:80ee8f3b695e	2439
EricLew	0:80ee8f3b695e	2440	/**
EricLew	0:80ee8f3b695e	2441	* @brief Starts the TIM Encoder Interface in interrupt mode.
EricLew	0:80ee8f3b695e	2442	* @param htim : TIM Encoder Interface handle
EricLew	0:80ee8f3b695e	2443	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	2444	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2445	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2446	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2447	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
EricLew	0:80ee8f3b695e	2448	* @retval HAL status
EricLew	0:80ee8f3b695e	2449	*/
EricLew	0:80ee8f3b695e	2450	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	2451	{
EricLew	0:80ee8f3b695e	2452	/* Check the parameters */
EricLew	0:80ee8f3b695e	2453	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2454
EricLew	0:80ee8f3b695e	2455	/* Enable the encoder interface channels */
EricLew	0:80ee8f3b695e	2456	/* Enable the capture compare Interrupts 1 and/or 2 */
EricLew	0:80ee8f3b695e	2457	switch (Channel)
EricLew	0:80ee8f3b695e	2458	{
EricLew	0:80ee8f3b695e	2459	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	2460	{
EricLew	0:80ee8f3b695e	2461	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2462	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	2463	break;
EricLew	0:80ee8f3b695e	2464	}
EricLew	0:80ee8f3b695e	2465	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	2466	{
EricLew	0:80ee8f3b695e	2467	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2468	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	2469	break;
EricLew	0:80ee8f3b695e	2470	}
EricLew	0:80ee8f3b695e	2471	default :
EricLew	0:80ee8f3b695e	2472	{
EricLew	0:80ee8f3b695e	2473	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2474	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2475	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	2476	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	2477	break;
EricLew	0:80ee8f3b695e	2478	}
EricLew	0:80ee8f3b695e	2479	}
EricLew	0:80ee8f3b695e	2480
EricLew	0:80ee8f3b695e	2481	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	2482	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	2483
EricLew	0:80ee8f3b695e	2484	/* Return function status */
EricLew	0:80ee8f3b695e	2485	return HAL_OK;
EricLew	0:80ee8f3b695e	2486	}
EricLew	0:80ee8f3b695e	2487
EricLew	0:80ee8f3b695e	2488	/**
EricLew	0:80ee8f3b695e	2489	* @brief Stops the TIM Encoder Interface in interrupt mode.
EricLew	0:80ee8f3b695e	2490	* @param htim : TIM Encoder Interface handle
EricLew	0:80ee8f3b695e	2491	* @param Channel : TIM Channels to be disabled
EricLew	0:80ee8f3b695e	2492	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2493	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2494	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2495	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
EricLew	0:80ee8f3b695e	2496	* @retval HAL status
EricLew	0:80ee8f3b695e	2497	*/
EricLew	0:80ee8f3b695e	2498	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	2499	{
EricLew	0:80ee8f3b695e	2500	/* Check the parameters */
EricLew	0:80ee8f3b695e	2501	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2502
EricLew	0:80ee8f3b695e	2503	/* Disable the Input Capture channels 1 and 2
EricLew	0:80ee8f3b695e	2504	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
EricLew	0:80ee8f3b695e	2505	if(Channel == TIM_CHANNEL_1)
EricLew	0:80ee8f3b695e	2506	{
EricLew	0:80ee8f3b695e	2507	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2508
EricLew	0:80ee8f3b695e	2509	/* Disable the capture compare Interrupts 1 */
EricLew	0:80ee8f3b695e	2510	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	2511	}
EricLew	0:80ee8f3b695e	2512	else if(Channel == TIM_CHANNEL_2)
EricLew	0:80ee8f3b695e	2513	{
EricLew	0:80ee8f3b695e	2514	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2515
EricLew	0:80ee8f3b695e	2516	/* Disable the capture compare Interrupts 2 */
EricLew	0:80ee8f3b695e	2517	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	2518	}
EricLew	0:80ee8f3b695e	2519	else
EricLew	0:80ee8f3b695e	2520	{
EricLew	0:80ee8f3b695e	2521	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2522	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2523
EricLew	0:80ee8f3b695e	2524	/* Disable the capture compare Interrupts 1 and 2 */
EricLew	0:80ee8f3b695e	2525	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	2526	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	2527	}
EricLew	0:80ee8f3b695e	2528
EricLew	0:80ee8f3b695e	2529	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	2530	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	2531
EricLew	0:80ee8f3b695e	2532	/* Change the htim state */
EricLew	0:80ee8f3b695e	2533	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	2534
EricLew	0:80ee8f3b695e	2535	/* Return function status */
EricLew	0:80ee8f3b695e	2536	return HAL_OK;
EricLew	0:80ee8f3b695e	2537	}
EricLew	0:80ee8f3b695e	2538
EricLew	0:80ee8f3b695e	2539	/**
EricLew	0:80ee8f3b695e	2540	* @brief Starts the TIM Encoder Interface in DMA mode.
EricLew	0:80ee8f3b695e	2541	* @param htim : TIM Encoder Interface handle
EricLew	0:80ee8f3b695e	2542	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	2543	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2544	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2545	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2546	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
EricLew	0:80ee8f3b695e	2547	* @param pData1: The destination Buffer address for IC1.
EricLew	0:80ee8f3b695e	2548	* @param pData2: The destination Buffer address for IC2.
EricLew	0:80ee8f3b695e	2549	* @param Length: The length of data to be transferred from TIM peripheral to memory.
EricLew	0:80ee8f3b695e	2550	* @retval HAL status
EricLew	0:80ee8f3b695e	2551	*/
EricLew	0:80ee8f3b695e	2552	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
EricLew	0:80ee8f3b695e	2553	{
EricLew	0:80ee8f3b695e	2554	/* Check the parameters */
EricLew	0:80ee8f3b695e	2555	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2556
EricLew	0:80ee8f3b695e	2557	if((htim->State == HAL_TIM_STATE_BUSY))
EricLew	0:80ee8f3b695e	2558	{
EricLew	0:80ee8f3b695e	2559	return HAL_BUSY;
EricLew	0:80ee8f3b695e	2560	}
EricLew	0:80ee8f3b695e	2561	else if((htim->State == HAL_TIM_STATE_READY))
EricLew	0:80ee8f3b695e	2562	{
EricLew	0:80ee8f3b695e	2563	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
EricLew	0:80ee8f3b695e	2564	{
EricLew	0:80ee8f3b695e	2565	return HAL_ERROR;
EricLew	0:80ee8f3b695e	2566	}
EricLew	0:80ee8f3b695e	2567	else
EricLew	0:80ee8f3b695e	2568	{
EricLew	0:80ee8f3b695e	2569	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	2570	}
EricLew	0:80ee8f3b695e	2571	}
EricLew	0:80ee8f3b695e	2572
EricLew	0:80ee8f3b695e	2573	switch (Channel)
EricLew	0:80ee8f3b695e	2574	{
EricLew	0:80ee8f3b695e	2575	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	2576	{
EricLew	0:80ee8f3b695e	2577	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	2578	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	2579
EricLew	0:80ee8f3b695e	2580	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	2581	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	2582
EricLew	0:80ee8f3b695e	2583	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	2584	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
EricLew	0:80ee8f3b695e	2585
EricLew	0:80ee8f3b695e	2586	/* Enable the TIM Input Capture DMA request */
EricLew	0:80ee8f3b695e	2587	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	2588
EricLew	0:80ee8f3b695e	2589	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	2590	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	2591
EricLew	0:80ee8f3b695e	2592	/* Enable the Capture compare channel */
EricLew	0:80ee8f3b695e	2593	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2594	}
EricLew	0:80ee8f3b695e	2595	break;
EricLew	0:80ee8f3b695e	2596
EricLew	0:80ee8f3b695e	2597	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	2598	{
EricLew	0:80ee8f3b695e	2599	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	2600	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	2601
EricLew	0:80ee8f3b695e	2602	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	2603	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
EricLew	0:80ee8f3b695e	2604	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	2605	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
EricLew	0:80ee8f3b695e	2606
EricLew	0:80ee8f3b695e	2607	/* Enable the TIM Input Capture DMA request */
EricLew	0:80ee8f3b695e	2608	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	2609
EricLew	0:80ee8f3b695e	2610	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	2611	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	2612
EricLew	0:80ee8f3b695e	2613	/* Enable the Capture compare channel */
EricLew	0:80ee8f3b695e	2614	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2615	}
EricLew	0:80ee8f3b695e	2616	break;
EricLew	0:80ee8f3b695e	2617
EricLew	0:80ee8f3b695e	2618	case TIM_CHANNEL_ALL:
EricLew	0:80ee8f3b695e	2619	{
EricLew	0:80ee8f3b695e	2620	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	2621	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	2622
EricLew	0:80ee8f3b695e	2623	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	2624	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	2625
EricLew	0:80ee8f3b695e	2626	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	2627	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
EricLew	0:80ee8f3b695e	2628
EricLew	0:80ee8f3b695e	2629	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	2630	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	2631
EricLew	0:80ee8f3b695e	2632	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	2633	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	2634
EricLew	0:80ee8f3b695e	2635	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	2636	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
EricLew	0:80ee8f3b695e	2637
EricLew	0:80ee8f3b695e	2638	/* Enable the Peripheral */
EricLew	0:80ee8f3b695e	2639	__HAL_TIM_ENABLE(htim);
EricLew	0:80ee8f3b695e	2640
EricLew	0:80ee8f3b695e	2641	/* Enable the Capture compare channel */
EricLew	0:80ee8f3b695e	2642	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2643	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
EricLew	0:80ee8f3b695e	2644
EricLew	0:80ee8f3b695e	2645	/* Enable the TIM Input Capture DMA request */
EricLew	0:80ee8f3b695e	2646	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	2647	/* Enable the TIM Input Capture DMA request */
EricLew	0:80ee8f3b695e	2648	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	2649	}
EricLew	0:80ee8f3b695e	2650	break;
EricLew	0:80ee8f3b695e	2651
EricLew	0:80ee8f3b695e	2652	default:
EricLew	0:80ee8f3b695e	2653	break;
EricLew	0:80ee8f3b695e	2654	}
EricLew	0:80ee8f3b695e	2655	/* Return function status */
EricLew	0:80ee8f3b695e	2656	return HAL_OK;
EricLew	0:80ee8f3b695e	2657	}
EricLew	0:80ee8f3b695e	2658
EricLew	0:80ee8f3b695e	2659	/**
EricLew	0:80ee8f3b695e	2660	* @brief Stops the TIM Encoder Interface in DMA mode.
EricLew	0:80ee8f3b695e	2661	* @param htim : TIM Encoder Interface handle
EricLew	0:80ee8f3b695e	2662	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	2663	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2664	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2665	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2666	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
EricLew	0:80ee8f3b695e	2667	* @retval HAL status
EricLew	0:80ee8f3b695e	2668	*/
EricLew	0:80ee8f3b695e	2669	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	2670	{
EricLew	0:80ee8f3b695e	2671	/* Check the parameters */
EricLew	0:80ee8f3b695e	2672	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2673
EricLew	0:80ee8f3b695e	2674	/* Disable the Input Capture channels 1 and 2
EricLew	0:80ee8f3b695e	2675	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
EricLew	0:80ee8f3b695e	2676	if(Channel == TIM_CHANNEL_1)
EricLew	0:80ee8f3b695e	2677	{
EricLew	0:80ee8f3b695e	2678	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2679
EricLew	0:80ee8f3b695e	2680	/* Disable the capture compare DMA Request 1 */
EricLew	0:80ee8f3b695e	2681	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	2682	}
EricLew	0:80ee8f3b695e	2683	else if(Channel == TIM_CHANNEL_2)
EricLew	0:80ee8f3b695e	2684	{
EricLew	0:80ee8f3b695e	2685	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2686
EricLew	0:80ee8f3b695e	2687	/* Disable the capture compare DMA Request 2 */
EricLew	0:80ee8f3b695e	2688	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	2689	}
EricLew	0:80ee8f3b695e	2690	else
EricLew	0:80ee8f3b695e	2691	{
EricLew	0:80ee8f3b695e	2692	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2693	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
EricLew	0:80ee8f3b695e	2694
EricLew	0:80ee8f3b695e	2695	/* Disable the capture compare DMA Request 1 and 2 */
EricLew	0:80ee8f3b695e	2696	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
EricLew	0:80ee8f3b695e	2697	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
EricLew	0:80ee8f3b695e	2698	}
EricLew	0:80ee8f3b695e	2699
EricLew	0:80ee8f3b695e	2700	/* Disable the Peripheral */
EricLew	0:80ee8f3b695e	2701	__HAL_TIM_DISABLE(htim);
EricLew	0:80ee8f3b695e	2702
EricLew	0:80ee8f3b695e	2703	/* Change the htim state */
EricLew	0:80ee8f3b695e	2704	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	2705
EricLew	0:80ee8f3b695e	2706	/* Return function status */
EricLew	0:80ee8f3b695e	2707	return HAL_OK;
EricLew	0:80ee8f3b695e	2708	}
EricLew	0:80ee8f3b695e	2709
EricLew	0:80ee8f3b695e	2710	/**
EricLew	0:80ee8f3b695e	2711	* @}
EricLew	0:80ee8f3b695e	2712	*/
EricLew	0:80ee8f3b695e	2713	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
EricLew	0:80ee8f3b695e	2714	* @brief IRQ handler management
EricLew	0:80ee8f3b695e	2715	*
EricLew	0:80ee8f3b695e	2716	@verbatim
EricLew	0:80ee8f3b695e	2717	==============================================================================
EricLew	0:80ee8f3b695e	2718	##### IRQ handler management #####
EricLew	0:80ee8f3b695e	2719	==============================================================================
EricLew	0:80ee8f3b695e	2720	[..]
EricLew	0:80ee8f3b695e	2721	This section provides Timer IRQ handler function.
EricLew	0:80ee8f3b695e	2722
EricLew	0:80ee8f3b695e	2723	@endverbatim
EricLew	0:80ee8f3b695e	2724	* @{
EricLew	0:80ee8f3b695e	2725	*/
EricLew	0:80ee8f3b695e	2726	/**
EricLew	0:80ee8f3b695e	2727	* @brief This function handles TIM interrupts requests.
EricLew	0:80ee8f3b695e	2728	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	2729	* @retval None
EricLew	0:80ee8f3b695e	2730	*/
EricLew	0:80ee8f3b695e	2731	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	2732	{
EricLew	0:80ee8f3b695e	2733	/* Capture compare 1 event */
EricLew	0:80ee8f3b695e	2734	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
EricLew	0:80ee8f3b695e	2735	{
EricLew	0:80ee8f3b695e	2736	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
EricLew	0:80ee8f3b695e	2737	{
EricLew	0:80ee8f3b695e	2738	{
EricLew	0:80ee8f3b695e	2739	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
EricLew	0:80ee8f3b695e	2740	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
EricLew	0:80ee8f3b695e	2741
EricLew	0:80ee8f3b695e	2742	/* Input capture event */
EricLew	0:80ee8f3b695e	2743	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
EricLew	0:80ee8f3b695e	2744	{
EricLew	0:80ee8f3b695e	2745	HAL_TIM_IC_CaptureCallback(htim);
EricLew	0:80ee8f3b695e	2746	}
EricLew	0:80ee8f3b695e	2747	/* Output compare event */
EricLew	0:80ee8f3b695e	2748	else
EricLew	0:80ee8f3b695e	2749	{
EricLew	0:80ee8f3b695e	2750	HAL_TIM_OC_DelayElapsedCallback(htim);
EricLew	0:80ee8f3b695e	2751	HAL_TIM_PWM_PulseFinishedCallback(htim);
EricLew	0:80ee8f3b695e	2752	}
EricLew	0:80ee8f3b695e	2753	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
EricLew	0:80ee8f3b695e	2754	}
EricLew	0:80ee8f3b695e	2755	}
EricLew	0:80ee8f3b695e	2756	}
EricLew	0:80ee8f3b695e	2757	/* Capture compare 2 event */
EricLew	0:80ee8f3b695e	2758	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
EricLew	0:80ee8f3b695e	2759	{
EricLew	0:80ee8f3b695e	2760	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
EricLew	0:80ee8f3b695e	2761	{
EricLew	0:80ee8f3b695e	2762	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
EricLew	0:80ee8f3b695e	2763	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
EricLew	0:80ee8f3b695e	2764	/* Input capture event */
EricLew	0:80ee8f3b695e	2765	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
EricLew	0:80ee8f3b695e	2766	{
EricLew	0:80ee8f3b695e	2767	HAL_TIM_IC_CaptureCallback(htim);
EricLew	0:80ee8f3b695e	2768	}
EricLew	0:80ee8f3b695e	2769	/* Output compare event */
EricLew	0:80ee8f3b695e	2770	else
EricLew	0:80ee8f3b695e	2771	{
EricLew	0:80ee8f3b695e	2772	HAL_TIM_OC_DelayElapsedCallback(htim);
EricLew	0:80ee8f3b695e	2773	HAL_TIM_PWM_PulseFinishedCallback(htim);
EricLew	0:80ee8f3b695e	2774	}
EricLew	0:80ee8f3b695e	2775	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
EricLew	0:80ee8f3b695e	2776	}
EricLew	0:80ee8f3b695e	2777	}
EricLew	0:80ee8f3b695e	2778	/* Capture compare 3 event */
EricLew	0:80ee8f3b695e	2779	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
EricLew	0:80ee8f3b695e	2780	{
EricLew	0:80ee8f3b695e	2781	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
EricLew	0:80ee8f3b695e	2782	{
EricLew	0:80ee8f3b695e	2783	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
EricLew	0:80ee8f3b695e	2784	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
EricLew	0:80ee8f3b695e	2785	/* Input capture event */
EricLew	0:80ee8f3b695e	2786	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
EricLew	0:80ee8f3b695e	2787	{
EricLew	0:80ee8f3b695e	2788	HAL_TIM_IC_CaptureCallback(htim);
EricLew	0:80ee8f3b695e	2789	}
EricLew	0:80ee8f3b695e	2790	/* Output compare event */
EricLew	0:80ee8f3b695e	2791	else
EricLew	0:80ee8f3b695e	2792	{
EricLew	0:80ee8f3b695e	2793	HAL_TIM_OC_DelayElapsedCallback(htim);
EricLew	0:80ee8f3b695e	2794	HAL_TIM_PWM_PulseFinishedCallback(htim);
EricLew	0:80ee8f3b695e	2795	}
EricLew	0:80ee8f3b695e	2796	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
EricLew	0:80ee8f3b695e	2797	}
EricLew	0:80ee8f3b695e	2798	}
EricLew	0:80ee8f3b695e	2799	/* Capture compare 4 event */
EricLew	0:80ee8f3b695e	2800	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
EricLew	0:80ee8f3b695e	2801	{
EricLew	0:80ee8f3b695e	2802	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
EricLew	0:80ee8f3b695e	2803	{
EricLew	0:80ee8f3b695e	2804	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
EricLew	0:80ee8f3b695e	2805	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
EricLew	0:80ee8f3b695e	2806	/* Input capture event */
EricLew	0:80ee8f3b695e	2807	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
EricLew	0:80ee8f3b695e	2808	{
EricLew	0:80ee8f3b695e	2809	HAL_TIM_IC_CaptureCallback(htim);
EricLew	0:80ee8f3b695e	2810	}
EricLew	0:80ee8f3b695e	2811	/* Output compare event */
EricLew	0:80ee8f3b695e	2812	else
EricLew	0:80ee8f3b695e	2813	{
EricLew	0:80ee8f3b695e	2814	HAL_TIM_OC_DelayElapsedCallback(htim);
EricLew	0:80ee8f3b695e	2815	HAL_TIM_PWM_PulseFinishedCallback(htim);
EricLew	0:80ee8f3b695e	2816	}
EricLew	0:80ee8f3b695e	2817	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
EricLew	0:80ee8f3b695e	2818	}
EricLew	0:80ee8f3b695e	2819	}
EricLew	0:80ee8f3b695e	2820	/* TIM Update event */
EricLew	0:80ee8f3b695e	2821	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
EricLew	0:80ee8f3b695e	2822	{
EricLew	0:80ee8f3b695e	2823	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
EricLew	0:80ee8f3b695e	2824	{
EricLew	0:80ee8f3b695e	2825	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
EricLew	0:80ee8f3b695e	2826	HAL_TIM_PeriodElapsedCallback(htim);
EricLew	0:80ee8f3b695e	2827	}
EricLew	0:80ee8f3b695e	2828	}
EricLew	0:80ee8f3b695e	2829	/* TIM Break input event */
EricLew	0:80ee8f3b695e	2830	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
EricLew	0:80ee8f3b695e	2831	{
EricLew	0:80ee8f3b695e	2832	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
EricLew	0:80ee8f3b695e	2833	{
EricLew	0:80ee8f3b695e	2834	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
EricLew	0:80ee8f3b695e	2835	HAL_TIMEx_BreakCallback(htim);
EricLew	0:80ee8f3b695e	2836	}
EricLew	0:80ee8f3b695e	2837	}
EricLew	0:80ee8f3b695e	2838	/* TIM Trigger detection event */
EricLew	0:80ee8f3b695e	2839	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
EricLew	0:80ee8f3b695e	2840	{
EricLew	0:80ee8f3b695e	2841	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
EricLew	0:80ee8f3b695e	2842	{
EricLew	0:80ee8f3b695e	2843	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
EricLew	0:80ee8f3b695e	2844	HAL_TIM_TriggerCallback(htim);
EricLew	0:80ee8f3b695e	2845	}
EricLew	0:80ee8f3b695e	2846	}
EricLew	0:80ee8f3b695e	2847	/* TIM commutation event */
EricLew	0:80ee8f3b695e	2848	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
EricLew	0:80ee8f3b695e	2849	{
EricLew	0:80ee8f3b695e	2850	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
EricLew	0:80ee8f3b695e	2851	{
EricLew	0:80ee8f3b695e	2852	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
EricLew	0:80ee8f3b695e	2853	HAL_TIMEx_CommutationCallback(htim);
EricLew	0:80ee8f3b695e	2854	}
EricLew	0:80ee8f3b695e	2855	}
EricLew	0:80ee8f3b695e	2856	}
EricLew	0:80ee8f3b695e	2857
EricLew	0:80ee8f3b695e	2858	/**
EricLew	0:80ee8f3b695e	2859	* @}
EricLew	0:80ee8f3b695e	2860	*/
EricLew	0:80ee8f3b695e	2861
EricLew	0:80ee8f3b695e	2862	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
EricLew	0:80ee8f3b695e	2863	* @brief Peripheral Control functions
EricLew	0:80ee8f3b695e	2864	*
EricLew	0:80ee8f3b695e	2865	@verbatim
EricLew	0:80ee8f3b695e	2866	==============================================================================
EricLew	0:80ee8f3b695e	2867	##### Peripheral Control functions #####
EricLew	0:80ee8f3b695e	2868	==============================================================================
EricLew	0:80ee8f3b695e	2869	[..]
EricLew	0:80ee8f3b695e	2870	This section provides functions allowing to:
EricLew	0:80ee8f3b695e	2871	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
EricLew	0:80ee8f3b695e	2872	(+) Configure External Clock source.
EricLew	0:80ee8f3b695e	2873	(+) Configure Complementary channels, break features and dead time.
EricLew	0:80ee8f3b695e	2874	(+) Configure Master and the Slave synchronization.
EricLew	0:80ee8f3b695e	2875	(+) Configure the DMA Burst Mode.
EricLew	0:80ee8f3b695e	2876
EricLew	0:80ee8f3b695e	2877	@endverbatim
EricLew	0:80ee8f3b695e	2878	* @{
EricLew	0:80ee8f3b695e	2879	*/
EricLew	0:80ee8f3b695e	2880
EricLew	0:80ee8f3b695e	2881	/**
EricLew	0:80ee8f3b695e	2882	* @brief Initializes the TIM Output Compare Channels according to the specified
EricLew	0:80ee8f3b695e	2883	* parameters in the TIM_OC_InitTypeDef.
EricLew	0:80ee8f3b695e	2884	* @param htim: TIM Output Compare handle
EricLew	0:80ee8f3b695e	2885	* @param sConfig: TIM Output Compare configuration structure
EricLew	0:80ee8f3b695e	2886	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	2887	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2888	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2889	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2890	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	2891	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	2892	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
EricLew	0:80ee8f3b695e	2893	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
EricLew	0:80ee8f3b695e	2894	* @retval HAL status
EricLew	0:80ee8f3b695e	2895	*/
EricLew	0:80ee8f3b695e	2896	__weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
EricLew	0:80ee8f3b695e	2897	{
EricLew	0:80ee8f3b695e	2898	/* Check the parameters */
EricLew	0:80ee8f3b695e	2899	assert_param(IS_TIM_CHANNELS(Channel));
EricLew	0:80ee8f3b695e	2900	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
EricLew	0:80ee8f3b695e	2901	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
EricLew	0:80ee8f3b695e	2902	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
EricLew	0:80ee8f3b695e	2903	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
EricLew	0:80ee8f3b695e	2904	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
EricLew	0:80ee8f3b695e	2905
EricLew	0:80ee8f3b695e	2906	/* Check input state */
EricLew	0:80ee8f3b695e	2907	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	2908
EricLew	0:80ee8f3b695e	2909	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	2910
EricLew	0:80ee8f3b695e	2911	switch (Channel)
EricLew	0:80ee8f3b695e	2912	{
EricLew	0:80ee8f3b695e	2913	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	2914	{
EricLew	0:80ee8f3b695e	2915	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2916	/* Configure the TIM Channel 1 in Output Compare */
EricLew	0:80ee8f3b695e	2917	TIM_OC1_SetConfig(htim->Instance, sConfig);
EricLew	0:80ee8f3b695e	2918	}
EricLew	0:80ee8f3b695e	2919	break;
EricLew	0:80ee8f3b695e	2920
EricLew	0:80ee8f3b695e	2921	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	2922	{
EricLew	0:80ee8f3b695e	2923	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2924	/* Configure the TIM Channel 2 in Output Compare */
EricLew	0:80ee8f3b695e	2925	TIM_OC2_SetConfig(htim->Instance, sConfig);
EricLew	0:80ee8f3b695e	2926	}
EricLew	0:80ee8f3b695e	2927	break;
EricLew	0:80ee8f3b695e	2928
EricLew	0:80ee8f3b695e	2929	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	2930	{
EricLew	0:80ee8f3b695e	2931	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2932	/* Configure the TIM Channel 3 in Output Compare */
EricLew	0:80ee8f3b695e	2933	TIM_OC3_SetConfig(htim->Instance, sConfig);
EricLew	0:80ee8f3b695e	2934	}
EricLew	0:80ee8f3b695e	2935	break;
EricLew	0:80ee8f3b695e	2936
EricLew	0:80ee8f3b695e	2937	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	2938	{
EricLew	0:80ee8f3b695e	2939	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2940	/* Configure the TIM Channel 4 in Output Compare */
EricLew	0:80ee8f3b695e	2941	TIM_OC4_SetConfig(htim->Instance, sConfig);
EricLew	0:80ee8f3b695e	2942	}
EricLew	0:80ee8f3b695e	2943	break;
EricLew	0:80ee8f3b695e	2944
EricLew	0:80ee8f3b695e	2945	default:
EricLew	0:80ee8f3b695e	2946	break;
EricLew	0:80ee8f3b695e	2947	}
EricLew	0:80ee8f3b695e	2948	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	2949
EricLew	0:80ee8f3b695e	2950	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	2951
EricLew	0:80ee8f3b695e	2952	return HAL_OK;
EricLew	0:80ee8f3b695e	2953	}
EricLew	0:80ee8f3b695e	2954
EricLew	0:80ee8f3b695e	2955	/**
EricLew	0:80ee8f3b695e	2956	* @brief Initializes the TIM Input Capture Channels according to the specified
EricLew	0:80ee8f3b695e	2957	* parameters in the TIM_IC_InitTypeDef.
EricLew	0:80ee8f3b695e	2958	* @param htim: TIM IC handle
EricLew	0:80ee8f3b695e	2959	* @param sConfig: TIM Input Capture configuration structure
EricLew	0:80ee8f3b695e	2960	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	2961	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2962	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	2963	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	2964	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	2965	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	2966	* @retval HAL status
EricLew	0:80ee8f3b695e	2967	*/
EricLew	0:80ee8f3b695e	2968	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
EricLew	0:80ee8f3b695e	2969	{
EricLew	0:80ee8f3b695e	2970	/* Check the parameters */
EricLew	0:80ee8f3b695e	2971	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2972	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
EricLew	0:80ee8f3b695e	2973	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
EricLew	0:80ee8f3b695e	2974	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
EricLew	0:80ee8f3b695e	2975	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
EricLew	0:80ee8f3b695e	2976
EricLew	0:80ee8f3b695e	2977	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	2978
EricLew	0:80ee8f3b695e	2979	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	2980
EricLew	0:80ee8f3b695e	2981	if (Channel == TIM_CHANNEL_1)
EricLew	0:80ee8f3b695e	2982	{
EricLew	0:80ee8f3b695e	2983	/* TI1 Configuration */
EricLew	0:80ee8f3b695e	2984	TIM_TI1_SetConfig(htim->Instance,
EricLew	0:80ee8f3b695e	2985	sConfig->ICPolarity,
EricLew	0:80ee8f3b695e	2986	sConfig->ICSelection,
EricLew	0:80ee8f3b695e	2987	sConfig->ICFilter);
EricLew	0:80ee8f3b695e	2988
EricLew	0:80ee8f3b695e	2989	/* Reset the IC1PSC Bits */
EricLew	0:80ee8f3b695e	2990	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
EricLew	0:80ee8f3b695e	2991
EricLew	0:80ee8f3b695e	2992	/* Set the IC1PSC value */
EricLew	0:80ee8f3b695e	2993	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
EricLew	0:80ee8f3b695e	2994	}
EricLew	0:80ee8f3b695e	2995	else if (Channel == TIM_CHANNEL_2)
EricLew	0:80ee8f3b695e	2996	{
EricLew	0:80ee8f3b695e	2997	/* TI2 Configuration */
EricLew	0:80ee8f3b695e	2998	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	2999
EricLew	0:80ee8f3b695e	3000	TIM_TI2_SetConfig(htim->Instance,
EricLew	0:80ee8f3b695e	3001	sConfig->ICPolarity,
EricLew	0:80ee8f3b695e	3002	sConfig->ICSelection,
EricLew	0:80ee8f3b695e	3003	sConfig->ICFilter);
EricLew	0:80ee8f3b695e	3004
EricLew	0:80ee8f3b695e	3005	/* Reset the IC2PSC Bits */
EricLew	0:80ee8f3b695e	3006	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
EricLew	0:80ee8f3b695e	3007
EricLew	0:80ee8f3b695e	3008	/* Set the IC2PSC value */
EricLew	0:80ee8f3b695e	3009	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
EricLew	0:80ee8f3b695e	3010	}
EricLew	0:80ee8f3b695e	3011	else if (Channel == TIM_CHANNEL_3)
EricLew	0:80ee8f3b695e	3012	{
EricLew	0:80ee8f3b695e	3013	/* TI3 Configuration */
EricLew	0:80ee8f3b695e	3014	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3015
EricLew	0:80ee8f3b695e	3016	TIM_TI3_SetConfig(htim->Instance,
EricLew	0:80ee8f3b695e	3017	sConfig->ICPolarity,
EricLew	0:80ee8f3b695e	3018	sConfig->ICSelection,
EricLew	0:80ee8f3b695e	3019	sConfig->ICFilter);
EricLew	0:80ee8f3b695e	3020
EricLew	0:80ee8f3b695e	3021	/* Reset the IC3PSC Bits */
EricLew	0:80ee8f3b695e	3022	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
EricLew	0:80ee8f3b695e	3023
EricLew	0:80ee8f3b695e	3024	/* Set the IC3PSC value */
EricLew	0:80ee8f3b695e	3025	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
EricLew	0:80ee8f3b695e	3026	}
EricLew	0:80ee8f3b695e	3027	else
EricLew	0:80ee8f3b695e	3028	{
EricLew	0:80ee8f3b695e	3029	/* TI4 Configuration */
EricLew	0:80ee8f3b695e	3030	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3031
EricLew	0:80ee8f3b695e	3032	TIM_TI4_SetConfig(htim->Instance,
EricLew	0:80ee8f3b695e	3033	sConfig->ICPolarity,
EricLew	0:80ee8f3b695e	3034	sConfig->ICSelection,
EricLew	0:80ee8f3b695e	3035	sConfig->ICFilter);
EricLew	0:80ee8f3b695e	3036
EricLew	0:80ee8f3b695e	3037	/* Reset the IC4PSC Bits */
EricLew	0:80ee8f3b695e	3038	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
EricLew	0:80ee8f3b695e	3039
EricLew	0:80ee8f3b695e	3040	/* Set the IC4PSC value */
EricLew	0:80ee8f3b695e	3041	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
EricLew	0:80ee8f3b695e	3042	}
EricLew	0:80ee8f3b695e	3043
EricLew	0:80ee8f3b695e	3044	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	3045
EricLew	0:80ee8f3b695e	3046	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	3047
EricLew	0:80ee8f3b695e	3048	return HAL_OK;
EricLew	0:80ee8f3b695e	3049	}
EricLew	0:80ee8f3b695e	3050
EricLew	0:80ee8f3b695e	3051	/**
EricLew	0:80ee8f3b695e	3052	* @brief Initializes the TIM PWM channels according to the specified
EricLew	0:80ee8f3b695e	3053	* parameters in the TIM_OC_InitTypeDef.
EricLew	0:80ee8f3b695e	3054	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	3055	* @param sConfig: TIM PWM configuration structure
EricLew	0:80ee8f3b695e	3056	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	3057	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3058	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	3059	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	3060	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	3061	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	3062	* @retval HAL status
EricLew	0:80ee8f3b695e	3063	*/
EricLew	0:80ee8f3b695e	3064	__weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
EricLew	0:80ee8f3b695e	3065	{
EricLew	0:80ee8f3b695e	3066	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	3067
EricLew	0:80ee8f3b695e	3068	/* Check the parameters */
EricLew	0:80ee8f3b695e	3069	assert_param(IS_TIM_CHANNELS(Channel));
EricLew	0:80ee8f3b695e	3070	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
EricLew	0:80ee8f3b695e	3071	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
EricLew	0:80ee8f3b695e	3072	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
EricLew	0:80ee8f3b695e	3073	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
EricLew	0:80ee8f3b695e	3074	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
EricLew	0:80ee8f3b695e	3075	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
EricLew	0:80ee8f3b695e	3076
EricLew	0:80ee8f3b695e	3077	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	3078
EricLew	0:80ee8f3b695e	3079	switch (Channel)
EricLew	0:80ee8f3b695e	3080	{
EricLew	0:80ee8f3b695e	3081	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	3082	{
EricLew	0:80ee8f3b695e	3083	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3084	/* Configure the Channel 1 in PWM mode */
EricLew	0:80ee8f3b695e	3085	TIM_OC1_SetConfig(htim->Instance, sConfig);
EricLew	0:80ee8f3b695e	3086
EricLew	0:80ee8f3b695e	3087	/* Set the Preload enable bit for channel1 */
EricLew	0:80ee8f3b695e	3088	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
EricLew	0:80ee8f3b695e	3089
EricLew	0:80ee8f3b695e	3090	/* Configure the Output Fast mode */
EricLew	0:80ee8f3b695e	3091	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
EricLew	0:80ee8f3b695e	3092	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
EricLew	0:80ee8f3b695e	3093	}
EricLew	0:80ee8f3b695e	3094	break;
EricLew	0:80ee8f3b695e	3095
EricLew	0:80ee8f3b695e	3096	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	3097	{
EricLew	0:80ee8f3b695e	3098	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3099	/* Configure the Channel 2 in PWM mode */
EricLew	0:80ee8f3b695e	3100	TIM_OC2_SetConfig(htim->Instance, sConfig);
EricLew	0:80ee8f3b695e	3101
EricLew	0:80ee8f3b695e	3102	/* Set the Preload enable bit for channel2 */
EricLew	0:80ee8f3b695e	3103	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
EricLew	0:80ee8f3b695e	3104
EricLew	0:80ee8f3b695e	3105	/* Configure the Output Fast mode */
EricLew	0:80ee8f3b695e	3106	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
EricLew	0:80ee8f3b695e	3107	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
EricLew	0:80ee8f3b695e	3108	}
EricLew	0:80ee8f3b695e	3109	break;
EricLew	0:80ee8f3b695e	3110
EricLew	0:80ee8f3b695e	3111	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	3112	{
EricLew	0:80ee8f3b695e	3113	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3114	/* Configure the Channel 3 in PWM mode */
EricLew	0:80ee8f3b695e	3115	TIM_OC3_SetConfig(htim->Instance, sConfig);
EricLew	0:80ee8f3b695e	3116
EricLew	0:80ee8f3b695e	3117	/* Set the Preload enable bit for channel3 */
EricLew	0:80ee8f3b695e	3118	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
EricLew	0:80ee8f3b695e	3119
EricLew	0:80ee8f3b695e	3120	/* Configure the Output Fast mode */
EricLew	0:80ee8f3b695e	3121	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
EricLew	0:80ee8f3b695e	3122	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
EricLew	0:80ee8f3b695e	3123	}
EricLew	0:80ee8f3b695e	3124	break;
EricLew	0:80ee8f3b695e	3125
EricLew	0:80ee8f3b695e	3126	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	3127	{
EricLew	0:80ee8f3b695e	3128	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3129	/* Configure the Channel 4 in PWM mode */
EricLew	0:80ee8f3b695e	3130	TIM_OC4_SetConfig(htim->Instance, sConfig);
EricLew	0:80ee8f3b695e	3131
EricLew	0:80ee8f3b695e	3132	/* Set the Preload enable bit for channel4 */
EricLew	0:80ee8f3b695e	3133	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
EricLew	0:80ee8f3b695e	3134
EricLew	0:80ee8f3b695e	3135	/* Configure the Output Fast mode */
EricLew	0:80ee8f3b695e	3136	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
EricLew	0:80ee8f3b695e	3137	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
EricLew	0:80ee8f3b695e	3138	}
EricLew	0:80ee8f3b695e	3139	break;
EricLew	0:80ee8f3b695e	3140
EricLew	0:80ee8f3b695e	3141	default:
EricLew	0:80ee8f3b695e	3142	break;
EricLew	0:80ee8f3b695e	3143	}
EricLew	0:80ee8f3b695e	3144
EricLew	0:80ee8f3b695e	3145	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	3146
EricLew	0:80ee8f3b695e	3147	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	3148
EricLew	0:80ee8f3b695e	3149	return HAL_OK;
EricLew	0:80ee8f3b695e	3150	}
EricLew	0:80ee8f3b695e	3151
EricLew	0:80ee8f3b695e	3152	/**
EricLew	0:80ee8f3b695e	3153	* @brief Initializes the TIM One Pulse Channels according to the specified
EricLew	0:80ee8f3b695e	3154	* parameters in the TIM_OnePulse_InitTypeDef.
EricLew	0:80ee8f3b695e	3155	* @param htim: TIM One Pulse handle
EricLew	0:80ee8f3b695e	3156	* @param sConfig: TIM One Pulse configuration structure
EricLew	0:80ee8f3b695e	3157	* @param OutputChannel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	3158	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3159	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	3160	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	3161	* @param InputChannel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	3162	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3163	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	3164	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	3165	* @retval HAL status
EricLew	0:80ee8f3b695e	3166	*/
EricLew	0:80ee8f3b695e	3167	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
EricLew	0:80ee8f3b695e	3168	{
EricLew	0:80ee8f3b695e	3169	TIM_OC_InitTypeDef temp1;
EricLew	0:80ee8f3b695e	3170
EricLew	0:80ee8f3b695e	3171	/* Check the parameters */
EricLew	0:80ee8f3b695e	3172	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
EricLew	0:80ee8f3b695e	3173	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
EricLew	0:80ee8f3b695e	3174
EricLew	0:80ee8f3b695e	3175	if(OutputChannel != InputChannel)
EricLew	0:80ee8f3b695e	3176	{
EricLew	0:80ee8f3b695e	3177	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	3178
EricLew	0:80ee8f3b695e	3179	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	3180
EricLew	0:80ee8f3b695e	3181	/* Extract the Ouput compare configuration from sConfig structure */
EricLew	0:80ee8f3b695e	3182	temp1.OCMode = sConfig->OCMode;
EricLew	0:80ee8f3b695e	3183	temp1.Pulse = sConfig->Pulse;
EricLew	0:80ee8f3b695e	3184	temp1.OCPolarity = sConfig->OCPolarity;
EricLew	0:80ee8f3b695e	3185	temp1.OCNPolarity = sConfig->OCNPolarity;
EricLew	0:80ee8f3b695e	3186	temp1.OCIdleState = sConfig->OCIdleState;
EricLew	0:80ee8f3b695e	3187	temp1.OCNIdleState = sConfig->OCNIdleState;
EricLew	0:80ee8f3b695e	3188
EricLew	0:80ee8f3b695e	3189	switch (OutputChannel)
EricLew	0:80ee8f3b695e	3190	{
EricLew	0:80ee8f3b695e	3191	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	3192	{
EricLew	0:80ee8f3b695e	3193	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3194
EricLew	0:80ee8f3b695e	3195	TIM_OC1_SetConfig(htim->Instance, &temp1);
EricLew	0:80ee8f3b695e	3196	}
EricLew	0:80ee8f3b695e	3197	break;
EricLew	0:80ee8f3b695e	3198	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	3199	{
EricLew	0:80ee8f3b695e	3200	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3201
EricLew	0:80ee8f3b695e	3202	TIM_OC2_SetConfig(htim->Instance, &temp1);
EricLew	0:80ee8f3b695e	3203	}
EricLew	0:80ee8f3b695e	3204	break;
EricLew	0:80ee8f3b695e	3205	default:
EricLew	0:80ee8f3b695e	3206	break;
EricLew	0:80ee8f3b695e	3207	}
EricLew	0:80ee8f3b695e	3208	switch (InputChannel)
EricLew	0:80ee8f3b695e	3209	{
EricLew	0:80ee8f3b695e	3210	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	3211	{
EricLew	0:80ee8f3b695e	3212	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3213
EricLew	0:80ee8f3b695e	3214	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
EricLew	0:80ee8f3b695e	3215	sConfig->ICSelection, sConfig->ICFilter);
EricLew	0:80ee8f3b695e	3216
EricLew	0:80ee8f3b695e	3217	/* Reset the IC1PSC Bits */
EricLew	0:80ee8f3b695e	3218	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
EricLew	0:80ee8f3b695e	3219
EricLew	0:80ee8f3b695e	3220	/* Select the Trigger source */
EricLew	0:80ee8f3b695e	3221	htim->Instance->SMCR &= ~TIM_SMCR_TS;
EricLew	0:80ee8f3b695e	3222	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
EricLew	0:80ee8f3b695e	3223
EricLew	0:80ee8f3b695e	3224	/* Select the Slave Mode */
EricLew	0:80ee8f3b695e	3225	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
EricLew	0:80ee8f3b695e	3226	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
EricLew	0:80ee8f3b695e	3227	}
EricLew	0:80ee8f3b695e	3228	break;
EricLew	0:80ee8f3b695e	3229	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	3230	{
EricLew	0:80ee8f3b695e	3231	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3232
EricLew	0:80ee8f3b695e	3233	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
EricLew	0:80ee8f3b695e	3234	sConfig->ICSelection, sConfig->ICFilter);
EricLew	0:80ee8f3b695e	3235
EricLew	0:80ee8f3b695e	3236	/* Reset the IC2PSC Bits */
EricLew	0:80ee8f3b695e	3237	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
EricLew	0:80ee8f3b695e	3238
EricLew	0:80ee8f3b695e	3239	/* Select the Trigger source */
EricLew	0:80ee8f3b695e	3240	htim->Instance->SMCR &= ~TIM_SMCR_TS;
EricLew	0:80ee8f3b695e	3241	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
EricLew	0:80ee8f3b695e	3242
EricLew	0:80ee8f3b695e	3243	/* Select the Slave Mode */
EricLew	0:80ee8f3b695e	3244	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
EricLew	0:80ee8f3b695e	3245	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
EricLew	0:80ee8f3b695e	3246	}
EricLew	0:80ee8f3b695e	3247	break;
EricLew	0:80ee8f3b695e	3248
EricLew	0:80ee8f3b695e	3249	default:
EricLew	0:80ee8f3b695e	3250	break;
EricLew	0:80ee8f3b695e	3251	}
EricLew	0:80ee8f3b695e	3252
EricLew	0:80ee8f3b695e	3253	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	3254
EricLew	0:80ee8f3b695e	3255	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	3256
EricLew	0:80ee8f3b695e	3257	return HAL_OK;
EricLew	0:80ee8f3b695e	3258	}
EricLew	0:80ee8f3b695e	3259	else
EricLew	0:80ee8f3b695e	3260	{
EricLew	0:80ee8f3b695e	3261	return HAL_ERROR;
EricLew	0:80ee8f3b695e	3262	}
EricLew	0:80ee8f3b695e	3263	}
EricLew	0:80ee8f3b695e	3264
EricLew	0:80ee8f3b695e	3265	/**
EricLew	0:80ee8f3b695e	3266	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
EricLew	0:80ee8f3b695e	3267	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	3268	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
EricLew	0:80ee8f3b695e	3269	* This parameters can be on of the following values:
EricLew	0:80ee8f3b695e	3270	* @arg TIM_DMABASE_CR1
EricLew	0:80ee8f3b695e	3271	* @arg TIM_DMABASE_CR2
EricLew	0:80ee8f3b695e	3272	* @arg TIM_DMABASE_SMCR
EricLew	0:80ee8f3b695e	3273	* @arg TIM_DMABASE_DIER
EricLew	0:80ee8f3b695e	3274	* @arg TIM_DMABASE_SR
EricLew	0:80ee8f3b695e	3275	* @arg TIM_DMABASE_EGR
EricLew	0:80ee8f3b695e	3276	* @arg TIM_DMABASE_CCMR1
EricLew	0:80ee8f3b695e	3277	* @arg TIM_DMABASE_CCMR2
EricLew	0:80ee8f3b695e	3278	* @arg TIM_DMABASE_CCER
EricLew	0:80ee8f3b695e	3279	* @arg TIM_DMABASE_CNT
EricLew	0:80ee8f3b695e	3280	* @arg TIM_DMABASE_PSC
EricLew	0:80ee8f3b695e	3281	* @arg TIM_DMABASE_ARR
EricLew	0:80ee8f3b695e	3282	* @arg TIM_DMABASE_RCR
EricLew	0:80ee8f3b695e	3283	* @arg TIM_DMABASE_CCR1
EricLew	0:80ee8f3b695e	3284	* @arg TIM_DMABASE_CCR2
EricLew	0:80ee8f3b695e	3285	* @arg TIM_DMABASE_CCR3
EricLew	0:80ee8f3b695e	3286	* @arg TIM_DMABASE_CCR4
EricLew	0:80ee8f3b695e	3287	* @arg TIM_DMABASE_BDTR
EricLew	0:80ee8f3b695e	3288	* @arg TIM_DMABASE_DCR
EricLew	0:80ee8f3b695e	3289	* @param BurstRequestSrc: TIM DMA Request sources
EricLew	0:80ee8f3b695e	3290	* This parameters can be on of the following values:
EricLew	0:80ee8f3b695e	3291	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
EricLew	0:80ee8f3b695e	3292	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
EricLew	0:80ee8f3b695e	3293	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
EricLew	0:80ee8f3b695e	3294	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
EricLew	0:80ee8f3b695e	3295	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
EricLew	0:80ee8f3b695e	3296	* @arg TIM_DMA_COM: TIM Commutation DMA source
EricLew	0:80ee8f3b695e	3297	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
EricLew	0:80ee8f3b695e	3298	* @param BurstBuffer: The Buffer address.
EricLew	0:80ee8f3b695e	3299	* @param BurstLength: DMA Burst length. This parameter can be one value
EricLew	0:80ee8f3b695e	3300	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
EricLew	0:80ee8f3b695e	3301	* @retval HAL status
EricLew	0:80ee8f3b695e	3302	*/
EricLew	0:80ee8f3b695e	3303	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
EricLew	0:80ee8f3b695e	3304	uint32_t* BurstBuffer, uint32_t BurstLength)
EricLew	0:80ee8f3b695e	3305	{
EricLew	0:80ee8f3b695e	3306	/* Check the parameters */
EricLew	0:80ee8f3b695e	3307	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3308	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
EricLew	0:80ee8f3b695e	3309	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
EricLew	0:80ee8f3b695e	3310	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
EricLew	0:80ee8f3b695e	3311
EricLew	0:80ee8f3b695e	3312	if((htim->State == HAL_TIM_STATE_BUSY))
EricLew	0:80ee8f3b695e	3313	{
EricLew	0:80ee8f3b695e	3314	return HAL_BUSY;
EricLew	0:80ee8f3b695e	3315	}
EricLew	0:80ee8f3b695e	3316	else if((htim->State == HAL_TIM_STATE_READY))
EricLew	0:80ee8f3b695e	3317	{
EricLew	0:80ee8f3b695e	3318	if((BurstBuffer == 0 ) && (BurstLength > 0))
EricLew	0:80ee8f3b695e	3319	{
EricLew	0:80ee8f3b695e	3320	return HAL_ERROR;
EricLew	0:80ee8f3b695e	3321	}
EricLew	0:80ee8f3b695e	3322	else
EricLew	0:80ee8f3b695e	3323	{
EricLew	0:80ee8f3b695e	3324	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	3325	}
EricLew	0:80ee8f3b695e	3326	}
EricLew	0:80ee8f3b695e	3327	switch(BurstRequestSrc)
EricLew	0:80ee8f3b695e	3328	{
EricLew	0:80ee8f3b695e	3329	case TIM_DMA_UPDATE:
EricLew	0:80ee8f3b695e	3330	{
EricLew	0:80ee8f3b695e	3331	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3332	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
EricLew	0:80ee8f3b695e	3333
EricLew	0:80ee8f3b695e	3334	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3335	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3336
EricLew	0:80ee8f3b695e	3337	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3338	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3339	}
EricLew	0:80ee8f3b695e	3340	break;
EricLew	0:80ee8f3b695e	3341	case TIM_DMA_CC1:
EricLew	0:80ee8f3b695e	3342	{
EricLew	0:80ee8f3b695e	3343	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3344	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	3345
EricLew	0:80ee8f3b695e	3346	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3347	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3348
EricLew	0:80ee8f3b695e	3349	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3350	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3351	}
EricLew	0:80ee8f3b695e	3352	break;
EricLew	0:80ee8f3b695e	3353	case TIM_DMA_CC2:
EricLew	0:80ee8f3b695e	3354	{
EricLew	0:80ee8f3b695e	3355	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3356	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	3357
EricLew	0:80ee8f3b695e	3358	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3359	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3360
EricLew	0:80ee8f3b695e	3361	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3362	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3363	}
EricLew	0:80ee8f3b695e	3364	break;
EricLew	0:80ee8f3b695e	3365	case TIM_DMA_CC3:
EricLew	0:80ee8f3b695e	3366	{
EricLew	0:80ee8f3b695e	3367	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3368	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	3369
EricLew	0:80ee8f3b695e	3370	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3371	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3372
EricLew	0:80ee8f3b695e	3373	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3374	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3375	}
EricLew	0:80ee8f3b695e	3376	break;
EricLew	0:80ee8f3b695e	3377	case TIM_DMA_CC4:
EricLew	0:80ee8f3b695e	3378	{
EricLew	0:80ee8f3b695e	3379	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3380	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
EricLew	0:80ee8f3b695e	3381
EricLew	0:80ee8f3b695e	3382	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3383	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3384
EricLew	0:80ee8f3b695e	3385	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3386	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3387	}
EricLew	0:80ee8f3b695e	3388	break;
EricLew	0:80ee8f3b695e	3389	case TIM_DMA_COM:
EricLew	0:80ee8f3b695e	3390	{
EricLew	0:80ee8f3b695e	3391	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3392	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
EricLew	0:80ee8f3b695e	3393
EricLew	0:80ee8f3b695e	3394	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3395	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3396
EricLew	0:80ee8f3b695e	3397	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3398	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3399	}
EricLew	0:80ee8f3b695e	3400	break;
EricLew	0:80ee8f3b695e	3401	case TIM_DMA_TRIGGER:
EricLew	0:80ee8f3b695e	3402	{
EricLew	0:80ee8f3b695e	3403	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3404	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
EricLew	0:80ee8f3b695e	3405
EricLew	0:80ee8f3b695e	3406	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3407	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3408
EricLew	0:80ee8f3b695e	3409	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3410	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3411	}
EricLew	0:80ee8f3b695e	3412	break;
EricLew	0:80ee8f3b695e	3413	default:
EricLew	0:80ee8f3b695e	3414	break;
EricLew	0:80ee8f3b695e	3415	}
EricLew	0:80ee8f3b695e	3416	/* configure the DMA Burst Mode */
EricLew	0:80ee8f3b695e	3417	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
EricLew	0:80ee8f3b695e	3418
EricLew	0:80ee8f3b695e	3419	/* Enable the TIM DMA Request */
EricLew	0:80ee8f3b695e	3420	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
EricLew	0:80ee8f3b695e	3421
EricLew	0:80ee8f3b695e	3422	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	3423
EricLew	0:80ee8f3b695e	3424	/* Return function status */
EricLew	0:80ee8f3b695e	3425	return HAL_OK;
EricLew	0:80ee8f3b695e	3426	}
EricLew	0:80ee8f3b695e	3427
EricLew	0:80ee8f3b695e	3428	/**
EricLew	0:80ee8f3b695e	3429	* @brief Stops the TIM DMA Burst mode
EricLew	0:80ee8f3b695e	3430	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	3431	* @param BurstRequestSrc: TIM DMA Request sources to disable
EricLew	0:80ee8f3b695e	3432	* @retval HAL status
EricLew	0:80ee8f3b695e	3433	*/
EricLew	0:80ee8f3b695e	3434	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
EricLew	0:80ee8f3b695e	3435	{
EricLew	0:80ee8f3b695e	3436	/* Check the parameters */
EricLew	0:80ee8f3b695e	3437	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
EricLew	0:80ee8f3b695e	3438
EricLew	0:80ee8f3b695e	3439	/* Abort the DMA transfer (at least disable the DMA channel) */
EricLew	0:80ee8f3b695e	3440	switch(BurstRequestSrc)
EricLew	0:80ee8f3b695e	3441	{
EricLew	0:80ee8f3b695e	3442	case TIM_DMA_UPDATE:
EricLew	0:80ee8f3b695e	3443	{
EricLew	0:80ee8f3b695e	3444	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
EricLew	0:80ee8f3b695e	3445	}
EricLew	0:80ee8f3b695e	3446	break;
EricLew	0:80ee8f3b695e	3447	case TIM_DMA_CC1:
EricLew	0:80ee8f3b695e	3448	{
EricLew	0:80ee8f3b695e	3449	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
EricLew	0:80ee8f3b695e	3450	}
EricLew	0:80ee8f3b695e	3451	break;
EricLew	0:80ee8f3b695e	3452	case TIM_DMA_CC2:
EricLew	0:80ee8f3b695e	3453	{
EricLew	0:80ee8f3b695e	3454	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
EricLew	0:80ee8f3b695e	3455	}
EricLew	0:80ee8f3b695e	3456	break;
EricLew	0:80ee8f3b695e	3457	case TIM_DMA_CC3:
EricLew	0:80ee8f3b695e	3458	{
EricLew	0:80ee8f3b695e	3459	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
EricLew	0:80ee8f3b695e	3460	}
EricLew	0:80ee8f3b695e	3461	break;
EricLew	0:80ee8f3b695e	3462	case TIM_DMA_CC4:
EricLew	0:80ee8f3b695e	3463	{
EricLew	0:80ee8f3b695e	3464	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
EricLew	0:80ee8f3b695e	3465	}
EricLew	0:80ee8f3b695e	3466	break;
EricLew	0:80ee8f3b695e	3467	case TIM_DMA_COM:
EricLew	0:80ee8f3b695e	3468	{
EricLew	0:80ee8f3b695e	3469	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
EricLew	0:80ee8f3b695e	3470	}
EricLew	0:80ee8f3b695e	3471	break;
EricLew	0:80ee8f3b695e	3472	case TIM_DMA_TRIGGER:
EricLew	0:80ee8f3b695e	3473	{
EricLew	0:80ee8f3b695e	3474	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
EricLew	0:80ee8f3b695e	3475	}
EricLew	0:80ee8f3b695e	3476	break;
EricLew	0:80ee8f3b695e	3477	default:
EricLew	0:80ee8f3b695e	3478	break;
EricLew	0:80ee8f3b695e	3479	}
EricLew	0:80ee8f3b695e	3480
EricLew	0:80ee8f3b695e	3481	/* Disable the TIM Update DMA request */
EricLew	0:80ee8f3b695e	3482	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
EricLew	0:80ee8f3b695e	3483
EricLew	0:80ee8f3b695e	3484	/* Return function status */
EricLew	0:80ee8f3b695e	3485	return HAL_OK;
EricLew	0:80ee8f3b695e	3486	}
EricLew	0:80ee8f3b695e	3487
EricLew	0:80ee8f3b695e	3488	/**
EricLew	0:80ee8f3b695e	3489	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
EricLew	0:80ee8f3b695e	3490	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	3491	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
EricLew	0:80ee8f3b695e	3492	* This parameters can be on of the following values:
EricLew	0:80ee8f3b695e	3493	* @arg TIM_DMABASE_CR1
EricLew	0:80ee8f3b695e	3494	* @arg TIM_DMABASE_CR2
EricLew	0:80ee8f3b695e	3495	* @arg TIM_DMABASE_SMCR
EricLew	0:80ee8f3b695e	3496	* @arg TIM_DMABASE_DIER
EricLew	0:80ee8f3b695e	3497	* @arg TIM_DMABASE_SR
EricLew	0:80ee8f3b695e	3498	* @arg TIM_DMABASE_EGR
EricLew	0:80ee8f3b695e	3499	* @arg TIM_DMABASE_CCMR1
EricLew	0:80ee8f3b695e	3500	* @arg TIM_DMABASE_CCMR2
EricLew	0:80ee8f3b695e	3501	* @arg TIM_DMABASE_CCER
EricLew	0:80ee8f3b695e	3502	* @arg TIM_DMABASE_CNT
EricLew	0:80ee8f3b695e	3503	* @arg TIM_DMABASE_PSC
EricLew	0:80ee8f3b695e	3504	* @arg TIM_DMABASE_ARR
EricLew	0:80ee8f3b695e	3505	* @arg TIM_DMABASE_RCR
EricLew	0:80ee8f3b695e	3506	* @arg TIM_DMABASE_CCR1
EricLew	0:80ee8f3b695e	3507	* @arg TIM_DMABASE_CCR2
EricLew	0:80ee8f3b695e	3508	* @arg TIM_DMABASE_CCR3
EricLew	0:80ee8f3b695e	3509	* @arg TIM_DMABASE_CCR4
EricLew	0:80ee8f3b695e	3510	* @arg TIM_DMABASE_BDTR
EricLew	0:80ee8f3b695e	3511	* @arg TIM_DMABASE_DCR
EricLew	0:80ee8f3b695e	3512	* @param BurstRequestSrc: TIM DMA Request sources
EricLew	0:80ee8f3b695e	3513	* This parameters can be on of the following values:
EricLew	0:80ee8f3b695e	3514	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
EricLew	0:80ee8f3b695e	3515	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
EricLew	0:80ee8f3b695e	3516	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
EricLew	0:80ee8f3b695e	3517	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
EricLew	0:80ee8f3b695e	3518	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
EricLew	0:80ee8f3b695e	3519	* @arg TIM_DMA_COM: TIM Commutation DMA source
EricLew	0:80ee8f3b695e	3520	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
EricLew	0:80ee8f3b695e	3521	* @param BurstBuffer: The Buffer address.
EricLew	0:80ee8f3b695e	3522	* @param BurstLength: DMA Burst length. This parameter can be one value
EricLew	0:80ee8f3b695e	3523	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
EricLew	0:80ee8f3b695e	3524	* @retval HAL status
EricLew	0:80ee8f3b695e	3525	*/
EricLew	0:80ee8f3b695e	3526	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
EricLew	0:80ee8f3b695e	3527	uint32_t *BurstBuffer, uint32_t BurstLength)
EricLew	0:80ee8f3b695e	3528	{
EricLew	0:80ee8f3b695e	3529	/* Check the parameters */
EricLew	0:80ee8f3b695e	3530	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3531	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
EricLew	0:80ee8f3b695e	3532	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
EricLew	0:80ee8f3b695e	3533	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
EricLew	0:80ee8f3b695e	3534
EricLew	0:80ee8f3b695e	3535	if((htim->State == HAL_TIM_STATE_BUSY))
EricLew	0:80ee8f3b695e	3536	{
EricLew	0:80ee8f3b695e	3537	return HAL_BUSY;
EricLew	0:80ee8f3b695e	3538	}
EricLew	0:80ee8f3b695e	3539	else if((htim->State == HAL_TIM_STATE_READY))
EricLew	0:80ee8f3b695e	3540	{
EricLew	0:80ee8f3b695e	3541	if((BurstBuffer == 0 ) && (BurstLength > 0))
EricLew	0:80ee8f3b695e	3542	{
EricLew	0:80ee8f3b695e	3543	return HAL_ERROR;
EricLew	0:80ee8f3b695e	3544	}
EricLew	0:80ee8f3b695e	3545	else
EricLew	0:80ee8f3b695e	3546	{
EricLew	0:80ee8f3b695e	3547	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	3548	}
EricLew	0:80ee8f3b695e	3549	}
EricLew	0:80ee8f3b695e	3550	switch(BurstRequestSrc)
EricLew	0:80ee8f3b695e	3551	{
EricLew	0:80ee8f3b695e	3552	case TIM_DMA_UPDATE:
EricLew	0:80ee8f3b695e	3553	{
EricLew	0:80ee8f3b695e	3554	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3555	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
EricLew	0:80ee8f3b695e	3556
EricLew	0:80ee8f3b695e	3557	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3558	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3559
EricLew	0:80ee8f3b695e	3560	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3561	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3562	}
EricLew	0:80ee8f3b695e	3563	break;
EricLew	0:80ee8f3b695e	3564	case TIM_DMA_CC1:
EricLew	0:80ee8f3b695e	3565	{
EricLew	0:80ee8f3b695e	3566	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3567	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	3568
EricLew	0:80ee8f3b695e	3569	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3570	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3571
EricLew	0:80ee8f3b695e	3572	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3573	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3574	}
EricLew	0:80ee8f3b695e	3575	break;
EricLew	0:80ee8f3b695e	3576	case TIM_DMA_CC2:
EricLew	0:80ee8f3b695e	3577	{
EricLew	0:80ee8f3b695e	3578	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3579	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	3580
EricLew	0:80ee8f3b695e	3581	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3582	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3583
EricLew	0:80ee8f3b695e	3584	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3585	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3586	}
EricLew	0:80ee8f3b695e	3587	break;
EricLew	0:80ee8f3b695e	3588	case TIM_DMA_CC3:
EricLew	0:80ee8f3b695e	3589	{
EricLew	0:80ee8f3b695e	3590	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3591	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	3592
EricLew	0:80ee8f3b695e	3593	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3594	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3595
EricLew	0:80ee8f3b695e	3596	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3597	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3598	}
EricLew	0:80ee8f3b695e	3599	break;
EricLew	0:80ee8f3b695e	3600	case TIM_DMA_CC4:
EricLew	0:80ee8f3b695e	3601	{
EricLew	0:80ee8f3b695e	3602	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3603	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
EricLew	0:80ee8f3b695e	3604
EricLew	0:80ee8f3b695e	3605	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3606	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3607
EricLew	0:80ee8f3b695e	3608	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3609	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3610	}
EricLew	0:80ee8f3b695e	3611	break;
EricLew	0:80ee8f3b695e	3612	case TIM_DMA_COM:
EricLew	0:80ee8f3b695e	3613	{
EricLew	0:80ee8f3b695e	3614	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3615	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
EricLew	0:80ee8f3b695e	3616
EricLew	0:80ee8f3b695e	3617	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3618	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3619
EricLew	0:80ee8f3b695e	3620	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3621	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3622	}
EricLew	0:80ee8f3b695e	3623	break;
EricLew	0:80ee8f3b695e	3624	case TIM_DMA_TRIGGER:
EricLew	0:80ee8f3b695e	3625	{
EricLew	0:80ee8f3b695e	3626	/* Set the DMA Period elapsed callback */
EricLew	0:80ee8f3b695e	3627	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
EricLew	0:80ee8f3b695e	3628
EricLew	0:80ee8f3b695e	3629	/* Set the DMA error callback */
EricLew	0:80ee8f3b695e	3630	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
EricLew	0:80ee8f3b695e	3631
EricLew	0:80ee8f3b695e	3632	/* Enable the DMA channel */
EricLew	0:80ee8f3b695e	3633	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
EricLew	0:80ee8f3b695e	3634	}
EricLew	0:80ee8f3b695e	3635	break;
EricLew	0:80ee8f3b695e	3636	default:
EricLew	0:80ee8f3b695e	3637	break;
EricLew	0:80ee8f3b695e	3638	}
EricLew	0:80ee8f3b695e	3639
EricLew	0:80ee8f3b695e	3640	/* configure the DMA Burst Mode */
EricLew	0:80ee8f3b695e	3641	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
EricLew	0:80ee8f3b695e	3642
EricLew	0:80ee8f3b695e	3643	/* Enable the TIM DMA Request */
EricLew	0:80ee8f3b695e	3644	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
EricLew	0:80ee8f3b695e	3645
EricLew	0:80ee8f3b695e	3646	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	3647
EricLew	0:80ee8f3b695e	3648	/* Return function status */
EricLew	0:80ee8f3b695e	3649	return HAL_OK;
EricLew	0:80ee8f3b695e	3650	}
EricLew	0:80ee8f3b695e	3651
EricLew	0:80ee8f3b695e	3652	/**
EricLew	0:80ee8f3b695e	3653	* @brief Stop the DMA burst reading
EricLew	0:80ee8f3b695e	3654	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	3655	* @param BurstRequestSrc: TIM DMA Request sources to disable.
EricLew	0:80ee8f3b695e	3656	* @retval HAL status
EricLew	0:80ee8f3b695e	3657	*/
EricLew	0:80ee8f3b695e	3658	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
EricLew	0:80ee8f3b695e	3659	{
EricLew	0:80ee8f3b695e	3660	/* Check the parameters */
EricLew	0:80ee8f3b695e	3661	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
EricLew	0:80ee8f3b695e	3662
EricLew	0:80ee8f3b695e	3663	/* Abort the DMA transfer (at least disable the DMA channel) */
EricLew	0:80ee8f3b695e	3664	switch(BurstRequestSrc)
EricLew	0:80ee8f3b695e	3665	{
EricLew	0:80ee8f3b695e	3666	case TIM_DMA_UPDATE:
EricLew	0:80ee8f3b695e	3667	{
EricLew	0:80ee8f3b695e	3668	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
EricLew	0:80ee8f3b695e	3669	}
EricLew	0:80ee8f3b695e	3670	break;
EricLew	0:80ee8f3b695e	3671	case TIM_DMA_CC1:
EricLew	0:80ee8f3b695e	3672	{
EricLew	0:80ee8f3b695e	3673	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
EricLew	0:80ee8f3b695e	3674	}
EricLew	0:80ee8f3b695e	3675	break;
EricLew	0:80ee8f3b695e	3676	case TIM_DMA_CC2:
EricLew	0:80ee8f3b695e	3677	{
EricLew	0:80ee8f3b695e	3678	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
EricLew	0:80ee8f3b695e	3679	}
EricLew	0:80ee8f3b695e	3680	break;
EricLew	0:80ee8f3b695e	3681	case TIM_DMA_CC3:
EricLew	0:80ee8f3b695e	3682	{
EricLew	0:80ee8f3b695e	3683	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
EricLew	0:80ee8f3b695e	3684	}
EricLew	0:80ee8f3b695e	3685	break;
EricLew	0:80ee8f3b695e	3686	case TIM_DMA_CC4:
EricLew	0:80ee8f3b695e	3687	{
EricLew	0:80ee8f3b695e	3688	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
EricLew	0:80ee8f3b695e	3689	}
EricLew	0:80ee8f3b695e	3690	break;
EricLew	0:80ee8f3b695e	3691	case TIM_DMA_COM:
EricLew	0:80ee8f3b695e	3692	{
EricLew	0:80ee8f3b695e	3693	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
EricLew	0:80ee8f3b695e	3694	}
EricLew	0:80ee8f3b695e	3695	break;
EricLew	0:80ee8f3b695e	3696	case TIM_DMA_TRIGGER:
EricLew	0:80ee8f3b695e	3697	{
EricLew	0:80ee8f3b695e	3698	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
EricLew	0:80ee8f3b695e	3699	}
EricLew	0:80ee8f3b695e	3700	break;
EricLew	0:80ee8f3b695e	3701	default:
EricLew	0:80ee8f3b695e	3702	break;
EricLew	0:80ee8f3b695e	3703	}
EricLew	0:80ee8f3b695e	3704
EricLew	0:80ee8f3b695e	3705	/* Disable the TIM Update DMA request */
EricLew	0:80ee8f3b695e	3706	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
EricLew	0:80ee8f3b695e	3707
EricLew	0:80ee8f3b695e	3708	/* Return function status */
EricLew	0:80ee8f3b695e	3709	return HAL_OK;
EricLew	0:80ee8f3b695e	3710	}
EricLew	0:80ee8f3b695e	3711
EricLew	0:80ee8f3b695e	3712	/**
EricLew	0:80ee8f3b695e	3713	* @brief Generate a software event
EricLew	0:80ee8f3b695e	3714	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	3715	* @param EventSource: specifies the event source.
EricLew	0:80ee8f3b695e	3716	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3717	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
EricLew	0:80ee8f3b695e	3718	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
EricLew	0:80ee8f3b695e	3719	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
EricLew	0:80ee8f3b695e	3720	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
EricLew	0:80ee8f3b695e	3721	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
EricLew	0:80ee8f3b695e	3722	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
EricLew	0:80ee8f3b695e	3723	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
EricLew	0:80ee8f3b695e	3724	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
EricLew	0:80ee8f3b695e	3725	* @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
EricLew	0:80ee8f3b695e	3726	* @retval None
EricLew	0:80ee8f3b695e	3727	*/
EricLew	0:80ee8f3b695e	3728
EricLew	0:80ee8f3b695e	3729	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
EricLew	0:80ee8f3b695e	3730	{
EricLew	0:80ee8f3b695e	3731	/* Check the parameters */
EricLew	0:80ee8f3b695e	3732	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3733	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
EricLew	0:80ee8f3b695e	3734
EricLew	0:80ee8f3b695e	3735	/* Process Locked */
EricLew	0:80ee8f3b695e	3736	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	3737
EricLew	0:80ee8f3b695e	3738	/* Change the TIM state */
EricLew	0:80ee8f3b695e	3739	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	3740
EricLew	0:80ee8f3b695e	3741	/* Set the event sources */
EricLew	0:80ee8f3b695e	3742	htim->Instance->EGR = EventSource;
EricLew	0:80ee8f3b695e	3743
EricLew	0:80ee8f3b695e	3744	/* Change the TIM state */
EricLew	0:80ee8f3b695e	3745	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	3746
EricLew	0:80ee8f3b695e	3747	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	3748
EricLew	0:80ee8f3b695e	3749	/* Return function status */
EricLew	0:80ee8f3b695e	3750	return HAL_OK;
EricLew	0:80ee8f3b695e	3751	}
EricLew	0:80ee8f3b695e	3752
EricLew	0:80ee8f3b695e	3753	/**
EricLew	0:80ee8f3b695e	3754	* @brief Configures the OCRef clear feature
EricLew	0:80ee8f3b695e	3755	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	3756	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
EricLew	0:80ee8f3b695e	3757	* contains the OCREF clear feature and parameters for the TIM peripheral.
EricLew	0:80ee8f3b695e	3758	* @param Channel: specifies the TIM Channel
EricLew	0:80ee8f3b695e	3759	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3760	* @arg TIM_CHANNEL_1: TIM Channel 1
EricLew	0:80ee8f3b695e	3761	* @arg TIM_CHANNEL_2: TIM Channel 2
EricLew	0:80ee8f3b695e	3762	* @arg TIM_CHANNEL_3: TIM Channel 3
EricLew	0:80ee8f3b695e	3763	* @arg TIM_CHANNEL_4: TIM Channel 4
EricLew	0:80ee8f3b695e	3764	* @retval HAL status
EricLew	0:80ee8f3b695e	3765	*/
EricLew	0:80ee8f3b695e	3766	__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
EricLew	0:80ee8f3b695e	3767	{
EricLew	0:80ee8f3b695e	3768	/* Check the parameters */
EricLew	0:80ee8f3b695e	3769	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3770	assert_param(IS_TIM_CHANNELS(Channel));
EricLew	0:80ee8f3b695e	3771	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
EricLew	0:80ee8f3b695e	3772
EricLew	0:80ee8f3b695e	3773	/* Process Locked */
EricLew	0:80ee8f3b695e	3774	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	3775
EricLew	0:80ee8f3b695e	3776	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	3777
EricLew	0:80ee8f3b695e	3778	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
EricLew	0:80ee8f3b695e	3779	{
EricLew	0:80ee8f3b695e	3780	/* Check the parameters */
EricLew	0:80ee8f3b695e	3781	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
EricLew	0:80ee8f3b695e	3782	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
EricLew	0:80ee8f3b695e	3783	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
EricLew	0:80ee8f3b695e	3784
EricLew	0:80ee8f3b695e	3785	TIM_ETR_SetConfig(htim->Instance,
EricLew	0:80ee8f3b695e	3786	sClearInputConfig->ClearInputPrescaler,
EricLew	0:80ee8f3b695e	3787	sClearInputConfig->ClearInputPolarity,
EricLew	0:80ee8f3b695e	3788	sClearInputConfig->ClearInputFilter);
EricLew	0:80ee8f3b695e	3789	}
EricLew	0:80ee8f3b695e	3790
EricLew	0:80ee8f3b695e	3791	switch (Channel)
EricLew	0:80ee8f3b695e	3792	{
EricLew	0:80ee8f3b695e	3793	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	3794	{
EricLew	0:80ee8f3b695e	3795	if(sClearInputConfig->ClearInputState != RESET)
EricLew	0:80ee8f3b695e	3796	{
EricLew	0:80ee8f3b695e	3797	/* Enable the OCREF clear feature for Channel 1 */
EricLew	0:80ee8f3b695e	3798	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
EricLew	0:80ee8f3b695e	3799	}
EricLew	0:80ee8f3b695e	3800	else
EricLew	0:80ee8f3b695e	3801	{
EricLew	0:80ee8f3b695e	3802	/* Disable the OCREF clear feature for Channel 1 */
EricLew	0:80ee8f3b695e	3803	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
EricLew	0:80ee8f3b695e	3804	}
EricLew	0:80ee8f3b695e	3805	}
EricLew	0:80ee8f3b695e	3806	break;
EricLew	0:80ee8f3b695e	3807	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	3808	{
EricLew	0:80ee8f3b695e	3809	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3810	if(sClearInputConfig->ClearInputState != RESET)
EricLew	0:80ee8f3b695e	3811	{
EricLew	0:80ee8f3b695e	3812	/* Enable the OCREF clear feature for Channel 2 */
EricLew	0:80ee8f3b695e	3813	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
EricLew	0:80ee8f3b695e	3814	}
EricLew	0:80ee8f3b695e	3815	else
EricLew	0:80ee8f3b695e	3816	{
EricLew	0:80ee8f3b695e	3817	/* Disable the OCREF clear feature for Channel 2 */
EricLew	0:80ee8f3b695e	3818	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
EricLew	0:80ee8f3b695e	3819	}
EricLew	0:80ee8f3b695e	3820	}
EricLew	0:80ee8f3b695e	3821	break;
EricLew	0:80ee8f3b695e	3822	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	3823	{
EricLew	0:80ee8f3b695e	3824	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3825	if(sClearInputConfig->ClearInputState != RESET)
EricLew	0:80ee8f3b695e	3826	{
EricLew	0:80ee8f3b695e	3827	/* Enable the OCREF clear feature for Channel 3 */
EricLew	0:80ee8f3b695e	3828	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
EricLew	0:80ee8f3b695e	3829	}
EricLew	0:80ee8f3b695e	3830	else
EricLew	0:80ee8f3b695e	3831	{
EricLew	0:80ee8f3b695e	3832	/* Disable the OCREF clear feature for Channel 3 */
EricLew	0:80ee8f3b695e	3833	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
EricLew	0:80ee8f3b695e	3834	}
EricLew	0:80ee8f3b695e	3835	}
EricLew	0:80ee8f3b695e	3836	break;
EricLew	0:80ee8f3b695e	3837	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	3838	{
EricLew	0:80ee8f3b695e	3839	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3840	if(sClearInputConfig->ClearInputState != RESET)
EricLew	0:80ee8f3b695e	3841	{
EricLew	0:80ee8f3b695e	3842	/* Enable the OCREF clear feature for Channel 4 */
EricLew	0:80ee8f3b695e	3843	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
EricLew	0:80ee8f3b695e	3844	}
EricLew	0:80ee8f3b695e	3845	else
EricLew	0:80ee8f3b695e	3846	{
EricLew	0:80ee8f3b695e	3847	/* Disable the OCREF clear feature for Channel 4 */
EricLew	0:80ee8f3b695e	3848	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
EricLew	0:80ee8f3b695e	3849	}
EricLew	0:80ee8f3b695e	3850	}
EricLew	0:80ee8f3b695e	3851	break;
EricLew	0:80ee8f3b695e	3852	default:
EricLew	0:80ee8f3b695e	3853	break;
EricLew	0:80ee8f3b695e	3854	}
EricLew	0:80ee8f3b695e	3855
EricLew	0:80ee8f3b695e	3856	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	3857
EricLew	0:80ee8f3b695e	3858	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	3859
EricLew	0:80ee8f3b695e	3860	return HAL_OK;
EricLew	0:80ee8f3b695e	3861	}
EricLew	0:80ee8f3b695e	3862
EricLew	0:80ee8f3b695e	3863	/**
EricLew	0:80ee8f3b695e	3864	* @brief Configures the clock source to be used
EricLew	0:80ee8f3b695e	3865	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	3866	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
EricLew	0:80ee8f3b695e	3867	* contains the clock source information for the TIM peripheral.
EricLew	0:80ee8f3b695e	3868	* @retval HAL status
EricLew	0:80ee8f3b695e	3869	*/
EricLew	0:80ee8f3b695e	3870	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
EricLew	0:80ee8f3b695e	3871	{
EricLew	0:80ee8f3b695e	3872	uint32_t tmpsmcr = 0;
EricLew	0:80ee8f3b695e	3873
EricLew	0:80ee8f3b695e	3874	/* Process Locked */
EricLew	0:80ee8f3b695e	3875	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	3876
EricLew	0:80ee8f3b695e	3877	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	3878
EricLew	0:80ee8f3b695e	3879	/* Check the parameters */
EricLew	0:80ee8f3b695e	3880	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
EricLew	0:80ee8f3b695e	3881	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
EricLew	0:80ee8f3b695e	3882	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
EricLew	0:80ee8f3b695e	3883	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
EricLew	0:80ee8f3b695e	3884
EricLew	0:80ee8f3b695e	3885	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
EricLew	0:80ee8f3b695e	3886	tmpsmcr = htim->Instance->SMCR;
EricLew	0:80ee8f3b695e	3887	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
EricLew	0:80ee8f3b695e	3888	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
EricLew	0:80ee8f3b695e	3889	htim->Instance->SMCR = tmpsmcr;
EricLew	0:80ee8f3b695e	3890
EricLew	0:80ee8f3b695e	3891	switch (sClockSourceConfig->ClockSource)
EricLew	0:80ee8f3b695e	3892	{
EricLew	0:80ee8f3b695e	3893	case TIM_CLOCKSOURCE_INTERNAL:
EricLew	0:80ee8f3b695e	3894	{
EricLew	0:80ee8f3b695e	3895	assert_param(IS_TIM_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3896	/* Disable slave mode to clock the prescaler directly with the internal clock */
EricLew	0:80ee8f3b695e	3897	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
EricLew	0:80ee8f3b695e	3898	}
EricLew	0:80ee8f3b695e	3899	break;
EricLew	0:80ee8f3b695e	3900
EricLew	0:80ee8f3b695e	3901	case TIM_CLOCKSOURCE_ETRMODE1:
EricLew	0:80ee8f3b695e	3902	{
EricLew	0:80ee8f3b695e	3903	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
EricLew	0:80ee8f3b695e	3904	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3905
EricLew	0:80ee8f3b695e	3906	/* Configure the ETR Clock source */
EricLew	0:80ee8f3b695e	3907	TIM_ETR_SetConfig(htim->Instance,
EricLew	0:80ee8f3b695e	3908	sClockSourceConfig->ClockPrescaler,
EricLew	0:80ee8f3b695e	3909	sClockSourceConfig->ClockPolarity,
EricLew	0:80ee8f3b695e	3910	sClockSourceConfig->ClockFilter);
EricLew	0:80ee8f3b695e	3911	/* Get the TIMx SMCR register value */
EricLew	0:80ee8f3b695e	3912	tmpsmcr = htim->Instance->SMCR;
EricLew	0:80ee8f3b695e	3913	/* Reset the SMS and TS Bits */
EricLew	0:80ee8f3b695e	3914	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
EricLew	0:80ee8f3b695e	3915	/* Select the External clock mode1 and the ETRF trigger */
EricLew	0:80ee8f3b695e	3916	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
EricLew	0:80ee8f3b695e	3917	/* Write to TIMx SMCR */
EricLew	0:80ee8f3b695e	3918	htim->Instance->SMCR = tmpsmcr;
EricLew	0:80ee8f3b695e	3919	}
EricLew	0:80ee8f3b695e	3920	break;
EricLew	0:80ee8f3b695e	3921
EricLew	0:80ee8f3b695e	3922	case TIM_CLOCKSOURCE_ETRMODE2:
EricLew	0:80ee8f3b695e	3923	{
EricLew	0:80ee8f3b695e	3924	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
EricLew	0:80ee8f3b695e	3925	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3926
EricLew	0:80ee8f3b695e	3927	/* Configure the ETR Clock source */
EricLew	0:80ee8f3b695e	3928	TIM_ETR_SetConfig(htim->Instance,
EricLew	0:80ee8f3b695e	3929	sClockSourceConfig->ClockPrescaler,
EricLew	0:80ee8f3b695e	3930	sClockSourceConfig->ClockPolarity,
EricLew	0:80ee8f3b695e	3931	sClockSourceConfig->ClockFilter);
EricLew	0:80ee8f3b695e	3932	/* Enable the External clock mode2 */
EricLew	0:80ee8f3b695e	3933	htim->Instance->SMCR \|= TIM_SMCR_ECE;
EricLew	0:80ee8f3b695e	3934	}
EricLew	0:80ee8f3b695e	3935	break;
EricLew	0:80ee8f3b695e	3936
EricLew	0:80ee8f3b695e	3937	case TIM_CLOCKSOURCE_TI1:
EricLew	0:80ee8f3b695e	3938	{
EricLew	0:80ee8f3b695e	3939	/* Check whether or not the timer instance supports external clock mode 1 */
EricLew	0:80ee8f3b695e	3940	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3941
EricLew	0:80ee8f3b695e	3942	TIM_TI1_ConfigInputStage(htim->Instance,
EricLew	0:80ee8f3b695e	3943	sClockSourceConfig->ClockPolarity,
EricLew	0:80ee8f3b695e	3944	sClockSourceConfig->ClockFilter);
EricLew	0:80ee8f3b695e	3945	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
EricLew	0:80ee8f3b695e	3946	}
EricLew	0:80ee8f3b695e	3947	break;
EricLew	0:80ee8f3b695e	3948
EricLew	0:80ee8f3b695e	3949	case TIM_CLOCKSOURCE_TI2:
EricLew	0:80ee8f3b695e	3950	{
EricLew	0:80ee8f3b695e	3951	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
EricLew	0:80ee8f3b695e	3952	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3953
EricLew	0:80ee8f3b695e	3954	TIM_TI2_ConfigInputStage(htim->Instance,
EricLew	0:80ee8f3b695e	3955	sClockSourceConfig->ClockPolarity,
EricLew	0:80ee8f3b695e	3956	sClockSourceConfig->ClockFilter);
EricLew	0:80ee8f3b695e	3957	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
EricLew	0:80ee8f3b695e	3958	}
EricLew	0:80ee8f3b695e	3959	break;
EricLew	0:80ee8f3b695e	3960
EricLew	0:80ee8f3b695e	3961	case TIM_CLOCKSOURCE_TI1ED:
EricLew	0:80ee8f3b695e	3962	{
EricLew	0:80ee8f3b695e	3963	/* Check whether or not the timer instance supports external clock mode 1 */
EricLew	0:80ee8f3b695e	3964	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3965
EricLew	0:80ee8f3b695e	3966	TIM_TI1_ConfigInputStage(htim->Instance,
EricLew	0:80ee8f3b695e	3967	sClockSourceConfig->ClockPolarity,
EricLew	0:80ee8f3b695e	3968	sClockSourceConfig->ClockFilter);
EricLew	0:80ee8f3b695e	3969	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
EricLew	0:80ee8f3b695e	3970	}
EricLew	0:80ee8f3b695e	3971	break;
EricLew	0:80ee8f3b695e	3972
EricLew	0:80ee8f3b695e	3973	case TIM_CLOCKSOURCE_ITR0:
EricLew	0:80ee8f3b695e	3974	{
EricLew	0:80ee8f3b695e	3975	/* Check whether or not the timer instance supports internal trigger input */
EricLew	0:80ee8f3b695e	3976	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3977
EricLew	0:80ee8f3b695e	3978	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
EricLew	0:80ee8f3b695e	3979	}
EricLew	0:80ee8f3b695e	3980	break;
EricLew	0:80ee8f3b695e	3981
EricLew	0:80ee8f3b695e	3982	case TIM_CLOCKSOURCE_ITR1:
EricLew	0:80ee8f3b695e	3983	{
EricLew	0:80ee8f3b695e	3984	/* Check whether or not the timer instance supports internal trigger input */
EricLew	0:80ee8f3b695e	3985	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3986
EricLew	0:80ee8f3b695e	3987	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
EricLew	0:80ee8f3b695e	3988	}
EricLew	0:80ee8f3b695e	3989	break;
EricLew	0:80ee8f3b695e	3990
EricLew	0:80ee8f3b695e	3991	case TIM_CLOCKSOURCE_ITR2:
EricLew	0:80ee8f3b695e	3992	{
EricLew	0:80ee8f3b695e	3993	/* Check whether or not the timer instance supports internal trigger input */
EricLew	0:80ee8f3b695e	3994	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	3995
EricLew	0:80ee8f3b695e	3996	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
EricLew	0:80ee8f3b695e	3997	}
EricLew	0:80ee8f3b695e	3998	break;
EricLew	0:80ee8f3b695e	3999
EricLew	0:80ee8f3b695e	4000	case TIM_CLOCKSOURCE_ITR3:
EricLew	0:80ee8f3b695e	4001	{
EricLew	0:80ee8f3b695e	4002	/* Check whether or not the timer instance supports internal trigger input */
EricLew	0:80ee8f3b695e	4003	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4004
EricLew	0:80ee8f3b695e	4005	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
EricLew	0:80ee8f3b695e	4006	}
EricLew	0:80ee8f3b695e	4007	break;
EricLew	0:80ee8f3b695e	4008
EricLew	0:80ee8f3b695e	4009	default:
EricLew	0:80ee8f3b695e	4010	break;
EricLew	0:80ee8f3b695e	4011	}
EricLew	0:80ee8f3b695e	4012	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	4013
EricLew	0:80ee8f3b695e	4014	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	4015
EricLew	0:80ee8f3b695e	4016	return HAL_OK;
EricLew	0:80ee8f3b695e	4017	}
EricLew	0:80ee8f3b695e	4018
EricLew	0:80ee8f3b695e	4019	/**
EricLew	0:80ee8f3b695e	4020	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
EricLew	0:80ee8f3b695e	4021	* or a XOR combination between CH1_input, CH2_input & CH3_input
EricLew	0:80ee8f3b695e	4022	* @param htim: TIM handle.
EricLew	0:80ee8f3b695e	4023	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
EricLew	0:80ee8f3b695e	4024	* output of a XOR gate.
EricLew	0:80ee8f3b695e	4025	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4026	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
EricLew	0:80ee8f3b695e	4027	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
EricLew	0:80ee8f3b695e	4028	* pins are connected to the TI1 input (XOR combination)
EricLew	0:80ee8f3b695e	4029	* @retval HAL status
EricLew	0:80ee8f3b695e	4030	*/
EricLew	0:80ee8f3b695e	4031	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
EricLew	0:80ee8f3b695e	4032	{
EricLew	0:80ee8f3b695e	4033	uint32_t tmpcr2 = 0;
EricLew	0:80ee8f3b695e	4034
EricLew	0:80ee8f3b695e	4035	/* Check the parameters */
EricLew	0:80ee8f3b695e	4036	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4037	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
EricLew	0:80ee8f3b695e	4038
EricLew	0:80ee8f3b695e	4039	/* Get the TIMx CR2 register value */
EricLew	0:80ee8f3b695e	4040	tmpcr2 = htim->Instance->CR2;
EricLew	0:80ee8f3b695e	4041
EricLew	0:80ee8f3b695e	4042	/* Reset the TI1 selection */
EricLew	0:80ee8f3b695e	4043	tmpcr2 &= ~TIM_CR2_TI1S;
EricLew	0:80ee8f3b695e	4044
EricLew	0:80ee8f3b695e	4045	/* Set the TI1 selection */
EricLew	0:80ee8f3b695e	4046	tmpcr2 \|= TI1_Selection;
EricLew	0:80ee8f3b695e	4047
EricLew	0:80ee8f3b695e	4048	/* Write to TIMxCR2 */
EricLew	0:80ee8f3b695e	4049	htim->Instance->CR2 = tmpcr2;
EricLew	0:80ee8f3b695e	4050
EricLew	0:80ee8f3b695e	4051	return HAL_OK;
EricLew	0:80ee8f3b695e	4052	}
EricLew	0:80ee8f3b695e	4053
EricLew	0:80ee8f3b695e	4054	/**
EricLew	0:80ee8f3b695e	4055	* @brief Configures the TIM in Slave mode
EricLew	0:80ee8f3b695e	4056	* @param htim: TIM handle.
EricLew	0:80ee8f3b695e	4057	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
EricLew	0:80ee8f3b695e	4058	* contains the selected trigger (internal trigger input, filtered
EricLew	0:80ee8f3b695e	4059	* timer input or external trigger input) and the ) and the Slave
EricLew	0:80ee8f3b695e	4060	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
EricLew	0:80ee8f3b695e	4061	* @retval HAL status
EricLew	0:80ee8f3b695e	4062	*/
EricLew	0:80ee8f3b695e	4063	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
EricLew	0:80ee8f3b695e	4064	{
EricLew	0:80ee8f3b695e	4065	/* Check the parameters */
EricLew	0:80ee8f3b695e	4066	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4067	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
EricLew	0:80ee8f3b695e	4068	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
EricLew	0:80ee8f3b695e	4069
EricLew	0:80ee8f3b695e	4070	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	4071
EricLew	0:80ee8f3b695e	4072	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	4073
EricLew	0:80ee8f3b695e	4074	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
EricLew	0:80ee8f3b695e	4075
EricLew	0:80ee8f3b695e	4076	/* Disable Trigger Interrupt */
EricLew	0:80ee8f3b695e	4077	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
EricLew	0:80ee8f3b695e	4078
EricLew	0:80ee8f3b695e	4079	/* Disable Trigger DMA request */
EricLew	0:80ee8f3b695e	4080	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
EricLew	0:80ee8f3b695e	4081
EricLew	0:80ee8f3b695e	4082	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	4083
EricLew	0:80ee8f3b695e	4084	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	4085
EricLew	0:80ee8f3b695e	4086	return HAL_OK;
EricLew	0:80ee8f3b695e	4087	}
EricLew	0:80ee8f3b695e	4088
EricLew	0:80ee8f3b695e	4089	/**
EricLew	0:80ee8f3b695e	4090	* @brief Configures the TIM in Slave mode in interrupt mode
EricLew	0:80ee8f3b695e	4091	* @param htim: TIM handle.
EricLew	0:80ee8f3b695e	4092	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
EricLew	0:80ee8f3b695e	4093	* contains the selected trigger (internal trigger input, filtered
EricLew	0:80ee8f3b695e	4094	* timer input or external trigger input) and the ) and the Slave
EricLew	0:80ee8f3b695e	4095	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
EricLew	0:80ee8f3b695e	4096	* @retval HAL status
EricLew	0:80ee8f3b695e	4097	*/
EricLew	0:80ee8f3b695e	4098	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
EricLew	0:80ee8f3b695e	4099	TIM_SlaveConfigTypeDef * sSlaveConfig)
EricLew	0:80ee8f3b695e	4100	{
EricLew	0:80ee8f3b695e	4101	/* Check the parameters */
EricLew	0:80ee8f3b695e	4102	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4103	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
EricLew	0:80ee8f3b695e	4104	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
EricLew	0:80ee8f3b695e	4105
EricLew	0:80ee8f3b695e	4106	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	4107
EricLew	0:80ee8f3b695e	4108	htim->State = HAL_TIM_STATE_BUSY;
EricLew	0:80ee8f3b695e	4109
EricLew	0:80ee8f3b695e	4110	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
EricLew	0:80ee8f3b695e	4111
EricLew	0:80ee8f3b695e	4112	/* Enable Trigger Interrupt */
EricLew	0:80ee8f3b695e	4113	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
EricLew	0:80ee8f3b695e	4114
EricLew	0:80ee8f3b695e	4115	/* Disable Trigger DMA request */
EricLew	0:80ee8f3b695e	4116	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
EricLew	0:80ee8f3b695e	4117
EricLew	0:80ee8f3b695e	4118	htim->State = HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	4119
EricLew	0:80ee8f3b695e	4120	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	4121
EricLew	0:80ee8f3b695e	4122	return HAL_OK;
EricLew	0:80ee8f3b695e	4123	}
EricLew	0:80ee8f3b695e	4124
EricLew	0:80ee8f3b695e	4125	/**
EricLew	0:80ee8f3b695e	4126	* @brief Read the captured value from Capture Compare unit
EricLew	0:80ee8f3b695e	4127	* @param htim: TIM handle.
EricLew	0:80ee8f3b695e	4128	* @param Channel : TIM Channels to be enabled
EricLew	0:80ee8f3b695e	4129	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4130	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
EricLew	0:80ee8f3b695e	4131	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
EricLew	0:80ee8f3b695e	4132	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
EricLew	0:80ee8f3b695e	4133	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
EricLew	0:80ee8f3b695e	4134	* @retval Captured value
EricLew	0:80ee8f3b695e	4135	*/
EricLew	0:80ee8f3b695e	4136	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
EricLew	0:80ee8f3b695e	4137	{
EricLew	0:80ee8f3b695e	4138	uint32_t tmpreg = 0;
EricLew	0:80ee8f3b695e	4139
EricLew	0:80ee8f3b695e	4140	__HAL_LOCK(htim);
EricLew	0:80ee8f3b695e	4141
EricLew	0:80ee8f3b695e	4142	switch (Channel)
EricLew	0:80ee8f3b695e	4143	{
EricLew	0:80ee8f3b695e	4144	case TIM_CHANNEL_1:
EricLew	0:80ee8f3b695e	4145	{
EricLew	0:80ee8f3b695e	4146	/* Check the parameters */
EricLew	0:80ee8f3b695e	4147	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4148
EricLew	0:80ee8f3b695e	4149	/* Return the capture 1 value */
EricLew	0:80ee8f3b695e	4150	tmpreg = htim->Instance->CCR1;
EricLew	0:80ee8f3b695e	4151
EricLew	0:80ee8f3b695e	4152	break;
EricLew	0:80ee8f3b695e	4153	}
EricLew	0:80ee8f3b695e	4154	case TIM_CHANNEL_2:
EricLew	0:80ee8f3b695e	4155	{
EricLew	0:80ee8f3b695e	4156	/* Check the parameters */
EricLew	0:80ee8f3b695e	4157	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4158
EricLew	0:80ee8f3b695e	4159	/* Return the capture 2 value */
EricLew	0:80ee8f3b695e	4160	tmpreg = htim->Instance->CCR2;
EricLew	0:80ee8f3b695e	4161
EricLew	0:80ee8f3b695e	4162	break;
EricLew	0:80ee8f3b695e	4163	}
EricLew	0:80ee8f3b695e	4164
EricLew	0:80ee8f3b695e	4165	case TIM_CHANNEL_3:
EricLew	0:80ee8f3b695e	4166	{
EricLew	0:80ee8f3b695e	4167	/* Check the parameters */
EricLew	0:80ee8f3b695e	4168	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4169
EricLew	0:80ee8f3b695e	4170	/* Return the capture 3 value */
EricLew	0:80ee8f3b695e	4171	tmpreg = htim->Instance->CCR3;
EricLew	0:80ee8f3b695e	4172
EricLew	0:80ee8f3b695e	4173	break;
EricLew	0:80ee8f3b695e	4174	}
EricLew	0:80ee8f3b695e	4175
EricLew	0:80ee8f3b695e	4176	case TIM_CHANNEL_4:
EricLew	0:80ee8f3b695e	4177	{
EricLew	0:80ee8f3b695e	4178	/* Check the parameters */
EricLew	0:80ee8f3b695e	4179	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4180
EricLew	0:80ee8f3b695e	4181	/* Return the capture 4 value */
EricLew	0:80ee8f3b695e	4182	tmpreg = htim->Instance->CCR4;
EricLew	0:80ee8f3b695e	4183
EricLew	0:80ee8f3b695e	4184	break;
EricLew	0:80ee8f3b695e	4185	}
EricLew	0:80ee8f3b695e	4186
EricLew	0:80ee8f3b695e	4187	default:
EricLew	0:80ee8f3b695e	4188	break;
EricLew	0:80ee8f3b695e	4189	}
EricLew	0:80ee8f3b695e	4190
EricLew	0:80ee8f3b695e	4191	__HAL_UNLOCK(htim);
EricLew	0:80ee8f3b695e	4192	return tmpreg;
EricLew	0:80ee8f3b695e	4193	}
EricLew	0:80ee8f3b695e	4194
EricLew	0:80ee8f3b695e	4195	/**
EricLew	0:80ee8f3b695e	4196	* @}
EricLew	0:80ee8f3b695e	4197	*/
EricLew	0:80ee8f3b695e	4198
EricLew	0:80ee8f3b695e	4199	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
EricLew	0:80ee8f3b695e	4200	* @brief TIM Callbacks functions
EricLew	0:80ee8f3b695e	4201	*
EricLew	0:80ee8f3b695e	4202	@verbatim
EricLew	0:80ee8f3b695e	4203	==============================================================================
EricLew	0:80ee8f3b695e	4204	##### TIM Callbacks functions #####
EricLew	0:80ee8f3b695e	4205	==============================================================================
EricLew	0:80ee8f3b695e	4206	[..]
EricLew	0:80ee8f3b695e	4207	This section provides TIM callback functions:
EricLew	0:80ee8f3b695e	4208	(+) Timer Period elapsed callback
EricLew	0:80ee8f3b695e	4209	(+) Timer Output Compare callback
EricLew	0:80ee8f3b695e	4210	(+) Timer Input capture callback
EricLew	0:80ee8f3b695e	4211	(+) Timer Trigger callback
EricLew	0:80ee8f3b695e	4212	(+) Timer Error callback
EricLew	0:80ee8f3b695e	4213
EricLew	0:80ee8f3b695e	4214	@endverbatim
EricLew	0:80ee8f3b695e	4215	* @{
EricLew	0:80ee8f3b695e	4216	*/
EricLew	0:80ee8f3b695e	4217
EricLew	0:80ee8f3b695e	4218	/**
EricLew	0:80ee8f3b695e	4219	* @brief Period elapsed callback in non-blocking mode
EricLew	0:80ee8f3b695e	4220	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	4221	* @retval None
EricLew	0:80ee8f3b695e	4222	*/
EricLew	0:80ee8f3b695e	4223	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4224	{
EricLew	0:80ee8f3b695e	4225	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	4226	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
EricLew	0:80ee8f3b695e	4227	*/
EricLew	0:80ee8f3b695e	4228
EricLew	0:80ee8f3b695e	4229	}
EricLew	0:80ee8f3b695e	4230	/**
EricLew	0:80ee8f3b695e	4231	* @brief Output Compare callback in non-blocking mode
EricLew	0:80ee8f3b695e	4232	* @param htim : TIM OC handle
EricLew	0:80ee8f3b695e	4233	* @retval None
EricLew	0:80ee8f3b695e	4234	*/
EricLew	0:80ee8f3b695e	4235	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4236	{
EricLew	0:80ee8f3b695e	4237	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	4238	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
EricLew	0:80ee8f3b695e	4239	*/
EricLew	0:80ee8f3b695e	4240	}
EricLew	0:80ee8f3b695e	4241	/**
EricLew	0:80ee8f3b695e	4242	* @brief Input Capture callback in non-blocking mode
EricLew	0:80ee8f3b695e	4243	* @param htim : TIM IC handle
EricLew	0:80ee8f3b695e	4244	* @retval None
EricLew	0:80ee8f3b695e	4245	*/
EricLew	0:80ee8f3b695e	4246	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4247	{
EricLew	0:80ee8f3b695e	4248	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	4249	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
EricLew	0:80ee8f3b695e	4250	*/
EricLew	0:80ee8f3b695e	4251	}
EricLew	0:80ee8f3b695e	4252
EricLew	0:80ee8f3b695e	4253	/**
EricLew	0:80ee8f3b695e	4254	* @brief PWM Pulse finished callback in non-blocking mode
EricLew	0:80ee8f3b695e	4255	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	4256	* @retval None
EricLew	0:80ee8f3b695e	4257	*/
EricLew	0:80ee8f3b695e	4258	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4259	{
EricLew	0:80ee8f3b695e	4260	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	4261	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
EricLew	0:80ee8f3b695e	4262	*/
EricLew	0:80ee8f3b695e	4263	}
EricLew	0:80ee8f3b695e	4264
EricLew	0:80ee8f3b695e	4265	/**
EricLew	0:80ee8f3b695e	4266	* @brief Hall Trigger detection callback in non-blocking mode
EricLew	0:80ee8f3b695e	4267	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	4268	* @retval None
EricLew	0:80ee8f3b695e	4269	*/
EricLew	0:80ee8f3b695e	4270	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4271	{
EricLew	0:80ee8f3b695e	4272	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	4273	the HAL_TIM_TriggerCallback could be implemented in the user file
EricLew	0:80ee8f3b695e	4274	*/
EricLew	0:80ee8f3b695e	4275	}
EricLew	0:80ee8f3b695e	4276
EricLew	0:80ee8f3b695e	4277	/**
EricLew	0:80ee8f3b695e	4278	* @brief Timer error callback in non-blocking mode
EricLew	0:80ee8f3b695e	4279	* @param htim : TIM handle
EricLew	0:80ee8f3b695e	4280	* @retval None
EricLew	0:80ee8f3b695e	4281	*/
EricLew	0:80ee8f3b695e	4282	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4283	{
EricLew	0:80ee8f3b695e	4284	/* NOTE : This function should not be modified, when the callback is needed,
EricLew	0:80ee8f3b695e	4285	the HAL_TIM_ErrorCallback could be implemented in the user file
EricLew	0:80ee8f3b695e	4286	*/
EricLew	0:80ee8f3b695e	4287	}
EricLew	0:80ee8f3b695e	4288
EricLew	0:80ee8f3b695e	4289	/**
EricLew	0:80ee8f3b695e	4290	* @}
EricLew	0:80ee8f3b695e	4291	*/
EricLew	0:80ee8f3b695e	4292
EricLew	0:80ee8f3b695e	4293	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
EricLew	0:80ee8f3b695e	4294	* @brief Peripheral State functions
EricLew	0:80ee8f3b695e	4295	*
EricLew	0:80ee8f3b695e	4296	@verbatim
EricLew	0:80ee8f3b695e	4297	==============================================================================
EricLew	0:80ee8f3b695e	4298	##### Peripheral State functions #####
EricLew	0:80ee8f3b695e	4299	==============================================================================
EricLew	0:80ee8f3b695e	4300	[..]
EricLew	0:80ee8f3b695e	4301	This subsection permits to get in run-time the status of the peripheral
EricLew	0:80ee8f3b695e	4302	and the data flow.
EricLew	0:80ee8f3b695e	4303
EricLew	0:80ee8f3b695e	4304	@endverbatim
EricLew	0:80ee8f3b695e	4305	* @{
EricLew	0:80ee8f3b695e	4306	*/
EricLew	0:80ee8f3b695e	4307
EricLew	0:80ee8f3b695e	4308	/**
EricLew	0:80ee8f3b695e	4309	* @brief Return the TIM Base handle state.
EricLew	0:80ee8f3b695e	4310	* @param htim: TIM Base handle
EricLew	0:80ee8f3b695e	4311	* @retval HAL state
EricLew	0:80ee8f3b695e	4312	*/
EricLew	0:80ee8f3b695e	4313	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4314	{
EricLew	0:80ee8f3b695e	4315	return htim->State;
EricLew	0:80ee8f3b695e	4316	}
EricLew	0:80ee8f3b695e	4317
EricLew	0:80ee8f3b695e	4318	/**
EricLew	0:80ee8f3b695e	4319	* @brief Return the TIM OC handle state.
EricLew	0:80ee8f3b695e	4320	* @param htim: TIM Ouput Compare handle
EricLew	0:80ee8f3b695e	4321	* @retval HAL state
EricLew	0:80ee8f3b695e	4322	*/
EricLew	0:80ee8f3b695e	4323	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4324	{
EricLew	0:80ee8f3b695e	4325	return htim->State;
EricLew	0:80ee8f3b695e	4326	}
EricLew	0:80ee8f3b695e	4327
EricLew	0:80ee8f3b695e	4328	/**
EricLew	0:80ee8f3b695e	4329	* @brief Return the TIM PWM handle state.
EricLew	0:80ee8f3b695e	4330	* @param htim: TIM handle
EricLew	0:80ee8f3b695e	4331	* @retval HAL state
EricLew	0:80ee8f3b695e	4332	*/
EricLew	0:80ee8f3b695e	4333	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4334	{
EricLew	0:80ee8f3b695e	4335	return htim->State;
EricLew	0:80ee8f3b695e	4336	}
EricLew	0:80ee8f3b695e	4337
EricLew	0:80ee8f3b695e	4338	/**
EricLew	0:80ee8f3b695e	4339	* @brief Return the TIM Input Capture handle state.
EricLew	0:80ee8f3b695e	4340	* @param htim: TIM IC handle
EricLew	0:80ee8f3b695e	4341	* @retval HAL state
EricLew	0:80ee8f3b695e	4342	*/
EricLew	0:80ee8f3b695e	4343	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4344	{
EricLew	0:80ee8f3b695e	4345	return htim->State;
EricLew	0:80ee8f3b695e	4346	}
EricLew	0:80ee8f3b695e	4347
EricLew	0:80ee8f3b695e	4348	/**
EricLew	0:80ee8f3b695e	4349	* @brief Return the TIM One Pulse Mode handle state.
EricLew	0:80ee8f3b695e	4350	* @param htim: TIM OPM handle
EricLew	0:80ee8f3b695e	4351	* @retval HAL state
EricLew	0:80ee8f3b695e	4352	*/
EricLew	0:80ee8f3b695e	4353	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4354	{
EricLew	0:80ee8f3b695e	4355	return htim->State;
EricLew	0:80ee8f3b695e	4356	}
EricLew	0:80ee8f3b695e	4357
EricLew	0:80ee8f3b695e	4358	/**
EricLew	0:80ee8f3b695e	4359	* @brief Return the TIM Encoder Mode handle state.
EricLew	0:80ee8f3b695e	4360	* @param htim: TIM Encoder handle
EricLew	0:80ee8f3b695e	4361	* @retval HAL state
EricLew	0:80ee8f3b695e	4362	*/
EricLew	0:80ee8f3b695e	4363	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
EricLew	0:80ee8f3b695e	4364	{
EricLew	0:80ee8f3b695e	4365	return htim->State;
EricLew	0:80ee8f3b695e	4366	}
EricLew	0:80ee8f3b695e	4367
EricLew	0:80ee8f3b695e	4368	/**
EricLew	0:80ee8f3b695e	4369	* @}
EricLew	0:80ee8f3b695e	4370	*/
EricLew	0:80ee8f3b695e	4371
EricLew	0:80ee8f3b695e	4372	/**
EricLew	0:80ee8f3b695e	4373	* @brief TIM DMA error callback
EricLew	0:80ee8f3b695e	4374	* @param hdma : pointer to DMA handle.
EricLew	0:80ee8f3b695e	4375	* @retval None
EricLew	0:80ee8f3b695e	4376	*/
EricLew	0:80ee8f3b695e	4377	void TIM_DMAError(DMA_HandleTypeDef *hdma)
EricLew	0:80ee8f3b695e	4378	{
EricLew	0:80ee8f3b695e	4379	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
EricLew	0:80ee8f3b695e	4380
EricLew	0:80ee8f3b695e	4381	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	4382
EricLew	0:80ee8f3b695e	4383	HAL_TIM_ErrorCallback(htim);
EricLew	0:80ee8f3b695e	4384	}
EricLew	0:80ee8f3b695e	4385
EricLew	0:80ee8f3b695e	4386	/**
EricLew	0:80ee8f3b695e	4387	* @brief TIM DMA Delay Pulse complete callback.
EricLew	0:80ee8f3b695e	4388	* @param hdma : pointer to DMA handle.
EricLew	0:80ee8f3b695e	4389	* @retval None
EricLew	0:80ee8f3b695e	4390	*/
EricLew	0:80ee8f3b695e	4391	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
EricLew	0:80ee8f3b695e	4392	{
EricLew	0:80ee8f3b695e	4393	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
EricLew	0:80ee8f3b695e	4394
EricLew	0:80ee8f3b695e	4395	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	4396
EricLew	0:80ee8f3b695e	4397	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
EricLew	0:80ee8f3b695e	4398	{
EricLew	0:80ee8f3b695e	4399	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
EricLew	0:80ee8f3b695e	4400	}
EricLew	0:80ee8f3b695e	4401	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
EricLew	0:80ee8f3b695e	4402	{
EricLew	0:80ee8f3b695e	4403	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
EricLew	0:80ee8f3b695e	4404	}
EricLew	0:80ee8f3b695e	4405	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
EricLew	0:80ee8f3b695e	4406	{
EricLew	0:80ee8f3b695e	4407	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
EricLew	0:80ee8f3b695e	4408	}
EricLew	0:80ee8f3b695e	4409	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
EricLew	0:80ee8f3b695e	4410	{
EricLew	0:80ee8f3b695e	4411	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
EricLew	0:80ee8f3b695e	4412	}
EricLew	0:80ee8f3b695e	4413
EricLew	0:80ee8f3b695e	4414	HAL_TIM_PWM_PulseFinishedCallback(htim);
EricLew	0:80ee8f3b695e	4415
EricLew	0:80ee8f3b695e	4416	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
EricLew	0:80ee8f3b695e	4417	}
EricLew	0:80ee8f3b695e	4418	/**
EricLew	0:80ee8f3b695e	4419	* @brief TIM DMA Capture complete callback.
EricLew	0:80ee8f3b695e	4420	* @param hdma : pointer to DMA handle.
EricLew	0:80ee8f3b695e	4421	* @retval None
EricLew	0:80ee8f3b695e	4422	*/
EricLew	0:80ee8f3b695e	4423	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
EricLew	0:80ee8f3b695e	4424	{
EricLew	0:80ee8f3b695e	4425	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
EricLew	0:80ee8f3b695e	4426
EricLew	0:80ee8f3b695e	4427	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	4428
EricLew	0:80ee8f3b695e	4429	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
EricLew	0:80ee8f3b695e	4430	{
EricLew	0:80ee8f3b695e	4431	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
EricLew	0:80ee8f3b695e	4432	}
EricLew	0:80ee8f3b695e	4433	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
EricLew	0:80ee8f3b695e	4434	{
EricLew	0:80ee8f3b695e	4435	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
EricLew	0:80ee8f3b695e	4436	}
EricLew	0:80ee8f3b695e	4437	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
EricLew	0:80ee8f3b695e	4438	{
EricLew	0:80ee8f3b695e	4439	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
EricLew	0:80ee8f3b695e	4440	}
EricLew	0:80ee8f3b695e	4441	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
EricLew	0:80ee8f3b695e	4442	{
EricLew	0:80ee8f3b695e	4443	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
EricLew	0:80ee8f3b695e	4444	}
EricLew	0:80ee8f3b695e	4445
EricLew	0:80ee8f3b695e	4446	HAL_TIM_IC_CaptureCallback(htim);
EricLew	0:80ee8f3b695e	4447
EricLew	0:80ee8f3b695e	4448	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
EricLew	0:80ee8f3b695e	4449	}
EricLew	0:80ee8f3b695e	4450
EricLew	0:80ee8f3b695e	4451	/**
EricLew	0:80ee8f3b695e	4452	* @brief TIM DMA Period Elapse complete callback.
EricLew	0:80ee8f3b695e	4453	* @param hdma : pointer to DMA handle.
EricLew	0:80ee8f3b695e	4454	* @retval None
EricLew	0:80ee8f3b695e	4455	*/
EricLew	0:80ee8f3b695e	4456	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
EricLew	0:80ee8f3b695e	4457	{
EricLew	0:80ee8f3b695e	4458	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
EricLew	0:80ee8f3b695e	4459
EricLew	0:80ee8f3b695e	4460	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	4461
EricLew	0:80ee8f3b695e	4462	HAL_TIM_PeriodElapsedCallback(htim);
EricLew	0:80ee8f3b695e	4463	}
EricLew	0:80ee8f3b695e	4464
EricLew	0:80ee8f3b695e	4465	/**
EricLew	0:80ee8f3b695e	4466	* @brief TIM DMA Trigger callback.
EricLew	0:80ee8f3b695e	4467	* @param hdma : pointer to DMA handle.
EricLew	0:80ee8f3b695e	4468	* @retval None
EricLew	0:80ee8f3b695e	4469	*/
EricLew	0:80ee8f3b695e	4470	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
EricLew	0:80ee8f3b695e	4471	{
EricLew	0:80ee8f3b695e	4472	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
EricLew	0:80ee8f3b695e	4473
EricLew	0:80ee8f3b695e	4474	htim->State= HAL_TIM_STATE_READY;
EricLew	0:80ee8f3b695e	4475
EricLew	0:80ee8f3b695e	4476	HAL_TIM_TriggerCallback(htim);
EricLew	0:80ee8f3b695e	4477	}
EricLew	0:80ee8f3b695e	4478
EricLew	0:80ee8f3b695e	4479	/**
EricLew	0:80ee8f3b695e	4480	* @brief Time Base configuration
EricLew	0:80ee8f3b695e	4481	* @param TIMx: TIM peripheral
EricLew	0:80ee8f3b695e	4482	* @param Structure: TIM Base configuration structure
EricLew	0:80ee8f3b695e	4483	* @retval None
EricLew	0:80ee8f3b695e	4484	*/
EricLew	0:80ee8f3b695e	4485	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
EricLew	0:80ee8f3b695e	4486	{
EricLew	0:80ee8f3b695e	4487	uint32_t tmpcr1 = 0;
EricLew	0:80ee8f3b695e	4488	tmpcr1 = TIMx->CR1;
EricLew	0:80ee8f3b695e	4489
EricLew	0:80ee8f3b695e	4490	/* Set TIM Time Base Unit parameters ---------------------------------------*/
EricLew	0:80ee8f3b695e	4491	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
EricLew	0:80ee8f3b695e	4492	{
EricLew	0:80ee8f3b695e	4493	/* Select the Counter Mode */
EricLew	0:80ee8f3b695e	4494	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
EricLew	0:80ee8f3b695e	4495	tmpcr1 \|= Structure->CounterMode;
EricLew	0:80ee8f3b695e	4496	}
EricLew	0:80ee8f3b695e	4497
EricLew	0:80ee8f3b695e	4498	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
EricLew	0:80ee8f3b695e	4499	{
EricLew	0:80ee8f3b695e	4500	/* Set the clock division */
EricLew	0:80ee8f3b695e	4501	tmpcr1 &= ~TIM_CR1_CKD;
EricLew	0:80ee8f3b695e	4502	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
EricLew	0:80ee8f3b695e	4503	}
EricLew	0:80ee8f3b695e	4504
EricLew	0:80ee8f3b695e	4505	TIMx->CR1 = tmpcr1;
EricLew	0:80ee8f3b695e	4506
EricLew	0:80ee8f3b695e	4507	/* Set the Autoreload value */
EricLew	0:80ee8f3b695e	4508	TIMx->ARR = (uint32_t)Structure->Period ;
EricLew	0:80ee8f3b695e	4509
EricLew	0:80ee8f3b695e	4510	/* Set the Prescaler value */
EricLew	0:80ee8f3b695e	4511	TIMx->PSC = (uint32_t)Structure->Prescaler;
EricLew	0:80ee8f3b695e	4512
EricLew	0:80ee8f3b695e	4513	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
EricLew	0:80ee8f3b695e	4514	{
EricLew	0:80ee8f3b695e	4515	/* Set the Repetition Counter value */
EricLew	0:80ee8f3b695e	4516	TIMx->RCR = Structure->RepetitionCounter;
EricLew	0:80ee8f3b695e	4517	}
EricLew	0:80ee8f3b695e	4518
EricLew	0:80ee8f3b695e	4519	/* Generate an update event to reload the Prescaler
EricLew	0:80ee8f3b695e	4520	and the repetition counter(only for TIM1 and TIM8) value immediately */
EricLew	0:80ee8f3b695e	4521	TIMx->EGR = TIM_EGR_UG;
EricLew	0:80ee8f3b695e	4522	}
EricLew	0:80ee8f3b695e	4523
EricLew	0:80ee8f3b695e	4524	/**
EricLew	0:80ee8f3b695e	4525	* @brief Time Ouput Compare 1 configuration
EricLew	0:80ee8f3b695e	4526	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	4527	* @param OC_Config: The ouput configuration structure
EricLew	0:80ee8f3b695e	4528	* @retval None
EricLew	0:80ee8f3b695e	4529	*/
EricLew	0:80ee8f3b695e	4530	void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
EricLew	0:80ee8f3b695e	4531	{
EricLew	0:80ee8f3b695e	4532	uint32_t tmpccmrx = 0;
EricLew	0:80ee8f3b695e	4533	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	4534	uint32_t tmpcr2 = 0;
EricLew	0:80ee8f3b695e	4535
EricLew	0:80ee8f3b695e	4536	/* Disable the Channel 1: Reset the CC1E Bit */
EricLew	0:80ee8f3b695e	4537	TIMx->CCER &= ~TIM_CCER_CC1E;
EricLew	0:80ee8f3b695e	4538
EricLew	0:80ee8f3b695e	4539	/* Get the TIMx CCER register value */
EricLew	0:80ee8f3b695e	4540	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	4541	/* Get the TIMx CR2 register value */
EricLew	0:80ee8f3b695e	4542	tmpcr2 = TIMx->CR2;
EricLew	0:80ee8f3b695e	4543
EricLew	0:80ee8f3b695e	4544	/* Get the TIMx CCMR1 register value */
EricLew	0:80ee8f3b695e	4545	tmpccmrx = TIMx->CCMR1;
EricLew	0:80ee8f3b695e	4546
EricLew	0:80ee8f3b695e	4547	/* Reset the Output Compare Mode Bits */
EricLew	0:80ee8f3b695e	4548	tmpccmrx &= ~TIM_CCMR1_OC1M;
EricLew	0:80ee8f3b695e	4549	tmpccmrx &= ~TIM_CCMR1_CC1S;
EricLew	0:80ee8f3b695e	4550	/* Select the Output Compare Mode */
EricLew	0:80ee8f3b695e	4551	tmpccmrx \|= OC_Config->OCMode;
EricLew	0:80ee8f3b695e	4552
EricLew	0:80ee8f3b695e	4553	/* Reset the Output Polarity level */
EricLew	0:80ee8f3b695e	4554	tmpccer &= ~TIM_CCER_CC1P;
EricLew	0:80ee8f3b695e	4555	/* Set the Output Compare Polarity */
EricLew	0:80ee8f3b695e	4556	tmpccer \|= OC_Config->OCPolarity;
EricLew	0:80ee8f3b695e	4557
EricLew	0:80ee8f3b695e	4558	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
EricLew	0:80ee8f3b695e	4559	{
EricLew	0:80ee8f3b695e	4560	/* Check parameters */
EricLew	0:80ee8f3b695e	4561	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
EricLew	0:80ee8f3b695e	4562
EricLew	0:80ee8f3b695e	4563	/* Reset the Output N Polarity level */
EricLew	0:80ee8f3b695e	4564	tmpccer &= ~TIM_CCER_CC1NP;
EricLew	0:80ee8f3b695e	4565	/* Set the Output N Polarity */
EricLew	0:80ee8f3b695e	4566	tmpccer \|= OC_Config->OCNPolarity;
EricLew	0:80ee8f3b695e	4567	/* Reset the Output N State */
EricLew	0:80ee8f3b695e	4568	tmpccer &= ~TIM_CCER_CC1NE;
EricLew	0:80ee8f3b695e	4569	}
EricLew	0:80ee8f3b695e	4570
EricLew	0:80ee8f3b695e	4571	if(IS_TIM_BREAK_INSTANCE(TIMx))
EricLew	0:80ee8f3b695e	4572	{
EricLew	0:80ee8f3b695e	4573	/* Check parameters */
EricLew	0:80ee8f3b695e	4574	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
EricLew	0:80ee8f3b695e	4575	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
EricLew	0:80ee8f3b695e	4576
EricLew	0:80ee8f3b695e	4577	/* Reset the Output Compare and Output Compare N IDLE State */
EricLew	0:80ee8f3b695e	4578	tmpcr2 &= ~TIM_CR2_OIS1;
EricLew	0:80ee8f3b695e	4579	tmpcr2 &= ~TIM_CR2_OIS1N;
EricLew	0:80ee8f3b695e	4580	/* Set the Output Idle state */
EricLew	0:80ee8f3b695e	4581	tmpcr2 \|= OC_Config->OCIdleState;
EricLew	0:80ee8f3b695e	4582	/* Set the Output N Idle state */
EricLew	0:80ee8f3b695e	4583	tmpcr2 \|= OC_Config->OCNIdleState;
EricLew	0:80ee8f3b695e	4584	}
EricLew	0:80ee8f3b695e	4585	/* Write to TIMx CR2 */
EricLew	0:80ee8f3b695e	4586	TIMx->CR2 = tmpcr2;
EricLew	0:80ee8f3b695e	4587
EricLew	0:80ee8f3b695e	4588	/* Write to TIMx CCMR1 */
EricLew	0:80ee8f3b695e	4589	TIMx->CCMR1 = tmpccmrx;
EricLew	0:80ee8f3b695e	4590
EricLew	0:80ee8f3b695e	4591	/* Set the Capture Compare Register value */
EricLew	0:80ee8f3b695e	4592	TIMx->CCR1 = OC_Config->Pulse;
EricLew	0:80ee8f3b695e	4593
EricLew	0:80ee8f3b695e	4594	/* Write to TIMx CCER */
EricLew	0:80ee8f3b695e	4595	TIMx->CCER = tmpccer;
EricLew	0:80ee8f3b695e	4596	}
EricLew	0:80ee8f3b695e	4597
EricLew	0:80ee8f3b695e	4598	/**
EricLew	0:80ee8f3b695e	4599	* @brief Time Ouput Compare 2 configuration
EricLew	0:80ee8f3b695e	4600	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	4601	* @param OC_Config: The ouput configuration structure
EricLew	0:80ee8f3b695e	4602	* @retval None
EricLew	0:80ee8f3b695e	4603	*/
EricLew	0:80ee8f3b695e	4604	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
EricLew	0:80ee8f3b695e	4605	{
EricLew	0:80ee8f3b695e	4606	uint32_t tmpccmrx = 0;
EricLew	0:80ee8f3b695e	4607	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	4608	uint32_t tmpcr2 = 0;
EricLew	0:80ee8f3b695e	4609
EricLew	0:80ee8f3b695e	4610	/* Disable the Channel 2: Reset the CC2E Bit */
EricLew	0:80ee8f3b695e	4611	TIMx->CCER &= ~TIM_CCER_CC2E;
EricLew	0:80ee8f3b695e	4612
EricLew	0:80ee8f3b695e	4613	/* Get the TIMx CCER register value */
EricLew	0:80ee8f3b695e	4614	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	4615	/* Get the TIMx CR2 register value */
EricLew	0:80ee8f3b695e	4616	tmpcr2 = TIMx->CR2;
EricLew	0:80ee8f3b695e	4617
EricLew	0:80ee8f3b695e	4618	/* Get the TIMx CCMR1 register value */
EricLew	0:80ee8f3b695e	4619	tmpccmrx = TIMx->CCMR1;
EricLew	0:80ee8f3b695e	4620
EricLew	0:80ee8f3b695e	4621	/* Reset the Output Compare mode and Capture/Compare selection Bits */
EricLew	0:80ee8f3b695e	4622	tmpccmrx &= ~TIM_CCMR1_OC2M;
EricLew	0:80ee8f3b695e	4623	tmpccmrx &= ~TIM_CCMR1_CC2S;
EricLew	0:80ee8f3b695e	4624
EricLew	0:80ee8f3b695e	4625	/* Select the Output Compare Mode */
EricLew	0:80ee8f3b695e	4626	tmpccmrx \|= (OC_Config->OCMode << 8);
EricLew	0:80ee8f3b695e	4627
EricLew	0:80ee8f3b695e	4628	/* Reset the Output Polarity level */
EricLew	0:80ee8f3b695e	4629	tmpccer &= ~TIM_CCER_CC2P;
EricLew	0:80ee8f3b695e	4630	/* Set the Output Compare Polarity */
EricLew	0:80ee8f3b695e	4631	tmpccer \|= (OC_Config->OCPolarity << 4);
EricLew	0:80ee8f3b695e	4632
EricLew	0:80ee8f3b695e	4633	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
EricLew	0:80ee8f3b695e	4634	{
EricLew	0:80ee8f3b695e	4635	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
EricLew	0:80ee8f3b695e	4636	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
EricLew	0:80ee8f3b695e	4637	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
EricLew	0:80ee8f3b695e	4638
EricLew	0:80ee8f3b695e	4639	/* Reset the Output N Polarity level */
EricLew	0:80ee8f3b695e	4640	tmpccer &= ~TIM_CCER_CC2NP;
EricLew	0:80ee8f3b695e	4641	/* Set the Output N Polarity */
EricLew	0:80ee8f3b695e	4642	tmpccer \|= (OC_Config->OCNPolarity << 4);
EricLew	0:80ee8f3b695e	4643	/* Reset the Output N State */
EricLew	0:80ee8f3b695e	4644	tmpccer &= ~TIM_CCER_CC2NE;
EricLew	0:80ee8f3b695e	4645
EricLew	0:80ee8f3b695e	4646	}
EricLew	0:80ee8f3b695e	4647
EricLew	0:80ee8f3b695e	4648	if(IS_TIM_BREAK_INSTANCE(TIMx))
EricLew	0:80ee8f3b695e	4649	{
EricLew	0:80ee8f3b695e	4650	/* Check parameters */
EricLew	0:80ee8f3b695e	4651	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
EricLew	0:80ee8f3b695e	4652	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
EricLew	0:80ee8f3b695e	4653
EricLew	0:80ee8f3b695e	4654	/* Reset the Output Compare and Output Compare N IDLE State */
EricLew	0:80ee8f3b695e	4655	tmpcr2 &= ~TIM_CR2_OIS2;
EricLew	0:80ee8f3b695e	4656	tmpcr2 &= ~TIM_CR2_OIS2N;
EricLew	0:80ee8f3b695e	4657	/* Set the Output Idle state */
EricLew	0:80ee8f3b695e	4658	tmpcr2 \|= (OC_Config->OCIdleState << 2);
EricLew	0:80ee8f3b695e	4659	/* Set the Output N Idle state */
EricLew	0:80ee8f3b695e	4660	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
EricLew	0:80ee8f3b695e	4661	}
EricLew	0:80ee8f3b695e	4662
EricLew	0:80ee8f3b695e	4663	/* Write to TIMx CR2 */
EricLew	0:80ee8f3b695e	4664	TIMx->CR2 = tmpcr2;
EricLew	0:80ee8f3b695e	4665
EricLew	0:80ee8f3b695e	4666	/* Write to TIMx CCMR1 */
EricLew	0:80ee8f3b695e	4667	TIMx->CCMR1 = tmpccmrx;
EricLew	0:80ee8f3b695e	4668
EricLew	0:80ee8f3b695e	4669	/* Set the Capture Compare Register value */
EricLew	0:80ee8f3b695e	4670	TIMx->CCR2 = OC_Config->Pulse;
EricLew	0:80ee8f3b695e	4671
EricLew	0:80ee8f3b695e	4672	/* Write to TIMx CCER */
EricLew	0:80ee8f3b695e	4673	TIMx->CCER = tmpccer;
EricLew	0:80ee8f3b695e	4674	}
EricLew	0:80ee8f3b695e	4675
EricLew	0:80ee8f3b695e	4676	/**
EricLew	0:80ee8f3b695e	4677	* @brief Time Ouput Compare 3 configuration
EricLew	0:80ee8f3b695e	4678	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	4679	* @param OC_Config: The ouput configuration structure
EricLew	0:80ee8f3b695e	4680	* @retval None
EricLew	0:80ee8f3b695e	4681	*/
EricLew	0:80ee8f3b695e	4682	void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
EricLew	0:80ee8f3b695e	4683	{
EricLew	0:80ee8f3b695e	4684	uint32_t tmpccmrx = 0;
EricLew	0:80ee8f3b695e	4685	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	4686	uint32_t tmpcr2 = 0;
EricLew	0:80ee8f3b695e	4687
EricLew	0:80ee8f3b695e	4688	/* Disable the Channel 3: Reset the CC2E Bit */
EricLew	0:80ee8f3b695e	4689	TIMx->CCER &= ~TIM_CCER_CC3E;
EricLew	0:80ee8f3b695e	4690
EricLew	0:80ee8f3b695e	4691	/* Get the TIMx CCER register value */
EricLew	0:80ee8f3b695e	4692	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	4693	/* Get the TIMx CR2 register value */
EricLew	0:80ee8f3b695e	4694	tmpcr2 = TIMx->CR2;
EricLew	0:80ee8f3b695e	4695
EricLew	0:80ee8f3b695e	4696	/* Get the TIMx CCMR2 register value */
EricLew	0:80ee8f3b695e	4697	tmpccmrx = TIMx->CCMR2;
EricLew	0:80ee8f3b695e	4698
EricLew	0:80ee8f3b695e	4699	/* Reset the Output Compare mode and Capture/Compare selection Bits */
EricLew	0:80ee8f3b695e	4700	tmpccmrx &= ~TIM_CCMR2_OC3M;
EricLew	0:80ee8f3b695e	4701	tmpccmrx &= ~TIM_CCMR2_CC3S;
EricLew	0:80ee8f3b695e	4702	/* Select the Output Compare Mode */
EricLew	0:80ee8f3b695e	4703	tmpccmrx \|= OC_Config->OCMode;
EricLew	0:80ee8f3b695e	4704
EricLew	0:80ee8f3b695e	4705	/* Reset the Output Polarity level */
EricLew	0:80ee8f3b695e	4706	tmpccer &= ~TIM_CCER_CC3P;
EricLew	0:80ee8f3b695e	4707	/* Set the Output Compare Polarity */
EricLew	0:80ee8f3b695e	4708	tmpccer \|= (OC_Config->OCPolarity << 8);
EricLew	0:80ee8f3b695e	4709
EricLew	0:80ee8f3b695e	4710	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
EricLew	0:80ee8f3b695e	4711	{
EricLew	0:80ee8f3b695e	4712	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
EricLew	0:80ee8f3b695e	4713	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
EricLew	0:80ee8f3b695e	4714	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
EricLew	0:80ee8f3b695e	4715
EricLew	0:80ee8f3b695e	4716	/* Reset the Output N Polarity level */
EricLew	0:80ee8f3b695e	4717	tmpccer &= ~TIM_CCER_CC3NP;
EricLew	0:80ee8f3b695e	4718	/* Set the Output N Polarity */
EricLew	0:80ee8f3b695e	4719	tmpccer \|= (OC_Config->OCNPolarity << 8);
EricLew	0:80ee8f3b695e	4720	/* Reset the Output N State */
EricLew	0:80ee8f3b695e	4721	tmpccer &= ~TIM_CCER_CC3NE;
EricLew	0:80ee8f3b695e	4722	}
EricLew	0:80ee8f3b695e	4723
EricLew	0:80ee8f3b695e	4724	if(IS_TIM_BREAK_INSTANCE(TIMx))
EricLew	0:80ee8f3b695e	4725	{
EricLew	0:80ee8f3b695e	4726	/* Check parameters */
EricLew	0:80ee8f3b695e	4727	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
EricLew	0:80ee8f3b695e	4728	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
EricLew	0:80ee8f3b695e	4729
EricLew	0:80ee8f3b695e	4730	/* Reset the Output Compare and Output Compare N IDLE State */
EricLew	0:80ee8f3b695e	4731	tmpcr2 &= ~TIM_CR2_OIS3;
EricLew	0:80ee8f3b695e	4732	tmpcr2 &= ~TIM_CR2_OIS3N;
EricLew	0:80ee8f3b695e	4733	/* Set the Output Idle state */
EricLew	0:80ee8f3b695e	4734	tmpcr2 \|= (OC_Config->OCIdleState << 4);
EricLew	0:80ee8f3b695e	4735	/* Set the Output N Idle state */
EricLew	0:80ee8f3b695e	4736	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
EricLew	0:80ee8f3b695e	4737	}
EricLew	0:80ee8f3b695e	4738
EricLew	0:80ee8f3b695e	4739	/* Write to TIMx CR2 */
EricLew	0:80ee8f3b695e	4740	TIMx->CR2 = tmpcr2;
EricLew	0:80ee8f3b695e	4741
EricLew	0:80ee8f3b695e	4742	/* Write to TIMx CCMR2 */
EricLew	0:80ee8f3b695e	4743	TIMx->CCMR2 = tmpccmrx;
EricLew	0:80ee8f3b695e	4744
EricLew	0:80ee8f3b695e	4745	/* Set the Capture Compare Register value */
EricLew	0:80ee8f3b695e	4746	TIMx->CCR3 = OC_Config->Pulse;
EricLew	0:80ee8f3b695e	4747
EricLew	0:80ee8f3b695e	4748	/* Write to TIMx CCER */
EricLew	0:80ee8f3b695e	4749	TIMx->CCER = tmpccer;
EricLew	0:80ee8f3b695e	4750	}
EricLew	0:80ee8f3b695e	4751
EricLew	0:80ee8f3b695e	4752	/**
EricLew	0:80ee8f3b695e	4753	* @brief Time Ouput Compare 4 configuration
EricLew	0:80ee8f3b695e	4754	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	4755	* @param OC_Config: The ouput configuration structure
EricLew	0:80ee8f3b695e	4756	* @retval None
EricLew	0:80ee8f3b695e	4757	*/
EricLew	0:80ee8f3b695e	4758	void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
EricLew	0:80ee8f3b695e	4759	{
EricLew	0:80ee8f3b695e	4760	uint32_t tmpccmrx = 0;
EricLew	0:80ee8f3b695e	4761	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	4762	uint32_t tmpcr2 = 0;
EricLew	0:80ee8f3b695e	4763
EricLew	0:80ee8f3b695e	4764	/* Disable the Channel 4: Reset the CC4E Bit */
EricLew	0:80ee8f3b695e	4765	TIMx->CCER &= ~TIM_CCER_CC4E;
EricLew	0:80ee8f3b695e	4766
EricLew	0:80ee8f3b695e	4767	/* Get the TIMx CCER register value */
EricLew	0:80ee8f3b695e	4768	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	4769	/* Get the TIMx CR2 register value */
EricLew	0:80ee8f3b695e	4770	tmpcr2 = TIMx->CR2;
EricLew	0:80ee8f3b695e	4771
EricLew	0:80ee8f3b695e	4772	/* Get the TIMx CCMR2 register value */
EricLew	0:80ee8f3b695e	4773	tmpccmrx = TIMx->CCMR2;
EricLew	0:80ee8f3b695e	4774
EricLew	0:80ee8f3b695e	4775	/* Reset the Output Compare mode and Capture/Compare selection Bits */
EricLew	0:80ee8f3b695e	4776	tmpccmrx &= ~TIM_CCMR2_OC4M;
EricLew	0:80ee8f3b695e	4777	tmpccmrx &= ~TIM_CCMR2_CC4S;
EricLew	0:80ee8f3b695e	4778
EricLew	0:80ee8f3b695e	4779	/* Select the Output Compare Mode */
EricLew	0:80ee8f3b695e	4780	tmpccmrx \|= (OC_Config->OCMode << 8);
EricLew	0:80ee8f3b695e	4781
EricLew	0:80ee8f3b695e	4782	/* Reset the Output Polarity level */
EricLew	0:80ee8f3b695e	4783	tmpccer &= ~TIM_CCER_CC4P;
EricLew	0:80ee8f3b695e	4784	/* Set the Output Compare Polarity */
EricLew	0:80ee8f3b695e	4785	tmpccer \|= (OC_Config->OCPolarity << 12);
EricLew	0:80ee8f3b695e	4786
EricLew	0:80ee8f3b695e	4787	if(IS_TIM_BREAK_INSTANCE(TIMx))
EricLew	0:80ee8f3b695e	4788	{
EricLew	0:80ee8f3b695e	4789	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
EricLew	0:80ee8f3b695e	4790
EricLew	0:80ee8f3b695e	4791	/* Reset the Output Compare IDLE State */
EricLew	0:80ee8f3b695e	4792	tmpcr2 &= ~TIM_CR2_OIS4;
EricLew	0:80ee8f3b695e	4793	/* Set the Output Idle state */
EricLew	0:80ee8f3b695e	4794	tmpcr2 \|= (OC_Config->OCIdleState << 6);
EricLew	0:80ee8f3b695e	4795	}
EricLew	0:80ee8f3b695e	4796
EricLew	0:80ee8f3b695e	4797	/* Write to TIMx CR2 */
EricLew	0:80ee8f3b695e	4798	TIMx->CR2 = tmpcr2;
EricLew	0:80ee8f3b695e	4799
EricLew	0:80ee8f3b695e	4800	/* Write to TIMx CCMR2 */
EricLew	0:80ee8f3b695e	4801	TIMx->CCMR2 = tmpccmrx;
EricLew	0:80ee8f3b695e	4802
EricLew	0:80ee8f3b695e	4803	/* Set the Capture Compare Register value */
EricLew	0:80ee8f3b695e	4804	TIMx->CCR4 = OC_Config->Pulse;
EricLew	0:80ee8f3b695e	4805
EricLew	0:80ee8f3b695e	4806	/* Write to TIMx CCER */
EricLew	0:80ee8f3b695e	4807	TIMx->CCER = tmpccer;
EricLew	0:80ee8f3b695e	4808	}
EricLew	0:80ee8f3b695e	4809
EricLew	0:80ee8f3b695e	4810	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
EricLew	0:80ee8f3b695e	4811	TIM_SlaveConfigTypeDef * sSlaveConfig)
EricLew	0:80ee8f3b695e	4812	{
EricLew	0:80ee8f3b695e	4813	uint32_t tmpsmcr = 0;
EricLew	0:80ee8f3b695e	4814	uint32_t tmpccmr1 = 0;
EricLew	0:80ee8f3b695e	4815	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	4816
EricLew	0:80ee8f3b695e	4817	/* Get the TIMx SMCR register value */
EricLew	0:80ee8f3b695e	4818	tmpsmcr = htim->Instance->SMCR;
EricLew	0:80ee8f3b695e	4819
EricLew	0:80ee8f3b695e	4820	/* Reset the Trigger Selection Bits */
EricLew	0:80ee8f3b695e	4821	tmpsmcr &= ~TIM_SMCR_TS;
EricLew	0:80ee8f3b695e	4822	/* Set the Input Trigger source */
EricLew	0:80ee8f3b695e	4823	tmpsmcr \|= sSlaveConfig->InputTrigger;
EricLew	0:80ee8f3b695e	4824
EricLew	0:80ee8f3b695e	4825	/* Reset the slave mode Bits */
EricLew	0:80ee8f3b695e	4826	tmpsmcr &= ~TIM_SMCR_SMS;
EricLew	0:80ee8f3b695e	4827	/* Set the slave mode */
EricLew	0:80ee8f3b695e	4828	tmpsmcr \|= sSlaveConfig->SlaveMode;
EricLew	0:80ee8f3b695e	4829
EricLew	0:80ee8f3b695e	4830	/* Write to TIMx SMCR */
EricLew	0:80ee8f3b695e	4831	htim->Instance->SMCR = tmpsmcr;
EricLew	0:80ee8f3b695e	4832
EricLew	0:80ee8f3b695e	4833	/* Configure the trigger prescaler, filter, and polarity */
EricLew	0:80ee8f3b695e	4834	switch (sSlaveConfig->InputTrigger)
EricLew	0:80ee8f3b695e	4835	{
EricLew	0:80ee8f3b695e	4836	case TIM_TS_ETRF:
EricLew	0:80ee8f3b695e	4837	{
EricLew	0:80ee8f3b695e	4838	/* Check the parameters */
EricLew	0:80ee8f3b695e	4839	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4840	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
EricLew	0:80ee8f3b695e	4841	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
EricLew	0:80ee8f3b695e	4842	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
EricLew	0:80ee8f3b695e	4843	/* Configure the ETR Trigger source */
EricLew	0:80ee8f3b695e	4844	TIM_ETR_SetConfig(htim->Instance,
EricLew	0:80ee8f3b695e	4845	sSlaveConfig->TriggerPrescaler,
EricLew	0:80ee8f3b695e	4846	sSlaveConfig->TriggerPolarity,
EricLew	0:80ee8f3b695e	4847	sSlaveConfig->TriggerFilter);
EricLew	0:80ee8f3b695e	4848	}
EricLew	0:80ee8f3b695e	4849	break;
EricLew	0:80ee8f3b695e	4850
EricLew	0:80ee8f3b695e	4851	case TIM_TS_TI1F_ED:
EricLew	0:80ee8f3b695e	4852	{
EricLew	0:80ee8f3b695e	4853	/* Check the parameters */
EricLew	0:80ee8f3b695e	4854	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4855	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
EricLew	0:80ee8f3b695e	4856
EricLew	0:80ee8f3b695e	4857	/* Disable the Channel 1: Reset the CC1E Bit */
EricLew	0:80ee8f3b695e	4858	tmpccer = htim->Instance->CCER;
EricLew	0:80ee8f3b695e	4859	htim->Instance->CCER &= ~TIM_CCER_CC1E;
EricLew	0:80ee8f3b695e	4860	tmpccmr1 = htim->Instance->CCMR1;
EricLew	0:80ee8f3b695e	4861
EricLew	0:80ee8f3b695e	4862	/* Set the filter */
EricLew	0:80ee8f3b695e	4863	tmpccmr1 &= ~TIM_CCMR1_IC1F;
EricLew	0:80ee8f3b695e	4864	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
EricLew	0:80ee8f3b695e	4865
EricLew	0:80ee8f3b695e	4866	/* Write to TIMx CCMR1 and CCER registers */
EricLew	0:80ee8f3b695e	4867	htim->Instance->CCMR1 = tmpccmr1;
EricLew	0:80ee8f3b695e	4868	htim->Instance->CCER = tmpccer;
EricLew	0:80ee8f3b695e	4869
EricLew	0:80ee8f3b695e	4870	}
EricLew	0:80ee8f3b695e	4871	break;
EricLew	0:80ee8f3b695e	4872
EricLew	0:80ee8f3b695e	4873	case TIM_TS_TI1FP1:
EricLew	0:80ee8f3b695e	4874	{
EricLew	0:80ee8f3b695e	4875	/* Check the parameters */
EricLew	0:80ee8f3b695e	4876	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4877	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
EricLew	0:80ee8f3b695e	4878	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
EricLew	0:80ee8f3b695e	4879
EricLew	0:80ee8f3b695e	4880	/* Configure TI1 Filter and Polarity */
EricLew	0:80ee8f3b695e	4881	TIM_TI1_ConfigInputStage(htim->Instance,
EricLew	0:80ee8f3b695e	4882	sSlaveConfig->TriggerPolarity,
EricLew	0:80ee8f3b695e	4883	sSlaveConfig->TriggerFilter);
EricLew	0:80ee8f3b695e	4884	}
EricLew	0:80ee8f3b695e	4885	break;
EricLew	0:80ee8f3b695e	4886
EricLew	0:80ee8f3b695e	4887	case TIM_TS_TI2FP2:
EricLew	0:80ee8f3b695e	4888	{
EricLew	0:80ee8f3b695e	4889	/* Check the parameters */
EricLew	0:80ee8f3b695e	4890	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4891	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
EricLew	0:80ee8f3b695e	4892	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
EricLew	0:80ee8f3b695e	4893
EricLew	0:80ee8f3b695e	4894	/* Configure TI2 Filter and Polarity */
EricLew	0:80ee8f3b695e	4895	TIM_TI2_ConfigInputStage(htim->Instance,
EricLew	0:80ee8f3b695e	4896	sSlaveConfig->TriggerPolarity,
EricLew	0:80ee8f3b695e	4897	sSlaveConfig->TriggerFilter);
EricLew	0:80ee8f3b695e	4898	}
EricLew	0:80ee8f3b695e	4899	break;
EricLew	0:80ee8f3b695e	4900
EricLew	0:80ee8f3b695e	4901	case TIM_TS_ITR0:
EricLew	0:80ee8f3b695e	4902	{
EricLew	0:80ee8f3b695e	4903	/* Check the parameter */
EricLew	0:80ee8f3b695e	4904	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4905	}
EricLew	0:80ee8f3b695e	4906	break;
EricLew	0:80ee8f3b695e	4907
EricLew	0:80ee8f3b695e	4908	case TIM_TS_ITR1:
EricLew	0:80ee8f3b695e	4909	{
EricLew	0:80ee8f3b695e	4910	/* Check the parameter */
EricLew	0:80ee8f3b695e	4911	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4912	}
EricLew	0:80ee8f3b695e	4913	break;
EricLew	0:80ee8f3b695e	4914
EricLew	0:80ee8f3b695e	4915	case TIM_TS_ITR2:
EricLew	0:80ee8f3b695e	4916	{
EricLew	0:80ee8f3b695e	4917	/* Check the parameter */
EricLew	0:80ee8f3b695e	4918	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4919	}
EricLew	0:80ee8f3b695e	4920	break;
EricLew	0:80ee8f3b695e	4921
EricLew	0:80ee8f3b695e	4922	case TIM_TS_ITR3:
EricLew	0:80ee8f3b695e	4923	{
EricLew	0:80ee8f3b695e	4924	/* Check the parameter */
EricLew	0:80ee8f3b695e	4925	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
EricLew	0:80ee8f3b695e	4926	}
EricLew	0:80ee8f3b695e	4927	break;
EricLew	0:80ee8f3b695e	4928
EricLew	0:80ee8f3b695e	4929	default:
EricLew	0:80ee8f3b695e	4930	break;
EricLew	0:80ee8f3b695e	4931	}
EricLew	0:80ee8f3b695e	4932	}
EricLew	0:80ee8f3b695e	4933
EricLew	0:80ee8f3b695e	4934	/**
EricLew	0:80ee8f3b695e	4935	* @brief Configure the TI1 as Input.
EricLew	0:80ee8f3b695e	4936	* @param TIMx to select the TIM peripheral.
EricLew	0:80ee8f3b695e	4937	* @param TIM_ICPolarity : The Input Polarity.
EricLew	0:80ee8f3b695e	4938	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4939	* @arg TIM_ICPolarity_Rising
EricLew	0:80ee8f3b695e	4940	* @arg TIM_ICPolarity_Falling
EricLew	0:80ee8f3b695e	4941	* @arg TIM_ICPolarity_BothEdge
EricLew	0:80ee8f3b695e	4942	* @param TIM_ICSelection: specifies the input to be used.
EricLew	0:80ee8f3b695e	4943	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4944	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
EricLew	0:80ee8f3b695e	4945	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
EricLew	0:80ee8f3b695e	4946	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
EricLew	0:80ee8f3b695e	4947	* @param TIM_ICFilter: Specifies the Input Capture Filter.
EricLew	0:80ee8f3b695e	4948	* This parameter must be a value between 0x00 and 0x0F.
EricLew	0:80ee8f3b695e	4949	* @retval None
EricLew	0:80ee8f3b695e	4950	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
EricLew	0:80ee8f3b695e	4951	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
EricLew	0:80ee8f3b695e	4952	* protected against un-initialized filter and polarity values.
EricLew	0:80ee8f3b695e	4953	*/
EricLew	0:80ee8f3b695e	4954	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
EricLew	0:80ee8f3b695e	4955	uint32_t TIM_ICFilter)
EricLew	0:80ee8f3b695e	4956	{
EricLew	0:80ee8f3b695e	4957	uint32_t tmpccmr1 = 0;
EricLew	0:80ee8f3b695e	4958	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	4959
EricLew	0:80ee8f3b695e	4960	/* Disable the Channel 1: Reset the CC1E Bit */
EricLew	0:80ee8f3b695e	4961	TIMx->CCER &= ~TIM_CCER_CC1E;
EricLew	0:80ee8f3b695e	4962	tmpccmr1 = TIMx->CCMR1;
EricLew	0:80ee8f3b695e	4963	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	4964
EricLew	0:80ee8f3b695e	4965	/* Select the Input */
EricLew	0:80ee8f3b695e	4966	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
EricLew	0:80ee8f3b695e	4967	{
EricLew	0:80ee8f3b695e	4968	tmpccmr1 &= ~TIM_CCMR1_CC1S;
EricLew	0:80ee8f3b695e	4969	tmpccmr1 \|= TIM_ICSelection;
EricLew	0:80ee8f3b695e	4970	}
EricLew	0:80ee8f3b695e	4971	else
EricLew	0:80ee8f3b695e	4972	{
EricLew	0:80ee8f3b695e	4973	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
EricLew	0:80ee8f3b695e	4974	}
EricLew	0:80ee8f3b695e	4975
EricLew	0:80ee8f3b695e	4976	/* Set the filter */
EricLew	0:80ee8f3b695e	4977	tmpccmr1 &= ~TIM_CCMR1_IC1F;
EricLew	0:80ee8f3b695e	4978	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
EricLew	0:80ee8f3b695e	4979
EricLew	0:80ee8f3b695e	4980	/* Select the Polarity and set the CC1E Bit */
EricLew	0:80ee8f3b695e	4981	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
EricLew	0:80ee8f3b695e	4982	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
EricLew	0:80ee8f3b695e	4983
EricLew	0:80ee8f3b695e	4984	/* Write to TIMx CCMR1 and CCER registers */
EricLew	0:80ee8f3b695e	4985	TIMx->CCMR1 = tmpccmr1;
EricLew	0:80ee8f3b695e	4986	TIMx->CCER = tmpccer;
EricLew	0:80ee8f3b695e	4987	}
EricLew	0:80ee8f3b695e	4988
EricLew	0:80ee8f3b695e	4989	/**
EricLew	0:80ee8f3b695e	4990	* @brief Configure the Polarity and Filter for TI1.
EricLew	0:80ee8f3b695e	4991	* @param TIMx to select the TIM peripheral.
EricLew	0:80ee8f3b695e	4992	* @param TIM_ICPolarity : The Input Polarity.
EricLew	0:80ee8f3b695e	4993	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	4994	* @arg TIM_ICPolarity_Rising
EricLew	0:80ee8f3b695e	4995	* @arg TIM_ICPolarity_Falling
EricLew	0:80ee8f3b695e	4996	* @arg TIM_ICPolarity_BothEdge
EricLew	0:80ee8f3b695e	4997	* @param TIM_ICFilter: Specifies the Input Capture Filter.
EricLew	0:80ee8f3b695e	4998	* This parameter must be a value between 0x00 and 0x0F.
EricLew	0:80ee8f3b695e	4999	* @retval None
EricLew	0:80ee8f3b695e	5000	*/
EricLew	0:80ee8f3b695e	5001	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
EricLew	0:80ee8f3b695e	5002	{
EricLew	0:80ee8f3b695e	5003	uint32_t tmpccmr1 = 0;
EricLew	0:80ee8f3b695e	5004	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	5005
EricLew	0:80ee8f3b695e	5006	/* Disable the Channel 1: Reset the CC1E Bit */
EricLew	0:80ee8f3b695e	5007	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	5008	TIMx->CCER &= ~TIM_CCER_CC1E;
EricLew	0:80ee8f3b695e	5009	tmpccmr1 = TIMx->CCMR1;
EricLew	0:80ee8f3b695e	5010
EricLew	0:80ee8f3b695e	5011	/* Set the filter */
EricLew	0:80ee8f3b695e	5012	tmpccmr1 &= ~TIM_CCMR1_IC1F;
EricLew	0:80ee8f3b695e	5013	tmpccmr1 \|= (TIM_ICFilter << 4);
EricLew	0:80ee8f3b695e	5014
EricLew	0:80ee8f3b695e	5015	/* Select the Polarity and set the CC1E Bit */
EricLew	0:80ee8f3b695e	5016	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
EricLew	0:80ee8f3b695e	5017	tmpccer \|= TIM_ICPolarity;
EricLew	0:80ee8f3b695e	5018
EricLew	0:80ee8f3b695e	5019	/* Write to TIMx CCMR1 and CCER registers */
EricLew	0:80ee8f3b695e	5020	TIMx->CCMR1 = tmpccmr1;
EricLew	0:80ee8f3b695e	5021	TIMx->CCER = tmpccer;
EricLew	0:80ee8f3b695e	5022	}
EricLew	0:80ee8f3b695e	5023
EricLew	0:80ee8f3b695e	5024	/**
EricLew	0:80ee8f3b695e	5025	* @brief Configure the TI2 as Input.
EricLew	0:80ee8f3b695e	5026	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	5027	* @param TIM_ICPolarity : The Input Polarity.
EricLew	0:80ee8f3b695e	5028	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5029	* @arg TIM_ICPolarity_Rising
EricLew	0:80ee8f3b695e	5030	* @arg TIM_ICPolarity_Falling
EricLew	0:80ee8f3b695e	5031	* @arg TIM_ICPolarity_BothEdge
EricLew	0:80ee8f3b695e	5032	* @param TIM_ICSelection: specifies the input to be used.
EricLew	0:80ee8f3b695e	5033	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5034	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
EricLew	0:80ee8f3b695e	5035	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
EricLew	0:80ee8f3b695e	5036	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
EricLew	0:80ee8f3b695e	5037	* @param TIM_ICFilter: Specifies the Input Capture Filter.
EricLew	0:80ee8f3b695e	5038	* This parameter must be a value between 0x00 and 0x0F.
EricLew	0:80ee8f3b695e	5039	* @retval None
EricLew	0:80ee8f3b695e	5040	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
EricLew	0:80ee8f3b695e	5041	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
EricLew	0:80ee8f3b695e	5042	* protected against un-initialized filter and polarity values.
EricLew	0:80ee8f3b695e	5043	*/
EricLew	0:80ee8f3b695e	5044	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
EricLew	0:80ee8f3b695e	5045	uint32_t TIM_ICFilter)
EricLew	0:80ee8f3b695e	5046	{
EricLew	0:80ee8f3b695e	5047	uint32_t tmpccmr1 = 0;
EricLew	0:80ee8f3b695e	5048	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	5049
EricLew	0:80ee8f3b695e	5050	/* Disable the Channel 2: Reset the CC2E Bit */
EricLew	0:80ee8f3b695e	5051	TIMx->CCER &= ~TIM_CCER_CC2E;
EricLew	0:80ee8f3b695e	5052	tmpccmr1 = TIMx->CCMR1;
EricLew	0:80ee8f3b695e	5053	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	5054
EricLew	0:80ee8f3b695e	5055	/* Select the Input */
EricLew	0:80ee8f3b695e	5056	tmpccmr1 &= ~TIM_CCMR1_CC2S;
EricLew	0:80ee8f3b695e	5057	tmpccmr1 \|= (TIM_ICSelection << 8);
EricLew	0:80ee8f3b695e	5058
EricLew	0:80ee8f3b695e	5059	/* Set the filter */
EricLew	0:80ee8f3b695e	5060	tmpccmr1 &= ~TIM_CCMR1_IC2F;
EricLew	0:80ee8f3b695e	5061	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
EricLew	0:80ee8f3b695e	5062
EricLew	0:80ee8f3b695e	5063	/* Select the Polarity and set the CC2E Bit */
EricLew	0:80ee8f3b695e	5064	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
EricLew	0:80ee8f3b695e	5065	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
EricLew	0:80ee8f3b695e	5066
EricLew	0:80ee8f3b695e	5067	/* Write to TIMx CCMR1 and CCER registers */
EricLew	0:80ee8f3b695e	5068	TIMx->CCMR1 = tmpccmr1 ;
EricLew	0:80ee8f3b695e	5069	TIMx->CCER = tmpccer;
EricLew	0:80ee8f3b695e	5070	}
EricLew	0:80ee8f3b695e	5071
EricLew	0:80ee8f3b695e	5072	/**
EricLew	0:80ee8f3b695e	5073	* @brief Configure the Polarity and Filter for TI2.
EricLew	0:80ee8f3b695e	5074	* @param TIMx to select the TIM peripheral.
EricLew	0:80ee8f3b695e	5075	* @param TIM_ICPolarity : The Input Polarity.
EricLew	0:80ee8f3b695e	5076	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5077	* @arg TIM_ICPolarity_Rising
EricLew	0:80ee8f3b695e	5078	* @arg TIM_ICPolarity_Falling
EricLew	0:80ee8f3b695e	5079	* @arg TIM_ICPolarity_BothEdge
EricLew	0:80ee8f3b695e	5080	* @param TIM_ICFilter: Specifies the Input Capture Filter.
EricLew	0:80ee8f3b695e	5081	* This parameter must be a value between 0x00 and 0x0F.
EricLew	0:80ee8f3b695e	5082	* @retval None
EricLew	0:80ee8f3b695e	5083	*/
EricLew	0:80ee8f3b695e	5084	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
EricLew	0:80ee8f3b695e	5085	{
EricLew	0:80ee8f3b695e	5086	uint32_t tmpccmr1 = 0;
EricLew	0:80ee8f3b695e	5087	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	5088
EricLew	0:80ee8f3b695e	5089	/* Disable the Channel 2: Reset the CC2E Bit */
EricLew	0:80ee8f3b695e	5090	TIMx->CCER &= ~TIM_CCER_CC2E;
EricLew	0:80ee8f3b695e	5091	tmpccmr1 = TIMx->CCMR1;
EricLew	0:80ee8f3b695e	5092	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	5093
EricLew	0:80ee8f3b695e	5094	/* Set the filter */
EricLew	0:80ee8f3b695e	5095	tmpccmr1 &= ~TIM_CCMR1_IC2F;
EricLew	0:80ee8f3b695e	5096	tmpccmr1 \|= (TIM_ICFilter << 12);
EricLew	0:80ee8f3b695e	5097
EricLew	0:80ee8f3b695e	5098	/* Select the Polarity and set the CC2E Bit */
EricLew	0:80ee8f3b695e	5099	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
EricLew	0:80ee8f3b695e	5100	tmpccer \|= (TIM_ICPolarity << 4);
EricLew	0:80ee8f3b695e	5101
EricLew	0:80ee8f3b695e	5102	/* Write to TIMx CCMR1 and CCER registers */
EricLew	0:80ee8f3b695e	5103	TIMx->CCMR1 = tmpccmr1 ;
EricLew	0:80ee8f3b695e	5104	TIMx->CCER = tmpccer;
EricLew	0:80ee8f3b695e	5105	}
EricLew	0:80ee8f3b695e	5106
EricLew	0:80ee8f3b695e	5107	/**
EricLew	0:80ee8f3b695e	5108	* @brief Configure the TI3 as Input.
EricLew	0:80ee8f3b695e	5109	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	5110	* @param TIM_ICPolarity : The Input Polarity.
EricLew	0:80ee8f3b695e	5111	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5112	* @arg TIM_ICPolarity_Rising
EricLew	0:80ee8f3b695e	5113	* @arg TIM_ICPolarity_Falling
EricLew	0:80ee8f3b695e	5114	* @arg TIM_ICPolarity_BothEdge
EricLew	0:80ee8f3b695e	5115	* @param TIM_ICSelection: specifies the input to be used.
EricLew	0:80ee8f3b695e	5116	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5117	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
EricLew	0:80ee8f3b695e	5118	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
EricLew	0:80ee8f3b695e	5119	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
EricLew	0:80ee8f3b695e	5120	* @param TIM_ICFilter: Specifies the Input Capture Filter.
EricLew	0:80ee8f3b695e	5121	* This parameter must be a value between 0x00 and 0x0F.
EricLew	0:80ee8f3b695e	5122	* @retval None
EricLew	0:80ee8f3b695e	5123	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
EricLew	0:80ee8f3b695e	5124	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
EricLew	0:80ee8f3b695e	5125	* protected against un-initialized filter and polarity values.
EricLew	0:80ee8f3b695e	5126	*/
EricLew	0:80ee8f3b695e	5127	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
EricLew	0:80ee8f3b695e	5128	uint32_t TIM_ICFilter)
EricLew	0:80ee8f3b695e	5129	{
EricLew	0:80ee8f3b695e	5130	uint32_t tmpccmr2 = 0;
EricLew	0:80ee8f3b695e	5131	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	5132
EricLew	0:80ee8f3b695e	5133	/* Disable the Channel 3: Reset the CC3E Bit */
EricLew	0:80ee8f3b695e	5134	TIMx->CCER &= ~TIM_CCER_CC3E;
EricLew	0:80ee8f3b695e	5135	tmpccmr2 = TIMx->CCMR2;
EricLew	0:80ee8f3b695e	5136	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	5137
EricLew	0:80ee8f3b695e	5138	/* Select the Input */
EricLew	0:80ee8f3b695e	5139	tmpccmr2 &= ~TIM_CCMR2_CC3S;
EricLew	0:80ee8f3b695e	5140	tmpccmr2 \|= TIM_ICSelection;
EricLew	0:80ee8f3b695e	5141
EricLew	0:80ee8f3b695e	5142	/* Set the filter */
EricLew	0:80ee8f3b695e	5143	tmpccmr2 &= ~TIM_CCMR2_IC3F;
EricLew	0:80ee8f3b695e	5144	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
EricLew	0:80ee8f3b695e	5145
EricLew	0:80ee8f3b695e	5146	/* Select the Polarity and set the CC3E Bit */
EricLew	0:80ee8f3b695e	5147	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
EricLew	0:80ee8f3b695e	5148	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
EricLew	0:80ee8f3b695e	5149
EricLew	0:80ee8f3b695e	5150	/* Write to TIMx CCMR2 and CCER registers */
EricLew	0:80ee8f3b695e	5151	TIMx->CCMR2 = tmpccmr2;
EricLew	0:80ee8f3b695e	5152	TIMx->CCER = tmpccer;
EricLew	0:80ee8f3b695e	5153	}
EricLew	0:80ee8f3b695e	5154
EricLew	0:80ee8f3b695e	5155	/**
EricLew	0:80ee8f3b695e	5156	* @brief Configure the TI4 as Input.
EricLew	0:80ee8f3b695e	5157	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	5158	* @param TIM_ICPolarity : The Input Polarity.
EricLew	0:80ee8f3b695e	5159	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5160	* @arg TIM_ICPolarity_Rising
EricLew	0:80ee8f3b695e	5161	* @arg TIM_ICPolarity_Falling
EricLew	0:80ee8f3b695e	5162	* @arg TIM_ICPolarity_BothEdge
EricLew	0:80ee8f3b695e	5163	* @param TIM_ICSelection: specifies the input to be used.
EricLew	0:80ee8f3b695e	5164	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5165	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
EricLew	0:80ee8f3b695e	5166	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
EricLew	0:80ee8f3b695e	5167	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
EricLew	0:80ee8f3b695e	5168	* @param TIM_ICFilter: Specifies the Input Capture Filter.
EricLew	0:80ee8f3b695e	5169	* This parameter must be a value between 0x00 and 0x0F.
EricLew	0:80ee8f3b695e	5170	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
EricLew	0:80ee8f3b695e	5171	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
EricLew	0:80ee8f3b695e	5172	* protected against un-initialized filter and polarity values.
EricLew	0:80ee8f3b695e	5173	* @retval None
EricLew	0:80ee8f3b695e	5174	*/
EricLew	0:80ee8f3b695e	5175	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
EricLew	0:80ee8f3b695e	5176	uint32_t TIM_ICFilter)
EricLew	0:80ee8f3b695e	5177	{
EricLew	0:80ee8f3b695e	5178	uint32_t tmpccmr2 = 0;
EricLew	0:80ee8f3b695e	5179	uint32_t tmpccer = 0;
EricLew	0:80ee8f3b695e	5180
EricLew	0:80ee8f3b695e	5181	/* Disable the Channel 4: Reset the CC4E Bit */
EricLew	0:80ee8f3b695e	5182	TIMx->CCER &= ~TIM_CCER_CC4E;
EricLew	0:80ee8f3b695e	5183	tmpccmr2 = TIMx->CCMR2;
EricLew	0:80ee8f3b695e	5184	tmpccer = TIMx->CCER;
EricLew	0:80ee8f3b695e	5185
EricLew	0:80ee8f3b695e	5186	/* Select the Input */
EricLew	0:80ee8f3b695e	5187	tmpccmr2 &= ~TIM_CCMR2_CC4S;
EricLew	0:80ee8f3b695e	5188	tmpccmr2 \|= (TIM_ICSelection << 8);
EricLew	0:80ee8f3b695e	5189
EricLew	0:80ee8f3b695e	5190	/* Set the filter */
EricLew	0:80ee8f3b695e	5191	tmpccmr2 &= ~TIM_CCMR2_IC4F;
EricLew	0:80ee8f3b695e	5192	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
EricLew	0:80ee8f3b695e	5193
EricLew	0:80ee8f3b695e	5194	/* Select the Polarity and set the CC4E Bit */
EricLew	0:80ee8f3b695e	5195	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
EricLew	0:80ee8f3b695e	5196	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
EricLew	0:80ee8f3b695e	5197
EricLew	0:80ee8f3b695e	5198	/* Write to TIMx CCMR2 and CCER registers */
EricLew	0:80ee8f3b695e	5199	TIMx->CCMR2 = tmpccmr2;
EricLew	0:80ee8f3b695e	5200	TIMx->CCER = tmpccer ;
EricLew	0:80ee8f3b695e	5201	}
EricLew	0:80ee8f3b695e	5202
EricLew	0:80ee8f3b695e	5203	/**
EricLew	0:80ee8f3b695e	5204	* @brief Selects the Input Trigger source
EricLew	0:80ee8f3b695e	5205	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	5206	* @param InputTriggerSource: The Input Trigger source.
EricLew	0:80ee8f3b695e	5207	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5208	* @arg TIM_TS_ITR0: Internal Trigger 0
EricLew	0:80ee8f3b695e	5209	* @arg TIM_TS_ITR1: Internal Trigger 1
EricLew	0:80ee8f3b695e	5210	* @arg TIM_TS_ITR2: Internal Trigger 2
EricLew	0:80ee8f3b695e	5211	* @arg TIM_TS_ITR3: Internal Trigger 3
EricLew	0:80ee8f3b695e	5212	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
EricLew	0:80ee8f3b695e	5213	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
EricLew	0:80ee8f3b695e	5214	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
EricLew	0:80ee8f3b695e	5215	* @arg TIM_TS_ETRF: External Trigger input
EricLew	0:80ee8f3b695e	5216	* @retval None
EricLew	0:80ee8f3b695e	5217	*/
EricLew	0:80ee8f3b695e	5218	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
EricLew	0:80ee8f3b695e	5219	{
EricLew	0:80ee8f3b695e	5220	uint32_t tmpsmcr = 0;
EricLew	0:80ee8f3b695e	5221
EricLew	0:80ee8f3b695e	5222	/* Get the TIMx SMCR register value */
EricLew	0:80ee8f3b695e	5223	tmpsmcr = TIMx->SMCR;
EricLew	0:80ee8f3b695e	5224	/* Reset the TS Bits */
EricLew	0:80ee8f3b695e	5225	tmpsmcr &= ~TIM_SMCR_TS;
EricLew	0:80ee8f3b695e	5226	/* Set the Input Trigger source and the slave mode*/
EricLew	0:80ee8f3b695e	5227	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
EricLew	0:80ee8f3b695e	5228	/* Write to TIMx SMCR */
EricLew	0:80ee8f3b695e	5229	TIMx->SMCR = tmpsmcr;
EricLew	0:80ee8f3b695e	5230	}
EricLew	0:80ee8f3b695e	5231	/**
EricLew	0:80ee8f3b695e	5232	* @brief Configures the TIMx External Trigger (ETR).
EricLew	0:80ee8f3b695e	5233	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	5234	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
EricLew	0:80ee8f3b695e	5235	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5236	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
EricLew	0:80ee8f3b695e	5237	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
EricLew	0:80ee8f3b695e	5238	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
EricLew	0:80ee8f3b695e	5239	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
EricLew	0:80ee8f3b695e	5240	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
EricLew	0:80ee8f3b695e	5241	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5242	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
EricLew	0:80ee8f3b695e	5243	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
EricLew	0:80ee8f3b695e	5244	* @param ExtTRGFilter: External Trigger Filter.
EricLew	0:80ee8f3b695e	5245	* This parameter must be a value between 0x00 and 0x0F
EricLew	0:80ee8f3b695e	5246	* @retval None
EricLew	0:80ee8f3b695e	5247	*/
EricLew	0:80ee8f3b695e	5248	void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
EricLew	0:80ee8f3b695e	5249	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
EricLew	0:80ee8f3b695e	5250	{
EricLew	0:80ee8f3b695e	5251	uint32_t tmpsmcr = 0;
EricLew	0:80ee8f3b695e	5252
EricLew	0:80ee8f3b695e	5253	tmpsmcr = TIMx->SMCR;
EricLew	0:80ee8f3b695e	5254
EricLew	0:80ee8f3b695e	5255	/* Reset the ETR Bits */
EricLew	0:80ee8f3b695e	5256	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
EricLew	0:80ee8f3b695e	5257
EricLew	0:80ee8f3b695e	5258	/* Set the Prescaler, the Filter value and the Polarity */
EricLew	0:80ee8f3b695e	5259	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
EricLew	0:80ee8f3b695e	5260
EricLew	0:80ee8f3b695e	5261	/* Write to TIMx SMCR */
EricLew	0:80ee8f3b695e	5262	TIMx->SMCR = tmpsmcr;
EricLew	0:80ee8f3b695e	5263	}
EricLew	0:80ee8f3b695e	5264
EricLew	0:80ee8f3b695e	5265	/**
EricLew	0:80ee8f3b695e	5266	* @brief Enables or disables the TIM Capture Compare Channel x.
EricLew	0:80ee8f3b695e	5267	* @param TIMx to select the TIM peripheral
EricLew	0:80ee8f3b695e	5268	* @param Channel: specifies the TIM Channel
EricLew	0:80ee8f3b695e	5269	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	5270	* @arg TIM_CHANNEL_1: TIM Channel 1
EricLew	0:80ee8f3b695e	5271	* @arg TIM_CHANNEL_2: TIM Channel 2
EricLew	0:80ee8f3b695e	5272	* @arg TIM_CHANNEL_3: TIM Channel 3
EricLew	0:80ee8f3b695e	5273	* @arg TIM_CHANNEL_4: TIM Channel 4
EricLew	0:80ee8f3b695e	5274	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
EricLew	0:80ee8f3b695e	5275	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
EricLew	0:80ee8f3b695e	5276	* @retval None
EricLew	0:80ee8f3b695e	5277	*/
EricLew	0:80ee8f3b695e	5278	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
EricLew	0:80ee8f3b695e	5279	{
EricLew	0:80ee8f3b695e	5280	uint32_t tmp = 0;
EricLew	0:80ee8f3b695e	5281
EricLew	0:80ee8f3b695e	5282	/* Check the parameters */
EricLew	0:80ee8f3b695e	5283	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
EricLew	0:80ee8f3b695e	5284	assert_param(IS_TIM_CHANNELS(Channel));
EricLew	0:80ee8f3b695e	5285
EricLew	0:80ee8f3b695e	5286	tmp = TIM_CCER_CC1E << Channel;
EricLew	0:80ee8f3b695e	5287
EricLew	0:80ee8f3b695e	5288	/* Reset the CCxE Bit */
EricLew	0:80ee8f3b695e	5289	TIMx->CCER &= ~tmp;
EricLew	0:80ee8f3b695e	5290
EricLew	0:80ee8f3b695e	5291	/* Set or reset the CCxE Bit */
EricLew	0:80ee8f3b695e	5292	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
EricLew	0:80ee8f3b695e	5293	}
EricLew	0:80ee8f3b695e	5294
EricLew	0:80ee8f3b695e	5295
EricLew	0:80ee8f3b695e	5296	/**
EricLew	0:80ee8f3b695e	5297	* @}
EricLew	0:80ee8f3b695e	5298	*/
EricLew	0:80ee8f3b695e	5299
EricLew	0:80ee8f3b695e	5300	#endif /* HAL_TIM_MODULE_ENABLED */
EricLew	0:80ee8f3b695e	5301	/**
EricLew	0:80ee8f3b695e	5302	* @}
EricLew	0:80ee8f3b695e	5303	*/
EricLew	0:80ee8f3b695e	5304
EricLew	0:80ee8f3b695e	5305	/**
EricLew	0:80ee8f3b695e	5306	* @}
EricLew	0:80ee8f3b695e	5307	*/
EricLew	0:80ee8f3b695e	5308	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	5309

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Type:	Library
Created:	02 Nov 2015
Imports:	1072
Forks:	1
Commits:	1
Dependents:	0
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Src/stm32l4xx_hal_tim.c@0:80ee8f3b695e, 2015-11-02 (annotated)

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