Semtech / SX126xLib

SX1261 and sx1262 common library

Dependents:   SX126xDevKit SX1262PingPong SX126X_TXonly SX126X_PingPong_Demo ... more

Fork of SX126xLib by Gregory Cristian

sx126x-hal.cpp@6:1e2345700991, 2018-07-18 (annotated)

Committer:
GregCr
Date:
Wed Jul 18 13:33:42 2018 +0000
Revision:
6:1e2345700991
Parent:
5:e488e6f185f3 
added support for sx1268

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:deaafdfde3bb 1 /*
GregCr 0:deaafdfde3bb 2 / _____) _ | |
GregCr 0:deaafdfde3bb 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:deaafdfde3bb 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:deaafdfde3bb 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:deaafdfde3bb 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 0:deaafdfde3bb 7 (C)2016 Semtech
GregCr 0:deaafdfde3bb 8
GregCr 0:deaafdfde3bb 9 Description: Handling of the node configuration protocol
GregCr 0:deaafdfde3bb 10
GregCr 0:deaafdfde3bb 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:deaafdfde3bb 12
GregCr 0:deaafdfde3bb 13 Maintainer: Miguel Luis, Gregory Cristian and Matthieu Verdy
GregCr 0:deaafdfde3bb 14 */
GregCr 1:35d34672a089 15 #include "sx126x-hal.h"
GregCr 0:deaafdfde3bb 16
GregCr 4:c6ef863d0b07 17 /*!
GregCr 4:c6ef863d0b07 18 * \brief Helper macro to create Interrupt objects only if the pin name is
GregCr 4:c6ef863d0b07 19 * different from NC
GregCr 4:c6ef863d0b07 20 */
GregCr 4:c6ef863d0b07 21 #define CreateDioPin( pinName, dio ) \
GregCr 4:c6ef863d0b07 22 if( pinName == NC ) \
GregCr 4:c6ef863d0b07 23 { \
GregCr 4:c6ef863d0b07 24 dio = NULL; \
GregCr 4:c6ef863d0b07 25 } \
GregCr 4:c6ef863d0b07 26 else \
GregCr 4:c6ef863d0b07 27 { \
GregCr 4:c6ef863d0b07 28 dio = new InterruptIn( pinName ); \
GregCr 4:c6ef863d0b07 29 }
GregCr 4:c6ef863d0b07 30
GregCr 4:c6ef863d0b07 31 /*!
GregCr 4:c6ef863d0b07 32 * \brief Helper macro to avoid duplicating code for setting dio pins parameters
GregCr 4:c6ef863d0b07 33 */
GregCr 4:c6ef863d0b07 34 #define DioAssignCallback( dio, pinMode, callback ) \
GregCr 4:c6ef863d0b07 35 if( dio != NULL ) \
GregCr 4:c6ef863d0b07 36 { \
GregCr 4:c6ef863d0b07 37 dio->mode( pinMode ); \
GregCr 4:c6ef863d0b07 38 dio->rise( this, static_cast <Trigger>( callback ) ); \
GregCr 4:c6ef863d0b07 39 }
GregCr 0:deaafdfde3bb 40
GregCr 0:deaafdfde3bb 41 /*!
GregCr 0:deaafdfde3bb 42 * \brief Used to block execution waiting for low state on radio busy pin.
GregCr 0:deaafdfde3bb 43 */
GregCr 4:c6ef863d0b07 44 #define WaitOnBusy( ) while( BUSY == 1 ){ }
GregCr 0:deaafdfde3bb 45
GregCr 0:deaafdfde3bb 46 /*!
GregCr 4:c6ef863d0b07 47 * \brief Used to block execution to give enough time to Busy to go up
GregCr 5:e488e6f185f3 48 * in order to respect Tsw, see datasheet ยง8.3.1
GregCr 0:deaafdfde3bb 49 */
GregCr 4:c6ef863d0b07 50 #define WaitOnCounter( ) for( uint8_t counter = 0; counter < 15; counter++ ) \
GregCr 5:e488e6f185f3 51 { __NOP( ); }
GregCr 0:deaafdfde3bb 52
GregCr 4:c6ef863d0b07 53
GregCr 4:c6ef863d0b07 54 // This code handles cases where assert_param is undefined
GregCr 4:c6ef863d0b07 55 #ifndef assert_param
GregCr 4:c6ef863d0b07 56 #define assert_param( ... )
GregCr 4:c6ef863d0b07 57 #endif
GregCr 0:deaafdfde3bb 58
GregCr 4:c6ef863d0b07 59 SX126xHal::SX126xHal( PinName mosi, PinName miso, PinName sclk, PinName nss,
GregCr 4:c6ef863d0b07 60 PinName busy, PinName dio1, PinName dio2, PinName dio3, PinName rst,
GregCr 5:e488e6f185f3 61 PinName freqSel, PinName deviceSelect, PinName antSwPower, RadioCallbacks_t *callbacks )
GregCr 4:c6ef863d0b07 62 : SX126x( callbacks ),
GregCr 0:deaafdfde3bb 63 RadioNss( nss ),
GregCr 0:deaafdfde3bb 64 RadioReset( rst ),
GregCr 0:deaafdfde3bb 65 BUSY( busy ),
GregCr 5:e488e6f185f3 66 FreqSelect( freqSel ),
GregCr 4:c6ef863d0b07 67 DeviceSelect( deviceSelect ),
GregCr 4:c6ef863d0b07 68 antSwitchPower( antSwPower )
GregCr 0:deaafdfde3bb 69 {
GregCr 4:c6ef863d0b07 70 CreateDioPin( dio1, DIO1 );
GregCr 4:c6ef863d0b07 71 CreateDioPin( dio2, DIO2 );
GregCr 4:c6ef863d0b07 72 CreateDioPin( dio3, DIO3 );
GregCr 0:deaafdfde3bb 73 RadioSpi = new SPI( mosi, miso, sclk );
GregCr 0:deaafdfde3bb 74
GregCr 0:deaafdfde3bb 75 RadioNss = 1;
GregCr 0:deaafdfde3bb 76 RadioReset = 1;
GregCr 0:deaafdfde3bb 77 }
GregCr 0:deaafdfde3bb 78
GregCr 4:c6ef863d0b07 79 SX126xHal::~SX126xHal( void )
GregCr 0:deaafdfde3bb 80 {
GregCr 4:c6ef863d0b07 81 if( this->RadioSpi != NULL )
GregCr 4:c6ef863d0b07 82 {
GregCr 4:c6ef863d0b07 83 delete RadioSpi;
GregCr 4:c6ef863d0b07 84 }
GregCr 4:c6ef863d0b07 85 if( DIO1 != NULL )
GregCr 4:c6ef863d0b07 86 {
GregCr 4:c6ef863d0b07 87 delete DIO1;
GregCr 4:c6ef863d0b07 88 }
GregCr 4:c6ef863d0b07 89 if( DIO2 != NULL )
GregCr 4:c6ef863d0b07 90 {
GregCr 4:c6ef863d0b07 91 delete DIO2;
GregCr 4:c6ef863d0b07 92 }
GregCr 4:c6ef863d0b07 93 if( DIO3 != NULL )
GregCr 4:c6ef863d0b07 94 {
GregCr 4:c6ef863d0b07 95 delete DIO3;
GregCr 4:c6ef863d0b07 96 }
GregCr 4:c6ef863d0b07 97 };
GregCr 0:deaafdfde3bb 98
GregCr 2:4ff11ea92fbe 99 void SX126xHal::SpiInit( void )
GregCr 0:deaafdfde3bb 100 {
GregCr 0:deaafdfde3bb 101 RadioNss = 1;
GregCr 0:deaafdfde3bb 102 RadioSpi->format( 8, 0 );
GregCr 2:4ff11ea92fbe 103 RadioSpi->frequency( SX126x_SPI_FREQ_DEFAULT );
GregCr 0:deaafdfde3bb 104
GregCr 0:deaafdfde3bb 105 wait( 0.1 );
GregCr 0:deaafdfde3bb 106 }
GregCr 0:deaafdfde3bb 107
GregCr 0:deaafdfde3bb 108
GregCr 2:4ff11ea92fbe 109 void SX126xHal::IoIrqInit( DioIrqHandler irqHandler )
GregCr 0:deaafdfde3bb 110 {
GregCr 4:c6ef863d0b07 111 assert_param( RadioSpi != NULL );
GregCr 0:deaafdfde3bb 112 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 113 {
GregCr 0:deaafdfde3bb 114 SpiInit( );
GregCr 0:deaafdfde3bb 115 }
GregCr 0:deaafdfde3bb 116
GregCr 4:c6ef863d0b07 117 BUSY.mode( PullNone );
GregCr 4:c6ef863d0b07 118 DioAssignCallback( DIO1, PullNone, irqHandler );
GregCr 4:c6ef863d0b07 119 // DioAssignCallback( DIO2, PullNone, irqHandler );
GregCr 4:c6ef863d0b07 120 // DioAssignCallback( DIO3, PullNone, irqHandler );
GregCr 0:deaafdfde3bb 121
GregCr 0:deaafdfde3bb 122 }
GregCr 0:deaafdfde3bb 123
GregCr 2:4ff11ea92fbe 124 void SX126xHal::Reset( void )
GregCr 0:deaafdfde3bb 125 {
GregCr 0:deaafdfde3bb 126 __disable_irq( );
GregCr 4:c6ef863d0b07 127 wait_ms( 20 );
GregCr 4:c6ef863d0b07 128 RadioReset.output( );
GregCr 0:deaafdfde3bb 129 RadioReset = 0;
GregCr 4:c6ef863d0b07 130 wait_ms( 50 );
GregCr 0:deaafdfde3bb 131 RadioReset = 1;
GregCr 4:c6ef863d0b07 132 RadioReset.input( ); // Using the internal pull-up
GregCr 4:c6ef863d0b07 133 wait_ms( 20 );
GregCr 0:deaafdfde3bb 134 __enable_irq( );
GregCr 0:deaafdfde3bb 135 }
GregCr 0:deaafdfde3bb 136
GregCr 2:4ff11ea92fbe 137 void SX126xHal::Wakeup( void )
GregCr 0:deaafdfde3bb 138 {
GregCr 0:deaafdfde3bb 139 __disable_irq( );
GregCr 0:deaafdfde3bb 140
GregCr 4:c6ef863d0b07 141 //Don't wait for BUSY here
GregCr 0:deaafdfde3bb 142
GregCr 0:deaafdfde3bb 143 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 144 {
GregCr 0:deaafdfde3bb 145 RadioNss = 0;
GregCr 0:deaafdfde3bb 146 RadioSpi->write( RADIO_GET_STATUS );
GregCr 0:deaafdfde3bb 147 RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 148 RadioNss = 1;
GregCr 0:deaafdfde3bb 149 }
GregCr 0:deaafdfde3bb 150
GregCr 0:deaafdfde3bb 151 // Wait for chip to be ready.
GregCr 4:c6ef863d0b07 152 WaitOnBusy( );
GregCr 0:deaafdfde3bb 153
GregCr 0:deaafdfde3bb 154 __enable_irq( );
GregCr 4:c6ef863d0b07 155
GregCr 4:c6ef863d0b07 156 AntSwOn( );
GregCr 0:deaafdfde3bb 157 }
GregCr 0:deaafdfde3bb 158
GregCr 2:4ff11ea92fbe 159 void SX126xHal::WriteCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 160 {
GregCr 4:c6ef863d0b07 161 #ifdef ADV_DEBUG
GregCr 4:c6ef863d0b07 162 printf("cmd: 0x%02x", command );
GregCr 4:c6ef863d0b07 163 for( uint8_t i = 0; i < size; i++ )
GregCr 4:c6ef863d0b07 164 {
GregCr 4:c6ef863d0b07 165 printf("-%02x", buffer[i] );
GregCr 4:c6ef863d0b07 166 }
GregCr 4:c6ef863d0b07 167 printf("\n\r");
GregCr 4:c6ef863d0b07 168 #endif
GregCr 4:c6ef863d0b07 169
GregCr 4:c6ef863d0b07 170 WaitOnBusy( );
GregCr 0:deaafdfde3bb 171
GregCr 0:deaafdfde3bb 172 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 173 {
GregCr 0:deaafdfde3bb 174 RadioNss = 0;
GregCr 0:deaafdfde3bb 175 RadioSpi->write( ( uint8_t )command );
GregCr 0:deaafdfde3bb 176 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 177 {
GregCr 0:deaafdfde3bb 178 RadioSpi->write( buffer[i] );
GregCr 0:deaafdfde3bb 179 }
GregCr 0:deaafdfde3bb 180 RadioNss = 1;
GregCr 0:deaafdfde3bb 181 }
GregCr 4:c6ef863d0b07 182 WaitOnCounter( );
GregCr 0:deaafdfde3bb 183 }
GregCr 0:deaafdfde3bb 184
GregCr 2:4ff11ea92fbe 185 void SX126xHal::ReadCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 186 {
GregCr 4:c6ef863d0b07 187 WaitOnBusy( );
GregCr 0:deaafdfde3bb 188
GregCr 0:deaafdfde3bb 189 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 190 {
GregCr 0:deaafdfde3bb 191 RadioNss = 0;
GregCr 0:deaafdfde3bb 192 RadioSpi->write( ( uint8_t )command );
GregCr 0:deaafdfde3bb 193 RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 194 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 195 {
GregCr 0:deaafdfde3bb 196 buffer[i] = RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 197 }
GregCr 0:deaafdfde3bb 198 RadioNss = 1;
GregCr 0:deaafdfde3bb 199 }
GregCr 0:deaafdfde3bb 200 }
GregCr 0:deaafdfde3bb 201
GregCr 2:4ff11ea92fbe 202 void SX126xHal::WriteRegister( uint16_t address, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 203 {
GregCr 4:c6ef863d0b07 204 WaitOnBusy( );
GregCr 0:deaafdfde3bb 205
GregCr 0:deaafdfde3bb 206 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 207 {
GregCr 0:deaafdfde3bb 208 RadioNss = 0;
GregCr 0:deaafdfde3bb 209 RadioSpi->write( RADIO_WRITE_REGISTER );
GregCr 0:deaafdfde3bb 210 RadioSpi->write( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 211 RadioSpi->write( address & 0x00FF );
GregCr 0:deaafdfde3bb 212 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 213 {
GregCr 0:deaafdfde3bb 214 RadioSpi->write( buffer[i] );
GregCr 0:deaafdfde3bb 215 }
GregCr 0:deaafdfde3bb 216 RadioNss = 1;
GregCr 0:deaafdfde3bb 217 }
GregCr 0:deaafdfde3bb 218 }
GregCr 0:deaafdfde3bb 219
GregCr 4:c6ef863d0b07 220 void SX126xHal::WriteReg( uint16_t address, uint8_t value )
GregCr 0:deaafdfde3bb 221 {
GregCr 0:deaafdfde3bb 222 WriteRegister( address, &value, 1 );
GregCr 0:deaafdfde3bb 223 }
GregCr 0:deaafdfde3bb 224
GregCr 2:4ff11ea92fbe 225 void SX126xHal::ReadRegister( uint16_t address, uint8_t *buffer, uint16_t size )
GregCr 0:deaafdfde3bb 226 {
GregCr 4:c6ef863d0b07 227 WaitOnBusy( );
GregCr 0:deaafdfde3bb 228
GregCr 0:deaafdfde3bb 229 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 230 {
GregCr 0:deaafdfde3bb 231 RadioNss = 0;
GregCr 0:deaafdfde3bb 232 RadioSpi->write( RADIO_READ_REGISTER );
GregCr 0:deaafdfde3bb 233 RadioSpi->write( ( address & 0xFF00 ) >> 8 );
GregCr 0:deaafdfde3bb 234 RadioSpi->write( address & 0x00FF );
GregCr 0:deaafdfde3bb 235 RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 236 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 237 {
GregCr 0:deaafdfde3bb 238 buffer[i] = RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 239 }
GregCr 0:deaafdfde3bb 240 RadioNss = 1;
GregCr 0:deaafdfde3bb 241 }
GregCr 0:deaafdfde3bb 242 }
GregCr 0:deaafdfde3bb 243
GregCr 4:c6ef863d0b07 244 uint8_t SX126xHal::ReadReg( uint16_t address )
GregCr 0:deaafdfde3bb 245 {
GregCr 0:deaafdfde3bb 246 uint8_t data;
GregCr 0:deaafdfde3bb 247
GregCr 0:deaafdfde3bb 248 ReadRegister( address, &data, 1 );
GregCr 0:deaafdfde3bb 249 return data;
GregCr 0:deaafdfde3bb 250 }
GregCr 0:deaafdfde3bb 251
GregCr 2:4ff11ea92fbe 252 void SX126xHal::WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size )
GregCr 0:deaafdfde3bb 253 {
GregCr 4:c6ef863d0b07 254 WaitOnBusy( );
GregCr 0:deaafdfde3bb 255
GregCr 0:deaafdfde3bb 256 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 257 {
GregCr 0:deaafdfde3bb 258 RadioNss = 0;
GregCr 0:deaafdfde3bb 259 RadioSpi->write( RADIO_WRITE_BUFFER );
GregCr 0:deaafdfde3bb 260 RadioSpi->write( offset );
GregCr 0:deaafdfde3bb 261 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 262 {
GregCr 0:deaafdfde3bb 263 RadioSpi->write( buffer[i] );
GregCr 0:deaafdfde3bb 264 }
GregCr 0:deaafdfde3bb 265 RadioNss = 1;
GregCr 0:deaafdfde3bb 266 }
GregCr 0:deaafdfde3bb 267 }
GregCr 0:deaafdfde3bb 268
GregCr 2:4ff11ea92fbe 269 void SX126xHal::ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size )
GregCr 0:deaafdfde3bb 270 {
GregCr 4:c6ef863d0b07 271 WaitOnBusy( );
GregCr 0:deaafdfde3bb 272
GregCr 0:deaafdfde3bb 273 if( RadioSpi != NULL )
GregCr 0:deaafdfde3bb 274 {
GregCr 0:deaafdfde3bb 275 RadioNss = 0;
GregCr 0:deaafdfde3bb 276 RadioSpi->write( RADIO_READ_BUFFER );
GregCr 0:deaafdfde3bb 277 RadioSpi->write( offset );
GregCr 0:deaafdfde3bb 278 RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 279 for( uint16_t i = 0; i < size; i++ )
GregCr 0:deaafdfde3bb 280 {
GregCr 0:deaafdfde3bb 281 buffer[i] = RadioSpi->write( 0 );
GregCr 0:deaafdfde3bb 282 }
GregCr 0:deaafdfde3bb 283 RadioNss = 1;
GregCr 0:deaafdfde3bb 284 }
GregCr 0:deaafdfde3bb 285 }
GregCr 0:deaafdfde3bb 286
GregCr 2:4ff11ea92fbe 287 uint8_t SX126xHal::GetDioStatus( void )
GregCr 0:deaafdfde3bb 288 {
GregCr 4:c6ef863d0b07 289 return ( *DIO3 << 3 ) | ( *DIO2 << 2 ) | ( *DIO1 << 1 ) | ( BUSY << 0 );
GregCr 4:c6ef863d0b07 290 }
GregCr 4:c6ef863d0b07 291
GregCr 4:c6ef863d0b07 292 uint8_t SX126xHal::GetDeviceType( void )
GregCr 4:c6ef863d0b07 293 {
GregCr 6:1e2345700991 294 uint16_t val = 0;
GregCr 6:1e2345700991 295 val = DeviceSelect.read_u16( );
GregCr 6:1e2345700991 296
GregCr 6:1e2345700991 297 if( val <= 0x2000 )
GregCr 6:1e2345700991 298 {
GregCr 6:1e2345700991 299 return( SX1262 );
GregCr 6:1e2345700991 300 }
GregCr 6:1e2345700991 301 else if( val <= 0xA000 )
GregCr 6:1e2345700991 302 {
GregCr 6:1e2345700991 303 return( SX1268 );
GregCr 6:1e2345700991 304 }
GregCr 6:1e2345700991 305 else
GregCr 6:1e2345700991 306 {
GregCr 6:1e2345700991 307 return( SX1261 );
GregCr 6:1e2345700991 308 }
GregCr 0:deaafdfde3bb 309 }
GregCr 0:deaafdfde3bb 310
GregCr 5:e488e6f185f3 311 uint8_t SX126xHal::GetFreqSelect( void )
GregCr 5:e488e6f185f3 312 {
GregCr 6:1e2345700991 313 uint16_t val = 0;
GregCr 6:1e2345700991 314 val = FreqSelect.read_u16( );
GregCr 6:1e2345700991 315
GregCr 6:1e2345700991 316 if( val < 100 )
GregCr 6:1e2345700991 317 {
GregCr 6:1e2345700991 318 return( MATCHING_FREQ_915 );
GregCr 6:1e2345700991 319 }
GregCr 6:1e2345700991 320 else if( val <= 0x3000 )
GregCr 6:1e2345700991 321 {
GregCr 6:1e2345700991 322 return( MATCHING_FREQ_780 );
GregCr 6:1e2345700991 323 }
GregCr 6:1e2345700991 324 else if( val <= 0x4900 ) // 0x4724
GregCr 6:1e2345700991 325 {
GregCr 6:1e2345700991 326 return( MATCHING_FREQ_490 );
GregCr 6:1e2345700991 327 }
GregCr 6:1e2345700991 328 else if( val <= 1 )
GregCr 6:1e2345700991 329 {
GregCr 6:1e2345700991 330 return( MATCHING_FREQ_434 );
GregCr 6:1e2345700991 331 }
GregCr 6:1e2345700991 332 else if( val <= 1 )
GregCr 6:1e2345700991 333 {
GregCr 6:1e2345700991 334 return( MATCHING_FREQ_280 );
GregCr 6:1e2345700991 335 }
GregCr 6:1e2345700991 336 else if( val <= 0xF000 )
GregCr 6:1e2345700991 337 {
GregCr 6:1e2345700991 338 return( MATCHING_FREQ_169 );
GregCr 6:1e2345700991 339 }
GregCr 6:1e2345700991 340 else
GregCr 6:1e2345700991 341 {
GregCr 6:1e2345700991 342 return( MATCHING_FREQ_868 );
GregCr 6:1e2345700991 343 }
GregCr 5:e488e6f185f3 344 }
GregCr 5:e488e6f185f3 345
GregCr 4:c6ef863d0b07 346 void SX126xHal::AntSwOn( void )
GregCr 4:c6ef863d0b07 347 {
GregCr 4:c6ef863d0b07 348 antSwitchPower = 1;
GregCr 4:c6ef863d0b07 349 }
GregCr 0:deaafdfde3bb 350
GregCr 4:c6ef863d0b07 351 void SX126xHal::AntSwOff( void )
GregCr 4:c6ef863d0b07 352 {
GregCr 4:c6ef863d0b07 353 antSwitchPower = 0;
GregCr 4:c6ef863d0b07 354 }