These are the core files for the Robot at Team conception.

Dependencies:   mbed UniServ

Committer:
obrie829
Date:
Wed Jun 07 11:35:59 2017 +0000
Revision:
17:ec52258b9472
Parent:
2:644553c019c5
v18

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Paulhd182 2:644553c019c5 1 /*
Paulhd182 2:644553c019c5 2 * EncoderCounter.cpp
Paulhd182 2:644553c019c5 3 * Copyright (c) 2016, ZHAW
Paulhd182 2:644553c019c5 4 * All rights reserved.
Paulhd182 2:644553c019c5 5 */
Paulhd182 2:644553c019c5 6
Paulhd182 2:644553c019c5 7 #include "EncoderCounter.h"
Paulhd182 2:644553c019c5 8
Paulhd182 2:644553c019c5 9 using namespace std;
Paulhd182 2:644553c019c5 10
Paulhd182 2:644553c019c5 11 /**
Paulhd182 2:644553c019c5 12 * Creates and initializes the driver to read the quadrature
Paulhd182 2:644553c019c5 13 * encoder counter of the STM32 microcontroller.
Paulhd182 2:644553c019c5 14 * @param a the input pin for the channel A.
Paulhd182 2:644553c019c5 15 * @param b the input pin for the channel B.
Paulhd182 2:644553c019c5 16 */
Paulhd182 2:644553c019c5 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
Paulhd182 2:644553c019c5 18
Paulhd182 2:644553c019c5 19 // check pins
Paulhd182 2:644553c019c5 20
Paulhd182 2:644553c019c5 21 if ((a == PA_6) && (b == PC_7)) {
Paulhd182 2:644553c019c5 22
Paulhd182 2:644553c019c5 23 // pinmap OK for TIM3 CH1 and CH2
Paulhd182 2:644553c019c5 24
Paulhd182 2:644553c019c5 25 TIM = TIM3;
Paulhd182 2:644553c019c5 26
Paulhd182 2:644553c019c5 27 // configure reset and clock control registers
Paulhd182 2:644553c019c5 28
Paulhd182 2:644553c019c5 29 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
Paulhd182 2:644553c019c5 30
Paulhd182 2:644553c019c5 31 // configure general purpose I/O registers
Paulhd182 2:644553c019c5 32
Paulhd182 2:644553c019c5 33 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
Paulhd182 2:644553c019c5 34 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
Paulhd182 2:644553c019c5 35 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
Paulhd182 2:644553c019c5 36 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
Paulhd182 2:644553c019c5 37 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
Paulhd182 2:644553c019c5 38 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
Paulhd182 2:644553c019c5 39
Paulhd182 2:644553c019c5 40 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
Paulhd182 2:644553c019c5 41 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
Paulhd182 2:644553c019c5 42 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
Paulhd182 2:644553c019c5 43 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
Paulhd182 2:644553c019c5 44 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
Paulhd182 2:644553c019c5 45 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
Paulhd182 2:644553c019c5 46
Paulhd182 2:644553c019c5 47 // configure reset and clock control registers
Paulhd182 2:644553c019c5 48
Paulhd182 2:644553c019c5 49 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
Paulhd182 2:644553c019c5 50 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
Paulhd182 2:644553c019c5 51
Paulhd182 2:644553c019c5 52 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
Paulhd182 2:644553c019c5 53
Paulhd182 2:644553c019c5 54 } else if ((a == PB_6) && (b == PB_7)) {
Paulhd182 2:644553c019c5 55
Paulhd182 2:644553c019c5 56 // pinmap OK for TIM4 CH1 and CH2
Paulhd182 2:644553c019c5 57
Paulhd182 2:644553c019c5 58 TIM = TIM4;
Paulhd182 2:644553c019c5 59
Paulhd182 2:644553c019c5 60 // configure reset and clock control registers
Paulhd182 2:644553c019c5 61
Paulhd182 2:644553c019c5 62 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
Paulhd182 2:644553c019c5 63
Paulhd182 2:644553c019c5 64 // configure general purpose I/O registers
Paulhd182 2:644553c019c5 65
Paulhd182 2:644553c019c5 66 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
Paulhd182 2:644553c019c5 67 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
Paulhd182 2:644553c019c5 68 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
Paulhd182 2:644553c019c5 69 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
Paulhd182 2:644553c019c5 70 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
Paulhd182 2:644553c019c5 71 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
Paulhd182 2:644553c019c5 72
Paulhd182 2:644553c019c5 73 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
Paulhd182 2:644553c019c5 74 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
Paulhd182 2:644553c019c5 75 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
Paulhd182 2:644553c019c5 76 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
Paulhd182 2:644553c019c5 77 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
Paulhd182 2:644553c019c5 78 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
Paulhd182 2:644553c019c5 79
Paulhd182 2:644553c019c5 80 // configure reset and clock control registers
Paulhd182 2:644553c019c5 81
Paulhd182 2:644553c019c5 82 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
Paulhd182 2:644553c019c5 83 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
Paulhd182 2:644553c019c5 84
Paulhd182 2:644553c019c5 85 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
Paulhd182 2:644553c019c5 86
Paulhd182 2:644553c019c5 87 } else {
Paulhd182 2:644553c019c5 88
Paulhd182 2:644553c019c5 89 printf("pinmap not found for peripheral\n");
Paulhd182 2:644553c019c5 90 }
Paulhd182 2:644553c019c5 91
Paulhd182 2:644553c019c5 92 // configure general purpose timer 3 or 4
Paulhd182 2:644553c019c5 93
Paulhd182 2:644553c019c5 94 TIM->CR1 = 0x0000; // counter disable
Paulhd182 2:644553c019c5 95 TIM->CR2 = 0x0000; // reset master mode selection
Paulhd182 2:644553c019c5 96 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
Paulhd182 2:644553c019c5 97 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
Paulhd182 2:644553c019c5 98 TIM->CCMR2 = 0x0000; // reset capture mode register 2
Paulhd182 2:644553c019c5 99 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
Paulhd182 2:644553c019c5 100 TIM->CNT = 0x0000; // reset counter value
Paulhd182 2:644553c019c5 101 TIM->ARR = 0xFFFF; // auto reload register
Paulhd182 2:644553c019c5 102 TIM->CR1 = TIM_CR1_CEN; // counter enable
Paulhd182 2:644553c019c5 103 }
Paulhd182 2:644553c019c5 104
Paulhd182 2:644553c019c5 105 EncoderCounter::~EncoderCounter() {}
Paulhd182 2:644553c019c5 106
Paulhd182 2:644553c019c5 107 /**
Paulhd182 2:644553c019c5 108 * Resets the counter value to zero.
Paulhd182 2:644553c019c5 109 */
Paulhd182 2:644553c019c5 110 void EncoderCounter::reset() {
Paulhd182 2:644553c019c5 111
Paulhd182 2:644553c019c5 112 TIM->CNT = 0x0000;
Paulhd182 2:644553c019c5 113 }
Paulhd182 2:644553c019c5 114
Paulhd182 2:644553c019c5 115 /**
Paulhd182 2:644553c019c5 116 * Resets the counter value to a given offset value.
Paulhd182 2:644553c019c5 117 * @param offset the offset value to reset the counter to.
Paulhd182 2:644553c019c5 118 */
Paulhd182 2:644553c019c5 119 void EncoderCounter::reset(short offset) {
Paulhd182 2:644553c019c5 120
Paulhd182 2:644553c019c5 121 TIM->CNT = -offset;
Paulhd182 2:644553c019c5 122 }
Paulhd182 2:644553c019c5 123
Paulhd182 2:644553c019c5 124 /**
Paulhd182 2:644553c019c5 125 * Reads the quadrature encoder counter value.
Paulhd182 2:644553c019c5 126 * @return the quadrature encoder counter as a signed 16-bit integer value.
Paulhd182 2:644553c019c5 127 */
Paulhd182 2:644553c019c5 128 short EncoderCounter::read() {
Paulhd182 2:644553c019c5 129
Paulhd182 2:644553c019c5 130 return (short)(-TIM->CNT);
Paulhd182 2:644553c019c5 131 }
Paulhd182 2:644553c019c5 132
Paulhd182 2:644553c019c5 133 /**
Paulhd182 2:644553c019c5 134 * The empty operator is a shorthand notation of the <code>read()</code> method.
Paulhd182 2:644553c019c5 135 */
Paulhd182 2:644553c019c5 136 EncoderCounter::operator short() {
Paulhd182 2:644553c019c5 137
Paulhd182 2:644553c019c5 138 return read();
Paulhd182 2:644553c019c5 139 }