Maxim Integrated / MAX77643/2

MAX77642/MAX77643 Ultra Configurable PMIC Featuring 93% Peak Efficiency Single-Inductor, 3-Output BuckBoost, 1-LDO for Long Battery Life Mbed Driver

MAX77643_2.cpp@0:55f664e8c56c, 21 months ago (annotated)

Committer:
Okan Sahin
Date:
Fri Aug 26 14:20:53 2022 +0300
Revision:
0:55f664e8c56c
Initial Commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Okan Sahin 0:55f664e8c56c 1 /*******************************************************************************
Okan Sahin 0:55f664e8c56c 2 * Copyright(C) Analog Devices Inc., All Rights Reserved.
Okan Sahin 0:55f664e8c56c 3 *
Okan Sahin 0:55f664e8c56c 4 * Permission is hereby granted, free of charge, to any person obtaining a
Okan Sahin 0:55f664e8c56c 5 * copy of this software and associated documentation files(the "Software"),
Okan Sahin 0:55f664e8c56c 6 * to deal in the Software without restriction, including without limitation
Okan Sahin 0:55f664e8c56c 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Okan Sahin 0:55f664e8c56c 8 * and/or sell copies of the Software, and to permit persons to whom the
Okan Sahin 0:55f664e8c56c 9 * Software is furnished to do so, subject to the following conditions:
Okan Sahin 0:55f664e8c56c 10 *
Okan Sahin 0:55f664e8c56c 11 * The above copyright notice and this permission notice shall be included
Okan Sahin 0:55f664e8c56c 12 * in all copies or substantial portions of the Software.
Okan Sahin 0:55f664e8c56c 13 *
Okan Sahin 0:55f664e8c56c 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Okan Sahin 0:55f664e8c56c 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Okan Sahin 0:55f664e8c56c 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Okan Sahin 0:55f664e8c56c 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Okan Sahin 0:55f664e8c56c 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Okan Sahin 0:55f664e8c56c 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Okan Sahin 0:55f664e8c56c 20 * OTHER DEALINGS IN THE SOFTWARE.
Okan Sahin 0:55f664e8c56c 21 *
Okan Sahin 0:55f664e8c56c 22 * Except as contained in this notice, the name of Analog Devices Inc.
Okan Sahin 0:55f664e8c56c 23 * shall not be used except as stated in the Analog Devices Inc.
Okan Sahin 0:55f664e8c56c 24 * Branding Policy.
Okan Sahin 0:55f664e8c56c 25 *
Okan Sahin 0:55f664e8c56c 26 * The mere transfer of this software does not imply any licenses
Okan Sahin 0:55f664e8c56c 27 * of trade secrets, proprietary technology, copyrights, patents,
Okan Sahin 0:55f664e8c56c 28 * trademarks, maskwork rights, or any other form of intellectual
Okan Sahin 0:55f664e8c56c 29 * property whatsoever. Analog Devices Inc.retains all ownership rights.
Okan Sahin 0:55f664e8c56c 30 *******************************************************************************
Okan Sahin 0:55f664e8c56c 31 */
Okan Sahin 0:55f664e8c56c 32
Okan Sahin 0:55f664e8c56c 33 #include <Thread.h>
Okan Sahin 0:55f664e8c56c 34 #include "MAX77643_2.h"
Okan Sahin 0:55f664e8c56c 35 #include <math.h>
Okan Sahin 0:55f664e8c56c 36
Okan Sahin 0:55f664e8c56c 37 #define POST_INTR_WORK_SIGNAL_ID 0x1
Okan Sahin 0:55f664e8c56c 38 #define TO_UINT8 0xFF
Okan Sahin 0:55f664e8c56c 39 #define TO_UINT16 0xFFFF
Okan Sahin 0:55f664e8c56c 40
Okan Sahin 0:55f664e8c56c 41 MAX77643_2::MAX77643_2(I2C *i2c, PinName IRQPin)
Okan Sahin 0:55f664e8c56c 42 {
Okan Sahin 0:55f664e8c56c 43 if (i2c == NULL)
Okan Sahin 0:55f664e8c56c 44 return;
Okan Sahin 0:55f664e8c56c 45
Okan Sahin 0:55f664e8c56c 46 i2c_handler = i2c;
Okan Sahin 0:55f664e8c56c 47 interrupt_handler_list = new handler[INTM_NUM_OF_BIT] {};
Okan Sahin 0:55f664e8c56c 48
Okan Sahin 0:55f664e8c56c 49 if (IRQPin != NC) {
Okan Sahin 0:55f664e8c56c 50 irq_disable_all();
Okan Sahin 0:55f664e8c56c 51 post_intr_work_thread = new Thread();
Okan Sahin 0:55f664e8c56c 52 post_intr_work_thread->start(Callback<void()>(this, &MAX77643_2::post_interrupt_work));
Okan Sahin 0:55f664e8c56c 53
Okan Sahin 0:55f664e8c56c 54 this->irq_pin = new InterruptIn(IRQPin);
Okan Sahin 0:55f664e8c56c 55 this->irq_pin->fall(Callback<void()>(this, &MAX77643_2::interrupt_handler));
Okan Sahin 0:55f664e8c56c 56 this->irq_pin->enable_irq();
Okan Sahin 0:55f664e8c56c 57 } else {
Okan Sahin 0:55f664e8c56c 58 this->irq_pin = NULL;
Okan Sahin 0:55f664e8c56c 59 }
Okan Sahin 0:55f664e8c56c 60 }
Okan Sahin 0:55f664e8c56c 61
Okan Sahin 0:55f664e8c56c 62 MAX77643_2::~MAX77643_2()
Okan Sahin 0:55f664e8c56c 63 {
Okan Sahin 0:55f664e8c56c 64 if (post_intr_work_thread)
Okan Sahin 0:55f664e8c56c 65 delete post_intr_work_thread;
Okan Sahin 0:55f664e8c56c 66
Okan Sahin 0:55f664e8c56c 67 if (irq_pin)
Okan Sahin 0:55f664e8c56c 68 delete irq_pin;
Okan Sahin 0:55f664e8c56c 69
Okan Sahin 0:55f664e8c56c 70 if (interrupt_handler_list)
Okan Sahin 0:55f664e8c56c 71 delete [] interrupt_handler_list;
Okan Sahin 0:55f664e8c56c 72 }
Okan Sahin 0:55f664e8c56c 73
Okan Sahin 0:55f664e8c56c 74 int MAX77643_2::read_register(uint8_t reg, uint8_t *value)
Okan Sahin 0:55f664e8c56c 75 {
Okan Sahin 0:55f664e8c56c 76 int rtn_val;
Okan Sahin 0:55f664e8c56c 77
Okan Sahin 0:55f664e8c56c 78 if (value == NULL)
Okan Sahin 0:55f664e8c56c 79 return MAX77643_2_VALUE_NULL;
Okan Sahin 0:55f664e8c56c 80
Okan Sahin 0:55f664e8c56c 81 rtn_val = i2c_handler->write(MAX77643_2_I2C_ADDRESS, (const char *)&reg, 1, true);
Okan Sahin 0:55f664e8c56c 82 if (rtn_val != 0)
Okan Sahin 0:55f664e8c56c 83 return MAX77643_2_WRITE_DATA_FAILED;
Okan Sahin 0:55f664e8c56c 84 rtn_val = i2c_handler->read(MAX77643_2_I2C_ADDRESS, (char *) value, 1, false);
Okan Sahin 0:55f664e8c56c 85 if (rtn_val < 0)
Okan Sahin 0:55f664e8c56c 86 return MAX77643_2_READ_DATA_FAILED;
Okan Sahin 0:55f664e8c56c 87
Okan Sahin 0:55f664e8c56c 88 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 89 }
Okan Sahin 0:55f664e8c56c 90
Okan Sahin 0:55f664e8c56c 91 int MAX77643_2::write_register(uint8_t reg, const uint8_t *value)
Okan Sahin 0:55f664e8c56c 92 {
Okan Sahin 0:55f664e8c56c 93 int rtn_val;
Okan Sahin 0:55f664e8c56c 94 unsigned char local_data[2];
Okan Sahin 0:55f664e8c56c 95
Okan Sahin 0:55f664e8c56c 96 if (value == NULL)
Okan Sahin 0:55f664e8c56c 97 return MAX77643_2_VALUE_NULL;
Okan Sahin 0:55f664e8c56c 98
Okan Sahin 0:55f664e8c56c 99 local_data[0] = reg;
Okan Sahin 0:55f664e8c56c 100
Okan Sahin 0:55f664e8c56c 101 memcpy(&local_data[1], value, 1);
Okan Sahin 0:55f664e8c56c 102
Okan Sahin 0:55f664e8c56c 103 rtn_val = i2c_handler->write(MAX77643_2_I2C_ADDRESS, (const char *)local_data, sizeof(local_data));
Okan Sahin 0:55f664e8c56c 104 if (rtn_val != MAX77643_2_NO_ERROR)
Okan Sahin 0:55f664e8c56c 105 return MAX77643_2_WRITE_DATA_FAILED;
Okan Sahin 0:55f664e8c56c 106
Okan Sahin 0:55f664e8c56c 107 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 108 }
Okan Sahin 0:55f664e8c56c 109
Okan Sahin 0:55f664e8c56c 110 #define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \
Okan Sahin 0:55f664e8c56c 111 int ret_val; \
Okan Sahin 0:55f664e8c56c 112 ret_val = read_register(address, (uint8_t *)&(reg_name)); \
Okan Sahin 0:55f664e8c56c 113 if (ret_val) { \
Okan Sahin 0:55f664e8c56c 114 return ret_val; \
Okan Sahin 0:55f664e8c56c 115 } \
Okan Sahin 0:55f664e8c56c 116 bit_field_name = value; \
Okan Sahin 0:55f664e8c56c 117 ret_val = write_register(address, (uint8_t *)&(reg_name)); \
Okan Sahin 0:55f664e8c56c 118 if (ret_val) { \
Okan Sahin 0:55f664e8c56c 119 return ret_val; \
Okan Sahin 0:55f664e8c56c 120 }
Okan Sahin 0:55f664e8c56c 121
Okan Sahin 0:55f664e8c56c 122 int MAX77643_2::get_ercflag(reg_bit_ercflag_t bit_field, uint8_t *flag)
Okan Sahin 0:55f664e8c56c 123 {
Okan Sahin 0:55f664e8c56c 124 int ret;
Okan Sahin 0:55f664e8c56c 125 reg_ercflag_t reg_ercflag = {0};
Okan Sahin 0:55f664e8c56c 126
Okan Sahin 0:55f664e8c56c 127 ret = read_register(ERCFLAG, (uint8_t *)&(reg_ercflag));
Okan Sahin 0:55f664e8c56c 128 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 129
Okan Sahin 0:55f664e8c56c 130 switch (bit_field)
Okan Sahin 0:55f664e8c56c 131 {
Okan Sahin 0:55f664e8c56c 132 case ERCFLAG_TOVLD:
Okan Sahin 0:55f664e8c56c 133 *flag = (uint8_t)reg_ercflag.bits.tovld;
Okan Sahin 0:55f664e8c56c 134 break;
Okan Sahin 0:55f664e8c56c 135 case ERCFLAG_INOVLO:
Okan Sahin 0:55f664e8c56c 136 *flag = (uint8_t)reg_ercflag.bits.inovlo;
Okan Sahin 0:55f664e8c56c 137 break;
Okan Sahin 0:55f664e8c56c 138 case ERCFLAG_INUVLO:
Okan Sahin 0:55f664e8c56c 139 *flag = (uint8_t)reg_ercflag.bits.inuvlo;
Okan Sahin 0:55f664e8c56c 140 break;
Okan Sahin 0:55f664e8c56c 141 case ERCFLAG_MRST_F:
Okan Sahin 0:55f664e8c56c 142 *flag = (uint8_t)reg_ercflag.bits.mrst_f;
Okan Sahin 0:55f664e8c56c 143 break;
Okan Sahin 0:55f664e8c56c 144 case ERCFLAG_SFT_OFF_F:
Okan Sahin 0:55f664e8c56c 145 *flag = (uint8_t)reg_ercflag.bits.sft_off_f;
Okan Sahin 0:55f664e8c56c 146 break;
Okan Sahin 0:55f664e8c56c 147 case ERCFLAG_SFT_CRST_F:
Okan Sahin 0:55f664e8c56c 148 *flag = (uint8_t)reg_ercflag.bits.sft_crst_f;
Okan Sahin 0:55f664e8c56c 149 break;
Okan Sahin 0:55f664e8c56c 150 case ERCFLAG_WDT_EXP_F:
Okan Sahin 0:55f664e8c56c 151 *flag = (uint8_t)reg_ercflag.bits.wdt_exp_f;
Okan Sahin 0:55f664e8c56c 152 break;
Okan Sahin 0:55f664e8c56c 153 case ERCFLAG_SBB_FAULT_F:
Okan Sahin 0:55f664e8c56c 154 *flag = (uint8_t)reg_ercflag.bits.sbb_fault_f;
Okan Sahin 0:55f664e8c56c 155 break;
Okan Sahin 0:55f664e8c56c 156 default:
Okan Sahin 0:55f664e8c56c 157 ret = MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 158 break;
Okan Sahin 0:55f664e8c56c 159 }
Okan Sahin 0:55f664e8c56c 160
Okan Sahin 0:55f664e8c56c 161 return ret;
Okan Sahin 0:55f664e8c56c 162 }
Okan Sahin 0:55f664e8c56c 163
Okan Sahin 0:55f664e8c56c 164 int MAX77643_2::get_stat_glbl(reg_bit_stat_glbl_t bit_field, uint8_t *status)
Okan Sahin 0:55f664e8c56c 165 {
Okan Sahin 0:55f664e8c56c 166 int ret;
Okan Sahin 0:55f664e8c56c 167 reg_stat_glbl_t reg_stat_glbl = {0};
Okan Sahin 0:55f664e8c56c 168
Okan Sahin 0:55f664e8c56c 169 ret = read_register(STAT_GLBL, (uint8_t *)&(reg_stat_glbl));
Okan Sahin 0:55f664e8c56c 170 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 171
Okan Sahin 0:55f664e8c56c 172 switch (bit_field)
Okan Sahin 0:55f664e8c56c 173 {
Okan Sahin 0:55f664e8c56c 174 case STAT_GLBL_STAT_IRQ:
Okan Sahin 0:55f664e8c56c 175 *status = (uint8_t)reg_stat_glbl.bits.stat_irq;
Okan Sahin 0:55f664e8c56c 176 break;
Okan Sahin 0:55f664e8c56c 177 case STAT_GLBL_STAT_EN:
Okan Sahin 0:55f664e8c56c 178 *status = (uint8_t)reg_stat_glbl.bits.stat_en;
Okan Sahin 0:55f664e8c56c 179 break;
Okan Sahin 0:55f664e8c56c 180 case STAT_GLBL_TJAL1_S:
Okan Sahin 0:55f664e8c56c 181 *status = (uint8_t)reg_stat_glbl.bits.tjal1_s;
Okan Sahin 0:55f664e8c56c 182 break;
Okan Sahin 0:55f664e8c56c 183 case STAT_GLBL_TJAL2_S:
Okan Sahin 0:55f664e8c56c 184 *status = (uint8_t)reg_stat_glbl.bits.tjal2_s;
Okan Sahin 0:55f664e8c56c 185 break;
Okan Sahin 0:55f664e8c56c 186 case STAT_GLBL_DOD_S:
Okan Sahin 0:55f664e8c56c 187 *status = (uint8_t)reg_stat_glbl.bits.dod_s;
Okan Sahin 0:55f664e8c56c 188 break;
Okan Sahin 0:55f664e8c56c 189 case STAT_GLBL_BOK:
Okan Sahin 0:55f664e8c56c 190 *status = (uint8_t)reg_stat_glbl.bits.bok;
Okan Sahin 0:55f664e8c56c 191 break;
Okan Sahin 0:55f664e8c56c 192 case STAT_GLBL_DIDM:
Okan Sahin 0:55f664e8c56c 193 *status = (uint8_t)reg_stat_glbl.bits.didm;
Okan Sahin 0:55f664e8c56c 194 break;
Okan Sahin 0:55f664e8c56c 195 default:
Okan Sahin 0:55f664e8c56c 196 ret = MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 197 break;
Okan Sahin 0:55f664e8c56c 198 }
Okan Sahin 0:55f664e8c56c 199
Okan Sahin 0:55f664e8c56c 200 return ret;
Okan Sahin 0:55f664e8c56c 201 }
Okan Sahin 0:55f664e8c56c 202
Okan Sahin 0:55f664e8c56c 203 int MAX77643_2::set_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t maskBit)
Okan Sahin 0:55f664e8c56c 204 {
Okan Sahin 0:55f664e8c56c 205 int ret;
Okan Sahin 0:55f664e8c56c 206 uint8_t reg_addr = 0;
Okan Sahin 0:55f664e8c56c 207 reg_intm_glbl0_t reg_intm_glbl0 = {0};
Okan Sahin 0:55f664e8c56c 208 reg_intm_glbl1_t reg_intm_glbl1 = {0};
Okan Sahin 0:55f664e8c56c 209
Okan Sahin 0:55f664e8c56c 210 //INTM_GLBL0 (0x04) and INTM_GLBL1 (0x05)
Okan Sahin 0:55f664e8c56c 211 reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x04;
Okan Sahin 0:55f664e8c56c 212
Okan Sahin 0:55f664e8c56c 213 if (reg_addr == INTM_GLBL0)
Okan Sahin 0:55f664e8c56c 214 ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
Okan Sahin 0:55f664e8c56c 215 else if (reg_addr == INTM_GLBL1)
Okan Sahin 0:55f664e8c56c 216 ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
Okan Sahin 0:55f664e8c56c 217 else
Okan Sahin 0:55f664e8c56c 218 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 219
Okan Sahin 0:55f664e8c56c 220 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 221
Okan Sahin 0:55f664e8c56c 222 switch (bit_field)
Okan Sahin 0:55f664e8c56c 223 {
Okan Sahin 0:55f664e8c56c 224 case INTM_GLBL0_GPI0_FM:
Okan Sahin 0:55f664e8c56c 225 reg_intm_glbl0.bits.gpi0_fm = maskBit;
Okan Sahin 0:55f664e8c56c 226 break;
Okan Sahin 0:55f664e8c56c 227 case INTM_GLBL0_GPI0_RM:
Okan Sahin 0:55f664e8c56c 228 reg_intm_glbl0.bits.gpi0_rm = maskBit;
Okan Sahin 0:55f664e8c56c 229 break;
Okan Sahin 0:55f664e8c56c 230 case INTM_GLBL0_nEN_FM:
Okan Sahin 0:55f664e8c56c 231 reg_intm_glbl0.bits.nen_fm = maskBit;
Okan Sahin 0:55f664e8c56c 232 break;
Okan Sahin 0:55f664e8c56c 233 case INTM_GLBL0_nEN_RM:
Okan Sahin 0:55f664e8c56c 234 reg_intm_glbl0.bits.nen_rm = maskBit;
Okan Sahin 0:55f664e8c56c 235 break;
Okan Sahin 0:55f664e8c56c 236 case INTM_GLBL0_TJAL1_RM:
Okan Sahin 0:55f664e8c56c 237 reg_intm_glbl0.bits.tjal1_rm = maskBit;
Okan Sahin 0:55f664e8c56c 238 break;
Okan Sahin 0:55f664e8c56c 239 case INTM_GLBL0_TJAL2_RM:
Okan Sahin 0:55f664e8c56c 240 reg_intm_glbl0.bits.tjal2_rm = maskBit;
Okan Sahin 0:55f664e8c56c 241 break;
Okan Sahin 0:55f664e8c56c 242 case INTM_GLBL0_DOD_RM:
Okan Sahin 0:55f664e8c56c 243 reg_intm_glbl0.bits.dod_rm = maskBit;
Okan Sahin 0:55f664e8c56c 244 break;
Okan Sahin 0:55f664e8c56c 245 case INTM_GLBL1_GPI1_FM:
Okan Sahin 0:55f664e8c56c 246 reg_intm_glbl1.bits.gpi1_fm = maskBit;
Okan Sahin 0:55f664e8c56c 247 break;
Okan Sahin 0:55f664e8c56c 248 case INTM_GLBL1_GPI1_RM:
Okan Sahin 0:55f664e8c56c 249 reg_intm_glbl1.bits.gpi1_rm = maskBit;
Okan Sahin 0:55f664e8c56c 250 break;
Okan Sahin 0:55f664e8c56c 251 case INTM_GLBL1_SBB0_FM:
Okan Sahin 0:55f664e8c56c 252 reg_intm_glbl1.bits.sbb0_fm = maskBit;
Okan Sahin 0:55f664e8c56c 253 break;
Okan Sahin 0:55f664e8c56c 254 case INTM_GLBL1_SBB1_FM:
Okan Sahin 0:55f664e8c56c 255 reg_intm_glbl1.bits.sbb1_fm = maskBit;
Okan Sahin 0:55f664e8c56c 256 break;
Okan Sahin 0:55f664e8c56c 257 case INTM_GLBL1_SBB2_FM:
Okan Sahin 0:55f664e8c56c 258 reg_intm_glbl1.bits.sbb2_fm = maskBit;
Okan Sahin 0:55f664e8c56c 259 break;
Okan Sahin 0:55f664e8c56c 260 case INTM_GLBL1_LDO_M:
Okan Sahin 0:55f664e8c56c 261 reg_intm_glbl1.bits.ldo_m = maskBit;
Okan Sahin 0:55f664e8c56c 262 break;
Okan Sahin 0:55f664e8c56c 263 default:
Okan Sahin 0:55f664e8c56c 264 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 265 break;
Okan Sahin 0:55f664e8c56c 266 }
Okan Sahin 0:55f664e8c56c 267
Okan Sahin 0:55f664e8c56c 268 if (reg_addr == INTM_GLBL0)
Okan Sahin 0:55f664e8c56c 269 return write_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
Okan Sahin 0:55f664e8c56c 270 else if (reg_addr == INTM_GLBL1)
Okan Sahin 0:55f664e8c56c 271 return write_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
Okan Sahin 0:55f664e8c56c 272 else
Okan Sahin 0:55f664e8c56c 273 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 274 }
Okan Sahin 0:55f664e8c56c 275
Okan Sahin 0:55f664e8c56c 276 int MAX77643_2::get_interrupt_mask(reg_bit_int_mask_t bit_field, uint8_t *maskBit)
Okan Sahin 0:55f664e8c56c 277 {
Okan Sahin 0:55f664e8c56c 278 int ret;
Okan Sahin 0:55f664e8c56c 279 uint8_t reg_addr = 0;
Okan Sahin 0:55f664e8c56c 280 reg_intm_glbl0_t reg_intm_glbl0 = {0};
Okan Sahin 0:55f664e8c56c 281 reg_intm_glbl1_t reg_intm_glbl1 = {0};
Okan Sahin 0:55f664e8c56c 282
Okan Sahin 0:55f664e8c56c 283 //INTM_GLBL0 (0x04) and INTM_GLBL1 (0x05)
Okan Sahin 0:55f664e8c56c 284 reg_addr = (uint8_t)floor((static_cast<uint8_t>(bit_field)) / 8) + 0x04;
Okan Sahin 0:55f664e8c56c 285
Okan Sahin 0:55f664e8c56c 286 if (reg_addr == INTM_GLBL0)
Okan Sahin 0:55f664e8c56c 287 ret = read_register(INTM_GLBL0, (uint8_t *)&(reg_intm_glbl0));
Okan Sahin 0:55f664e8c56c 288 else if (reg_addr == INTM_GLBL1)
Okan Sahin 0:55f664e8c56c 289 ret = read_register(INTM_GLBL1, (uint8_t *)&(reg_intm_glbl1));
Okan Sahin 0:55f664e8c56c 290 else
Okan Sahin 0:55f664e8c56c 291 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 292
Okan Sahin 0:55f664e8c56c 293 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 294
Okan Sahin 0:55f664e8c56c 295 switch (bit_field)
Okan Sahin 0:55f664e8c56c 296 {
Okan Sahin 0:55f664e8c56c 297 case INTM_GLBL0_GPI0_FM:
Okan Sahin 0:55f664e8c56c 298 *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_fm;
Okan Sahin 0:55f664e8c56c 299 break;
Okan Sahin 0:55f664e8c56c 300 case INTM_GLBL0_GPI0_RM:
Okan Sahin 0:55f664e8c56c 301 *maskBit = (uint8_t)reg_intm_glbl0.bits.gpi0_rm;
Okan Sahin 0:55f664e8c56c 302 break;
Okan Sahin 0:55f664e8c56c 303 case INTM_GLBL0_nEN_FM:
Okan Sahin 0:55f664e8c56c 304 *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_fm;
Okan Sahin 0:55f664e8c56c 305 break;
Okan Sahin 0:55f664e8c56c 306 case INTM_GLBL0_nEN_RM:
Okan Sahin 0:55f664e8c56c 307 *maskBit = (uint8_t)reg_intm_glbl0.bits.nen_rm;
Okan Sahin 0:55f664e8c56c 308 break;
Okan Sahin 0:55f664e8c56c 309 case INTM_GLBL0_TJAL1_RM:
Okan Sahin 0:55f664e8c56c 310 *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal1_rm;
Okan Sahin 0:55f664e8c56c 311 break;
Okan Sahin 0:55f664e8c56c 312 case INTM_GLBL0_TJAL2_RM:
Okan Sahin 0:55f664e8c56c 313 *maskBit = (uint8_t)reg_intm_glbl0.bits.tjal2_rm;
Okan Sahin 0:55f664e8c56c 314 break;
Okan Sahin 0:55f664e8c56c 315 case INTM_GLBL0_DOD_RM:
Okan Sahin 0:55f664e8c56c 316 *maskBit = (uint8_t)reg_intm_glbl0.bits.dod_rm;
Okan Sahin 0:55f664e8c56c 317 break;
Okan Sahin 0:55f664e8c56c 318 case INTM_GLBL1_GPI1_FM:
Okan Sahin 0:55f664e8c56c 319 *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_fm;
Okan Sahin 0:55f664e8c56c 320 break;
Okan Sahin 0:55f664e8c56c 321 case INTM_GLBL1_GPI1_RM:
Okan Sahin 0:55f664e8c56c 322 *maskBit = (uint8_t)reg_intm_glbl1.bits.gpi1_rm;
Okan Sahin 0:55f664e8c56c 323 break;
Okan Sahin 0:55f664e8c56c 324 case INTM_GLBL1_SBB0_FM:
Okan Sahin 0:55f664e8c56c 325 *maskBit = (uint8_t)reg_intm_glbl1.bits.sbb0_fm;
Okan Sahin 0:55f664e8c56c 326 break;
Okan Sahin 0:55f664e8c56c 327 case INTM_GLBL1_SBB1_FM:
Okan Sahin 0:55f664e8c56c 328 *maskBit = (uint8_t)reg_intm_glbl1.bits.sbb1_fm;
Okan Sahin 0:55f664e8c56c 329 break;
Okan Sahin 0:55f664e8c56c 330 case INTM_GLBL1_SBB2_FM:
Okan Sahin 0:55f664e8c56c 331 *maskBit = (uint8_t)reg_intm_glbl1.bits.sbb2_fm;
Okan Sahin 0:55f664e8c56c 332 break;
Okan Sahin 0:55f664e8c56c 333 case INTM_GLBL1_LDO_M:
Okan Sahin 0:55f664e8c56c 334 *maskBit = (uint8_t)reg_intm_glbl1.bits.ldo_m;
Okan Sahin 0:55f664e8c56c 335 break;
Okan Sahin 0:55f664e8c56c 336 default:
Okan Sahin 0:55f664e8c56c 337 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 338 break;
Okan Sahin 0:55f664e8c56c 339 }
Okan Sahin 0:55f664e8c56c 340
Okan Sahin 0:55f664e8c56c 341 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 342 }
Okan Sahin 0:55f664e8c56c 343
Okan Sahin 0:55f664e8c56c 344 int MAX77643_2::set_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t config)
Okan Sahin 0:55f664e8c56c 345 {
Okan Sahin 0:55f664e8c56c 346 int ret;
Okan Sahin 0:55f664e8c56c 347 reg_cnfg_glbl0_t reg_cnfg_glbl0 = {0};
Okan Sahin 0:55f664e8c56c 348
Okan Sahin 0:55f664e8c56c 349 ret = read_register(CNFG_GLBL0, (uint8_t *)&(reg_cnfg_glbl0));
Okan Sahin 0:55f664e8c56c 350 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 351
Okan Sahin 0:55f664e8c56c 352 switch (bit_field)
Okan Sahin 0:55f664e8c56c 353 {
Okan Sahin 0:55f664e8c56c 354 case CNFG_GLBL0_SFT_CTRL:
Okan Sahin 0:55f664e8c56c 355 reg_cnfg_glbl0.bits.sft_ctrl = config;
Okan Sahin 0:55f664e8c56c 356 break;
Okan Sahin 0:55f664e8c56c 357 case CNFG_GLBL0_DBEN_nEN:
Okan Sahin 0:55f664e8c56c 358 reg_cnfg_glbl0.bits.dben_nen = config;
Okan Sahin 0:55f664e8c56c 359 break;
Okan Sahin 0:55f664e8c56c 360 case CNFG_GLBL0_nEN_MODE:
Okan Sahin 0:55f664e8c56c 361 reg_cnfg_glbl0.bits.nen_mode = config;
Okan Sahin 0:55f664e8c56c 362 break;
Okan Sahin 0:55f664e8c56c 363 case CNFG_GLBL0_SBIA_LPM:
Okan Sahin 0:55f664e8c56c 364 reg_cnfg_glbl0.bits.sbia_lpm = config;
Okan Sahin 0:55f664e8c56c 365 break;
Okan Sahin 0:55f664e8c56c 366 case CNFG_GLBL0_T_MRST:
Okan Sahin 0:55f664e8c56c 367 reg_cnfg_glbl0.bits.t_mrst = config;
Okan Sahin 0:55f664e8c56c 368 break;
Okan Sahin 0:55f664e8c56c 369 case CNFG_GLBL0_PU_DIS:
Okan Sahin 0:55f664e8c56c 370 reg_cnfg_glbl0.bits.pu_dis = config;
Okan Sahin 0:55f664e8c56c 371 break;
Okan Sahin 0:55f664e8c56c 372 default:
Okan Sahin 0:55f664e8c56c 373 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 374 break;
Okan Sahin 0:55f664e8c56c 375 }
Okan Sahin 0:55f664e8c56c 376
Okan Sahin 0:55f664e8c56c 377 return write_register(CNFG_GLBL0, (uint8_t *)&(reg_cnfg_glbl0));
Okan Sahin 0:55f664e8c56c 378 }
Okan Sahin 0:55f664e8c56c 379
Okan Sahin 0:55f664e8c56c 380 int MAX77643_2::get_cnfg_glbl0(reg_bit_cnfg_glbl0_t bit_field, uint8_t *config)
Okan Sahin 0:55f664e8c56c 381 {
Okan Sahin 0:55f664e8c56c 382 int ret;
Okan Sahin 0:55f664e8c56c 383 reg_cnfg_glbl0_t reg_cnfg_glbl0 = {0};
Okan Sahin 0:55f664e8c56c 384
Okan Sahin 0:55f664e8c56c 385 ret = read_register(CNFG_GLBL0, (uint8_t *)&(reg_cnfg_glbl0));
Okan Sahin 0:55f664e8c56c 386 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 387
Okan Sahin 0:55f664e8c56c 388 switch (bit_field)
Okan Sahin 0:55f664e8c56c 389 {
Okan Sahin 0:55f664e8c56c 390 case CNFG_GLBL0_SFT_CTRL:
Okan Sahin 0:55f664e8c56c 391 *config = (uint8_t)reg_cnfg_glbl0.bits.sft_ctrl;
Okan Sahin 0:55f664e8c56c 392 break;
Okan Sahin 0:55f664e8c56c 393 case CNFG_GLBL0_DBEN_nEN:
Okan Sahin 0:55f664e8c56c 394 *config = (uint8_t)reg_cnfg_glbl0.bits.dben_nen;
Okan Sahin 0:55f664e8c56c 395 break;
Okan Sahin 0:55f664e8c56c 396 case CNFG_GLBL0_nEN_MODE:
Okan Sahin 0:55f664e8c56c 397 *config = (uint8_t)reg_cnfg_glbl0.bits.nen_mode;
Okan Sahin 0:55f664e8c56c 398 break;
Okan Sahin 0:55f664e8c56c 399 case CNFG_GLBL0_SBIA_LPM:
Okan Sahin 0:55f664e8c56c 400 *config = (uint8_t)reg_cnfg_glbl0.bits.sbia_lpm;
Okan Sahin 0:55f664e8c56c 401 break;
Okan Sahin 0:55f664e8c56c 402 case CNFG_GLBL0_T_MRST:
Okan Sahin 0:55f664e8c56c 403 *config = (uint8_t)reg_cnfg_glbl0.bits.t_mrst;
Okan Sahin 0:55f664e8c56c 404 break;
Okan Sahin 0:55f664e8c56c 405 case CNFG_GLBL0_PU_DIS:
Okan Sahin 0:55f664e8c56c 406 *config = (uint8_t)reg_cnfg_glbl0.bits.pu_dis;
Okan Sahin 0:55f664e8c56c 407 break;
Okan Sahin 0:55f664e8c56c 408 default:
Okan Sahin 0:55f664e8c56c 409 ret = MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 410 break;
Okan Sahin 0:55f664e8c56c 411 }
Okan Sahin 0:55f664e8c56c 412
Okan Sahin 0:55f664e8c56c 413 return ret;
Okan Sahin 0:55f664e8c56c 414 }
Okan Sahin 0:55f664e8c56c 415
Okan Sahin 0:55f664e8c56c 416 int MAX77643_2::set_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t config)
Okan Sahin 0:55f664e8c56c 417 {
Okan Sahin 0:55f664e8c56c 418 int ret;
Okan Sahin 0:55f664e8c56c 419 reg_cnfg_glbl1_t reg_cnfg_glbl1;
Okan Sahin 0:55f664e8c56c 420
Okan Sahin 0:55f664e8c56c 421 ret = read_register(CNFG_GLBL1, (uint8_t *)&(reg_cnfg_glbl1));
Okan Sahin 0:55f664e8c56c 422 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 423
Okan Sahin 0:55f664e8c56c 424 switch (bit_field)
Okan Sahin 0:55f664e8c56c 425 {
Okan Sahin 0:55f664e8c56c 426 case CNFG_GLBL1_AUTO_WKT:
Okan Sahin 0:55f664e8c56c 427 reg_cnfg_glbl1.bits.auto_wkt = config;
Okan Sahin 0:55f664e8c56c 428 break;
Okan Sahin 0:55f664e8c56c 429 case CNFG_GLBL1_SBB_F_SHUTDN:
Okan Sahin 0:55f664e8c56c 430 reg_cnfg_glbl1.bits.sbb_f_shutdn = config;
Okan Sahin 0:55f664e8c56c 431 break;
Okan Sahin 0:55f664e8c56c 432 default:
Okan Sahin 0:55f664e8c56c 433 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 434 break;
Okan Sahin 0:55f664e8c56c 435 }
Okan Sahin 0:55f664e8c56c 436
Okan Sahin 0:55f664e8c56c 437 return write_register(CNFG_GLBL1, (uint8_t *)&(reg_cnfg_glbl1));
Okan Sahin 0:55f664e8c56c 438 }
Okan Sahin 0:55f664e8c56c 439
Okan Sahin 0:55f664e8c56c 440 int MAX77643_2::get_cnfg_glbl1(reg_bit_cnfg_glbl1_t bit_field, uint8_t *config)
Okan Sahin 0:55f664e8c56c 441 {
Okan Sahin 0:55f664e8c56c 442 int ret;
Okan Sahin 0:55f664e8c56c 443 reg_cnfg_glbl1_t reg_cnfg_glbl1 = {0};
Okan Sahin 0:55f664e8c56c 444
Okan Sahin 0:55f664e8c56c 445 ret = read_register(CNFG_GLBL1, (uint8_t *)&(reg_cnfg_glbl1));
Okan Sahin 0:55f664e8c56c 446 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 447
Okan Sahin 0:55f664e8c56c 448 switch (bit_field)
Okan Sahin 0:55f664e8c56c 449 {
Okan Sahin 0:55f664e8c56c 450 case CNFG_GLBL1_AUTO_WKT:
Okan Sahin 0:55f664e8c56c 451 *config = (uint8_t)reg_cnfg_glbl1.bits.auto_wkt;
Okan Sahin 0:55f664e8c56c 452 break;
Okan Sahin 0:55f664e8c56c 453 case CNFG_GLBL1_SBB_F_SHUTDN:
Okan Sahin 0:55f664e8c56c 454 *config = (uint8_t)reg_cnfg_glbl1.bits.sbb_f_shutdn;
Okan Sahin 0:55f664e8c56c 455 break;
Okan Sahin 0:55f664e8c56c 456 default:
Okan Sahin 0:55f664e8c56c 457 ret = MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 458 break;
Okan Sahin 0:55f664e8c56c 459 }
Okan Sahin 0:55f664e8c56c 460
Okan Sahin 0:55f664e8c56c 461 return ret;
Okan Sahin 0:55f664e8c56c 462 }
Okan Sahin 0:55f664e8c56c 463
Okan Sahin 0:55f664e8c56c 464 int MAX77643_2::set_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t config)
Okan Sahin 0:55f664e8c56c 465 {
Okan Sahin 0:55f664e8c56c 466 int ret;
Okan Sahin 0:55f664e8c56c 467 reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
Okan Sahin 0:55f664e8c56c 468 reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
Okan Sahin 0:55f664e8c56c 469
Okan Sahin 0:55f664e8c56c 470 if (channel == 0)
Okan Sahin 0:55f664e8c56c 471 {
Okan Sahin 0:55f664e8c56c 472 ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
Okan Sahin 0:55f664e8c56c 473 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 474
Okan Sahin 0:55f664e8c56c 475 switch (bit_field)
Okan Sahin 0:55f664e8c56c 476 {
Okan Sahin 0:55f664e8c56c 477 case CNFG_GPIO_DIR:
Okan Sahin 0:55f664e8c56c 478 reg_cnfg_gpio0.bits.gpo_dir = config;
Okan Sahin 0:55f664e8c56c 479 break;
Okan Sahin 0:55f664e8c56c 480 case CNFG_GPIO_DI:
Okan Sahin 0:55f664e8c56c 481 reg_cnfg_gpio0.bits.gpo_di = config;
Okan Sahin 0:55f664e8c56c 482 break;
Okan Sahin 0:55f664e8c56c 483 case CNFG_GPIO_DRV:
Okan Sahin 0:55f664e8c56c 484 reg_cnfg_gpio0.bits.gpo_drv = config;
Okan Sahin 0:55f664e8c56c 485 break;
Okan Sahin 0:55f664e8c56c 486 case CNFG_GPIO_DO:
Okan Sahin 0:55f664e8c56c 487 reg_cnfg_gpio0.bits.gpo_do = config;
Okan Sahin 0:55f664e8c56c 488 break;
Okan Sahin 0:55f664e8c56c 489 case CNFG_GPIO_DBEN_GPI:
Okan Sahin 0:55f664e8c56c 490 reg_cnfg_gpio0.bits.dben_gpi = config;
Okan Sahin 0:55f664e8c56c 491 break;
Okan Sahin 0:55f664e8c56c 492 case CNFG_GPIO_ALT_GPIO:
Okan Sahin 0:55f664e8c56c 493 reg_cnfg_gpio0.bits.alt_gpio = config;
Okan Sahin 0:55f664e8c56c 494 break;
Okan Sahin 0:55f664e8c56c 495 default:
Okan Sahin 0:55f664e8c56c 496 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 497 break;
Okan Sahin 0:55f664e8c56c 498 }
Okan Sahin 0:55f664e8c56c 499
Okan Sahin 0:55f664e8c56c 500 return write_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
Okan Sahin 0:55f664e8c56c 501 }
Okan Sahin 0:55f664e8c56c 502 else if (channel == 1)
Okan Sahin 0:55f664e8c56c 503 {
Okan Sahin 0:55f664e8c56c 504 ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
Okan Sahin 0:55f664e8c56c 505 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 506
Okan Sahin 0:55f664e8c56c 507 switch (bit_field)
Okan Sahin 0:55f664e8c56c 508 {
Okan Sahin 0:55f664e8c56c 509 case CNFG_GPIO_DIR:
Okan Sahin 0:55f664e8c56c 510 reg_cnfg_gpio1.bits.gpo_dir = config;
Okan Sahin 0:55f664e8c56c 511 break;
Okan Sahin 0:55f664e8c56c 512 case CNFG_GPIO_DI:
Okan Sahin 0:55f664e8c56c 513 reg_cnfg_gpio1.bits.gpo_di = config;
Okan Sahin 0:55f664e8c56c 514 break;
Okan Sahin 0:55f664e8c56c 515 case CNFG_GPIO_DRV:
Okan Sahin 0:55f664e8c56c 516 reg_cnfg_gpio1.bits.gpo_drv = config;
Okan Sahin 0:55f664e8c56c 517 break;
Okan Sahin 0:55f664e8c56c 518 case CNFG_GPIO_DO:
Okan Sahin 0:55f664e8c56c 519 reg_cnfg_gpio1.bits.gpo_do = config;
Okan Sahin 0:55f664e8c56c 520 break;
Okan Sahin 0:55f664e8c56c 521 case CNFG_GPIO_DBEN_GPI:
Okan Sahin 0:55f664e8c56c 522 reg_cnfg_gpio1.bits.dben_gpi = config;
Okan Sahin 0:55f664e8c56c 523 break;
Okan Sahin 0:55f664e8c56c 524 case CNFG_GPIO_ALT_GPIO:
Okan Sahin 0:55f664e8c56c 525 reg_cnfg_gpio1.bits.alt_gpio = config;
Okan Sahin 0:55f664e8c56c 526 break;
Okan Sahin 0:55f664e8c56c 527 default:
Okan Sahin 0:55f664e8c56c 528 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 529 break;
Okan Sahin 0:55f664e8c56c 530 }
Okan Sahin 0:55f664e8c56c 531
Okan Sahin 0:55f664e8c56c 532 return write_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
Okan Sahin 0:55f664e8c56c 533 }
Okan Sahin 0:55f664e8c56c 534 else {
Okan Sahin 0:55f664e8c56c 535 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 536 }
Okan Sahin 0:55f664e8c56c 537 }
Okan Sahin 0:55f664e8c56c 538
Okan Sahin 0:55f664e8c56c 539 int MAX77643_2::get_cnfg_gpio(reg_bit_cnfg_gpio_t bit_field, uint8_t channel, uint8_t *config)
Okan Sahin 0:55f664e8c56c 540 {
Okan Sahin 0:55f664e8c56c 541 int ret;
Okan Sahin 0:55f664e8c56c 542 reg_cnfg_gpio0_t reg_cnfg_gpio0 = {0};
Okan Sahin 0:55f664e8c56c 543 reg_cnfg_gpio1_t reg_cnfg_gpio1 = {0};
Okan Sahin 0:55f664e8c56c 544
Okan Sahin 0:55f664e8c56c 545 if (channel == 0)
Okan Sahin 0:55f664e8c56c 546 {
Okan Sahin 0:55f664e8c56c 547 ret = read_register(CNFG_GPIO0, (uint8_t *)&(reg_cnfg_gpio0));
Okan Sahin 0:55f664e8c56c 548 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 549
Okan Sahin 0:55f664e8c56c 550 switch (bit_field)
Okan Sahin 0:55f664e8c56c 551 {
Okan Sahin 0:55f664e8c56c 552 case CNFG_GPIO_DIR:
Okan Sahin 0:55f664e8c56c 553 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_dir;
Okan Sahin 0:55f664e8c56c 554 break;
Okan Sahin 0:55f664e8c56c 555 case CNFG_GPIO_DI:
Okan Sahin 0:55f664e8c56c 556 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_di;
Okan Sahin 0:55f664e8c56c 557 break;
Okan Sahin 0:55f664e8c56c 558 case CNFG_GPIO_DRV:
Okan Sahin 0:55f664e8c56c 559 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_drv;
Okan Sahin 0:55f664e8c56c 560 break;
Okan Sahin 0:55f664e8c56c 561 case CNFG_GPIO_DO:
Okan Sahin 0:55f664e8c56c 562 *config = (uint8_t)reg_cnfg_gpio0.bits.gpo_do;
Okan Sahin 0:55f664e8c56c 563 break;
Okan Sahin 0:55f664e8c56c 564 case CNFG_GPIO_DBEN_GPI:
Okan Sahin 0:55f664e8c56c 565 *config = (uint8_t)reg_cnfg_gpio0.bits.dben_gpi;
Okan Sahin 0:55f664e8c56c 566 break;
Okan Sahin 0:55f664e8c56c 567 case CNFG_GPIO_ALT_GPIO:
Okan Sahin 0:55f664e8c56c 568 *config = (uint8_t)reg_cnfg_gpio0.bits.alt_gpio;
Okan Sahin 0:55f664e8c56c 569 break;
Okan Sahin 0:55f664e8c56c 570 default:
Okan Sahin 0:55f664e8c56c 571 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 572 break;
Okan Sahin 0:55f664e8c56c 573 }
Okan Sahin 0:55f664e8c56c 574 }
Okan Sahin 0:55f664e8c56c 575 else if (channel == 1)
Okan Sahin 0:55f664e8c56c 576 {
Okan Sahin 0:55f664e8c56c 577 ret = read_register(CNFG_GPIO1, (uint8_t *)&(reg_cnfg_gpio1));
Okan Sahin 0:55f664e8c56c 578 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 579
Okan Sahin 0:55f664e8c56c 580 switch (bit_field)
Okan Sahin 0:55f664e8c56c 581 {
Okan Sahin 0:55f664e8c56c 582 case CNFG_GPIO_DIR:
Okan Sahin 0:55f664e8c56c 583 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_dir;
Okan Sahin 0:55f664e8c56c 584 break;
Okan Sahin 0:55f664e8c56c 585 case CNFG_GPIO_DI:
Okan Sahin 0:55f664e8c56c 586 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_di;
Okan Sahin 0:55f664e8c56c 587 break;
Okan Sahin 0:55f664e8c56c 588 case CNFG_GPIO_DRV:
Okan Sahin 0:55f664e8c56c 589 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_drv;
Okan Sahin 0:55f664e8c56c 590 break;
Okan Sahin 0:55f664e8c56c 591 case CNFG_GPIO_DO:
Okan Sahin 0:55f664e8c56c 592 *config = (uint8_t)reg_cnfg_gpio1.bits.gpo_do;
Okan Sahin 0:55f664e8c56c 593 break;
Okan Sahin 0:55f664e8c56c 594 case CNFG_GPIO_DBEN_GPI:
Okan Sahin 0:55f664e8c56c 595 *config = (uint8_t)reg_cnfg_gpio1.bits.dben_gpi;
Okan Sahin 0:55f664e8c56c 596 break;
Okan Sahin 0:55f664e8c56c 597 case CNFG_GPIO_ALT_GPIO:
Okan Sahin 0:55f664e8c56c 598 *config = (uint8_t)reg_cnfg_gpio1.bits.alt_gpio;
Okan Sahin 0:55f664e8c56c 599 break;
Okan Sahin 0:55f664e8c56c 600 default:
Okan Sahin 0:55f664e8c56c 601 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 602 break;
Okan Sahin 0:55f664e8c56c 603 }
Okan Sahin 0:55f664e8c56c 604 }
Okan Sahin 0:55f664e8c56c 605 else {
Okan Sahin 0:55f664e8c56c 606 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 607 }
Okan Sahin 0:55f664e8c56c 608
Okan Sahin 0:55f664e8c56c 609 return ret;
Okan Sahin 0:55f664e8c56c 610 }
Okan Sahin 0:55f664e8c56c 611
Okan Sahin 0:55f664e8c56c 612 int MAX77643_2::get_cid(void) {
Okan Sahin 0:55f664e8c56c 613 char rbuf[1] = {0};
Okan Sahin 0:55f664e8c56c 614 int ret;
Okan Sahin 0:55f664e8c56c 615
Okan Sahin 0:55f664e8c56c 616 ret = read_register(CID, (uint8_t *)&(rbuf));
Okan Sahin 0:55f664e8c56c 617 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 618
Okan Sahin 0:55f664e8c56c 619 return *rbuf;
Okan Sahin 0:55f664e8c56c 620 }
Okan Sahin 0:55f664e8c56c 621
Okan Sahin 0:55f664e8c56c 622 int MAX77643_2::set_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t config)
Okan Sahin 0:55f664e8c56c 623 {
Okan Sahin 0:55f664e8c56c 624 int ret;
Okan Sahin 0:55f664e8c56c 625 reg_cnfg_wdt_t reg_cnfg_wdt = {0};
Okan Sahin 0:55f664e8c56c 626
Okan Sahin 0:55f664e8c56c 627 ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
Okan Sahin 0:55f664e8c56c 628 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 629
Okan Sahin 0:55f664e8c56c 630 switch (bit_field)
Okan Sahin 0:55f664e8c56c 631 {
Okan Sahin 0:55f664e8c56c 632 case CNFG_WDT_WDT_LOCK:
Okan Sahin 0:55f664e8c56c 633 reg_cnfg_wdt.bits.wdt_lock = config;
Okan Sahin 0:55f664e8c56c 634 break;
Okan Sahin 0:55f664e8c56c 635 case CNFG_WDT_WDT_EN:
Okan Sahin 0:55f664e8c56c 636 reg_cnfg_wdt.bits.wdt_en = config;
Okan Sahin 0:55f664e8c56c 637 break;
Okan Sahin 0:55f664e8c56c 638 case CNFG_WDT_WDT_CLR:
Okan Sahin 0:55f664e8c56c 639 reg_cnfg_wdt.bits.wdt_clr = config;
Okan Sahin 0:55f664e8c56c 640 break;
Okan Sahin 0:55f664e8c56c 641 case CNFG_WDT_WDT_MODE:
Okan Sahin 0:55f664e8c56c 642 reg_cnfg_wdt.bits.wdt_mode = config;
Okan Sahin 0:55f664e8c56c 643 break;
Okan Sahin 0:55f664e8c56c 644 case CNFG_WDT_WDT_PER:
Okan Sahin 0:55f664e8c56c 645 reg_cnfg_wdt.bits.wdt_per = config;
Okan Sahin 0:55f664e8c56c 646 break;
Okan Sahin 0:55f664e8c56c 647 default:
Okan Sahin 0:55f664e8c56c 648 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 649 break;
Okan Sahin 0:55f664e8c56c 650 }
Okan Sahin 0:55f664e8c56c 651
Okan Sahin 0:55f664e8c56c 652 return write_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
Okan Sahin 0:55f664e8c56c 653 }
Okan Sahin 0:55f664e8c56c 654
Okan Sahin 0:55f664e8c56c 655 int MAX77643_2::get_cnfg_wdt(reg_bit_cnfg_wdt_t bit_field, uint8_t *config)
Okan Sahin 0:55f664e8c56c 656 {
Okan Sahin 0:55f664e8c56c 657 int ret;
Okan Sahin 0:55f664e8c56c 658 reg_cnfg_wdt_t reg_cnfg_wdt = {0};
Okan Sahin 0:55f664e8c56c 659
Okan Sahin 0:55f664e8c56c 660 ret = read_register(CNFG_WDT, (uint8_t *)&(reg_cnfg_wdt));
Okan Sahin 0:55f664e8c56c 661 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 662
Okan Sahin 0:55f664e8c56c 663 switch (bit_field)
Okan Sahin 0:55f664e8c56c 664 {
Okan Sahin 0:55f664e8c56c 665 case CNFG_WDT_WDT_LOCK:
Okan Sahin 0:55f664e8c56c 666 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_lock;
Okan Sahin 0:55f664e8c56c 667 break;
Okan Sahin 0:55f664e8c56c 668 case CNFG_WDT_WDT_EN:
Okan Sahin 0:55f664e8c56c 669 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_en;
Okan Sahin 0:55f664e8c56c 670 break;
Okan Sahin 0:55f664e8c56c 671 case CNFG_WDT_WDT_CLR:
Okan Sahin 0:55f664e8c56c 672 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_clr;
Okan Sahin 0:55f664e8c56c 673 break;
Okan Sahin 0:55f664e8c56c 674 case CNFG_WDT_WDT_MODE:
Okan Sahin 0:55f664e8c56c 675 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_mode;
Okan Sahin 0:55f664e8c56c 676 break;
Okan Sahin 0:55f664e8c56c 677 case CNFG_WDT_WDT_PER:
Okan Sahin 0:55f664e8c56c 678 *config = (uint8_t)reg_cnfg_wdt.bits.wdt_per;
Okan Sahin 0:55f664e8c56c 679 break;
Okan Sahin 0:55f664e8c56c 680 default:
Okan Sahin 0:55f664e8c56c 681 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 682 break;
Okan Sahin 0:55f664e8c56c 683 }
Okan Sahin 0:55f664e8c56c 684
Okan Sahin 0:55f664e8c56c 685 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 686 }
Okan Sahin 0:55f664e8c56c 687
Okan Sahin 0:55f664e8c56c 688 int MAX77643_2::set_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t config)
Okan Sahin 0:55f664e8c56c 689 {
Okan Sahin 0:55f664e8c56c 690 int ret;
Okan Sahin 0:55f664e8c56c 691 reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
Okan Sahin 0:55f664e8c56c 692
Okan Sahin 0:55f664e8c56c 693 ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
Okan Sahin 0:55f664e8c56c 694 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 695
Okan Sahin 0:55f664e8c56c 696 switch (bit_field)
Okan Sahin 0:55f664e8c56c 697 {
Okan Sahin 0:55f664e8c56c 698 case CNFG_SBB_TOP_DRV_SBB:
Okan Sahin 0:55f664e8c56c 699 reg_cnfg_sbb_top.bits.drv_sbb = config;
Okan Sahin 0:55f664e8c56c 700 break;
Okan Sahin 0:55f664e8c56c 701 case CNFG_SBB_TOP_DIS_LPM:
Okan Sahin 0:55f664e8c56c 702 reg_cnfg_sbb_top.bits.dis_lpm = config;
Okan Sahin 0:55f664e8c56c 703 break;
Okan Sahin 0:55f664e8c56c 704 default:
Okan Sahin 0:55f664e8c56c 705 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 706 break;
Okan Sahin 0:55f664e8c56c 707 }
Okan Sahin 0:55f664e8c56c 708
Okan Sahin 0:55f664e8c56c 709 return write_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
Okan Sahin 0:55f664e8c56c 710 }
Okan Sahin 0:55f664e8c56c 711
Okan Sahin 0:55f664e8c56c 712 int MAX77643_2::get_cnfg_sbb_top(reg_bit_cnfg_sbb_top_t bit_field, uint8_t *config)
Okan Sahin 0:55f664e8c56c 713 {
Okan Sahin 0:55f664e8c56c 714 int ret;
Okan Sahin 0:55f664e8c56c 715 reg_cnfg_sbb_top_t reg_cnfg_sbb_top = {0};
Okan Sahin 0:55f664e8c56c 716
Okan Sahin 0:55f664e8c56c 717 ret = read_register(CNFG_SBB_TOP, (uint8_t *)&(reg_cnfg_sbb_top));
Okan Sahin 0:55f664e8c56c 718 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 719
Okan Sahin 0:55f664e8c56c 720 switch (bit_field)
Okan Sahin 0:55f664e8c56c 721 {
Okan Sahin 0:55f664e8c56c 722 case CNFG_SBB_TOP_DRV_SBB:
Okan Sahin 0:55f664e8c56c 723 *config = (uint8_t)reg_cnfg_sbb_top.bits.drv_sbb;
Okan Sahin 0:55f664e8c56c 724 break;
Okan Sahin 0:55f664e8c56c 725 case CNFG_SBB_TOP_DIS_LPM:
Okan Sahin 0:55f664e8c56c 726 *config = (uint8_t)reg_cnfg_sbb_top.bits.dis_lpm;
Okan Sahin 0:55f664e8c56c 727 break;
Okan Sahin 0:55f664e8c56c 728 default:
Okan Sahin 0:55f664e8c56c 729 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 730 break;
Okan Sahin 0:55f664e8c56c 731 }
Okan Sahin 0:55f664e8c56c 732
Okan Sahin 0:55f664e8c56c 733 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 734 }
Okan Sahin 0:55f664e8c56c 735
Okan Sahin 0:55f664e8c56c 736 int MAX77643_2::set_tv_sbb(uint8_t channel, float voltV)
Okan Sahin 0:55f664e8c56c 737 {
Okan Sahin 0:55f664e8c56c 738 uint8_t value;
Okan Sahin 0:55f664e8c56c 739 reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
Okan Sahin 0:55f664e8c56c 740 reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
Okan Sahin 0:55f664e8c56c 741 reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
Okan Sahin 0:55f664e8c56c 742 float voltmV = voltV * 1000;
Okan Sahin 0:55f664e8c56c 743
Okan Sahin 0:55f664e8c56c 744 if (voltmV < 500) voltmV = 500;
Okan Sahin 0:55f664e8c56c 745 else if (voltmV > 5500) voltmV = 5500;
Okan Sahin 0:55f664e8c56c 746
Okan Sahin 0:55f664e8c56c 747 value = (voltmV - 500) / 25;
Okan Sahin 0:55f664e8c56c 748
Okan Sahin 0:55f664e8c56c 749 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 750 SET_BIT_FIELD(CNFG_SBB0_A, reg_cnfg_sbb0_a, reg_cnfg_sbb0_a.bits.tv_sbb0, value);
Okan Sahin 0:55f664e8c56c 751 }
Okan Sahin 0:55f664e8c56c 752 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 753 SET_BIT_FIELD(CNFG_SBB1_A, reg_cnfg_sbb1_a, reg_cnfg_sbb1_a.bits.tv_sbb1, value);
Okan Sahin 0:55f664e8c56c 754 }
Okan Sahin 0:55f664e8c56c 755 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 756 SET_BIT_FIELD(CNFG_SBB2_A, reg_cnfg_sbb2_a, reg_cnfg_sbb2_a.bits.tv_sbb2, value);
Okan Sahin 0:55f664e8c56c 757 }
Okan Sahin 0:55f664e8c56c 758 else {
Okan Sahin 0:55f664e8c56c 759 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 760 }
Okan Sahin 0:55f664e8c56c 761
Okan Sahin 0:55f664e8c56c 762 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 763 }
Okan Sahin 0:55f664e8c56c 764
Okan Sahin 0:55f664e8c56c 765 int MAX77643_2::get_tv_sbb(uint8_t channel, float *voltV)
Okan Sahin 0:55f664e8c56c 766 {
Okan Sahin 0:55f664e8c56c 767 int ret;
Okan Sahin 0:55f664e8c56c 768 uint8_t bit_value;
Okan Sahin 0:55f664e8c56c 769 reg_cnfg_sbb0_a_t reg_cnfg_sbb0_a = {0};
Okan Sahin 0:55f664e8c56c 770 reg_cnfg_sbb1_a_t reg_cnfg_sbb1_a = {0};
Okan Sahin 0:55f664e8c56c 771 reg_cnfg_sbb2_a_t reg_cnfg_sbb2_a = {0};
Okan Sahin 0:55f664e8c56c 772
Okan Sahin 0:55f664e8c56c 773 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 774 ret = read_register(CNFG_SBB0_A, (uint8_t *)&(reg_cnfg_sbb0_a));
Okan Sahin 0:55f664e8c56c 775 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 776
Okan Sahin 0:55f664e8c56c 777 bit_value = (uint8_t)reg_cnfg_sbb0_a.bits.tv_sbb0;
Okan Sahin 0:55f664e8c56c 778 }
Okan Sahin 0:55f664e8c56c 779 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 780 ret = read_register(CNFG_SBB1_A, (uint8_t *)&(reg_cnfg_sbb1_a));
Okan Sahin 0:55f664e8c56c 781 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 782
Okan Sahin 0:55f664e8c56c 783 bit_value = (uint8_t)reg_cnfg_sbb1_a.bits.tv_sbb1;
Okan Sahin 0:55f664e8c56c 784 }
Okan Sahin 0:55f664e8c56c 785 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 786 ret = read_register(CNFG_SBB2_A, (uint8_t *)&(reg_cnfg_sbb2_a));
Okan Sahin 0:55f664e8c56c 787 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 788
Okan Sahin 0:55f664e8c56c 789 bit_value = (uint8_t)reg_cnfg_sbb2_a.bits.tv_sbb2;
Okan Sahin 0:55f664e8c56c 790 }
Okan Sahin 0:55f664e8c56c 791 else return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 792
Okan Sahin 0:55f664e8c56c 793 if (bit_value > 200) bit_value = 200;
Okan Sahin 0:55f664e8c56c 794 *voltV = (bit_value * 0.025f) + 0.5f;
Okan Sahin 0:55f664e8c56c 795
Okan Sahin 0:55f664e8c56c 796 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 797 }
Okan Sahin 0:55f664e8c56c 798
Okan Sahin 0:55f664e8c56c 799 int MAX77643_2::set_op_mode(uint8_t channel, decode_op_mode_t mode)
Okan Sahin 0:55f664e8c56c 800 {
Okan Sahin 0:55f664e8c56c 801 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:55f664e8c56c 802 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:55f664e8c56c 803 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:55f664e8c56c 804
Okan Sahin 0:55f664e8c56c 805 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 806 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.op_mode0, mode);
Okan Sahin 0:55f664e8c56c 807 }
Okan Sahin 0:55f664e8c56c 808 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 809 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.op_mode1, mode);
Okan Sahin 0:55f664e8c56c 810 }
Okan Sahin 0:55f664e8c56c 811 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 812 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.op_mode2, mode);
Okan Sahin 0:55f664e8c56c 813 }
Okan Sahin 0:55f664e8c56c 814 else {
Okan Sahin 0:55f664e8c56c 815 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 816 }
Okan Sahin 0:55f664e8c56c 817
Okan Sahin 0:55f664e8c56c 818 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 819 }
Okan Sahin 0:55f664e8c56c 820
Okan Sahin 0:55f664e8c56c 821 int MAX77643_2::get_op_mode(uint8_t channel, decode_op_mode_t *mode)
Okan Sahin 0:55f664e8c56c 822 {
Okan Sahin 0:55f664e8c56c 823 int ret;
Okan Sahin 0:55f664e8c56c 824 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:55f664e8c56c 825 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:55f664e8c56c 826 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:55f664e8c56c 827
Okan Sahin 0:55f664e8c56c 828 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 829 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
Okan Sahin 0:55f664e8c56c 830 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 831
Okan Sahin 0:55f664e8c56c 832 *mode = (decode_op_mode_t)reg_cnfg_sbb0_b.bits.op_mode0;
Okan Sahin 0:55f664e8c56c 833 }
Okan Sahin 0:55f664e8c56c 834 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 835 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
Okan Sahin 0:55f664e8c56c 836 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 837
Okan Sahin 0:55f664e8c56c 838 *mode = (decode_op_mode_t)reg_cnfg_sbb1_b.bits.op_mode1;
Okan Sahin 0:55f664e8c56c 839 }
Okan Sahin 0:55f664e8c56c 840 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 841 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
Okan Sahin 0:55f664e8c56c 842 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 843
Okan Sahin 0:55f664e8c56c 844 *mode = (decode_op_mode_t)reg_cnfg_sbb2_b.bits.op_mode2;
Okan Sahin 0:55f664e8c56c 845 }
Okan Sahin 0:55f664e8c56c 846 else {
Okan Sahin 0:55f664e8c56c 847 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 848 }
Okan Sahin 0:55f664e8c56c 849
Okan Sahin 0:55f664e8c56c 850 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 851 }
Okan Sahin 0:55f664e8c56c 852
Okan Sahin 0:55f664e8c56c 853 int MAX77643_2::set_ip_sbb(uint8_t channel, decode_ip_sbb_t ip_sbb)
Okan Sahin 0:55f664e8c56c 854 {
Okan Sahin 0:55f664e8c56c 855 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:55f664e8c56c 856 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:55f664e8c56c 857 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:55f664e8c56c 858
Okan Sahin 0:55f664e8c56c 859 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 860 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ip_sbb0, ip_sbb);
Okan Sahin 0:55f664e8c56c 861 }
Okan Sahin 0:55f664e8c56c 862 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 863 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ip_sbb1, ip_sbb);
Okan Sahin 0:55f664e8c56c 864 }
Okan Sahin 0:55f664e8c56c 865 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 866 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ip_sbb2, ip_sbb);
Okan Sahin 0:55f664e8c56c 867 }
Okan Sahin 0:55f664e8c56c 868 else {
Okan Sahin 0:55f664e8c56c 869 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 870 }
Okan Sahin 0:55f664e8c56c 871
Okan Sahin 0:55f664e8c56c 872 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 873 }
Okan Sahin 0:55f664e8c56c 874
Okan Sahin 0:55f664e8c56c 875 int MAX77643_2::get_ip_sbb(uint8_t channel, decode_ip_sbb_t *ip_sbb)
Okan Sahin 0:55f664e8c56c 876 {
Okan Sahin 0:55f664e8c56c 877 int ret;
Okan Sahin 0:55f664e8c56c 878 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:55f664e8c56c 879 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:55f664e8c56c 880 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:55f664e8c56c 881
Okan Sahin 0:55f664e8c56c 882 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 883 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
Okan Sahin 0:55f664e8c56c 884 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 885
Okan Sahin 0:55f664e8c56c 886 *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb0_b.bits.ip_sbb0;
Okan Sahin 0:55f664e8c56c 887 }
Okan Sahin 0:55f664e8c56c 888 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 889 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
Okan Sahin 0:55f664e8c56c 890 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 891
Okan Sahin 0:55f664e8c56c 892 *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb1_b.bits.ip_sbb1;
Okan Sahin 0:55f664e8c56c 893 }
Okan Sahin 0:55f664e8c56c 894 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 895 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
Okan Sahin 0:55f664e8c56c 896 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 897
Okan Sahin 0:55f664e8c56c 898 *ip_sbb = (decode_ip_sbb_t)reg_cnfg_sbb2_b.bits.ip_sbb2;
Okan Sahin 0:55f664e8c56c 899 }
Okan Sahin 0:55f664e8c56c 900 else {
Okan Sahin 0:55f664e8c56c 901 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 902 }
Okan Sahin 0:55f664e8c56c 903
Okan Sahin 0:55f664e8c56c 904 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 905 }
Okan Sahin 0:55f664e8c56c 906
Okan Sahin 0:55f664e8c56c 907 int MAX77643_2::set_ade_sbb(uint8_t channel, decode_ade_sbb_t ade_sbb)
Okan Sahin 0:55f664e8c56c 908 {
Okan Sahin 0:55f664e8c56c 909 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:55f664e8c56c 910 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:55f664e8c56c 911 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:55f664e8c56c 912
Okan Sahin 0:55f664e8c56c 913 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 914 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.ade_sbb0, ade_sbb);
Okan Sahin 0:55f664e8c56c 915 }
Okan Sahin 0:55f664e8c56c 916 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 917 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.ade_sbb1, ade_sbb);
Okan Sahin 0:55f664e8c56c 918 }
Okan Sahin 0:55f664e8c56c 919 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 920 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.ade_sbb2, ade_sbb);
Okan Sahin 0:55f664e8c56c 921 }
Okan Sahin 0:55f664e8c56c 922 else {
Okan Sahin 0:55f664e8c56c 923 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 924 }
Okan Sahin 0:55f664e8c56c 925
Okan Sahin 0:55f664e8c56c 926 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 927 }
Okan Sahin 0:55f664e8c56c 928
Okan Sahin 0:55f664e8c56c 929 int MAX77643_2::get_ade_sbb(uint8_t channel, decode_ade_sbb_t *ade_sbb)
Okan Sahin 0:55f664e8c56c 930 {
Okan Sahin 0:55f664e8c56c 931 int ret;
Okan Sahin 0:55f664e8c56c 932 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:55f664e8c56c 933 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:55f664e8c56c 934 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:55f664e8c56c 935
Okan Sahin 0:55f664e8c56c 936 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 937 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
Okan Sahin 0:55f664e8c56c 938 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 939
Okan Sahin 0:55f664e8c56c 940 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb0_b.bits.ade_sbb0;
Okan Sahin 0:55f664e8c56c 941 }
Okan Sahin 0:55f664e8c56c 942 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 943 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
Okan Sahin 0:55f664e8c56c 944 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 945
Okan Sahin 0:55f664e8c56c 946 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb1_b.bits.ade_sbb1;
Okan Sahin 0:55f664e8c56c 947 }
Okan Sahin 0:55f664e8c56c 948 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 949 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
Okan Sahin 0:55f664e8c56c 950 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 951
Okan Sahin 0:55f664e8c56c 952 *ade_sbb = (decode_ade_sbb_t)reg_cnfg_sbb2_b.bits.ade_sbb2;
Okan Sahin 0:55f664e8c56c 953 }
Okan Sahin 0:55f664e8c56c 954 else {
Okan Sahin 0:55f664e8c56c 955 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 956 }
Okan Sahin 0:55f664e8c56c 957
Okan Sahin 0:55f664e8c56c 958 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 959 }
Okan Sahin 0:55f664e8c56c 960
Okan Sahin 0:55f664e8c56c 961 int MAX77643_2::set_en_sbb(uint8_t channel, decode_en_sbb_t en_sbb)
Okan Sahin 0:55f664e8c56c 962 {
Okan Sahin 0:55f664e8c56c 963 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:55f664e8c56c 964 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:55f664e8c56c 965 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:55f664e8c56c 966
Okan Sahin 0:55f664e8c56c 967 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 968 SET_BIT_FIELD(CNFG_SBB0_B, reg_cnfg_sbb0_b, reg_cnfg_sbb0_b.bits.en_sbb0, en_sbb);
Okan Sahin 0:55f664e8c56c 969 }
Okan Sahin 0:55f664e8c56c 970 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 971 SET_BIT_FIELD(CNFG_SBB1_B, reg_cnfg_sbb1_b, reg_cnfg_sbb1_b.bits.en_sbb1, en_sbb);
Okan Sahin 0:55f664e8c56c 972 }
Okan Sahin 0:55f664e8c56c 973 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 974 SET_BIT_FIELD(CNFG_SBB2_B, reg_cnfg_sbb2_b, reg_cnfg_sbb2_b.bits.en_sbb2, en_sbb);
Okan Sahin 0:55f664e8c56c 975 }
Okan Sahin 0:55f664e8c56c 976 else {
Okan Sahin 0:55f664e8c56c 977 return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 978 }
Okan Sahin 0:55f664e8c56c 979
Okan Sahin 0:55f664e8c56c 980 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 981 }
Okan Sahin 0:55f664e8c56c 982
Okan Sahin 0:55f664e8c56c 983 int MAX77643_2::get_en_sbb(uint8_t channel, decode_en_sbb_t *en_sbb)
Okan Sahin 0:55f664e8c56c 984 {
Okan Sahin 0:55f664e8c56c 985 int ret;
Okan Sahin 0:55f664e8c56c 986 reg_cnfg_sbb0_b_t reg_cnfg_sbb0_b = {0};
Okan Sahin 0:55f664e8c56c 987 reg_cnfg_sbb1_b_t reg_cnfg_sbb1_b = {0};
Okan Sahin 0:55f664e8c56c 988 reg_cnfg_sbb2_b_t reg_cnfg_sbb2_b = {0};
Okan Sahin 0:55f664e8c56c 989
Okan Sahin 0:55f664e8c56c 990 if (channel == 0) {
Okan Sahin 0:55f664e8c56c 991 ret = read_register(CNFG_SBB0_B, (uint8_t *)&(reg_cnfg_sbb0_b));
Okan Sahin 0:55f664e8c56c 992 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 993
Okan Sahin 0:55f664e8c56c 994 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb0_b.bits.en_sbb0;
Okan Sahin 0:55f664e8c56c 995 }
Okan Sahin 0:55f664e8c56c 996 else if (channel == 1) {
Okan Sahin 0:55f664e8c56c 997 ret = read_register(CNFG_SBB1_B, (uint8_t *)&(reg_cnfg_sbb1_b));
Okan Sahin 0:55f664e8c56c 998 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 999
Okan Sahin 0:55f664e8c56c 1000 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb1_b.bits.en_sbb1;
Okan Sahin 0:55f664e8c56c 1001 }
Okan Sahin 0:55f664e8c56c 1002 else if (channel == 2) {
Okan Sahin 0:55f664e8c56c 1003 ret = read_register(CNFG_SBB2_B, (uint8_t *)&(reg_cnfg_sbb2_b));
Okan Sahin 0:55f664e8c56c 1004 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1005
Okan Sahin 0:55f664e8c56c 1006 *en_sbb = (decode_en_sbb_t)reg_cnfg_sbb2_b.bits.en_sbb2;
Okan Sahin 0:55f664e8c56c 1007 }
Okan Sahin 0:55f664e8c56c 1008 else return MAX77643_2_INVALID_DATA;
Okan Sahin 0:55f664e8c56c 1009
Okan Sahin 0:55f664e8c56c 1010 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1011 }
Okan Sahin 0:55f664e8c56c 1012
Okan Sahin 0:55f664e8c56c 1013 int MAX77643_2::set_tv_sbb_dvs(float voltV)
Okan Sahin 0:55f664e8c56c 1014 {
Okan Sahin 0:55f664e8c56c 1015 uint8_t value;
Okan Sahin 0:55f664e8c56c 1016 reg_cnfg_dvs_sbb0_a_t reg_cnfg_dvs_sbb0_a = {0};
Okan Sahin 0:55f664e8c56c 1017 float voltmV = voltV * 1000;
Okan Sahin 0:55f664e8c56c 1018
Okan Sahin 0:55f664e8c56c 1019 if (voltmV < 500) voltmV = 500;
Okan Sahin 0:55f664e8c56c 1020 else if (voltmV > 5500) voltmV = 5500;
Okan Sahin 0:55f664e8c56c 1021
Okan Sahin 0:55f664e8c56c 1022 value = (voltmV - 500) / 25;
Okan Sahin 0:55f664e8c56c 1023
Okan Sahin 0:55f664e8c56c 1024 SET_BIT_FIELD(CNFG_DVS_SBB0_A, reg_cnfg_dvs_sbb0_a, reg_cnfg_dvs_sbb0_a.bits.tv_sbb0_dvs, value);
Okan Sahin 0:55f664e8c56c 1025 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1026 }
Okan Sahin 0:55f664e8c56c 1027
Okan Sahin 0:55f664e8c56c 1028 int MAX77643_2::get_tv_sbb_dvs(float *voltV)
Okan Sahin 0:55f664e8c56c 1029 {
Okan Sahin 0:55f664e8c56c 1030 int ret;
Okan Sahin 0:55f664e8c56c 1031 uint8_t bit_value;
Okan Sahin 0:55f664e8c56c 1032 reg_cnfg_dvs_sbb0_a_t reg_cnfg_dvs_sbb0_a = {0};
Okan Sahin 0:55f664e8c56c 1033
Okan Sahin 0:55f664e8c56c 1034 ret = read_register(CNFG_DVS_SBB0_A, (uint8_t *)&(reg_cnfg_dvs_sbb0_a));
Okan Sahin 0:55f664e8c56c 1035 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1036
Okan Sahin 0:55f664e8c56c 1037 bit_value = (uint8_t)reg_cnfg_dvs_sbb0_a.bits.tv_sbb0_dvs;
Okan Sahin 0:55f664e8c56c 1038
Okan Sahin 0:55f664e8c56c 1039 if (bit_value > 200) bit_value = 200;
Okan Sahin 0:55f664e8c56c 1040
Okan Sahin 0:55f664e8c56c 1041 *voltV = (bit_value * 0.025f) + 0.5f;
Okan Sahin 0:55f664e8c56c 1042 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1043 }
Okan Sahin 0:55f664e8c56c 1044
Okan Sahin 0:55f664e8c56c 1045 int MAX77643_2::set_tv_ldo(float voltV)
Okan Sahin 0:55f664e8c56c 1046 {
Okan Sahin 0:55f664e8c56c 1047 int ret;
Okan Sahin 0:55f664e8c56c 1048 uint8_t value;
Okan Sahin 0:55f664e8c56c 1049 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
Okan Sahin 0:55f664e8c56c 1050 float voltmV = voltV * 1000;
Okan Sahin 0:55f664e8c56c 1051 const float offsetmV = 1325;
Okan Sahin 0:55f664e8c56c 1052 const float incrementmV = 25;
Okan Sahin 0:55f664e8c56c 1053 float lower_limit_voltmV = 500, upper_limit_voltmV = 3675;
Okan Sahin 0:55f664e8c56c 1054
Okan Sahin 0:55f664e8c56c 1055 ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
Okan Sahin 0:55f664e8c56c 1056 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1057
Okan Sahin 0:55f664e8c56c 1058 if ((uint8_t)reg_cnfg_ldo0_a.bits.tv_ofs_ldo == 1) { // 1.325V Offset
Okan Sahin 0:55f664e8c56c 1059 lower_limit_voltmV += offsetmV;
Okan Sahin 0:55f664e8c56c 1060 upper_limit_voltmV += offsetmV;
Okan Sahin 0:55f664e8c56c 1061 }
Okan Sahin 0:55f664e8c56c 1062
Okan Sahin 0:55f664e8c56c 1063 voltmV = (voltmV < lower_limit_voltmV) ? lower_limit_voltmV : upper_limit_voltmV;
Okan Sahin 0:55f664e8c56c 1064 value = (voltmV - lower_limit_voltmV) / incrementmV;
Okan Sahin 0:55f664e8c56c 1065
Okan Sahin 0:55f664e8c56c 1066 SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ldo0, value);
Okan Sahin 0:55f664e8c56c 1067
Okan Sahin 0:55f664e8c56c 1068 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1069 }
Okan Sahin 0:55f664e8c56c 1070
Okan Sahin 0:55f664e8c56c 1071 int MAX77643_2::get_tv_ldo(float *voltV)
Okan Sahin 0:55f664e8c56c 1072 {
Okan Sahin 0:55f664e8c56c 1073 int ret;
Okan Sahin 0:55f664e8c56c 1074 uint8_t bit_value;
Okan Sahin 0:55f664e8c56c 1075 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
Okan Sahin 0:55f664e8c56c 1076 float lower_limitV = 0.5f;
Okan Sahin 0:55f664e8c56c 1077 const float incrementV = 0.025f;
Okan Sahin 0:55f664e8c56c 1078 const float offsetV = 1.325f;
Okan Sahin 0:55f664e8c56c 1079
Okan Sahin 0:55f664e8c56c 1080 ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
Okan Sahin 0:55f664e8c56c 1081 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1082
Okan Sahin 0:55f664e8c56c 1083 bit_value = (uint8_t)reg_cnfg_ldo0_a.bits.tv_ldo0;
Okan Sahin 0:55f664e8c56c 1084 if ((uint8_t)reg_cnfg_ldo0_a.bits.tv_ofs_ldo == 0) //No Offset
Okan Sahin 0:55f664e8c56c 1085 *voltV = (bit_value * incrementV) + lower_limitV;
Okan Sahin 0:55f664e8c56c 1086 else //1.325V Offset
Okan Sahin 0:55f664e8c56c 1087 *voltV = (bit_value * incrementV) + (lower_limitV + offsetV);
Okan Sahin 0:55f664e8c56c 1088
Okan Sahin 0:55f664e8c56c 1089 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1090 }
Okan Sahin 0:55f664e8c56c 1091
Okan Sahin 0:55f664e8c56c 1092 int MAX77643_2::set_tv_ofs_ldo(decode_tv_ofs_ldo_t offset)
Okan Sahin 0:55f664e8c56c 1093 {
Okan Sahin 0:55f664e8c56c 1094 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
Okan Sahin 0:55f664e8c56c 1095
Okan Sahin 0:55f664e8c56c 1096 SET_BIT_FIELD(CNFG_LDO0_A, reg_cnfg_ldo0_a, reg_cnfg_ldo0_a.bits.tv_ofs_ldo, offset);
Okan Sahin 0:55f664e8c56c 1097
Okan Sahin 0:55f664e8c56c 1098 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1099 }
Okan Sahin 0:55f664e8c56c 1100
Okan Sahin 0:55f664e8c56c 1101 int MAX77643_2::get_tv_ofs_ldo(decode_tv_ofs_ldo_t *offset)
Okan Sahin 0:55f664e8c56c 1102 {
Okan Sahin 0:55f664e8c56c 1103 int ret;
Okan Sahin 0:55f664e8c56c 1104 reg_cnfg_ldo0_a_t reg_cnfg_ldo0_a = {0};
Okan Sahin 0:55f664e8c56c 1105
Okan Sahin 0:55f664e8c56c 1106 ret = read_register(CNFG_LDO0_A, (uint8_t *)&(reg_cnfg_ldo0_a));
Okan Sahin 0:55f664e8c56c 1107 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1108
Okan Sahin 0:55f664e8c56c 1109 *offset = (decode_tv_ofs_ldo_t)reg_cnfg_ldo0_a.bits.tv_ofs_ldo;
Okan Sahin 0:55f664e8c56c 1110
Okan Sahin 0:55f664e8c56c 1111 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1112 }
Okan Sahin 0:55f664e8c56c 1113
Okan Sahin 0:55f664e8c56c 1114 int MAX77643_2::set_en_ldo(decode_en_ldo_t en_ldo)
Okan Sahin 0:55f664e8c56c 1115 {
Okan Sahin 0:55f664e8c56c 1116 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
Okan Sahin 0:55f664e8c56c 1117
Okan Sahin 0:55f664e8c56c 1118 SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.en_ldo, en_ldo);
Okan Sahin 0:55f664e8c56c 1119
Okan Sahin 0:55f664e8c56c 1120 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1121 }
Okan Sahin 0:55f664e8c56c 1122
Okan Sahin 0:55f664e8c56c 1123 int MAX77643_2::get_en_ldo(decode_en_ldo_t *en_ldo)
Okan Sahin 0:55f664e8c56c 1124 {
Okan Sahin 0:55f664e8c56c 1125 int ret;
Okan Sahin 0:55f664e8c56c 1126 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
Okan Sahin 0:55f664e8c56c 1127
Okan Sahin 0:55f664e8c56c 1128 ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
Okan Sahin 0:55f664e8c56c 1129 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1130
Okan Sahin 0:55f664e8c56c 1131 *en_ldo = (decode_en_ldo_t)reg_cnfg_ldo0_b.bits.en_ldo;
Okan Sahin 0:55f664e8c56c 1132
Okan Sahin 0:55f664e8c56c 1133 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1134 }
Okan Sahin 0:55f664e8c56c 1135
Okan Sahin 0:55f664e8c56c 1136 int MAX77643_2::set_ade_ldo(decode_ade_ldo_t ade_ldo)
Okan Sahin 0:55f664e8c56c 1137 {
Okan Sahin 0:55f664e8c56c 1138 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
Okan Sahin 0:55f664e8c56c 1139
Okan Sahin 0:55f664e8c56c 1140 SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ade_ldo, ade_ldo);
Okan Sahin 0:55f664e8c56c 1141
Okan Sahin 0:55f664e8c56c 1142 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1143 }
Okan Sahin 0:55f664e8c56c 1144
Okan Sahin 0:55f664e8c56c 1145 int MAX77643_2::get_ade_ldo(decode_ade_ldo_t *ade_ldo)
Okan Sahin 0:55f664e8c56c 1146 {
Okan Sahin 0:55f664e8c56c 1147 int ret;
Okan Sahin 0:55f664e8c56c 1148 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
Okan Sahin 0:55f664e8c56c 1149
Okan Sahin 0:55f664e8c56c 1150 ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
Okan Sahin 0:55f664e8c56c 1151 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1152
Okan Sahin 0:55f664e8c56c 1153 *ade_ldo = (decode_ade_ldo_t)reg_cnfg_ldo0_b.bits.ade_ldo;
Okan Sahin 0:55f664e8c56c 1154
Okan Sahin 0:55f664e8c56c 1155 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1156 }
Okan Sahin 0:55f664e8c56c 1157
Okan Sahin 0:55f664e8c56c 1158 int MAX77643_2::set_ldo_md(decode_ldo_md_t mode)
Okan Sahin 0:55f664e8c56c 1159 {
Okan Sahin 0:55f664e8c56c 1160 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
Okan Sahin 0:55f664e8c56c 1161
Okan Sahin 0:55f664e8c56c 1162 SET_BIT_FIELD(CNFG_LDO0_B, reg_cnfg_ldo0_b, reg_cnfg_ldo0_b.bits.ldo_md, mode);
Okan Sahin 0:55f664e8c56c 1163
Okan Sahin 0:55f664e8c56c 1164 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1165 }
Okan Sahin 0:55f664e8c56c 1166
Okan Sahin 0:55f664e8c56c 1167 int MAX77643_2::get_ldo_md(decode_ldo_md_t *mode)
Okan Sahin 0:55f664e8c56c 1168 {
Okan Sahin 0:55f664e8c56c 1169 int ret;
Okan Sahin 0:55f664e8c56c 1170 reg_cnfg_ldo0_b_t reg_cnfg_ldo0_b = {0};
Okan Sahin 0:55f664e8c56c 1171
Okan Sahin 0:55f664e8c56c 1172 ret = read_register(CNFG_LDO0_B, (uint8_t *)&(reg_cnfg_ldo0_b));
Okan Sahin 0:55f664e8c56c 1173 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1174
Okan Sahin 0:55f664e8c56c 1175 *mode = (decode_ldo_md_t)reg_cnfg_ldo0_b.bits.ldo_md;
Okan Sahin 0:55f664e8c56c 1176
Okan Sahin 0:55f664e8c56c 1177 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1178 }
Okan Sahin 0:55f664e8c56c 1179
Okan Sahin 0:55f664e8c56c 1180 int MAX77643_2::irq_disable_all()
Okan Sahin 0:55f664e8c56c 1181 {
Okan Sahin 0:55f664e8c56c 1182 int ret;
Okan Sahin 0:55f664e8c56c 1183 uint8_t reg = 0;
Okan Sahin 0:55f664e8c56c 1184 uint8_t status = 0;
Okan Sahin 0:55f664e8c56c 1185
Okan Sahin 0:55f664e8c56c 1186 //Disable Masks in INTM_GLBL1
Okan Sahin 0:55f664e8c56c 1187 ret = write_register(INTM_GLBL1, &reg);
Okan Sahin 0:55f664e8c56c 1188 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1189
Okan Sahin 0:55f664e8c56c 1190 //Disable Masks in INTM_GLBL0
Okan Sahin 0:55f664e8c56c 1191 ret = write_register(INTM_GLBL0, &reg);
Okan Sahin 0:55f664e8c56c 1192 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1193
Okan Sahin 0:55f664e8c56c 1194 // Clear Interrupt Flags in INT_GLBL1
Okan Sahin 0:55f664e8c56c 1195 ret = read_register(INT_GLBL1, &status);
Okan Sahin 0:55f664e8c56c 1196 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1197
Okan Sahin 0:55f664e8c56c 1198 // Clear Interrupt Flags in INT_GLBL0
Okan Sahin 0:55f664e8c56c 1199 ret = read_register(INT_GLBL0, &status);
Okan Sahin 0:55f664e8c56c 1200 if (ret != MAX77643_2_NO_ERROR) return ret;
Okan Sahin 0:55f664e8c56c 1201
Okan Sahin 0:55f664e8c56c 1202 return MAX77643_2_NO_ERROR;
Okan Sahin 0:55f664e8c56c 1203 }
Okan Sahin 0:55f664e8c56c 1204
Okan Sahin 0:55f664e8c56c 1205 void MAX77643_2::set_interrupt_handler(reg_bit_int_glbl_t id, interrupt_handler_function func, void *cb)
Okan Sahin 0:55f664e8c56c 1206 {
Okan Sahin 0:55f664e8c56c 1207 interrupt_handler_list[id].func = func;
Okan Sahin 0:55f664e8c56c 1208 interrupt_handler_list[id].cb = cb;
Okan Sahin 0:55f664e8c56c 1209 }
Okan Sahin 0:55f664e8c56c 1210
Okan Sahin 0:55f664e8c56c 1211 void MAX77643_2::post_interrupt_work()
Okan Sahin 0:55f664e8c56c 1212 {
Okan Sahin 0:55f664e8c56c 1213 int ret;
Okan Sahin 0:55f664e8c56c 1214 uint8_t reg = 0, inten = 0, not_inten = 0, mask = 0;
Okan Sahin 0:55f664e8c56c 1215
Okan Sahin 0:55f664e8c56c 1216 while (true) {
Okan Sahin 0:55f664e8c56c 1217
Okan Sahin 0:55f664e8c56c 1218 ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID);
Okan Sahin 0:55f664e8c56c 1219
Okan Sahin 0:55f664e8c56c 1220 // Check Interrupt Flags in INT_GLBL0
Okan Sahin 0:55f664e8c56c 1221 ret = read_register(INT_GLBL0, &reg);
Okan Sahin 0:55f664e8c56c 1222 if (ret != MAX77643_2_NO_ERROR) return;
Okan Sahin 0:55f664e8c56c 1223
Okan Sahin 0:55f664e8c56c 1224 ret = read_register(INTM_GLBL0, &inten);
Okan Sahin 0:55f664e8c56c 1225 if (ret != MAX77643_2_NO_ERROR) return;
Okan Sahin 0:55f664e8c56c 1226
Okan Sahin 0:55f664e8c56c 1227 not_inten = ~inten; // 0 means unmasked.
Okan Sahin 0:55f664e8c56c 1228
Okan Sahin 0:55f664e8c56c 1229 for (int i = 0; i < INT_GLBL1_GPI1_F; i++) {
Okan Sahin 0:55f664e8c56c 1230 mask = (1 << i);
Okan Sahin 0:55f664e8c56c 1231 if ((reg & mask) && (not_inten & mask)) {
Okan Sahin 0:55f664e8c56c 1232 if (interrupt_handler_list[i].func != NULL) {
Okan Sahin 0:55f664e8c56c 1233 interrupt_handler_list[i]
Okan Sahin 0:55f664e8c56c 1234 .func(interrupt_handler_list[i].cb);
Okan Sahin 0:55f664e8c56c 1235 }
Okan Sahin 0:55f664e8c56c 1236 }
Okan Sahin 0:55f664e8c56c 1237 }
Okan Sahin 0:55f664e8c56c 1238
Okan Sahin 0:55f664e8c56c 1239 // Check Interrupt Flags in INT_GLBL1
Okan Sahin 0:55f664e8c56c 1240 ret = read_register(INT_GLBL1, &reg);
Okan Sahin 0:55f664e8c56c 1241 if (ret != MAX77643_2_NO_ERROR) return;
Okan Sahin 0:55f664e8c56c 1242
Okan Sahin 0:55f664e8c56c 1243 ret = read_register(INTM_GLBL1, &inten);
Okan Sahin 0:55f664e8c56c 1244 if (ret != MAX77643_2_NO_ERROR) return;
Okan Sahin 0:55f664e8c56c 1245
Okan Sahin 0:55f664e8c56c 1246 not_inten = ~inten; // 0 means unmasked.
Okan Sahin 0:55f664e8c56c 1247
Okan Sahin 0:55f664e8c56c 1248 for (int i = INT_GLBL1_GPI1_F; i < INT_CHG_END; i++) {
Okan Sahin 0:55f664e8c56c 1249 mask = (1 << (i - INT_GLBL1_GPI1_F));
Okan Sahin 0:55f664e8c56c 1250 if ((reg & mask) && (not_inten & mask)) {
Okan Sahin 0:55f664e8c56c 1251 if (interrupt_handler_list[i].func != NULL) {
Okan Sahin 0:55f664e8c56c 1252 interrupt_handler_list[i]
Okan Sahin 0:55f664e8c56c 1253 .func(interrupt_handler_list[i].cb);
Okan Sahin 0:55f664e8c56c 1254 }
Okan Sahin 0:55f664e8c56c 1255 }
Okan Sahin 0:55f664e8c56c 1256 }
Okan Sahin 0:55f664e8c56c 1257 }
Okan Sahin 0:55f664e8c56c 1258 }
Okan Sahin 0:55f664e8c56c 1259
Okan Sahin 0:55f664e8c56c 1260 void MAX77643_2::interrupt_handler()
Okan Sahin 0:55f664e8c56c 1261 {
Okan Sahin 0:55f664e8c56c 1262 post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID);
Okan Sahin 0:55f664e8c56c 1263 }
Okan Sahin 0:55f664e8c56c 1264