CRAC Team / CRAC-Strat_2017-19-05-2017

strat des robots

Fork of CRAC-Strat_2017 by CRAC Team

mbed/SPISlave.h@17:d1594579eec6, 2017-05-19 (annotated)

Committer:
ClementBreteau
Date:
Fri May 19 17:14:07 2017 +0000
Revision:
17:d1594579eec6
Parent:
0:ad97421fb1fb 
strat du robot, 19-05-2017, 19h

Who changed what in which revision?

UserRevisionLine numberNew contents of line
antbig 0:ad97421fb1fb 1 /* mbed Microcontroller Library - SPISlave
antbig 0:ad97421fb1fb 2 * Copyright (c) 2010-2011 ARM Limited. All rights reserved.
antbig 0:ad97421fb1fb 3 */
antbig 0:ad97421fb1fb 4
antbig 0:ad97421fb1fb 5 #ifndef MBED_SPISLAVE_H
antbig 0:ad97421fb1fb 6 #define MBED_SPISLAVE_H
antbig 0:ad97421fb1fb 7
antbig 0:ad97421fb1fb 8 #include "device.h"
antbig 0:ad97421fb1fb 9
antbig 0:ad97421fb1fb 10 #if DEVICE_SPISLAVE
antbig 0:ad97421fb1fb 11
antbig 0:ad97421fb1fb 12 #include "platform.h"
antbig 0:ad97421fb1fb 13 #include "PinNames.h"
antbig 0:ad97421fb1fb 14 #include "PeripheralNames.h"
antbig 0:ad97421fb1fb 15 #include "Base.h"
antbig 0:ad97421fb1fb 16
antbig 0:ad97421fb1fb 17 namespace mbed {
antbig 0:ad97421fb1fb 18
antbig 0:ad97421fb1fb 19 /* Class: SPISlave
antbig 0:ad97421fb1fb 20 * A SPI slave, used for communicating with a SPI Master device
antbig 0:ad97421fb1fb 21 *
antbig 0:ad97421fb1fb 22 * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
antbig 0:ad97421fb1fb 23 *
antbig 0:ad97421fb1fb 24 * Example:
antbig 0:ad97421fb1fb 25 * > // Reply to a SPI master as slave
antbig 0:ad97421fb1fb 26 * >
antbig 0:ad97421fb1fb 27 * > #include "mbed.h"
antbig 0:ad97421fb1fb 28 * >
antbig 0:ad97421fb1fb 29 * > SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
antbig 0:ad97421fb1fb 30 * >
antbig 0:ad97421fb1fb 31 * > int main() {
antbig 0:ad97421fb1fb 32 * > device.reply(0x00); // Prime SPI with first reply
antbig 0:ad97421fb1fb 33 * > while(1) {
antbig 0:ad97421fb1fb 34 * > if(device.receive()) {
antbig 0:ad97421fb1fb 35 * > int v = device.read(); // Read byte from master
antbig 0:ad97421fb1fb 36 * > v = (v + 1) % 0x100; // Add one to it, modulo 256
antbig 0:ad97421fb1fb 37 * > device.reply(v); // Make this the next reply
antbig 0:ad97421fb1fb 38 * > }
antbig 0:ad97421fb1fb 39 * > }
antbig 0:ad97421fb1fb 40 * > }
antbig 0:ad97421fb1fb 41 */
antbig 0:ad97421fb1fb 42 class SPISlave : public Base {
antbig 0:ad97421fb1fb 43
antbig 0:ad97421fb1fb 44 public:
antbig 0:ad97421fb1fb 45
antbig 0:ad97421fb1fb 46 /* Constructor: SPI
antbig 0:ad97421fb1fb 47 * Create a SPI slave connected to the specified pins
antbig 0:ad97421fb1fb 48 *
antbig 0:ad97421fb1fb 49 * Variables:
antbig 0:ad97421fb1fb 50 * mosi - SPI Master Out, Slave In pin
antbig 0:ad97421fb1fb 51 * miso - SPI Master In, Slave Out pin
antbig 0:ad97421fb1fb 52 * sclk - SPI Clock pin
antbig 0:ad97421fb1fb 53 * ssel - SPI chip select pin
antbig 0:ad97421fb1fb 54 * name - (optional) A string to identify the object
antbig 0:ad97421fb1fb 55 *
antbig 0:ad97421fb1fb 56 * Pin Options:
antbig 0:ad97421fb1fb 57 * (5, 6, 7i, 8) or (11, 12, 13, 14)
antbig 0:ad97421fb1fb 58 *
antbig 0:ad97421fb1fb 59 * mosi or miso can be specfied as NC if not used
antbig 0:ad97421fb1fb 60 */
antbig 0:ad97421fb1fb 61 SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel,
antbig 0:ad97421fb1fb 62 const char *name = NULL);
antbig 0:ad97421fb1fb 63
antbig 0:ad97421fb1fb 64 /* Function: format
antbig 0:ad97421fb1fb 65 * Configure the data transmission format
antbig 0:ad97421fb1fb 66 *
antbig 0:ad97421fb1fb 67 * Variables:
antbig 0:ad97421fb1fb 68 * bits - Number of bits per SPI frame (4 - 16)
antbig 0:ad97421fb1fb 69 * mode - Clock polarity and phase mode (0 - 3)
antbig 0:ad97421fb1fb 70 *
antbig 0:ad97421fb1fb 71 * > mode | POL PHA
antbig 0:ad97421fb1fb 72 * > -----+--------
antbig 0:ad97421fb1fb 73 * > 0 | 0 0
antbig 0:ad97421fb1fb 74 * > 1 | 0 1
antbig 0:ad97421fb1fb 75 * > 2 | 1 0
antbig 0:ad97421fb1fb 76 * > 3 | 1 1
antbig 0:ad97421fb1fb 77 */
antbig 0:ad97421fb1fb 78 void format(int bits, int mode = 0);
antbig 0:ad97421fb1fb 79
antbig 0:ad97421fb1fb 80 /* Function: frequency
antbig 0:ad97421fb1fb 81 * Set the spi bus clock frequency
antbig 0:ad97421fb1fb 82 *
antbig 0:ad97421fb1fb 83 * Variables:
antbig 0:ad97421fb1fb 84 * hz - SCLK frequency in hz (default = 1MHz)
antbig 0:ad97421fb1fb 85 */
antbig 0:ad97421fb1fb 86 void frequency(int hz = 1000000);
antbig 0:ad97421fb1fb 87
antbig 0:ad97421fb1fb 88 /* Function: receive
antbig 0:ad97421fb1fb 89 * Polls the SPI to see if data has been received
antbig 0:ad97421fb1fb 90 *
antbig 0:ad97421fb1fb 91 * Variables:
antbig 0:ad97421fb1fb 92 * returns - zero if no data, 1 otherwise
antbig 0:ad97421fb1fb 93 */
antbig 0:ad97421fb1fb 94 int receive(void);
antbig 0:ad97421fb1fb 95
antbig 0:ad97421fb1fb 96 /* Function: read
antbig 0:ad97421fb1fb 97 * Retrieve data from receive buffer as slave
antbig 0:ad97421fb1fb 98 *
antbig 0:ad97421fb1fb 99 * Variables:
antbig 0:ad97421fb1fb 100 * returns - the data in the receive buffer
antbig 0:ad97421fb1fb 101 */
antbig 0:ad97421fb1fb 102 int read(void);
antbig 0:ad97421fb1fb 103
antbig 0:ad97421fb1fb 104 /* Function: reply
antbig 0:ad97421fb1fb 105 * Fill the transmission buffer with the value to be written out
antbig 0:ad97421fb1fb 106 * as slave on the next received message from the master.
antbig 0:ad97421fb1fb 107 *
antbig 0:ad97421fb1fb 108 * Variables:
antbig 0:ad97421fb1fb 109 * value - the data to be transmitted next
antbig 0:ad97421fb1fb 110 */
antbig 0:ad97421fb1fb 111 void reply(int value);
antbig 0:ad97421fb1fb 112
antbig 0:ad97421fb1fb 113 protected:
antbig 0:ad97421fb1fb 114
antbig 0:ad97421fb1fb 115 SPIName _spi;
antbig 0:ad97421fb1fb 116
antbig 0:ad97421fb1fb 117 int _bits;
antbig 0:ad97421fb1fb 118 int _mode;
antbig 0:ad97421fb1fb 119 int _hz;
antbig 0:ad97421fb1fb 120
antbig 0:ad97421fb1fb 121 };
antbig 0:ad97421fb1fb 122
antbig 0:ad97421fb1fb 123 } // namespace mbed
antbig 0:ad97421fb1fb 124
antbig 0:ad97421fb1fb 125 #endif
antbig 0:ad97421fb1fb 126
antbig 0:ad97421fb1fb 127 #endif