CRAC Team / CRAC-Strat_2017-19-05-2017

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mbed/SPIHalfDuplex.h@17:d1594579eec6, 2017-05-19 (annotated)

Committer:
ClementBreteau
Date:
Fri May 19 17:14:07 2017 +0000
Revision:
17:d1594579eec6
Parent:
0:ad97421fb1fb 
strat du robot, 19-05-2017, 19h

Who changed what in which revision?

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antbig 0:ad97421fb1fb 1 /* mbed Microcontroller Library - SPIHalfDuplex
antbig 0:ad97421fb1fb 2 * Copyright (c) 2010-2011 ARM Limited. All rights reserved.
antbig 0:ad97421fb1fb 3 */
antbig 0:ad97421fb1fb 4
antbig 0:ad97421fb1fb 5 #ifndef MBED_SPIHALFDUPLEX_H
antbig 0:ad97421fb1fb 6 #define MBED_SPIHALFDUPLEX_H
antbig 0:ad97421fb1fb 7
antbig 0:ad97421fb1fb 8 #include "device.h"
antbig 0:ad97421fb1fb 9
antbig 0:ad97421fb1fb 10 #if DEVICE_SPI
antbig 0:ad97421fb1fb 11
antbig 0:ad97421fb1fb 12 #include "SPI.h"
antbig 0:ad97421fb1fb 13
antbig 0:ad97421fb1fb 14 namespace mbed {
antbig 0:ad97421fb1fb 15
antbig 0:ad97421fb1fb 16 /* Class: SPIHalfDuplex
antbig 0:ad97421fb1fb 17 * A SPI half-duplex master, used for communicating with SPI slave devices
antbig 0:ad97421fb1fb 18 * over a shared data line.
antbig 0:ad97421fb1fb 19 *
antbig 0:ad97421fb1fb 20 * The default format is set to 8-bits for both master and slave, and a
antbig 0:ad97421fb1fb 21 * clock frequency of 1MHz
antbig 0:ad97421fb1fb 22 *
antbig 0:ad97421fb1fb 23 * Most SPI devies will also require Chip Select and Reset signals. These
antbig 0:ad97421fb1fb 24 * can be controlled using <DigitalOut> pins.
antbig 0:ad97421fb1fb 25 *
antbig 0:ad97421fb1fb 26 * Although this is for a shared data line, both MISO and MOSI are defined,
antbig 0:ad97421fb1fb 27 * and should be tied together externally to the mbed. This class handles
antbig 0:ad97421fb1fb 28 * the tri-stating of the MOSI pin.
antbig 0:ad97421fb1fb 29 *
antbig 0:ad97421fb1fb 30 * Example:
antbig 0:ad97421fb1fb 31 * > // Send a byte to a SPI half-duplex slave, and record the response
antbig 0:ad97421fb1fb 32 * >
antbig 0:ad97421fb1fb 33 * > #include "mbed.h"
antbig 0:ad97421fb1fb 34 * >
antbig 0:ad97421fb1fb 35 * > SPIHalfDuplex device(p5, p6, p7) // mosi, miso, sclk
antbig 0:ad97421fb1fb 36 * >
antbig 0:ad97421fb1fb 37 * > int main() {
antbig 0:ad97421fb1fb 38 * > int respone = device.write(0xAA);
antbig 0:ad97421fb1fb 39 * > }
antbig 0:ad97421fb1fb 40 */
antbig 0:ad97421fb1fb 41
antbig 0:ad97421fb1fb 42 class SPIHalfDuplex : public SPI {
antbig 0:ad97421fb1fb 43
antbig 0:ad97421fb1fb 44 public:
antbig 0:ad97421fb1fb 45
antbig 0:ad97421fb1fb 46 /* Constructor: SPIHalfDuplex
antbig 0:ad97421fb1fb 47 * Create a SPI half-duplex master connected to the specified pins
antbig 0:ad97421fb1fb 48 *
antbig 0:ad97421fb1fb 49 * Variables:
antbig 0:ad97421fb1fb 50 * mosi - SPI Master Out, Slave In pin
antbig 0:ad97421fb1fb 51 * miso - SPI Master In, Slave Out pin
antbig 0:ad97421fb1fb 52 * sclk - SPI Clock pin
antbig 0:ad97421fb1fb 53 * name - (optional) A string to identify the object
antbig 0:ad97421fb1fb 54 *
antbig 0:ad97421fb1fb 55 * Pin Options:
antbig 0:ad97421fb1fb 56 * (5, 6, 7) or (11, 12, 13)
antbig 0:ad97421fb1fb 57 *
antbig 0:ad97421fb1fb 58 * mosi or miso can be specfied as NC if not used
antbig 0:ad97421fb1fb 59 */
antbig 0:ad97421fb1fb 60 SPIHalfDuplex(PinName mosi, PinName miso, PinName sclk,
antbig 0:ad97421fb1fb 61 const char *name = NULL);
antbig 0:ad97421fb1fb 62
antbig 0:ad97421fb1fb 63 #if 0 // Inherited from SPI - documentation only
antbig 0:ad97421fb1fb 64 /* Function: format
antbig 0:ad97421fb1fb 65 * Configure the data transmission format
antbig 0:ad97421fb1fb 66 *
antbig 0:ad97421fb1fb 67 * Variables:
antbig 0:ad97421fb1fb 68 * bits - Number of bits per SPI frame (4 - 16)
antbig 0:ad97421fb1fb 69 * mode - Clock polarity and phase mode (0 - 3)
antbig 0:ad97421fb1fb 70 *
antbig 0:ad97421fb1fb 71 * > mode | POL PHA
antbig 0:ad97421fb1fb 72 * > -----+--------
antbig 0:ad97421fb1fb 73 * > 0 | 0 0
antbig 0:ad97421fb1fb 74 * > 1 | 0 1
antbig 0:ad97421fb1fb 75 * > 2 | 1 0
antbig 0:ad97421fb1fb 76 * > 3 | 1 1
antbig 0:ad97421fb1fb 77 */
antbig 0:ad97421fb1fb 78 void format(int bits, int mode = 0);
antbig 0:ad97421fb1fb 79
antbig 0:ad97421fb1fb 80 /* Function: frequency
antbig 0:ad97421fb1fb 81 * Set the spi bus clock frequency
antbig 0:ad97421fb1fb 82 *
antbig 0:ad97421fb1fb 83 * Variables:
antbig 0:ad97421fb1fb 84 * hz - SCLK frequency in hz (default = 1MHz)
antbig 0:ad97421fb1fb 85 */
antbig 0:ad97421fb1fb 86 void frequency(int hz = 1000000);
antbig 0:ad97421fb1fb 87 #endif
antbig 0:ad97421fb1fb 88
antbig 0:ad97421fb1fb 89 /* Function: write
antbig 0:ad97421fb1fb 90 * Write to the SPI Slave and return the response
antbig 0:ad97421fb1fb 91 *
antbig 0:ad97421fb1fb 92 * Variables:
antbig 0:ad97421fb1fb 93 * value - Data to be sent to the SPI slave
antbig 0:ad97421fb1fb 94 * returns - Response from the SPI slave
antbig 0:ad97421fb1fb 95 */
antbig 0:ad97421fb1fb 96 virtual int write(int value);
antbig 0:ad97421fb1fb 97
antbig 0:ad97421fb1fb 98 /* Function: slave_format
antbig 0:ad97421fb1fb 99 * Set the number of databits expected from the slave, from 4-16
antbig 0:ad97421fb1fb 100 *
antbig 0:ad97421fb1fb 101 * Variables:
antbig 0:ad97421fb1fb 102 * sbits - Number of expected bits in the slave response
antbig 0:ad97421fb1fb 103 */
antbig 0:ad97421fb1fb 104 void slave_format(int sbits);
antbig 0:ad97421fb1fb 105
antbig 0:ad97421fb1fb 106 protected:
antbig 0:ad97421fb1fb 107 PinName _mosi;
antbig 0:ad97421fb1fb 108 PinName _miso;
antbig 0:ad97421fb1fb 109 int _sbits;
antbig 0:ad97421fb1fb 110
antbig 0:ad97421fb1fb 111 }; // End of class
antbig 0:ad97421fb1fb 112
antbig 0:ad97421fb1fb 113 } // End of namespace mbed
antbig 0:ad97421fb1fb 114
antbig 0:ad97421fb1fb 115 #endif
antbig 0:ad97421fb1fb 116
antbig 0:ad97421fb1fb 117 #endif