CRAC Team / CRAC-Strat_2017-19-05-2017

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mbed/PeripheralNames.h@17:d1594579eec6, 2017-05-19 (annotated)

Committer:
ClementBreteau
Date:
Fri May 19 17:14:07 2017 +0000
Revision:
17:d1594579eec6
Parent:
0:ad97421fb1fb 
strat du robot, 19-05-2017, 19h

Who changed what in which revision?

UserRevisionLine numberNew contents of line
antbig 0:ad97421fb1fb 1 /* mbed Microcontroller Library - PeripheralNames
antbig 0:ad97421fb1fb 2 * Copyright (C) 2008-2011 ARM Limited. All rights reserved.
antbig 0:ad97421fb1fb 3 *
antbig 0:ad97421fb1fb 4 * Provides the mappings for peripherals
antbig 0:ad97421fb1fb 5 */
antbig 0:ad97421fb1fb 6
antbig 0:ad97421fb1fb 7 #ifndef MBED_PERIPHERALNAMES_H
antbig 0:ad97421fb1fb 8 #define MBED_PERIPHERALNAMES_H
antbig 0:ad97421fb1fb 9
antbig 0:ad97421fb1fb 10 #include "cmsis.h"
antbig 0:ad97421fb1fb 11
antbig 0:ad97421fb1fb 12 #ifdef __cplusplus
antbig 0:ad97421fb1fb 13 extern "C" {
antbig 0:ad97421fb1fb 14 #endif
antbig 0:ad97421fb1fb 15
antbig 0:ad97421fb1fb 16 #if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
antbig 0:ad97421fb1fb 17
antbig 0:ad97421fb1fb 18 enum UARTName {
antbig 0:ad97421fb1fb 19 UART_0 = (int)LPC_UART0_BASE
antbig 0:ad97421fb1fb 20 , UART_1 = (int)LPC_UART1_BASE
antbig 0:ad97421fb1fb 21 , UART_2 = (int)LPC_UART2_BASE
antbig 0:ad97421fb1fb 22 , UART_3 = (int)LPC_UART3_BASE
antbig 0:ad97421fb1fb 23 };
antbig 0:ad97421fb1fb 24 typedef enum UARTName UARTName;
antbig 0:ad97421fb1fb 25
antbig 0:ad97421fb1fb 26 enum ADCName {
antbig 0:ad97421fb1fb 27 ADC0_0 = 0
antbig 0:ad97421fb1fb 28 , ADC0_1
antbig 0:ad97421fb1fb 29 , ADC0_2
antbig 0:ad97421fb1fb 30 , ADC0_3
antbig 0:ad97421fb1fb 31 , ADC0_4
antbig 0:ad97421fb1fb 32 , ADC0_5
antbig 0:ad97421fb1fb 33 , ADC0_6
antbig 0:ad97421fb1fb 34 , ADC0_7
antbig 0:ad97421fb1fb 35 };
antbig 0:ad97421fb1fb 36 typedef enum ADCName ADCName;
antbig 0:ad97421fb1fb 37
antbig 0:ad97421fb1fb 38 enum DACName {
antbig 0:ad97421fb1fb 39 DAC_0 = 0
antbig 0:ad97421fb1fb 40 };
antbig 0:ad97421fb1fb 41 typedef enum DACName DACName;
antbig 0:ad97421fb1fb 42
antbig 0:ad97421fb1fb 43 enum SPIName {
antbig 0:ad97421fb1fb 44 SPI_0 = (int)LPC_SSP0_BASE
antbig 0:ad97421fb1fb 45 , SPI_1 = (int)LPC_SSP1_BASE
antbig 0:ad97421fb1fb 46 };
antbig 0:ad97421fb1fb 47 typedef enum SPIName SPIName;
antbig 0:ad97421fb1fb 48
antbig 0:ad97421fb1fb 49 enum I2CName {
antbig 0:ad97421fb1fb 50 I2C_0 = (int)LPC_I2C0_BASE
antbig 0:ad97421fb1fb 51 , I2C_1 = (int)LPC_I2C1_BASE
antbig 0:ad97421fb1fb 52 , I2C_2 = (int)LPC_I2C2_BASE
antbig 0:ad97421fb1fb 53 };
antbig 0:ad97421fb1fb 54 typedef enum I2CName I2CName;
antbig 0:ad97421fb1fb 55
antbig 0:ad97421fb1fb 56 enum PWMName {
antbig 0:ad97421fb1fb 57 PWM_1 = 1
antbig 0:ad97421fb1fb 58 , PWM_2
antbig 0:ad97421fb1fb 59 , PWM_3
antbig 0:ad97421fb1fb 60 , PWM_4
antbig 0:ad97421fb1fb 61 , PWM_5
antbig 0:ad97421fb1fb 62 , PWM_6
antbig 0:ad97421fb1fb 63 };
antbig 0:ad97421fb1fb 64 typedef enum PWMName PWMName;
antbig 0:ad97421fb1fb 65
antbig 0:ad97421fb1fb 66 enum TimerName {
antbig 0:ad97421fb1fb 67 TIMER_0 = (int)LPC_TIM0_BASE
antbig 0:ad97421fb1fb 68 , TIMER_1 = (int)LPC_TIM1_BASE
antbig 0:ad97421fb1fb 69 , TIMER_2 = (int)LPC_TIM2_BASE
antbig 0:ad97421fb1fb 70 , TIMER_3 = (int)LPC_TIM3_BASE
antbig 0:ad97421fb1fb 71 };
antbig 0:ad97421fb1fb 72 typedef enum TimerName TimerName;
antbig 0:ad97421fb1fb 73
antbig 0:ad97421fb1fb 74 enum CANName {
antbig 0:ad97421fb1fb 75 CAN_1 = (int)LPC_CAN1_BASE,
antbig 0:ad97421fb1fb 76 CAN_2 = (int)LPC_CAN2_BASE
antbig 0:ad97421fb1fb 77 };
antbig 0:ad97421fb1fb 78 typedef enum CANName CANName;
antbig 0:ad97421fb1fb 79
antbig 0:ad97421fb1fb 80 #define US_TICKER_TIMER TIMER_3
antbig 0:ad97421fb1fb 81 #define US_TICKER_TIMER_IRQn TIMER3_IRQn
antbig 0:ad97421fb1fb 82
antbig 0:ad97421fb1fb 83 #elif defined(TARGET_LPC11U24)
antbig 0:ad97421fb1fb 84
antbig 0:ad97421fb1fb 85 enum UARTName {
antbig 0:ad97421fb1fb 86 UART_0 = (int)LPC_USART_BASE
antbig 0:ad97421fb1fb 87 };
antbig 0:ad97421fb1fb 88 typedef enum UARTName UARTName;
antbig 0:ad97421fb1fb 89
antbig 0:ad97421fb1fb 90 enum I2CName {
antbig 0:ad97421fb1fb 91 I2C_0 = (int)LPC_I2C_BASE
antbig 0:ad97421fb1fb 92 };
antbig 0:ad97421fb1fb 93 typedef enum I2CName I2CName;
antbig 0:ad97421fb1fb 94
antbig 0:ad97421fb1fb 95 enum TimerName {
antbig 0:ad97421fb1fb 96 TIMER_0 = (int)LPC_CT32B0_BASE
antbig 0:ad97421fb1fb 97 , TIMER_1 = (int)LPC_CT32B1_BASE
antbig 0:ad97421fb1fb 98 };
antbig 0:ad97421fb1fb 99 typedef enum TimerName TimerName;
antbig 0:ad97421fb1fb 100
antbig 0:ad97421fb1fb 101 enum ADCName {
antbig 0:ad97421fb1fb 102 ADC0_0 = 0
antbig 0:ad97421fb1fb 103 , ADC0_1
antbig 0:ad97421fb1fb 104 , ADC0_2
antbig 0:ad97421fb1fb 105 , ADC0_3
antbig 0:ad97421fb1fb 106 , ADC0_4
antbig 0:ad97421fb1fb 107 , ADC0_5
antbig 0:ad97421fb1fb 108 , ADC0_6
antbig 0:ad97421fb1fb 109 , ADC0_7
antbig 0:ad97421fb1fb 110 };
antbig 0:ad97421fb1fb 111 typedef enum ADCName ADCName;
antbig 0:ad97421fb1fb 112
antbig 0:ad97421fb1fb 113 enum SPIName {
antbig 0:ad97421fb1fb 114 SPI_0 = (int)LPC_SSP0_BASE
antbig 0:ad97421fb1fb 115 , SPI_1 = (int)LPC_SSP1_BASE
antbig 0:ad97421fb1fb 116 };
antbig 0:ad97421fb1fb 117 typedef enum SPIName SPIName;
antbig 0:ad97421fb1fb 118
antbig 0:ad97421fb1fb 119 #define US_TICKER_TIMER TIMER_1
antbig 0:ad97421fb1fb 120 #define US_TICKER_TIMER_IRQn TIMER_32_1_IRQn
antbig 0:ad97421fb1fb 121
antbig 0:ad97421fb1fb 122 typedef enum PWMName {
antbig 0:ad97421fb1fb 123 PWM_1 = 0
antbig 0:ad97421fb1fb 124 , PWM_2
antbig 0:ad97421fb1fb 125 , PWM_3
antbig 0:ad97421fb1fb 126 , PWM_4
antbig 0:ad97421fb1fb 127 , PWM_5
antbig 0:ad97421fb1fb 128 , PWM_6
antbig 0:ad97421fb1fb 129 , PWM_7
antbig 0:ad97421fb1fb 130 , PWM_8
antbig 0:ad97421fb1fb 131 , PWM_9
antbig 0:ad97421fb1fb 132 , PWM_10
antbig 0:ad97421fb1fb 133 , PWM_11
antbig 0:ad97421fb1fb 134 } PWMName;
antbig 0:ad97421fb1fb 135
antbig 0:ad97421fb1fb 136 #endif
antbig 0:ad97421fb1fb 137
antbig 0:ad97421fb1fb 138 #define STDIO_UART_TX USBTX
antbig 0:ad97421fb1fb 139 #define STDIO_UART_RX USBRX
antbig 0:ad97421fb1fb 140 #define STDIO_UART UART_0
antbig 0:ad97421fb1fb 141
antbig 0:ad97421fb1fb 142 #ifdef __cplusplus
antbig 0:ad97421fb1fb 143 }
antbig 0:ad97421fb1fb 144 #endif
antbig 0:ad97421fb1fb 145
antbig 0:ad97421fb1fb 146 #endif