CQ Publishing / Mbed 2 deprecated tg_201410s9_FG

Transistor Gijutsu, October 2014, Special Features Chapter 9， Software of the Function Generator トランジスタ技術2014年10月号　特集第9章のソフトウェア わがまま波形発生器のソフトウェア

Dependencies:   USBDevice mbed

Information

tg_201410s8_AD7714 トランジスタ技術 2014年 10月号 第9章のソフトウェア

Program for Section 9 in October. 2014 issue of the Transistor Gijutsu
(Japanese electronics magazine)

概要

このプログラムは、ソフトウエアDDSにより、任意の波形を出力（2ch）します。 特徴は次のとおりです。

  • PWM出力をDAコンバータとして利用します。
  • 周波数や波形、バースト条件などを個別に設定できる独立した出力を２チャネル持っています。
  • 周波数分解能0.023ｍHz
  • 周波数範囲0.023ｍHz～１０ｋHz
  • 各チャネルにそれぞれ、波形の先頭で出力されるトリガ出力があります。
  • 出力波形を関数で定義できます。
  • 休止波数、出力波数、を設定することでバースト波形が出力できます。

ファイル

このソフトウエアは、次のファイルから構成されています。

  • DDS.cpp - DDSによる波形発生
  • main.cpp - main()関数

詳細については、10月号の記事および上記ファイル中のコメントを参照してください。

USBDevice/USBDevice/USBHAL_STM32F4.cpp@0:f1ecca559ec3, 2014-08-29 (annotated)

Committer:
Dance
Date:
Fri Aug 29 08:33:17 2014 +0000
Revision:
0:f1ecca559ec3
Transistor Gijutsu, October 2014, Special Features Chapter 9; ????????2014?10??????9????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Dance 0:f1ecca559ec3 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
Dance 0:f1ecca559ec3 2 *
Dance 0:f1ecca559ec3 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
Dance 0:f1ecca559ec3 4 * and associated documentation files (the "Software"), to deal in the Software without
Dance 0:f1ecca559ec3 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
Dance 0:f1ecca559ec3 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
Dance 0:f1ecca559ec3 7 * Software is furnished to do so, subject to the following conditions:
Dance 0:f1ecca559ec3 8 *
Dance 0:f1ecca559ec3 9 * The above copyright notice and this permission notice shall be included in all copies or
Dance 0:f1ecca559ec3 10 * substantial portions of the Software.
Dance 0:f1ecca559ec3 11 *
Dance 0:f1ecca559ec3 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
Dance 0:f1ecca559ec3 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
Dance 0:f1ecca559ec3 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
Dance 0:f1ecca559ec3 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Dance 0:f1ecca559ec3 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Dance 0:f1ecca559ec3 17 */
Dance 0:f1ecca559ec3 18
Dance 0:f1ecca559ec3 19 #if defined(TARGET_STM32F4XX)
Dance 0:f1ecca559ec3 20
Dance 0:f1ecca559ec3 21 #include "USBHAL.h"
Dance 0:f1ecca559ec3 22 #include "USBRegs_STM32.h"
Dance 0:f1ecca559ec3 23 #include "pinmap.h"
Dance 0:f1ecca559ec3 24
Dance 0:f1ecca559ec3 25 USBHAL * USBHAL::instance;
Dance 0:f1ecca559ec3 26
Dance 0:f1ecca559ec3 27 static volatile int epComplete = 0;
Dance 0:f1ecca559ec3 28
Dance 0:f1ecca559ec3 29 static uint32_t bufferEnd = 0;
Dance 0:f1ecca559ec3 30 static const uint32_t rxFifoSize = 512;
Dance 0:f1ecca559ec3 31 static uint32_t rxFifoCount = 0;
Dance 0:f1ecca559ec3 32
Dance 0:f1ecca559ec3 33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
Dance 0:f1ecca559ec3 34
Dance 0:f1ecca559ec3 35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
Dance 0:f1ecca559ec3 36 return 0;
Dance 0:f1ecca559ec3 37 }
Dance 0:f1ecca559ec3 38
Dance 0:f1ecca559ec3 39 USBHAL::USBHAL(void) {
Dance 0:f1ecca559ec3 40 NVIC_DisableIRQ(OTG_FS_IRQn);
Dance 0:f1ecca559ec3 41 epCallback[0] = &USBHAL::EP1_OUT_callback;
Dance 0:f1ecca559ec3 42 epCallback[1] = &USBHAL::EP1_IN_callback;
Dance 0:f1ecca559ec3 43 epCallback[2] = &USBHAL::EP2_OUT_callback;
Dance 0:f1ecca559ec3 44 epCallback[3] = &USBHAL::EP2_IN_callback;
Dance 0:f1ecca559ec3 45 epCallback[4] = &USBHAL::EP3_OUT_callback;
Dance 0:f1ecca559ec3 46 epCallback[5] = &USBHAL::EP3_IN_callback;
Dance 0:f1ecca559ec3 47
Dance 0:f1ecca559ec3 48 // Enable power and clocking
Dance 0:f1ecca559ec3 49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
Dance 0:f1ecca559ec3 50
Dance 0:f1ecca559ec3 51 pin_function(PA_8, STM_PIN_DATA(2, 10));
Dance 0:f1ecca559ec3 52 pin_function(PA_9, STM_PIN_DATA(0, 0));
Dance 0:f1ecca559ec3 53 pin_function(PA_10, STM_PIN_DATA(2, 10));
Dance 0:f1ecca559ec3 54 pin_function(PA_11, STM_PIN_DATA(2, 10));
Dance 0:f1ecca559ec3 55 pin_function(PA_12, STM_PIN_DATA(2, 10));
Dance 0:f1ecca559ec3 56
Dance 0:f1ecca559ec3 57 // Set ID pin to open drain with pull-up resistor
Dance 0:f1ecca559ec3 58 pin_mode(PA_10, OpenDrain);
Dance 0:f1ecca559ec3 59 GPIOA->PUPDR &= ~(0x3 << 20);
Dance 0:f1ecca559ec3 60 GPIOA->PUPDR |= 1 << 20;
Dance 0:f1ecca559ec3 61
Dance 0:f1ecca559ec3 62 // Set VBUS pin to open drain
Dance 0:f1ecca559ec3 63 pin_mode(PA_9, OpenDrain);
Dance 0:f1ecca559ec3 64
Dance 0:f1ecca559ec3 65 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
Dance 0:f1ecca559ec3 66
Dance 0:f1ecca559ec3 67 // Enable interrupts
Dance 0:f1ecca559ec3 68 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
Dance 0:f1ecca559ec3 69
Dance 0:f1ecca559ec3 70 // Turnaround time to maximum value - too small causes packet loss
Dance 0:f1ecca559ec3 71 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
Dance 0:f1ecca559ec3 72
Dance 0:f1ecca559ec3 73 // Unmask global interrupts
Dance 0:f1ecca559ec3 74 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
Dance 0:f1ecca559ec3 75 (1 << 4) | // RX FIFO not empty
Dance 0:f1ecca559ec3 76 (1 << 12); // USB reset
Dance 0:f1ecca559ec3 77
Dance 0:f1ecca559ec3 78 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
Dance 0:f1ecca559ec3 79 (1 << 2); // Non-zero-length status OUT handshake
Dance 0:f1ecca559ec3 80
Dance 0:f1ecca559ec3 81 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
Dance 0:f1ecca559ec3 82 (1 << 16); // Power Up
Dance 0:f1ecca559ec3 83
Dance 0:f1ecca559ec3 84 instance = this;
Dance 0:f1ecca559ec3 85 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
Dance 0:f1ecca559ec3 86 NVIC_SetPriority(OTG_FS_IRQn, 1);
Dance 0:f1ecca559ec3 87 }
Dance 0:f1ecca559ec3 88
Dance 0:f1ecca559ec3 89 USBHAL::~USBHAL(void) {
Dance 0:f1ecca559ec3 90 }
Dance 0:f1ecca559ec3 91
Dance 0:f1ecca559ec3 92 void USBHAL::connect(void) {
Dance 0:f1ecca559ec3 93 NVIC_EnableIRQ(OTG_FS_IRQn);
Dance 0:f1ecca559ec3 94 }
Dance 0:f1ecca559ec3 95
Dance 0:f1ecca559ec3 96 void USBHAL::disconnect(void) {
Dance 0:f1ecca559ec3 97 NVIC_DisableIRQ(OTG_FS_IRQn);
Dance 0:f1ecca559ec3 98 }
Dance 0:f1ecca559ec3 99
Dance 0:f1ecca559ec3 100 void USBHAL::configureDevice(void) {
Dance 0:f1ecca559ec3 101 // Not needed
Dance 0:f1ecca559ec3 102 }
Dance 0:f1ecca559ec3 103
Dance 0:f1ecca559ec3 104 void USBHAL::unconfigureDevice(void) {
Dance 0:f1ecca559ec3 105 // Not needed
Dance 0:f1ecca559ec3 106 }
Dance 0:f1ecca559ec3 107
Dance 0:f1ecca559ec3 108 void USBHAL::setAddress(uint8_t address) {
Dance 0:f1ecca559ec3 109 OTG_FS->DREGS.DCFG |= (address << 4);
Dance 0:f1ecca559ec3 110 EP0write(0, 0);
Dance 0:f1ecca559ec3 111 }
Dance 0:f1ecca559ec3 112
Dance 0:f1ecca559ec3 113 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
Dance 0:f1ecca559ec3 114 uint32_t flags) {
Dance 0:f1ecca559ec3 115 uint32_t epIndex = endpoint >> 1;
Dance 0:f1ecca559ec3 116
Dance 0:f1ecca559ec3 117 uint32_t type;
Dance 0:f1ecca559ec3 118 switch (endpoint) {
Dance 0:f1ecca559ec3 119 case EP0IN:
Dance 0:f1ecca559ec3 120 case EP0OUT:
Dance 0:f1ecca559ec3 121 type = 0;
Dance 0:f1ecca559ec3 122 break;
Dance 0:f1ecca559ec3 123 case EPISO_IN:
Dance 0:f1ecca559ec3 124 case EPISO_OUT:
Dance 0:f1ecca559ec3 125 type = 1;
Dance 0:f1ecca559ec3 126 case EPBULK_IN:
Dance 0:f1ecca559ec3 127 case EPBULK_OUT:
Dance 0:f1ecca559ec3 128 type = 2;
Dance 0:f1ecca559ec3 129 break;
Dance 0:f1ecca559ec3 130 case EPINT_IN:
Dance 0:f1ecca559ec3 131 case EPINT_OUT:
Dance 0:f1ecca559ec3 132 type = 3;
Dance 0:f1ecca559ec3 133 break;
Dance 0:f1ecca559ec3 134 }
Dance 0:f1ecca559ec3 135
Dance 0:f1ecca559ec3 136 // Generic in or out EP controls
Dance 0:f1ecca559ec3 137 uint32_t control = (maxPacket << 0) | // Packet size
Dance 0:f1ecca559ec3 138 (1 << 15) | // Active endpoint
Dance 0:f1ecca559ec3 139 (type << 18); // Endpoint type
Dance 0:f1ecca559ec3 140
Dance 0:f1ecca559ec3 141 if (endpoint & 0x1) { // In Endpoint
Dance 0:f1ecca559ec3 142 // Set up the Tx FIFO
Dance 0:f1ecca559ec3 143 if (endpoint == EP0IN) {
Dance 0:f1ecca559ec3 144 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
Dance 0:f1ecca559ec3 145 (bufferEnd << 0);
Dance 0:f1ecca559ec3 146 }
Dance 0:f1ecca559ec3 147 else {
Dance 0:f1ecca559ec3 148 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
Dance 0:f1ecca559ec3 149 (bufferEnd << 0);
Dance 0:f1ecca559ec3 150 }
Dance 0:f1ecca559ec3 151 bufferEnd += maxPacket >> 2;
Dance 0:f1ecca559ec3 152
Dance 0:f1ecca559ec3 153 // Set the In EP specific control settings
Dance 0:f1ecca559ec3 154 if (endpoint != EP0IN) {
Dance 0:f1ecca559ec3 155 control |= (1 << 28); // SD0PID
Dance 0:f1ecca559ec3 156 }
Dance 0:f1ecca559ec3 157
Dance 0:f1ecca559ec3 158 control |= (epIndex << 22) | // TxFIFO index
Dance 0:f1ecca559ec3 159 (1 << 27); // SNAK
Dance 0:f1ecca559ec3 160 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
Dance 0:f1ecca559ec3 161
Dance 0:f1ecca559ec3 162 // Unmask the interrupt
Dance 0:f1ecca559ec3 163 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
Dance 0:f1ecca559ec3 164 }
Dance 0:f1ecca559ec3 165 else { // Out endpoint
Dance 0:f1ecca559ec3 166 // Set the out EP specific control settings
Dance 0:f1ecca559ec3 167 control |= (1 << 26); // CNAK
Dance 0:f1ecca559ec3 168 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
Dance 0:f1ecca559ec3 169
Dance 0:f1ecca559ec3 170 // Unmask the interrupt
Dance 0:f1ecca559ec3 171 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
Dance 0:f1ecca559ec3 172 }
Dance 0:f1ecca559ec3 173 return true;
Dance 0:f1ecca559ec3 174 }
Dance 0:f1ecca559ec3 175
Dance 0:f1ecca559ec3 176 // read setup packet
Dance 0:f1ecca559ec3 177 void USBHAL::EP0setup(uint8_t *buffer) {
Dance 0:f1ecca559ec3 178 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
Dance 0:f1ecca559ec3 179 }
Dance 0:f1ecca559ec3 180
Dance 0:f1ecca559ec3 181 void USBHAL::EP0readStage(void) {
Dance 0:f1ecca559ec3 182 }
Dance 0:f1ecca559ec3 183
Dance 0:f1ecca559ec3 184 void USBHAL::EP0read(void) {
Dance 0:f1ecca559ec3 185 }
Dance 0:f1ecca559ec3 186
Dance 0:f1ecca559ec3 187 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
Dance 0:f1ecca559ec3 188 uint32_t* buffer32 = (uint32_t *) buffer;
Dance 0:f1ecca559ec3 189 uint32_t length = rxFifoCount;
Dance 0:f1ecca559ec3 190 for (uint32_t i = 0; i < length; i += 4) {
Dance 0:f1ecca559ec3 191 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
Dance 0:f1ecca559ec3 192 }
Dance 0:f1ecca559ec3 193
Dance 0:f1ecca559ec3 194 rxFifoCount = 0;
Dance 0:f1ecca559ec3 195 return length;
Dance 0:f1ecca559ec3 196 }
Dance 0:f1ecca559ec3 197
Dance 0:f1ecca559ec3 198 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
Dance 0:f1ecca559ec3 199 endpointWrite(0, buffer, size);
Dance 0:f1ecca559ec3 200 }
Dance 0:f1ecca559ec3 201
Dance 0:f1ecca559ec3 202 void USBHAL::EP0getWriteResult(void) {
Dance 0:f1ecca559ec3 203 }
Dance 0:f1ecca559ec3 204
Dance 0:f1ecca559ec3 205 void USBHAL::EP0stall(void) {
Dance 0:f1ecca559ec3 206 // If we stall the out endpoint here then we have problems transferring
Dance 0:f1ecca559ec3 207 // and setup requests after the (stalled) get device qualifier requests.
Dance 0:f1ecca559ec3 208 // TODO: Find out if this is correct behavior, or whether we are doing
Dance 0:f1ecca559ec3 209 // something else wrong
Dance 0:f1ecca559ec3 210 stallEndpoint(EP0IN);
Dance 0:f1ecca559ec3 211 // stallEndpoint(EP0OUT);
Dance 0:f1ecca559ec3 212 }
Dance 0:f1ecca559ec3 213
Dance 0:f1ecca559ec3 214 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
Dance 0:f1ecca559ec3 215 uint32_t epIndex = endpoint >> 1;
Dance 0:f1ecca559ec3 216 uint32_t size = (1 << 19) | // 1 packet
Dance 0:f1ecca559ec3 217 (maximumSize << 0); // Packet size
Dance 0:f1ecca559ec3 218 // if (endpoint == EP0OUT) {
Dance 0:f1ecca559ec3 219 size |= (1 << 29); // 1 setup packet
Dance 0:f1ecca559ec3 220 // }
Dance 0:f1ecca559ec3 221 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
Dance 0:f1ecca559ec3 222 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
Dance 0:f1ecca559ec3 223 (1 << 26); // Clear NAK
Dance 0:f1ecca559ec3 224
Dance 0:f1ecca559ec3 225 epComplete &= ~(1 << endpoint);
Dance 0:f1ecca559ec3 226 return EP_PENDING;
Dance 0:f1ecca559ec3 227 }
Dance 0:f1ecca559ec3 228
Dance 0:f1ecca559ec3 229 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
Dance 0:f1ecca559ec3 230 if (!(epComplete & (1 << endpoint))) {
Dance 0:f1ecca559ec3 231 return EP_PENDING;
Dance 0:f1ecca559ec3 232 }
Dance 0:f1ecca559ec3 233
Dance 0:f1ecca559ec3 234 uint32_t* buffer32 = (uint32_t *) buffer;
Dance 0:f1ecca559ec3 235 uint32_t length = rxFifoCount;
Dance 0:f1ecca559ec3 236 for (uint32_t i = 0; i < length; i += 4) {
Dance 0:f1ecca559ec3 237 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
Dance 0:f1ecca559ec3 238 }
Dance 0:f1ecca559ec3 239 rxFifoCount = 0;
Dance 0:f1ecca559ec3 240 *bytesRead = length;
Dance 0:f1ecca559ec3 241 return EP_COMPLETED;
Dance 0:f1ecca559ec3 242 }
Dance 0:f1ecca559ec3 243
Dance 0:f1ecca559ec3 244 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
Dance 0:f1ecca559ec3 245 uint32_t epIndex = endpoint >> 1;
Dance 0:f1ecca559ec3 246 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
Dance 0:f1ecca559ec3 247 (size << 0); // Size of packet
Dance 0:f1ecca559ec3 248 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
Dance 0:f1ecca559ec3 249 (1 << 26); // CNAK
Dance 0:f1ecca559ec3 250 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
Dance 0:f1ecca559ec3 251
Dance 0:f1ecca559ec3 252 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
Dance 0:f1ecca559ec3 253
Dance 0:f1ecca559ec3 254 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
Dance 0:f1ecca559ec3 255 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
Dance 0:f1ecca559ec3 256 }
Dance 0:f1ecca559ec3 257
Dance 0:f1ecca559ec3 258 epComplete &= ~(1 << endpoint);
Dance 0:f1ecca559ec3 259
Dance 0:f1ecca559ec3 260 return EP_PENDING;
Dance 0:f1ecca559ec3 261 }
Dance 0:f1ecca559ec3 262
Dance 0:f1ecca559ec3 263 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
Dance 0:f1ecca559ec3 264 if (epComplete & (1 << endpoint)) {
Dance 0:f1ecca559ec3 265 epComplete &= ~(1 << endpoint);
Dance 0:f1ecca559ec3 266 return EP_COMPLETED;
Dance 0:f1ecca559ec3 267 }
Dance 0:f1ecca559ec3 268
Dance 0:f1ecca559ec3 269 return EP_PENDING;
Dance 0:f1ecca559ec3 270 }
Dance 0:f1ecca559ec3 271
Dance 0:f1ecca559ec3 272 void USBHAL::stallEndpoint(uint8_t endpoint) {
Dance 0:f1ecca559ec3 273 if (endpoint & 0x1) { // In EP
Dance 0:f1ecca559ec3 274 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
Dance 0:f1ecca559ec3 275 (1 << 21); // Stall
Dance 0:f1ecca559ec3 276 }
Dance 0:f1ecca559ec3 277 else { // Out EP
Dance 0:f1ecca559ec3 278 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
Dance 0:f1ecca559ec3 279 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
Dance 0:f1ecca559ec3 280 (1 << 21); // Stall
Dance 0:f1ecca559ec3 281 }
Dance 0:f1ecca559ec3 282 }
Dance 0:f1ecca559ec3 283
Dance 0:f1ecca559ec3 284 void USBHAL::unstallEndpoint(uint8_t endpoint) {
Dance 0:f1ecca559ec3 285
Dance 0:f1ecca559ec3 286 }
Dance 0:f1ecca559ec3 287
Dance 0:f1ecca559ec3 288 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
Dance 0:f1ecca559ec3 289 return false;
Dance 0:f1ecca559ec3 290 }
Dance 0:f1ecca559ec3 291
Dance 0:f1ecca559ec3 292 void USBHAL::remoteWakeup(void) {
Dance 0:f1ecca559ec3 293 }
Dance 0:f1ecca559ec3 294
Dance 0:f1ecca559ec3 295
Dance 0:f1ecca559ec3 296 void USBHAL::_usbisr(void) {
Dance 0:f1ecca559ec3 297 instance->usbisr();
Dance 0:f1ecca559ec3 298 }
Dance 0:f1ecca559ec3 299
Dance 0:f1ecca559ec3 300
Dance 0:f1ecca559ec3 301 void USBHAL::usbisr(void) {
Dance 0:f1ecca559ec3 302 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
Dance 0:f1ecca559ec3 303 // Set SNAK bits
Dance 0:f1ecca559ec3 304 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
Dance 0:f1ecca559ec3 305 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
Dance 0:f1ecca559ec3 306 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
Dance 0:f1ecca559ec3 307 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
Dance 0:f1ecca559ec3 308
Dance 0:f1ecca559ec3 309 OTG_FS->DREGS.DIEPMSK = (1 << 0);
Dance 0:f1ecca559ec3 310
Dance 0:f1ecca559ec3 311 bufferEnd = 0;
Dance 0:f1ecca559ec3 312
Dance 0:f1ecca559ec3 313 // Set the receive FIFO size
Dance 0:f1ecca559ec3 314 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
Dance 0:f1ecca559ec3 315 bufferEnd += rxFifoSize >> 2;
Dance 0:f1ecca559ec3 316
Dance 0:f1ecca559ec3 317 // Create the endpoints, and wait for setup packets on out EP0
Dance 0:f1ecca559ec3 318 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
Dance 0:f1ecca559ec3 319 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
Dance 0:f1ecca559ec3 320 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
Dance 0:f1ecca559ec3 321
Dance 0:f1ecca559ec3 322 OTG_FS->GREGS.GINTSTS = (1 << 12);
Dance 0:f1ecca559ec3 323 }
Dance 0:f1ecca559ec3 324
Dance 0:f1ecca559ec3 325 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
Dance 0:f1ecca559ec3 326 uint32_t status = OTG_FS->GREGS.GRXSTSP;
Dance 0:f1ecca559ec3 327
Dance 0:f1ecca559ec3 328 uint32_t endpoint = (status & 0xF) << 1;
Dance 0:f1ecca559ec3 329 uint32_t length = (status >> 4) & 0x7FF;
Dance 0:f1ecca559ec3 330 uint32_t type = (status >> 17) & 0xF;
Dance 0:f1ecca559ec3 331
Dance 0:f1ecca559ec3 332 rxFifoCount = length;
Dance 0:f1ecca559ec3 333
Dance 0:f1ecca559ec3 334 if (type == 0x6) {
Dance 0:f1ecca559ec3 335 // Setup packet
Dance 0:f1ecca559ec3 336 for (uint32_t i=0; i<length; i+=4) {
Dance 0:f1ecca559ec3 337 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
Dance 0:f1ecca559ec3 338 }
Dance 0:f1ecca559ec3 339 rxFifoCount = 0;
Dance 0:f1ecca559ec3 340 }
Dance 0:f1ecca559ec3 341
Dance 0:f1ecca559ec3 342 if (type == 0x4) {
Dance 0:f1ecca559ec3 343 // Setup complete
Dance 0:f1ecca559ec3 344 EP0setupCallback();
Dance 0:f1ecca559ec3 345 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
Dance 0:f1ecca559ec3 346 }
Dance 0:f1ecca559ec3 347
Dance 0:f1ecca559ec3 348 if (type == 0x2) {
Dance 0:f1ecca559ec3 349 // Out packet
Dance 0:f1ecca559ec3 350 if (endpoint == EP0OUT) {
Dance 0:f1ecca559ec3 351 EP0out();
Dance 0:f1ecca559ec3 352 }
Dance 0:f1ecca559ec3 353 else {
Dance 0:f1ecca559ec3 354 epComplete |= (1 << endpoint);
Dance 0:f1ecca559ec3 355 if ((instance->*(epCallback[endpoint - 2]))()) {
Dance 0:f1ecca559ec3 356 epComplete &= (1 << endpoint);
Dance 0:f1ecca559ec3 357 }
Dance 0:f1ecca559ec3 358 }
Dance 0:f1ecca559ec3 359 }
Dance 0:f1ecca559ec3 360
Dance 0:f1ecca559ec3 361 for (uint32_t i=0; i<rxFifoCount; i+=4) {
Dance 0:f1ecca559ec3 362 (void) OTG_FS->FIFO[0][0];
Dance 0:f1ecca559ec3 363 }
Dance 0:f1ecca559ec3 364 OTG_FS->GREGS.GINTSTS = (1 << 4);
Dance 0:f1ecca559ec3 365 }
Dance 0:f1ecca559ec3 366
Dance 0:f1ecca559ec3 367 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
Dance 0:f1ecca559ec3 368 // Loop through the in endpoints
Dance 0:f1ecca559ec3 369 for (uint32_t i=0; i<4; i++) {
Dance 0:f1ecca559ec3 370 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
Dance 0:f1ecca559ec3 371
Dance 0:f1ecca559ec3 372 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
Dance 0:f1ecca559ec3 373 // If the Tx FIFO is empty on EP0 we need to send a further
Dance 0:f1ecca559ec3 374 // packet, so call EP0in()
Dance 0:f1ecca559ec3 375 if (i == 0) {
Dance 0:f1ecca559ec3 376 EP0in();
Dance 0:f1ecca559ec3 377 }
Dance 0:f1ecca559ec3 378 // Clear the interrupt
Dance 0:f1ecca559ec3 379 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
Dance 0:f1ecca559ec3 380 // Stop firing Tx empty interrupts
Dance 0:f1ecca559ec3 381 // Will get turned on again if another write is called
Dance 0:f1ecca559ec3 382 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
Dance 0:f1ecca559ec3 383 }
Dance 0:f1ecca559ec3 384
Dance 0:f1ecca559ec3 385 // If the transfer is complete
Dance 0:f1ecca559ec3 386 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
Dance 0:f1ecca559ec3 387 epComplete |= (1 << (1 + (i << 1)));
Dance 0:f1ecca559ec3 388 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
Dance 0:f1ecca559ec3 389 }
Dance 0:f1ecca559ec3 390 }
Dance 0:f1ecca559ec3 391 }
Dance 0:f1ecca559ec3 392 OTG_FS->GREGS.GINTSTS = (1 << 18);
Dance 0:f1ecca559ec3 393 }
Dance 0:f1ecca559ec3 394
Dance 0:f1ecca559ec3 395 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
Dance 0:f1ecca559ec3 396 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
Dance 0:f1ecca559ec3 397 OTG_FS->GREGS.GINTSTS = (1 << 3);
Dance 0:f1ecca559ec3 398 }
Dance 0:f1ecca559ec3 399 }
Dance 0:f1ecca559ec3 400
Dance 0:f1ecca559ec3 401
Dance 0:f1ecca559ec3 402 #endif