Ales Zupanc

Important changes to forums and questions

All forums and questions are now archived. To start a new conversation or read the latest updates go to forums.mbed.com.

6 years, 7 months ago.

Interrupts help

Hi guys,

can somebody please help me work out with these NVIC "settings" for external interrupts in mbed online compiler for NUCLEO-F767ZI? So I'd like to have 50 input interrupts. I thought that I can configure them simple by using mbed function 

InterruptIn in[]={...pin names...}

and it works UNTIL I use more than 5 Interrupt pins. When I use 6, then 1 won't work, when I use 7, then 2 won't work, and so on... A think thad thad might be MBED online compilers bug. I think that the only way to configure 50 interrupts on input pins is by using NVIC or is there any other way? I know that STM32F7 doesn't have 50 external interrupt handlers - the pins are grouped together by same pin numbers, but that doesn't even bother me. I just need to have at least one interrupt handler for all 50 pins.

Best regards, Ales Zupanc

1 Answer

Mark Peter Vargha
6 years, 7 months ago.

You can not use EXTI on all pins at the same time. See this question: https://developer.mbed.org/questions/78709/What-are-mbed-files-that-contain-pin-ext

And check STM32F7xx datasheet on page 26: http://www.st.com/content/ccc/resource/technical/document/datasheet/group3/c5/37/9c/1d/a6/09/4e/1a/DM00273119/files/DM00273119.pdf/jcr:content/translations/en.DM00273119.pdf

Hm... So How can I configure all those pins as interrupt pins? PA_0, PC_15, PA_1, PC_14, PA_4, PH_1, PB_0, PC_1, PC_2, PC_0, PC_3, PD_3, PD_4, PG_2, PD_5, PG_3, PD_6, PE_2, PD_7, PE_4, PE_3, PE_5, PF_2, PF_1, PF_8, PF_0, PF_9, PD_1, PD_0, PG_1, PG_0, PE_1, PG_9, PG_15, PG_12, PG_10, PG_13, PD_9, PG_11

posted by Ales Zupanc 04 Sep 2017

You can't. Have you read my answer on the other question? Have you read the MCU's reference manual? There are 16 + 8 EXTI lines in an F7. GPIOs are grouped to EXTI channels, so you can not set same IO of multiple ports. (Example: PA_0 and PB_0 could not be interrupt in at the same time.) See figure 30 (292p) in the reference manual here: http://www.st.com/content/ccc/resource/technical/document/reference_manual/c5/cf/ef/52/c0/f1/4b/fa/DM00124865.pdf/files/DM00124865.pdf/jcr:content/translations/en.DM00124865.pdf

posted by Mark Peter Vargha 05 Sep 2017