So next question about shady regions in the manual:: ADC/DMA/LL?
What do you put in the Linked List when you use them during ADC? The channel registers ADODR0..7? How else does it know what channels to pick (See page 581 of user.manual.lpc17xx.pdf).
Do DMA modes like p2m not just say one address is incremented (memory) and the other isn't (the peripheral).
When DMA is using the global ADC register that creates the slip, it reads this register a number of times. But if you have a linked list it can't (my guess) and it maybe that you can start using the slip-less channel data registers (ie ADODR0..7) in the LL. The DMA would even clear the done bit (just by reading).
I also start to get the impression that the burst mode requirement is only caused by triggering the ADC by DMA. But if you can run the DMA itself with a LL on the ADODR0..7 registers you can use it for cherry picking samples from a continuous stream if you let the ADC run free at a much higher rate. Then what is the difference between ADODR0..7 and GPIO (both are just memory addresses).
As I look to the LL stuff it also seems (at least I get the impression from p613 of user.manual.lpc17xx.pdf) like a nice way to get rid of the interleaved ADC samples (from burst DMA) and store everything in a separate array.
Another question: Is it possible to set the PLL clock to 65 MHz without loosing timers, USB etc?
On 65 MHz (or 130 MHz) you can exactly time the DMA to 5us multiples because of the 65 cycles for a conversion. OK this would scarifies some processing power but it would free the CPU from interrupt overhead.
Personally I would still like to be able to use the DMA as it's silent and runs in the background without interrupts overhead etc. The 96 MHz clock and the 65 cycles just make DMA not usable from a timing perspective.