seiichi horie
First Publish. Works fine.
Dependents: unzen_sample_nucleo_f746 unzen_delay_sample_nucleo_f746 skeleton_unzen_nucleo_f746 ifmag_noise_canceller ... more
Nucleo F746ZG用のオーディオ・フレームワークです。フレームワーク地震の詳細は『雲仙』オーディオ・フレームワークを参照してください。
参考リンク
- skeleton_unzen_nucleo_f746 Nucleo F746ZGおよびUI基板を使う場合のスケルトンプログラム。F746を使う方はここから読み始めると良いでしょう。
Diff: unzen_hal.cpp
- Revision:
- 16:9db140409038
- Parent:
- 15:76871e578c10
--- a/unzen_hal.cpp Sun Jun 05 06:31:00 2016 +0000
+++ b/unzen_hal.cpp Sun Jun 12 13:46:43 2016 +0000
@@ -1,5 +1,6 @@
#include "unzen_hal.h"
+// #define DEBUGSAI
namespace unzen
{
// for timing control.
@@ -19,6 +20,17 @@
// Setup PLL
// RCC_PLLCFGR : Has PLLM ( Division Factor M )
// RCC_CIR : PLL clock interrupt register
+ // RCC_CFGR
+
+ // RCC_DKCFGR1 : RCC Dedicated clocks configuration register
+ // clear the relevant field
+ RCC->DCKCFGR1 &= ~ (
+ 3 << 20 | // SAI1 SEL
+ 31 << 8 ); // PLLSAIDIVQ
+ // set the value
+ RCC->DCKCFGR1 |=
+ 0 << 20 | // SAI1 SEL : 0, PLLSAI
+ 0 << 8 ; // PLLSAIDIVQ : 0, div by 1
// RCC_PLLSAICFGR : PLLSAI configuration register. mbed set the pre-devider as 8. So, PLL input is 1MHz
// The VCO have to be more than 100Mhaz. So, set it 192MHz.
@@ -34,16 +46,6 @@
while ( !( RCC->CR & ( 1<<29 ) ) )
;
- // RCC_CFGR
- // RCC_DKCFGR1 : RCC Dedicated clocks configuration register
- // clear the relevant field
- RCC->DCKCFGR1 &= ~ (
- 3 << 20 | // SAI1 SEL
- 31 << 8 ); // PLLSAIDIVQ
- // set the value
- RCC->DCKCFGR1 |=
- 0 << 20 | // SAI1 SEL : 0, PLLSAI
- 0 << 8 ; // PLLSAIDIVQ : 0, div by 1
// RCC_APB2ENR : APB2 peripherals clock enable register
RCC->APB2ENR |= ( 1 << 22); // SAI1 enable
@@ -82,19 +84,26 @@
// Block A : RX
// Block B : TX
SAI1_Block_A->CR1 =
+#ifndef DEBUGSAI
0 << 20 | // MCKDIV : Meaningless because the block is slave mode.
- 0 << 19 | // NODIV : Master clock divider is enabled ( perhaps, meaningless in slave mode )
+#else
+ 2 << 20 | // MCKDIV : Master Clock Divider.: Div by 4
+#endif
+ 1 << 19 | // NODIV : Master clock divider is enabled ( perhaps, meaningless in slave mode )
0 << 17 | // DMAEN : 0, DMA disanble, 1: DMA Enable
0 << 16 | // SAIXEN : 0, Disable, 1, Enable. Disable at this moment
0 << 13 | // OUTDRIV : 0, Audio is driven only when SAIXEN is 1. 1, Audio is driven
0 << 12 | // MONO : 0, Stereo. 1, Mono
0 << 10 | // SYNCEN : 0, Async mode. The Async mode referes the outside sync signal in slave mode.
- 0 << 9 | // CKSTR : 0, sample by falling edge, 1, sample by rising edge. I2S is sample by falling edge
+ 1 << 9 | // CKSTR : 0, sample by falling edge, 1, sample by rising edge. I2S is sample by rising edge
0 << 8 | // LSBFIRST : 0, MSB first. 1, LSB first. I2S is MSB first
7 << 5 | // DS : 7, 32bit.
0 << 2 | // PRTCFG : 0, Free protocol, 1, SPDIF, 2, AC97. I2S is Free protocol
+#ifndef DEBUGSAI
3 << 0 ; // MODE : 0, master tx. 1, master rx. 2, slave tx. 3, slave rx
-
+#else
+ 1 << 0 ; // MODE : 0, master tx. 1, master rx. 2, slave tx. 3, slave rx
+#endif
// configuration register 2
SAI1_Block_A->CR2 =
0 << 14 | // COMP : 0, No companding
@@ -118,7 +127,7 @@
SAI1_Block_A->SLOTR =
0xFFFF << 16 | // SLOTEN : bit mask to specify the active slot. In I2S, 2 slts are active.
1 << 8 | // NBSLOT : Number of slots - 1 ( Ref manual seems to be wrong )
- 0 << 6 | // SLOTSZ : 0, same with data size. 1, 16bit. 2, 32bit
+ 2 << 6 | // SLOTSZ : 0, same with data size. 1, 16bit. 2, 32bit
0 << 0 ; // FBOFF : The manual is not clear. Perhaps, 0 is OK.
// interrupt mask. Only FIFO interrupt is allowed.
@@ -145,7 +154,7 @@
0 << 13 | // OUTDRIV : 0, Audio is driven only when SAIXEN is 1. 1, Audio is driven
0 << 12 | // MONO : 0, Stereo. 1, Mono
1 << 10 | // SYNCEN : 1, sync with internal audio block.
- 0 << 9 | // CKSTR : 0, sample by falling edge, 1, sample by rising edge. I2S is sample by falling edge
+ 1 << 9 | // CKSTR : 0, sample by falling edge, 1, sample by rising edge. I2S is sample by rising edge
0 << 8 | // LSBFIRST : 0, MSB first. 1, LSB first. I2S is MSB first
7 << 5 | // DS : 7, 32bit.
0 << 2 | // PRTCFG : 0, Free protocol, 1, SPDIF, 2, AC97. I2S is Free protocol
@@ -174,7 +183,7 @@
SAI1_Block_B->SLOTR =
0xFFFF << 16 | // SLOTEN : bit mask to specify the active slot. In I2S, 2 slts are active.
1 << 8 | // NBSLOT : Number of slots - 1 ( Ref manual seems to be wrong )
- 0 << 6 | // SLOTSZ : 0, same with data size. 1, 16bit. 2, 32bit
+ 2 << 6 | // SLOTSZ : 0, same with data size. 1, 16bit. 2, 32bit
0 << 0 ; // FBOFF : The manual is not clear. Perhaps, 0 is OK.
// interrupt mask : TX doesn't trigger interrupt
@@ -223,9 +232,9 @@
// Set the pin mode
GPIOE->MODER |=
2 << 6 | // PE3 is Alternate Function
- 0 << 8 | // PE4 is input
- 0 << 10 | // PE5 is input
- 0 << 12; // PE6 is input
+ 2 << 8 | // PE4 is Alternate Function
+ 2 << 10 | // PE5 is Alternate Function
+ 2 << 12; // PE6 is Alternate Function
// Clear the OTYPE field of PE3-6 ( Clear is push-pull )