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TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:: Kojto
Date:: Tue Oct 28 16:40:41 2014 +0000
Revision:: 90:cb3d968589d8
Parent:: 85:024bf7f99721
Child:: 99:dbbf35b96557

Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_hal_adc.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
Kojto	90:cb3d968589d8	5	* @version V1.1.0
Kojto	90:cb3d968589d8	6	* @date 19-June-2014
emilmont	77:869cf507173a	7	* @brief Header file of ADC HAL extension module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
emilmont	77:869cf507173a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_ADC_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_ADC_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	47	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	48
emilmont	77:869cf507173a	49	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
emilmont	77:869cf507173a	52
emilmont	77:869cf507173a	53	/** @addtogroup ADC
emilmont	77:869cf507173a	54	* @{
emilmont	77:869cf507173a	55	*/
emilmont	77:869cf507173a	56
emilmont	77:869cf507173a	57	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	58
emilmont	77:869cf507173a	59	/**
emilmont	77:869cf507173a	60	* @brief HAL State structures definition
emilmont	77:869cf507173a	61	*/
emilmont	77:869cf507173a	62	typedef enum
emilmont	77:869cf507173a	63	{
emilmont	77:869cf507173a	64	HAL_ADC_STATE_RESET = 0x00, /!< ADC not yet initialized or disabled /
emilmont	77:869cf507173a	65	HAL_ADC_STATE_READY = 0x01, /!< ADC peripheral ready for use /
emilmont	77:869cf507173a	66	HAL_ADC_STATE_BUSY = 0x02, /!< An internal process is ongoing /
emilmont	77:869cf507173a	67	HAL_ADC_STATE_BUSY_REG = 0x12, /!< Regular conversion is ongoing /
emilmont	77:869cf507173a	68	HAL_ADC_STATE_BUSY_INJ = 0x22, /!< Injected conversion is ongoing /
emilmont	77:869cf507173a	69	HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /!< Injected and regular conversion are ongoing /
emilmont	77:869cf507173a	70	HAL_ADC_STATE_TIMEOUT = 0x03, /!< Timeout state /
emilmont	77:869cf507173a	71	HAL_ADC_STATE_ERROR = 0x04, /!< ADC state error /
emilmont	77:869cf507173a	72	HAL_ADC_STATE_EOC = 0x05, /!< Conversion is completed /
emilmont	77:869cf507173a	73	HAL_ADC_STATE_EOC_REG = 0x15, /!< Regular conversion is completed /
emilmont	77:869cf507173a	74	HAL_ADC_STATE_EOC_INJ = 0x25, /!< Injected conversion is completed /
emilmont	77:869cf507173a	75	HAL_ADC_STATE_EOC_INJ_REG = 0x35, /!< Injected and regular conversion are completed /
emilmont	77:869cf507173a	76	HAL_ADC_STATE_AWD = 0x06 /!< ADC state analog watchdog /
emilmont	77:869cf507173a	77
emilmont	77:869cf507173a	78	}HAL_ADC_StateTypeDef;
emilmont	77:869cf507173a	79
emilmont	77:869cf507173a	80	/**
emilmont	77:869cf507173a	81	* @brief ADC Init structure definition
emilmont	77:869cf507173a	82	*/
emilmont	77:869cf507173a	83	typedef struct
emilmont	77:869cf507173a	84	{
emilmont	77:869cf507173a	85	uint32_t ClockPrescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for
emilmont	77:869cf507173a	86	all the ADCs.
emilmont	77:869cf507173a	87	This parameter can be a value of @ref ADC_ClockPrescaler */
emilmont	77:869cf507173a	88	uint32_t Resolution; /*!< Configures the ADC resolution dual mode.
emilmont	77:869cf507173a	89	This parameter can be a value of @ref ADC_Resolution */
emilmont	77:869cf507173a	90	uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
emilmont	77:869cf507173a	91	This parameter can be a value of @ref ADC_data_align */
emilmont	77:869cf507173a	92	uint32_t ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multi channels) or
emilmont	77:869cf507173a	93	Single (one channel) mode.
emilmont	77:869cf507173a	94	This parameter can be set to ENABLE or DISABLE */
emilmont	77:869cf507173a	95	uint32_t EOCSelection; /*!< Specifies whether the EOC flag is set
emilmont	77:869cf507173a	96	at the end of single channel conversion or at the end of all conversions.
emilmont	77:869cf507173a	97	This parameter can be a value of @ref ADC_EOCSelection */
emilmont	77:869cf507173a	98	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
emilmont	77:869cf507173a	99	This parameter can be set to ENABLE or DISABLE. */
emilmont	77:869cf507173a	100	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
emilmont	77:869cf507173a	101	This parameter can be set to ENABLE or DISABLE. */
emilmont	77:869cf507173a	102	uint32_t NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
emilmont	77:869cf507173a	103	regular channel group.
emilmont	77:869cf507173a	104	This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
emilmont	77:869cf507173a	105	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
emilmont	77:869cf507173a	106	for regular channels.
emilmont	77:869cf507173a	107	This parameter can be set to ENABLE or DISABLE. */
emilmont	77:869cf507173a	108	uint32_t NbrOfDiscConversion; /*!< Specifies the number of ADC discontinuous conversions that will be done
emilmont	77:869cf507173a	109	using the sequencer for regular channel group.
emilmont	77:869cf507173a	110	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
emilmont	77:869cf507173a	111	uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group.
emilmont	77:869cf507173a	112	This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
emilmont	77:869cf507173a	113	uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group.
emilmont	77:869cf507173a	114	This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
emilmont	77:869cf507173a	115	}ADC_InitTypeDef;
emilmont	77:869cf507173a	116
emilmont	77:869cf507173a	117	/**
emilmont	77:869cf507173a	118	* @brief ADC handle Structure definition
emilmont	77:869cf507173a	119	*/
emilmont	77:869cf507173a	120	typedef struct
emilmont	77:869cf507173a	121	{
emilmont	77:869cf507173a	122	ADC_TypeDef Instance; /!< Register base address */
emilmont	77:869cf507173a	123
emilmont	77:869cf507173a	124	ADC_InitTypeDef Init; /!< ADC required parameters /
emilmont	77:869cf507173a	125
emilmont	77:869cf507173a	126	__IO uint32_t NbrOfCurrentConversionRank; /!< ADC number of current conversion rank /
emilmont	77:869cf507173a	127
emilmont	77:869cf507173a	128	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
emilmont	77:869cf507173a	129
emilmont	77:869cf507173a	130	HAL_LockTypeDef Lock; /!< ADC locking object /
emilmont	77:869cf507173a	131
emilmont	77:869cf507173a	132	__IO HAL_ADC_StateTypeDef State; /!< ADC communication state /
emilmont	77:869cf507173a	133
emilmont	77:869cf507173a	134	__IO uint32_t ErrorCode; /!< ADC Error code /
emilmont	77:869cf507173a	135	}ADC_HandleTypeDef;
emilmont	77:869cf507173a	136
emilmont	77:869cf507173a	137	/**
emilmont	77:869cf507173a	138	* @brief ADC Configuration regular Channel structure definition
emilmont	77:869cf507173a	139	*/
emilmont	77:869cf507173a	140	typedef struct
emilmont	77:869cf507173a	141	{
bogdanm	85:024bf7f99721	142	uint32_t Channel; /*!< The ADC channel to configure.
emilmont	77:869cf507173a	143	This parameter can be a value of @ref ADC_channels */
bogdanm	85:024bf7f99721	144	uint32_t Rank; /*!< The rank in the regular group sequencer.
emilmont	77:869cf507173a	145	This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
emilmont	77:869cf507173a	146	uint32_t SamplingTime; /*!< The sample time value to be set for the selected channel.
emilmont	77:869cf507173a	147	This parameter can be a value of @ref ADC_sampling_times */
emilmont	77:869cf507173a	148	uint32_t Offset; /!< Reserved for future use, can be set to 0 /
emilmont	77:869cf507173a	149	}ADC_ChannelConfTypeDef;
emilmont	77:869cf507173a	150
emilmont	77:869cf507173a	151	/**
emilmont	77:869cf507173a	152	* @brief ADC Configuration multi-mode structure definition
emilmont	77:869cf507173a	153	*/
emilmont	77:869cf507173a	154	typedef struct
emilmont	77:869cf507173a	155	{
emilmont	77:869cf507173a	156	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
bogdanm	85:024bf7f99721	157	This parameter can be a value of @ref ADC_analog_watchdog_selection */
emilmont	77:869cf507173a	158	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
emilmont	77:869cf507173a	159	This parameter must be a 12-bit value. */
emilmont	77:869cf507173a	160	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
emilmont	77:869cf507173a	161	This parameter must be a 12-bit value. */
emilmont	77:869cf507173a	162	uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
emilmont	77:869cf507173a	163	This parameter has an effect only if watchdog mode is configured on single channel
bogdanm	85:024bf7f99721	164	This parameter can be a value of @ref ADC_channels */
emilmont	77:869cf507173a	165	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
emilmont	77:869cf507173a	166	is interrupt mode or in polling mode.
emilmont	77:869cf507173a	167	This parameter can be set to ENABLE or DISABLE */
emilmont	77:869cf507173a	168	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
emilmont	77:869cf507173a	169	}ADC_AnalogWDGConfTypeDef;
emilmont	77:869cf507173a	170
emilmont	77:869cf507173a	171	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	172
emilmont	77:869cf507173a	173	/** @defgroup ADC_Exported_Constants
emilmont	77:869cf507173a	174	* @{
emilmont	77:869cf507173a	175	*/
emilmont	77:869cf507173a	176
emilmont	77:869cf507173a	177
emilmont	77:869cf507173a	178	/** @defgroup ADC_Error_Code
emilmont	77:869cf507173a	179	* @{
emilmont	77:869cf507173a	180	*/
emilmont	77:869cf507173a	181
emilmont	77:869cf507173a	182	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /!< No error /
emilmont	77:869cf507173a	183	#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /!< OVR error /
emilmont	77:869cf507173a	184	#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /!< DMA transfer error /
emilmont	77:869cf507173a	185	/**
emilmont	77:869cf507173a	186	* @}
emilmont	77:869cf507173a	187	*/
emilmont	77:869cf507173a	188
emilmont	77:869cf507173a	189
emilmont	77:869cf507173a	190	/** @defgroup ADC_ClockPrescaler
emilmont	77:869cf507173a	191	* @{
emilmont	77:869cf507173a	192	*/
emilmont	77:869cf507173a	193	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	194	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
emilmont	77:869cf507173a	195	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
emilmont	77:869cf507173a	196	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
emilmont	77:869cf507173a	197	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) \|\| \
emilmont	77:869cf507173a	198	((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) \|\| \
emilmont	77:869cf507173a	199	((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) \|\| \
emilmont	77:869cf507173a	200	((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
emilmont	77:869cf507173a	201	/**
emilmont	77:869cf507173a	202	* @}
emilmont	77:869cf507173a	203	*/
emilmont	77:869cf507173a	204
Kojto	90:cb3d968589d8	205	/** @defgroup ADC_delay_between_2_sampling_phases
Kojto	90:cb3d968589d8	206	* @{
Kojto	90:cb3d968589d8	207	*/
Kojto	90:cb3d968589d8	208	#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	209	#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
Kojto	90:cb3d968589d8	210	#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
Kojto	90:cb3d968589d8	211	#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
Kojto	90:cb3d968589d8	212	#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
Kojto	90:cb3d968589d8	213	#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0))
Kojto	90:cb3d968589d8	214	#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1))
Kojto	90:cb3d968589d8	215	#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
Kojto	90:cb3d968589d8	216	#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
Kojto	90:cb3d968589d8	217	#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0))
Kojto	90:cb3d968589d8	218	#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1))
Kojto	90:cb3d968589d8	219	#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
Kojto	90:cb3d968589d8	220	#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2))
Kojto	90:cb3d968589d8	221	#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0))
Kojto	90:cb3d968589d8	222	#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1))
Kojto	90:cb3d968589d8	223	#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
Kojto	90:cb3d968589d8	224
Kojto	90:cb3d968589d8	225	#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) \|\| \
Kojto	90:cb3d968589d8	226	((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) \|\| \
Kojto	90:cb3d968589d8	227	((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) \|\| \
Kojto	90:cb3d968589d8	228	((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) \|\| \
Kojto	90:cb3d968589d8	229	((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) \|\| \
Kojto	90:cb3d968589d8	230	((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) \|\| \
Kojto	90:cb3d968589d8	231	((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) \|\| \
Kojto	90:cb3d968589d8	232	((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) \|\| \
Kojto	90:cb3d968589d8	233	((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) \|\| \
Kojto	90:cb3d968589d8	234	((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) \|\| \
Kojto	90:cb3d968589d8	235	((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) \|\| \
Kojto	90:cb3d968589d8	236	((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) \|\| \
Kojto	90:cb3d968589d8	237	((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) \|\| \
Kojto	90:cb3d968589d8	238	((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) \|\| \
Kojto	90:cb3d968589d8	239	((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) \|\| \
Kojto	90:cb3d968589d8	240	((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
Kojto	90:cb3d968589d8	241	/**
Kojto	90:cb3d968589d8	242	* @}
Kojto	90:cb3d968589d8	243	*/
Kojto	90:cb3d968589d8	244
emilmont	77:869cf507173a	245	/** @defgroup ADC_Resolution
emilmont	77:869cf507173a	246	* @{
emilmont	77:869cf507173a	247	*/
emilmont	77:869cf507173a	248	#define ADC_RESOLUTION12b ((uint32_t)0x00000000)
emilmont	77:869cf507173a	249	#define ADC_RESOLUTION10b ((uint32_t)ADC_CR1_RES_0)
emilmont	77:869cf507173a	250	#define ADC_RESOLUTION8b ((uint32_t)ADC_CR1_RES_1)
emilmont	77:869cf507173a	251	#define ADC_RESOLUTION6b ((uint32_t)ADC_CR1_RES)
emilmont	77:869cf507173a	252
emilmont	77:869cf507173a	253	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) \|\| \
emilmont	77:869cf507173a	254	((RESOLUTION) == ADC_RESOLUTION10b) \|\| \
emilmont	77:869cf507173a	255	((RESOLUTION) == ADC_RESOLUTION8b) \|\| \
emilmont	77:869cf507173a	256	((RESOLUTION) == ADC_RESOLUTION6b))
emilmont	77:869cf507173a	257	/**
emilmont	77:869cf507173a	258	* @}
emilmont	77:869cf507173a	259	*/
emilmont	77:869cf507173a	260
emilmont	77:869cf507173a	261	/** @defgroup ADC_External_trigger_edge_Regular
emilmont	77:869cf507173a	262	* @{
emilmont	77:869cf507173a	263	*/
emilmont	77:869cf507173a	264	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	265	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
emilmont	77:869cf507173a	266	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
emilmont	77:869cf507173a	267	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
emilmont	77:869cf507173a	268
emilmont	77:869cf507173a	269	#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
emilmont	77:869cf507173a	270	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
emilmont	77:869cf507173a	271	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
emilmont	77:869cf507173a	272	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
emilmont	77:869cf507173a	273	/**
emilmont	77:869cf507173a	274	* @}
emilmont	77:869cf507173a	275	*/
emilmont	77:869cf507173a	276
emilmont	77:869cf507173a	277	/** @defgroup ADC_External_trigger_Source_Regular
emilmont	77:869cf507173a	278	* @{
emilmont	77:869cf507173a	279	*/
emilmont	77:869cf507173a	280	#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	281	#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
emilmont	77:869cf507173a	282	#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
emilmont	77:869cf507173a	283	#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
emilmont	77:869cf507173a	284	#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
emilmont	77:869cf507173a	285	#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
emilmont	77:869cf507173a	286	#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1))
emilmont	77:869cf507173a	287	#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
emilmont	77:869cf507173a	288	#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
emilmont	77:869cf507173a	289	#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0))
emilmont	77:869cf507173a	290	#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1))
emilmont	77:869cf507173a	291	#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
emilmont	77:869cf507173a	292	#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2))
emilmont	77:869cf507173a	293	#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
emilmont	77:869cf507173a	294	#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1))
emilmont	77:869cf507173a	295	#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
emilmont	77:869cf507173a	296
emilmont	77:869cf507173a	297	#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
emilmont	77:869cf507173a	298	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
emilmont	77:869cf507173a	299	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
emilmont	77:869cf507173a	300	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
emilmont	77:869cf507173a	301	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \|\| \
emilmont	77:869cf507173a	302	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) \|\| \
emilmont	77:869cf507173a	303	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
emilmont	77:869cf507173a	304	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) \|\| \
emilmont	77:869cf507173a	305	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
emilmont	77:869cf507173a	306	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
emilmont	77:869cf507173a	307	((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) \|\| \
emilmont	77:869cf507173a	308	((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) \|\| \
emilmont	77:869cf507173a	309	((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) \|\| \
emilmont	77:869cf507173a	310	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) \|\| \
emilmont	77:869cf507173a	311	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) \|\| \
emilmont	77:869cf507173a	312	((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
emilmont	77:869cf507173a	313	/**
emilmont	77:869cf507173a	314	* @}
emilmont	77:869cf507173a	315	*/
emilmont	77:869cf507173a	316
emilmont	77:869cf507173a	317	/** @defgroup ADC_data_align
emilmont	77:869cf507173a	318	* @{
emilmont	77:869cf507173a	319	*/
emilmont	77:869cf507173a	320	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
emilmont	77:869cf507173a	321	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
emilmont	77:869cf507173a	322
emilmont	77:869cf507173a	323	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
emilmont	77:869cf507173a	324	((ALIGN) == ADC_DATAALIGN_LEFT))
emilmont	77:869cf507173a	325	/**
emilmont	77:869cf507173a	326	* @}
emilmont	77:869cf507173a	327	*/
emilmont	77:869cf507173a	328
emilmont	77:869cf507173a	329	/** @defgroup ADC_channels
emilmont	77:869cf507173a	330	* @{
emilmont	77:869cf507173a	331	*/
emilmont	77:869cf507173a	332	#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	333	#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
emilmont	77:869cf507173a	334	#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
emilmont	77:869cf507173a	335	#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
emilmont	77:869cf507173a	336	#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
emilmont	77:869cf507173a	337	#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0))
emilmont	77:869cf507173a	338	#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1))
emilmont	77:869cf507173a	339	#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
emilmont	77:869cf507173a	340	#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
emilmont	77:869cf507173a	341	#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0))
emilmont	77:869cf507173a	342	#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1))
emilmont	77:869cf507173a	343	#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
emilmont	77:869cf507173a	344	#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2))
emilmont	77:869cf507173a	345	#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0))
emilmont	77:869cf507173a	346	#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1))
emilmont	77:869cf507173a	347	#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
emilmont	77:869cf507173a	348	#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
emilmont	77:869cf507173a	349	#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_0))
emilmont	77:869cf507173a	350	#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_1))
emilmont	77:869cf507173a	351
emilmont	77:869cf507173a	352	#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
emilmont	77:869cf507173a	353	#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
emilmont	77:869cf507173a	354	#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
emilmont	77:869cf507173a	355
emilmont	77:869cf507173a	356	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
emilmont	77:869cf507173a	357	((CHANNEL) == ADC_CHANNEL_1) \|\| \
emilmont	77:869cf507173a	358	((CHANNEL) == ADC_CHANNEL_2) \|\| \
emilmont	77:869cf507173a	359	((CHANNEL) == ADC_CHANNEL_3) \|\| \
emilmont	77:869cf507173a	360	((CHANNEL) == ADC_CHANNEL_4) \|\| \
emilmont	77:869cf507173a	361	((CHANNEL) == ADC_CHANNEL_5) \|\| \
emilmont	77:869cf507173a	362	((CHANNEL) == ADC_CHANNEL_6) \|\| \
emilmont	77:869cf507173a	363	((CHANNEL) == ADC_CHANNEL_7) \|\| \
emilmont	77:869cf507173a	364	((CHANNEL) == ADC_CHANNEL_8) \|\| \
emilmont	77:869cf507173a	365	((CHANNEL) == ADC_CHANNEL_9) \|\| \
emilmont	77:869cf507173a	366	((CHANNEL) == ADC_CHANNEL_10) \|\| \
emilmont	77:869cf507173a	367	((CHANNEL) == ADC_CHANNEL_11) \|\| \
emilmont	77:869cf507173a	368	((CHANNEL) == ADC_CHANNEL_12) \|\| \
emilmont	77:869cf507173a	369	((CHANNEL) == ADC_CHANNEL_13) \|\| \
emilmont	77:869cf507173a	370	((CHANNEL) == ADC_CHANNEL_14) \|\| \
emilmont	77:869cf507173a	371	((CHANNEL) == ADC_CHANNEL_15) \|\| \
emilmont	77:869cf507173a	372	((CHANNEL) == ADC_CHANNEL_16) \|\| \
emilmont	77:869cf507173a	373	((CHANNEL) == ADC_CHANNEL_17) \|\| \
emilmont	77:869cf507173a	374	((CHANNEL) == ADC_CHANNEL_18))
emilmont	77:869cf507173a	375	/**
emilmont	77:869cf507173a	376	* @}
emilmont	77:869cf507173a	377	*/
emilmont	77:869cf507173a	378
emilmont	77:869cf507173a	379	/** @defgroup ADC_sampling_times
emilmont	77:869cf507173a	380	* @{
emilmont	77:869cf507173a	381	*/
emilmont	77:869cf507173a	382	#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
emilmont	77:869cf507173a	383	#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
emilmont	77:869cf507173a	384	#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
emilmont	77:869cf507173a	385	#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 \| ADC_SMPR1_SMP10_0))
emilmont	77:869cf507173a	386	#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
emilmont	77:869cf507173a	387	#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_0))
emilmont	77:869cf507173a	388	#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_1))
emilmont	77:869cf507173a	389	#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
emilmont	77:869cf507173a	390
emilmont	77:869cf507173a	391	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) \|\| \
emilmont	77:869cf507173a	392	((TIME) == ADC_SAMPLETIME_15CYCLES) \|\| \
emilmont	77:869cf507173a	393	((TIME) == ADC_SAMPLETIME_28CYCLES) \|\| \
emilmont	77:869cf507173a	394	((TIME) == ADC_SAMPLETIME_56CYCLES) \|\| \
emilmont	77:869cf507173a	395	((TIME) == ADC_SAMPLETIME_84CYCLES) \|\| \
emilmont	77:869cf507173a	396	((TIME) == ADC_SAMPLETIME_112CYCLES) \|\| \
emilmont	77:869cf507173a	397	((TIME) == ADC_SAMPLETIME_144CYCLES) \|\| \
emilmont	77:869cf507173a	398	((TIME) == ADC_SAMPLETIME_480CYCLES))
emilmont	77:869cf507173a	399	/**
emilmont	77:869cf507173a	400	* @}
emilmont	77:869cf507173a	401	*/
emilmont	77:869cf507173a	402
emilmont	77:869cf507173a	403	/** @defgroup ADC_EOCSelection
emilmont	77:869cf507173a	404	* @{
emilmont	77:869cf507173a	405	*/
emilmont	77:869cf507173a	406	#define EOC_SEQ_CONV ((uint32_t)0x00000000)
emilmont	77:869cf507173a	407	#define EOC_SINGLE_CONV ((uint32_t)0x00000001)
emilmont	77:869cf507173a	408	#define EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /!< reserved for future use /
emilmont	77:869cf507173a	409
emilmont	77:869cf507173a	410	#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV) \|\| \
emilmont	77:869cf507173a	411	((EOCSelection) == EOC_SEQ_CONV) \|\| \
emilmont	77:869cf507173a	412	((EOCSelection) == EOC_SINGLE_SEQ_CONV))
emilmont	77:869cf507173a	413	/**
emilmont	77:869cf507173a	414	* @}
emilmont	77:869cf507173a	415	*/
emilmont	77:869cf507173a	416
emilmont	77:869cf507173a	417	/** @defgroup ADC_Event_type
emilmont	77:869cf507173a	418	* @{
emilmont	77:869cf507173a	419	*/
emilmont	77:869cf507173a	420	#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
emilmont	77:869cf507173a	421	#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
emilmont	77:869cf507173a	422
emilmont	77:869cf507173a	423	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) \|\| \
emilmont	77:869cf507173a	424	((EVENT) == OVR_EVENT))
emilmont	77:869cf507173a	425	/**
emilmont	77:869cf507173a	426	* @}
emilmont	77:869cf507173a	427	*/
emilmont	77:869cf507173a	428
emilmont	77:869cf507173a	429	/** @defgroup ADC_analog_watchdog_selection
emilmont	77:869cf507173a	430	* @{
emilmont	77:869cf507173a	431	*/
emilmont	77:869cf507173a	432	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
emilmont	77:869cf507173a	433	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
emilmont	77:869cf507173a	434	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
emilmont	77:869cf507173a	435	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
emilmont	77:869cf507173a	436	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
emilmont	77:869cf507173a	437	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
emilmont	77:869cf507173a	438	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	439
emilmont	77:869cf507173a	440	#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
emilmont	77:869cf507173a	441	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
emilmont	77:869cf507173a	442	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
emilmont	77:869cf507173a	443	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
emilmont	77:869cf507173a	444	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
emilmont	77:869cf507173a	445	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) \|\| \
emilmont	77:869cf507173a	446	((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
emilmont	77:869cf507173a	447	/**
emilmont	77:869cf507173a	448	* @}
emilmont	77:869cf507173a	449	*/
emilmont	77:869cf507173a	450
emilmont	77:869cf507173a	451	/** @defgroup ADC_interrupts_definition
emilmont	77:869cf507173a	452	* @{
emilmont	77:869cf507173a	453	*/
emilmont	77:869cf507173a	454	#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
emilmont	77:869cf507173a	455	#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
emilmont	77:869cf507173a	456	#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
emilmont	77:869cf507173a	457	#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
emilmont	77:869cf507173a	458
emilmont	77:869cf507173a	459	#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) \|\| ((IT) == ADC_IT_AWD) \|\| \
emilmont	77:869cf507173a	460	((IT) == ADC_IT_JEOC)\|\| ((IT) == ADC_IT_OVR))
emilmont	77:869cf507173a	461	/**
emilmont	77:869cf507173a	462	* @}
emilmont	77:869cf507173a	463	*/
emilmont	77:869cf507173a	464
emilmont	77:869cf507173a	465	/** @defgroup ADC_flags_definition
emilmont	77:869cf507173a	466	* @{
emilmont	77:869cf507173a	467	*/
emilmont	77:869cf507173a	468	#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
emilmont	77:869cf507173a	469	#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
emilmont	77:869cf507173a	470	#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
emilmont	77:869cf507173a	471	#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
emilmont	77:869cf507173a	472	#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
emilmont	77:869cf507173a	473	#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
emilmont	77:869cf507173a	474	/**
emilmont	77:869cf507173a	475	* @}
emilmont	77:869cf507173a	476	*/
emilmont	77:869cf507173a	477
emilmont	77:869cf507173a	478	/** @defgroup ADC_channels_type
emilmont	77:869cf507173a	479	* @{
emilmont	77:869cf507173a	480	*/
emilmont	77:869cf507173a	481	#define ALL_CHANNELS ((uint32_t)0x00000001)
emilmont	77:869cf507173a	482	#define REGULAR_CHANNELS ((uint32_t)0x00000002) /!< reserved for future use /
emilmont	77:869cf507173a	483	#define INJECTED_CHANNELS ((uint32_t)0x00000003) /!< reserved for future use /
emilmont	77:869cf507173a	484
emilmont	77:869cf507173a	485	#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) \|\| \
emilmont	77:869cf507173a	486	((CHANNEL_TYPE) == REGULAR_CHANNELS) \|\| \
emilmont	77:869cf507173a	487	((CHANNEL_TYPE) == INJECTED_CHANNELS))
emilmont	77:869cf507173a	488	/**
emilmont	77:869cf507173a	489	* @}
emilmont	77:869cf507173a	490	*/
emilmont	77:869cf507173a	491
emilmont	77:869cf507173a	492	/** @defgroup ADC_thresholds
emilmont	77:869cf507173a	493	* @{
emilmont	77:869cf507173a	494	*/
emilmont	77:869cf507173a	495	#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
emilmont	77:869cf507173a	496	/**
emilmont	77:869cf507173a	497	* @}
emilmont	77:869cf507173a	498	*/
emilmont	77:869cf507173a	499
emilmont	77:869cf507173a	500	/** @defgroup ADC_regular_length
emilmont	77:869cf507173a	501	* @{
emilmont	77:869cf507173a	502	*/
emilmont	77:869cf507173a	503	#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
emilmont	77:869cf507173a	504	/**
emilmont	77:869cf507173a	505	* @}
emilmont	77:869cf507173a	506	*/
emilmont	77:869cf507173a	507
emilmont	77:869cf507173a	508	/** @defgroup ADC_regular_rank
emilmont	77:869cf507173a	509	* @{
emilmont	77:869cf507173a	510	*/
emilmont	77:869cf507173a	511	#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
emilmont	77:869cf507173a	512	/**
emilmont	77:869cf507173a	513	* @}
emilmont	77:869cf507173a	514	*/
emilmont	77:869cf507173a	515
emilmont	77:869cf507173a	516	/** @defgroup ADC_regular_discontinuous_mode_number
emilmont	77:869cf507173a	517	* @{
emilmont	77:869cf507173a	518	*/
emilmont	77:869cf507173a	519	#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
emilmont	77:869cf507173a	520	/**
emilmont	77:869cf507173a	521	* @}
emilmont	77:869cf507173a	522	*/
emilmont	77:869cf507173a	523
emilmont	77:869cf507173a	524	/** @defgroup ADC_range_verification
emilmont	77:869cf507173a	525	* @{
emilmont	77:869cf507173a	526	*/
emilmont	77:869cf507173a	527	#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
emilmont	77:869cf507173a	528	((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) \|\| \
emilmont	77:869cf507173a	529	(((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) \|\| \
emilmont	77:869cf507173a	530	(((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) \|\| \
emilmont	77:869cf507173a	531	(((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
emilmont	77:869cf507173a	532	/**
emilmont	77:869cf507173a	533	* @}
emilmont	77:869cf507173a	534	*/
emilmont	77:869cf507173a	535
emilmont	77:869cf507173a	536	/**
emilmont	77:869cf507173a	537	* @}
emilmont	77:869cf507173a	538	*/
emilmont	77:869cf507173a	539
emilmont	77:869cf507173a	540	/* Exported macro ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	541
bogdanm	85:024bf7f99721	542	/** @brief Reset ADC handle state
bogdanm	85:024bf7f99721	543	* @param __HANDLE__: ADC handle
bogdanm	85:024bf7f99721	544	* @retval None
bogdanm	85:024bf7f99721	545	*/
bogdanm	85:024bf7f99721	546	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
bogdanm	85:024bf7f99721	547
emilmont	77:869cf507173a	548	/**
emilmont	77:869cf507173a	549	* @brief Enable the ADC peripheral.
emilmont	77:869cf507173a	550	* @param __HANDLE__: ADC handle
emilmont	77:869cf507173a	551	* @retval None
emilmont	77:869cf507173a	552	*/
emilmont	77:869cf507173a	553	#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 \|= ADC_CR2_ADON)
emilmont	77:869cf507173a	554
emilmont	77:869cf507173a	555	/**
emilmont	77:869cf507173a	556	* @brief Disable the ADC peripheral.
emilmont	77:869cf507173a	557	* @param __HANDLE__: ADC handle
emilmont	77:869cf507173a	558	* @retval None
emilmont	77:869cf507173a	559	*/
emilmont	77:869cf507173a	560	#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
emilmont	77:869cf507173a	561
emilmont	77:869cf507173a	562	/**
emilmont	77:869cf507173a	563	* @brief Set ADC Regular channel sequence length.
emilmont	77:869cf507173a	564	* @param _NbrOfConversion_: Regular channel sequence length.
emilmont	77:869cf507173a	565	* @retval None
emilmont	77:869cf507173a	566	*/
emilmont	77:869cf507173a	567	#define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
emilmont	77:869cf507173a	568
emilmont	77:869cf507173a	569	/**
emilmont	77:869cf507173a	570	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
emilmont	77:869cf507173a	571	* @param _SAMPLETIME_: Sample time parameter.
emilmont	77:869cf507173a	572	* @param _CHANNELNB_: Channel number.
emilmont	77:869cf507173a	573	* @retval None
emilmont	77:869cf507173a	574	*/
emilmont	77:869cf507173a	575	#define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
emilmont	77:869cf507173a	576
emilmont	77:869cf507173a	577	/**
emilmont	77:869cf507173a	578	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
emilmont	77:869cf507173a	579	* @param _SAMPLETIME_: Sample time parameter.
emilmont	77:869cf507173a	580	* @param _CHANNELNB_: Channel number.
emilmont	77:869cf507173a	581	* @retval None
emilmont	77:869cf507173a	582	*/
emilmont	77:869cf507173a	583	#define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
emilmont	77:869cf507173a	584
emilmont	77:869cf507173a	585	/**
emilmont	77:869cf507173a	586	* @brief Set the selected regular channel rank for rank between 1 and 6.
emilmont	77:869cf507173a	587	* @param _CHANNELNB_: Channel number.
emilmont	77:869cf507173a	588	* @param _RANKNB_: Rank number.
emilmont	77:869cf507173a	589	* @retval None
emilmont	77:869cf507173a	590	*/
emilmont	77:869cf507173a	591	#define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
emilmont	77:869cf507173a	592
emilmont	77:869cf507173a	593	/**
emilmont	77:869cf507173a	594	* @brief Set the selected regular channel rank for rank between 7 and 12.
emilmont	77:869cf507173a	595	* @param _CHANNELNB_: Channel number.
emilmont	77:869cf507173a	596	* @param _RANKNB_: Rank number.
emilmont	77:869cf507173a	597	* @retval None
emilmont	77:869cf507173a	598	*/
emilmont	77:869cf507173a	599	#define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
emilmont	77:869cf507173a	600
emilmont	77:869cf507173a	601	/**
emilmont	77:869cf507173a	602	* @brief Set the selected regular channel rank for rank between 13 and 16.
emilmont	77:869cf507173a	603	* @param _CHANNELNB_: Channel number.
emilmont	77:869cf507173a	604	* @param _RANKNB_: Rank number.
emilmont	77:869cf507173a	605	* @retval None
emilmont	77:869cf507173a	606	*/
emilmont	77:869cf507173a	607	#define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
emilmont	77:869cf507173a	608
emilmont	77:869cf507173a	609	/**
emilmont	77:869cf507173a	610	* @brief Enable ADC continuous conversion mode.
emilmont	77:869cf507173a	611	* @param _CONTINUOUS_MODE_: Continuous mode.
emilmont	77:869cf507173a	612	* @retval None
emilmont	77:869cf507173a	613	*/
emilmont	77:869cf507173a	614	#define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
emilmont	77:869cf507173a	615
emilmont	77:869cf507173a	616	/**
emilmont	77:869cf507173a	617	* @brief Configures the number of discontinuous conversions for the regular group channels.
emilmont	77:869cf507173a	618	* @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
emilmont	77:869cf507173a	619	* @retval None
emilmont	77:869cf507173a	620	*/
emilmont	77:869cf507173a	621	#define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
emilmont	77:869cf507173a	622
emilmont	77:869cf507173a	623	/**
emilmont	77:869cf507173a	624	* @brief Enable ADC scan mode.
emilmont	77:869cf507173a	625	* @param _SCANCONV_MODE_: Scan conversion mode.
emilmont	77:869cf507173a	626	* @retval None
emilmont	77:869cf507173a	627	*/
emilmont	77:869cf507173a	628	#define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
emilmont	77:869cf507173a	629
emilmont	77:869cf507173a	630	/**
emilmont	77:869cf507173a	631	* @brief Enable the ADC end of conversion selection.
emilmont	77:869cf507173a	632	* @param _EOCSelection_MODE_: End of conversion selection mode.
emilmont	77:869cf507173a	633	* @retval None
emilmont	77:869cf507173a	634	*/
emilmont	77:869cf507173a	635	#define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
emilmont	77:869cf507173a	636
emilmont	77:869cf507173a	637	/**
emilmont	77:869cf507173a	638	* @brief Enable the ADC DMA continuous request.
emilmont	77:869cf507173a	639	* @param _DMAContReq_MODE_: DMA continuous request mode.
emilmont	77:869cf507173a	640	* @retval None
emilmont	77:869cf507173a	641	*/
emilmont	77:869cf507173a	642	#define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
emilmont	77:869cf507173a	643
emilmont	77:869cf507173a	644	/**
emilmont	77:869cf507173a	645	* @brief Enable the ADC end of conversion interrupt.
emilmont	77:869cf507173a	646	* @param __HANDLE__: specifies the ADC Handle.
emilmont	77:869cf507173a	647	* @param __INTERRUPT__: ADC Interrupt.
emilmont	77:869cf507173a	648	* @retval None
emilmont	77:869cf507173a	649	*/
emilmont	77:869cf507173a	650	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) \|= (__INTERRUPT__))
emilmont	77:869cf507173a	651
emilmont	77:869cf507173a	652	/**
emilmont	77:869cf507173a	653	* @brief Disable the ADC end of conversion interrupt.
emilmont	77:869cf507173a	654	* @param __HANDLE__: specifies the ADC Handle.
emilmont	77:869cf507173a	655	* @param __INTERRUPT__: ADC interrupt.
emilmont	77:869cf507173a	656	* @retval None
emilmont	77:869cf507173a	657	*/
emilmont	77:869cf507173a	658	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	659
emilmont	77:869cf507173a	660	/** @brief Check if the specified ADC interrupt source is enabled or disabled.
emilmont	77:869cf507173a	661	* @param __HANDLE__: specifies the ADC Handle.
emilmont	77:869cf507173a	662	* @param __INTERRUPT__: specifies the ADC interrupt source to check.
emilmont	77:869cf507173a	663	* @retval The new state of __IT__ (TRUE or FALSE).
emilmont	77:869cf507173a	664	*/
emilmont	77:869cf507173a	665	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
emilmont	77:869cf507173a	666
emilmont	77:869cf507173a	667	/**
emilmont	77:869cf507173a	668	* @brief Clear the ADC's pending flags.
emilmont	77:869cf507173a	669	* @param __HANDLE__: specifies the ADC Handle.
emilmont	77:869cf507173a	670	* @param __FLAG__: ADC flag.
emilmont	77:869cf507173a	671	* @retval None
emilmont	77:869cf507173a	672	*/
Kojto	90:cb3d968589d8	673	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
emilmont	77:869cf507173a	674
emilmont	77:869cf507173a	675	/**
emilmont	77:869cf507173a	676	* @brief Get the selected ADC's flag status.
emilmont	77:869cf507173a	677	* @param __HANDLE__: specifies the ADC Handle.
emilmont	77:869cf507173a	678	* @param __FLAG__: ADC flag.
emilmont	77:869cf507173a	679	* @retval None
emilmont	77:869cf507173a	680	*/
emilmont	77:869cf507173a	681	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
emilmont	77:869cf507173a	682
emilmont	77:869cf507173a	683	/**
emilmont	77:869cf507173a	684	* @brief Return resolution bits in CR1 register.
emilmont	77:869cf507173a	685	* @param __HANDLE__: ADC handle
emilmont	77:869cf507173a	686	* @retval None
emilmont	77:869cf507173a	687	*/
emilmont	77:869cf507173a	688	#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
emilmont	77:869cf507173a	689
emilmont	77:869cf507173a	690	/* Include ADC HAL Extension module */
emilmont	77:869cf507173a	691	#include "stm32f4xx_hal_adc_ex.h"
emilmont	77:869cf507173a	692
emilmont	77:869cf507173a	693	/* Exported functions --------------------------------------------------------*/
emilmont	77:869cf507173a	694	/* Initialization/de-initialization functions ***********************************/
emilmont	77:869cf507173a	695	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	696	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
bogdanm	81:7d30d6019079	697	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
bogdanm	81:7d30d6019079	698	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	699
emilmont	77:869cf507173a	700	/* I/O operation functions ******************************************************/
emilmont	77:869cf507173a	701	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	702	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	703	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
emilmont	77:869cf507173a	704
emilmont	77:869cf507173a	705	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
emilmont	77:869cf507173a	706
emilmont	77:869cf507173a	707	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	708	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	709
emilmont	77:869cf507173a	710	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	711
emilmont	77:869cf507173a	712	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
emilmont	77:869cf507173a	713	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	714
emilmont	77:869cf507173a	715	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	716
bogdanm	81:7d30d6019079	717	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm	81:7d30d6019079	718	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm	81:7d30d6019079	719	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
bogdanm	81:7d30d6019079	720	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
emilmont	77:869cf507173a	721
emilmont	77:869cf507173a	722	/* Peripheral Control functions *************************************************/
emilmont	77:869cf507173a	723	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
emilmont	77:869cf507173a	724	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
emilmont	77:869cf507173a	725
emilmont	77:869cf507173a	726	/* Peripheral State functions ***************************************************/
emilmont	77:869cf507173a	727	HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
emilmont	77:869cf507173a	728	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
emilmont	77:869cf507173a	729
emilmont	77:869cf507173a	730	/**
emilmont	77:869cf507173a	731	* @}
emilmont	77:869cf507173a	732	*/
emilmont	77:869cf507173a	733
emilmont	77:869cf507173a	734	/**
emilmont	77:869cf507173a	735	* @}
emilmont	77:869cf507173a	736	*/
emilmont	77:869cf507173a	737
emilmont	77:869cf507173a	738	#ifdef __cplusplus
emilmont	77:869cf507173a	739	}
emilmont	77:869cf507173a	740	#endif
emilmont	77:869cf507173a	741
emilmont	77:869cf507173a	742	#endif /__STM32F4xx_ADC_H /
emilmont	77:869cf507173a	743
emilmont	77:869cf507173a	744
emilmont	77:869cf507173a	745	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/