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TARGET_NUCLEO_L152RE/stm32l1xx_rcc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: 81:7d30d6019079

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32l1xx_rcc.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
emilmont	77:869cf507173a	5	* @version V1.3.0
emilmont	77:869cf507173a	6	* @date 31-January-2014
emilmont	77:869cf507173a	7	* @brief This file contains all the functions prototypes for the RCC
emilmont	77:869cf507173a	8	* firmware library.
emilmont	77:869cf507173a	9	******************************************************************************
emilmont	77:869cf507173a	10	* @attention
emilmont	77:869cf507173a	11	*
bogdanm	81:7d30d6019079	12	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	13	*
bogdanm	81:7d30d6019079	14	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	81:7d30d6019079	15	* are permitted provided that the following conditions are met:
bogdanm	81:7d30d6019079	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	81:7d30d6019079	17	* this list of conditions and the following disclaimer.
bogdanm	81:7d30d6019079	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	81:7d30d6019079	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	81:7d30d6019079	20	* and/or other materials provided with the distribution.
bogdanm	81:7d30d6019079	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	81:7d30d6019079	22	* may be used to endorse or promote products derived from this software
bogdanm	81:7d30d6019079	23	* without specific prior written permission.
emilmont	77:869cf507173a	24	*
bogdanm	81:7d30d6019079	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	81:7d30d6019079	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	81:7d30d6019079	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	81:7d30d6019079	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	81:7d30d6019079	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	81:7d30d6019079	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	81:7d30d6019079	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	81:7d30d6019079	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	81:7d30d6019079	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	81:7d30d6019079	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	35	*
emilmont	77:869cf507173a	36	******************************************************************************
emilmont	77:869cf507173a	37	*/
emilmont	77:869cf507173a	38
emilmont	77:869cf507173a	39	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	40	#ifndef __STM32L1xx_RCC_H
emilmont	77:869cf507173a	41	#define __STM32L1xx_RCC_H
emilmont	77:869cf507173a	42
emilmont	77:869cf507173a	43	#ifdef __cplusplus
emilmont	77:869cf507173a	44	extern "C" {
emilmont	77:869cf507173a	45	#endif
emilmont	77:869cf507173a	46
emilmont	77:869cf507173a	47	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	48	#include "stm32l1xx.h"
emilmont	77:869cf507173a	49
emilmont	77:869cf507173a	50	/** @addtogroup STM32L1xx_StdPeriph_Driver
emilmont	77:869cf507173a	51	* @{
emilmont	77:869cf507173a	52	*/
emilmont	77:869cf507173a	53
emilmont	77:869cf507173a	54	/** @addtogroup RCC
emilmont	77:869cf507173a	55	* @{
emilmont	77:869cf507173a	56	*/
emilmont	77:869cf507173a	57
emilmont	77:869cf507173a	58	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	59
emilmont	77:869cf507173a	60	typedef struct
emilmont	77:869cf507173a	61	{
emilmont	77:869cf507173a	62	uint32_t SYSCLK_Frequency;
emilmont	77:869cf507173a	63	uint32_t HCLK_Frequency;
emilmont	77:869cf507173a	64	uint32_t PCLK1_Frequency;
emilmont	77:869cf507173a	65	uint32_t PCLK2_Frequency;
emilmont	77:869cf507173a	66	}RCC_ClocksTypeDef;
emilmont	77:869cf507173a	67
emilmont	77:869cf507173a	68	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	69
emilmont	77:869cf507173a	70	/** @defgroup RCC_Exported_Constants
emilmont	77:869cf507173a	71	* @{
emilmont	77:869cf507173a	72	*/
emilmont	77:869cf507173a	73
emilmont	77:869cf507173a	74	/** @defgroup RCC_HSE_configuration
emilmont	77:869cf507173a	75	* @{
emilmont	77:869cf507173a	76	*/
emilmont	77:869cf507173a	77
emilmont	77:869cf507173a	78	#define RCC_HSE_OFF ((uint8_t)0x00)
emilmont	77:869cf507173a	79	#define RCC_HSE_ON ((uint8_t)0x01)
emilmont	77:869cf507173a	80	#define RCC_HSE_Bypass ((uint8_t)0x05)
emilmont	77:869cf507173a	81	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
emilmont	77:869cf507173a	82	((HSE) == RCC_HSE_Bypass))
emilmont	77:869cf507173a	83
emilmont	77:869cf507173a	84	/**
emilmont	77:869cf507173a	85	* @}
emilmont	77:869cf507173a	86	*/
emilmont	77:869cf507173a	87
emilmont	77:869cf507173a	88	/** @defgroup RCC_MSI_Clock_Range
emilmont	77:869cf507173a	89	* @{
emilmont	77:869cf507173a	90	*/
emilmont	77:869cf507173a	91
emilmont	77:869cf507173a	92	#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
emilmont	77:869cf507173a	93	#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
emilmont	77:869cf507173a	94	#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
emilmont	77:869cf507173a	95	#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
emilmont	77:869cf507173a	96	#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
emilmont	77:869cf507173a	97	#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
emilmont	77:869cf507173a	98	#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
emilmont	77:869cf507173a	99
emilmont	77:869cf507173a	100	#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) \|\| \
emilmont	77:869cf507173a	101	((RANGE) == RCC_MSIRange_1) \|\| \
emilmont	77:869cf507173a	102	((RANGE) == RCC_MSIRange_2) \|\| \
emilmont	77:869cf507173a	103	((RANGE) == RCC_MSIRange_3) \|\| \
emilmont	77:869cf507173a	104	((RANGE) == RCC_MSIRange_4) \|\| \
emilmont	77:869cf507173a	105	((RANGE) == RCC_MSIRange_5) \|\| \
emilmont	77:869cf507173a	106	((RANGE) == RCC_MSIRange_6))
emilmont	77:869cf507173a	107
emilmont	77:869cf507173a	108	/**
emilmont	77:869cf507173a	109	* @}
emilmont	77:869cf507173a	110	*/
emilmont	77:869cf507173a	111
emilmont	77:869cf507173a	112	/** @defgroup RCC_PLL_Clock_Source
emilmont	77:869cf507173a	113	* @{
emilmont	77:869cf507173a	114	*/
emilmont	77:869cf507173a	115
emilmont	77:869cf507173a	116	#define RCC_PLLSource_HSI ((uint8_t)0x00)
emilmont	77:869cf507173a	117	#define RCC_PLLSource_HSE ((uint8_t)0x01)
emilmont	77:869cf507173a	118
emilmont	77:869cf507173a	119	#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) \|\| \
emilmont	77:869cf507173a	120	((SOURCE) == RCC_PLLSource_HSE))
emilmont	77:869cf507173a	121	/**
emilmont	77:869cf507173a	122	* @}
emilmont	77:869cf507173a	123	*/
emilmont	77:869cf507173a	124
emilmont	77:869cf507173a	125	/** @defgroup RCC_PLL_Multiplication_Factor
emilmont	77:869cf507173a	126	* @{
emilmont	77:869cf507173a	127	*/
emilmont	77:869cf507173a	128
emilmont	77:869cf507173a	129	#define RCC_PLLMul_3 ((uint8_t)0x00)
emilmont	77:869cf507173a	130	#define RCC_PLLMul_4 ((uint8_t)0x04)
emilmont	77:869cf507173a	131	#define RCC_PLLMul_6 ((uint8_t)0x08)
emilmont	77:869cf507173a	132	#define RCC_PLLMul_8 ((uint8_t)0x0C)
emilmont	77:869cf507173a	133	#define RCC_PLLMul_12 ((uint8_t)0x10)
emilmont	77:869cf507173a	134	#define RCC_PLLMul_16 ((uint8_t)0x14)
emilmont	77:869cf507173a	135	#define RCC_PLLMul_24 ((uint8_t)0x18)
emilmont	77:869cf507173a	136	#define RCC_PLLMul_32 ((uint8_t)0x1C)
emilmont	77:869cf507173a	137	#define RCC_PLLMul_48 ((uint8_t)0x20)
emilmont	77:869cf507173a	138
emilmont	77:869cf507173a	139
emilmont	77:869cf507173a	140	#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) \|\| ((MUL) == RCC_PLLMul_4) \|\| \
emilmont	77:869cf507173a	141	((MUL) == RCC_PLLMul_6) \|\| ((MUL) == RCC_PLLMul_8) \|\| \
emilmont	77:869cf507173a	142	((MUL) == RCC_PLLMul_12) \|\| ((MUL) == RCC_PLLMul_16) \|\| \
emilmont	77:869cf507173a	143	((MUL) == RCC_PLLMul_24) \|\| ((MUL) == RCC_PLLMul_32) \|\| \
emilmont	77:869cf507173a	144	((MUL) == RCC_PLLMul_48))
emilmont	77:869cf507173a	145	/**
emilmont	77:869cf507173a	146	* @}
emilmont	77:869cf507173a	147	*/
emilmont	77:869cf507173a	148
emilmont	77:869cf507173a	149	/** @defgroup RCC_PLL_Divider_Factor
emilmont	77:869cf507173a	150	* @{
emilmont	77:869cf507173a	151	*/
emilmont	77:869cf507173a	152
emilmont	77:869cf507173a	153	#define RCC_PLLDiv_2 ((uint8_t)0x40)
emilmont	77:869cf507173a	154	#define RCC_PLLDiv_3 ((uint8_t)0x80)
emilmont	77:869cf507173a	155	#define RCC_PLLDiv_4 ((uint8_t)0xC0)
emilmont	77:869cf507173a	156
emilmont	77:869cf507173a	157
emilmont	77:869cf507173a	158	#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) \|\| ((DIV) == RCC_PLLDiv_3) \|\| \
emilmont	77:869cf507173a	159	((DIV) == RCC_PLLDiv_4))
emilmont	77:869cf507173a	160	/**
emilmont	77:869cf507173a	161	* @}
emilmont	77:869cf507173a	162	*/
emilmont	77:869cf507173a	163
emilmont	77:869cf507173a	164	/** @defgroup RCC_System_Clock_Source
emilmont	77:869cf507173a	165	* @{
emilmont	77:869cf507173a	166	*/
emilmont	77:869cf507173a	167
emilmont	77:869cf507173a	168	#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI
emilmont	77:869cf507173a	169	#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
emilmont	77:869cf507173a	170	#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
emilmont	77:869cf507173a	171	#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
emilmont	77:869cf507173a	172	#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) \|\| \
emilmont	77:869cf507173a	173	((SOURCE) == RCC_SYSCLKSource_HSI) \|\| \
emilmont	77:869cf507173a	174	((SOURCE) == RCC_SYSCLKSource_HSE) \|\| \
emilmont	77:869cf507173a	175	((SOURCE) == RCC_SYSCLKSource_PLLCLK))
emilmont	77:869cf507173a	176	/**
emilmont	77:869cf507173a	177	* @}
emilmont	77:869cf507173a	178	*/
emilmont	77:869cf507173a	179
emilmont	77:869cf507173a	180	/** @defgroup RCC_AHB_Clock_Source
emilmont	77:869cf507173a	181	* @{
emilmont	77:869cf507173a	182	*/
emilmont	77:869cf507173a	183
emilmont	77:869cf507173a	184	#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
emilmont	77:869cf507173a	185	#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
emilmont	77:869cf507173a	186	#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
emilmont	77:869cf507173a	187	#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
emilmont	77:869cf507173a	188	#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
emilmont	77:869cf507173a	189	#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
emilmont	77:869cf507173a	190	#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
emilmont	77:869cf507173a	191	#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
emilmont	77:869cf507173a	192	#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
emilmont	77:869cf507173a	193	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) \|\| ((HCLK) == RCC_SYSCLK_Div2) \|\| \
emilmont	77:869cf507173a	194	((HCLK) == RCC_SYSCLK_Div4) \|\| ((HCLK) == RCC_SYSCLK_Div8) \|\| \
emilmont	77:869cf507173a	195	((HCLK) == RCC_SYSCLK_Div16) \|\| ((HCLK) == RCC_SYSCLK_Div64) \|\| \
emilmont	77:869cf507173a	196	((HCLK) == RCC_SYSCLK_Div128) \|\| ((HCLK) == RCC_SYSCLK_Div256) \|\| \
emilmont	77:869cf507173a	197	((HCLK) == RCC_SYSCLK_Div512))
emilmont	77:869cf507173a	198	/**
emilmont	77:869cf507173a	199	* @}
emilmont	77:869cf507173a	200	*/
emilmont	77:869cf507173a	201
emilmont	77:869cf507173a	202	/** @defgroup RCC_APB1_APB2_Clock_Source
emilmont	77:869cf507173a	203	* @{
emilmont	77:869cf507173a	204	*/
emilmont	77:869cf507173a	205
emilmont	77:869cf507173a	206	#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1
emilmont	77:869cf507173a	207	#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2
emilmont	77:869cf507173a	208	#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4
emilmont	77:869cf507173a	209	#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8
emilmont	77:869cf507173a	210	#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16
emilmont	77:869cf507173a	211	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) \|\| ((PCLK) == RCC_HCLK_Div2) \|\| \
emilmont	77:869cf507173a	212	((PCLK) == RCC_HCLK_Div4) \|\| ((PCLK) == RCC_HCLK_Div8) \|\| \
emilmont	77:869cf507173a	213	((PCLK) == RCC_HCLK_Div16))
emilmont	77:869cf507173a	214	/**
emilmont	77:869cf507173a	215	* @}
emilmont	77:869cf507173a	216	*/
emilmont	77:869cf507173a	217
emilmont	77:869cf507173a	218
emilmont	77:869cf507173a	219	/** @defgroup RCC_Interrupt_Source
emilmont	77:869cf507173a	220	* @{
emilmont	77:869cf507173a	221	*/
emilmont	77:869cf507173a	222
emilmont	77:869cf507173a	223	#define RCC_IT_LSIRDY ((uint8_t)0x01)
emilmont	77:869cf507173a	224	#define RCC_IT_LSERDY ((uint8_t)0x02)
emilmont	77:869cf507173a	225	#define RCC_IT_HSIRDY ((uint8_t)0x04)
emilmont	77:869cf507173a	226	#define RCC_IT_HSERDY ((uint8_t)0x08)
emilmont	77:869cf507173a	227	#define RCC_IT_PLLRDY ((uint8_t)0x10)
emilmont	77:869cf507173a	228	#define RCC_IT_MSIRDY ((uint8_t)0x20)
emilmont	77:869cf507173a	229	#define RCC_IT_LSECSS ((uint8_t)0x40)
emilmont	77:869cf507173a	230	#define RCC_IT_CSS ((uint8_t)0x80)
emilmont	77:869cf507173a	231
emilmont	77:869cf507173a	232	#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
emilmont	77:869cf507173a	233
emilmont	77:869cf507173a	234	#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) \|\| ((IT) == RCC_IT_LSERDY) \|\| \
emilmont	77:869cf507173a	235	((IT) == RCC_IT_HSIRDY) \|\| ((IT) == RCC_IT_HSERDY) \|\| \
emilmont	77:869cf507173a	236	((IT) == RCC_IT_PLLRDY) \|\| ((IT) == RCC_IT_MSIRDY) \|\| \
emilmont	77:869cf507173a	237	((IT) == RCC_IT_CSS) \|\| ((IT) == RCC_IT_LSECSS))
emilmont	77:869cf507173a	238
emilmont	77:869cf507173a	239	#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00))
emilmont	77:869cf507173a	240
emilmont	77:869cf507173a	241	/**
emilmont	77:869cf507173a	242	* @}
emilmont	77:869cf507173a	243	*/
emilmont	77:869cf507173a	244
emilmont	77:869cf507173a	245	/** @defgroup RCC_LSE_Configuration
emilmont	77:869cf507173a	246	* @{
emilmont	77:869cf507173a	247	*/
emilmont	77:869cf507173a	248
emilmont	77:869cf507173a	249	#define RCC_LSE_OFF ((uint8_t)0x00)
emilmont	77:869cf507173a	250	#define RCC_LSE_ON ((uint8_t)0x01)
emilmont	77:869cf507173a	251	#define RCC_LSE_Bypass ((uint8_t)0x05)
emilmont	77:869cf507173a	252	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
emilmont	77:869cf507173a	253	((LSE) == RCC_LSE_Bypass))
emilmont	77:869cf507173a	254	/**
emilmont	77:869cf507173a	255	* @}
emilmont	77:869cf507173a	256	*/
emilmont	77:869cf507173a	257
emilmont	77:869cf507173a	258	/** @defgroup RCC_RTC_Clock_Source
emilmont	77:869cf507173a	259	* @{
emilmont	77:869cf507173a	260	*/
emilmont	77:869cf507173a	261
emilmont	77:869cf507173a	262	#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE
emilmont	77:869cf507173a	263	#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI
emilmont	77:869cf507173a	264	#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE
emilmont	77:869cf507173a	265	#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
emilmont	77:869cf507173a	266	#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
emilmont	77:869cf507173a	267	#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
emilmont	77:869cf507173a	268	#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) \|\| \
emilmont	77:869cf507173a	269	((SOURCE) == RCC_RTCCLKSource_LSI) \|\| \
emilmont	77:869cf507173a	270	((SOURCE) == RCC_RTCCLKSource_HSE_Div2) \|\| \
emilmont	77:869cf507173a	271	((SOURCE) == RCC_RTCCLKSource_HSE_Div4) \|\| \
emilmont	77:869cf507173a	272	((SOURCE) == RCC_RTCCLKSource_HSE_Div8) \|\| \
emilmont	77:869cf507173a	273	((SOURCE) == RCC_RTCCLKSource_HSE_Div16))
emilmont	77:869cf507173a	274	/**
emilmont	77:869cf507173a	275	* @}
emilmont	77:869cf507173a	276	*/
emilmont	77:869cf507173a	277
emilmont	77:869cf507173a	278	/** @defgroup RCC_AHB_Peripherals
emilmont	77:869cf507173a	279	* @{
emilmont	77:869cf507173a	280	*/
emilmont	77:869cf507173a	281
emilmont	77:869cf507173a	282	#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
emilmont	77:869cf507173a	283	#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
emilmont	77:869cf507173a	284	#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
emilmont	77:869cf507173a	285	#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
emilmont	77:869cf507173a	286	#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
emilmont	77:869cf507173a	287	#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN
emilmont	77:869cf507173a	288	#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
emilmont	77:869cf507173a	289	#define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN
emilmont	77:869cf507173a	290	#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
emilmont	77:869cf507173a	291	#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
emilmont	77:869cf507173a	292	#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN
emilmont	77:869cf507173a	293	#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
emilmont	77:869cf507173a	294	#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
emilmont	77:869cf507173a	295	#define RCC_AHBPeriph_AES RCC_AHBENR_AESEN
emilmont	77:869cf507173a	296	#define RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN
emilmont	77:869cf507173a	297
emilmont	77:869cf507173a	298	#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
emilmont	77:869cf507173a	299	#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
emilmont	77:869cf507173a	300
emilmont	77:869cf507173a	301	/**
emilmont	77:869cf507173a	302	* @}
emilmont	77:869cf507173a	303	*/
emilmont	77:869cf507173a	304
emilmont	77:869cf507173a	305	/** @defgroup RCC_APB2_Peripherals
emilmont	77:869cf507173a	306	* @{
emilmont	77:869cf507173a	307	*/
emilmont	77:869cf507173a	308
emilmont	77:869cf507173a	309	#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
emilmont	77:869cf507173a	310	#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN
emilmont	77:869cf507173a	311	#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN
emilmont	77:869cf507173a	312	#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN
emilmont	77:869cf507173a	313	#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
emilmont	77:869cf507173a	314	#define RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN
emilmont	77:869cf507173a	315	#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
emilmont	77:869cf507173a	316	#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
emilmont	77:869cf507173a	317
emilmont	77:869cf507173a	318	#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00))
emilmont	77:869cf507173a	319	/**
emilmont	77:869cf507173a	320	* @}
emilmont	77:869cf507173a	321	*/
emilmont	77:869cf507173a	322
emilmont	77:869cf507173a	323	/** @defgroup RCC_APB1_Peripherals
emilmont	77:869cf507173a	324	* @{
emilmont	77:869cf507173a	325	*/
emilmont	77:869cf507173a	326
emilmont	77:869cf507173a	327	#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
emilmont	77:869cf507173a	328	#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
emilmont	77:869cf507173a	329	#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
emilmont	77:869cf507173a	330	#define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN
emilmont	77:869cf507173a	331	#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
emilmont	77:869cf507173a	332	#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
emilmont	77:869cf507173a	333	#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN
emilmont	77:869cf507173a	334	#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
emilmont	77:869cf507173a	335	#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
emilmont	77:869cf507173a	336	#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
emilmont	77:869cf507173a	337	#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
emilmont	77:869cf507173a	338	#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
emilmont	77:869cf507173a	339	#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
emilmont	77:869cf507173a	340	#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
emilmont	77:869cf507173a	341	#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
emilmont	77:869cf507173a	342	#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
emilmont	77:869cf507173a	343	#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
emilmont	77:869cf507173a	344	#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
emilmont	77:869cf507173a	345	#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN
emilmont	77:869cf507173a	346	#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN
emilmont	77:869cf507173a	347
emilmont	77:869cf507173a	348
emilmont	77:869cf507173a	349	#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00))
emilmont	77:869cf507173a	350	/**
emilmont	77:869cf507173a	351	* @}
emilmont	77:869cf507173a	352	*/
emilmont	77:869cf507173a	353
emilmont	77:869cf507173a	354	/** @defgroup RCC_MCO_Clock_Source
emilmont	77:869cf507173a	355	* @{
emilmont	77:869cf507173a	356	*/
emilmont	77:869cf507173a	357
emilmont	77:869cf507173a	358	#define RCC_MCOSource_NoClock ((uint8_t)0x00)
emilmont	77:869cf507173a	359	#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)
emilmont	77:869cf507173a	360	#define RCC_MCOSource_HSI ((uint8_t)0x02)
emilmont	77:869cf507173a	361	#define RCC_MCOSource_MSI ((uint8_t)0x03)
emilmont	77:869cf507173a	362	#define RCC_MCOSource_HSE ((uint8_t)0x04)
emilmont	77:869cf507173a	363	#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)
emilmont	77:869cf507173a	364	#define RCC_MCOSource_LSI ((uint8_t)0x06)
emilmont	77:869cf507173a	365	#define RCC_MCOSource_LSE ((uint8_t)0x07)
emilmont	77:869cf507173a	366
emilmont	77:869cf507173a	367	#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) \|\| ((SOURCE) == RCC_MCOSource_SYSCLK) \|\| \
emilmont	77:869cf507173a	368	((SOURCE) == RCC_MCOSource_HSI) \|\| ((SOURCE) == RCC_MCOSource_MSI) \|\| \
emilmont	77:869cf507173a	369	((SOURCE) == RCC_MCOSource_HSE) \|\| ((SOURCE) == RCC_MCOSource_PLLCLK) \|\| \
emilmont	77:869cf507173a	370	((SOURCE) == RCC_MCOSource_LSI) \|\| ((SOURCE) == RCC_MCOSource_LSE))
emilmont	77:869cf507173a	371	/**
emilmont	77:869cf507173a	372	* @}
emilmont	77:869cf507173a	373	*/
emilmont	77:869cf507173a	374
emilmont	77:869cf507173a	375	/** @defgroup RCC_MCO_Output_Divider
emilmont	77:869cf507173a	376	* @{
emilmont	77:869cf507173a	377	*/
emilmont	77:869cf507173a	378
emilmont	77:869cf507173a	379	#define RCC_MCODiv_1 ((uint8_t)0x00)
emilmont	77:869cf507173a	380	#define RCC_MCODiv_2 ((uint8_t)0x10)
emilmont	77:869cf507173a	381	#define RCC_MCODiv_4 ((uint8_t)0x20)
emilmont	77:869cf507173a	382	#define RCC_MCODiv_8 ((uint8_t)0x30)
emilmont	77:869cf507173a	383	#define RCC_MCODiv_16 ((uint8_t)0x40)
emilmont	77:869cf507173a	384
emilmont	77:869cf507173a	385	#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) \|\| ((DIV) == RCC_MCODiv_2) \|\| \
emilmont	77:869cf507173a	386	((DIV) == RCC_MCODiv_4) \|\| ((DIV) == RCC_MCODiv_8) \|\| \
emilmont	77:869cf507173a	387	((DIV) == RCC_MCODiv_16))
emilmont	77:869cf507173a	388	/**
emilmont	77:869cf507173a	389	* @}
emilmont	77:869cf507173a	390	*/
emilmont	77:869cf507173a	391
emilmont	77:869cf507173a	392	/** @defgroup RCC_Flag
emilmont	77:869cf507173a	393	* @{
emilmont	77:869cf507173a	394	*/
emilmont	77:869cf507173a	395
emilmont	77:869cf507173a	396	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
emilmont	77:869cf507173a	397	#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
emilmont	77:869cf507173a	398	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
emilmont	77:869cf507173a	399	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
emilmont	77:869cf507173a	400	#define RCC_FLAG_LSERDY ((uint8_t)0x49)
emilmont	77:869cf507173a	401	#define RCC_FLAG_LSECSS ((uint8_t)0x4A)
emilmont	77:869cf507173a	402	#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
emilmont	77:869cf507173a	403	#define RCC_FLAG_OBLRST ((uint8_t)0x59)
emilmont	77:869cf507173a	404	#define RCC_FLAG_PINRST ((uint8_t)0x5A)
emilmont	77:869cf507173a	405	#define RCC_FLAG_PORRST ((uint8_t)0x5B)
emilmont	77:869cf507173a	406	#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
emilmont	77:869cf507173a	407	#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
emilmont	77:869cf507173a	408	#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
emilmont	77:869cf507173a	409	#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
emilmont	77:869cf507173a	410
emilmont	77:869cf507173a	411	#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) \|\| ((FLAG) == RCC_FLAG_HSERDY) \|\| \
emilmont	77:869cf507173a	412	((FLAG) == RCC_FLAG_MSIRDY) \|\| ((FLAG) == RCC_FLAG_PLLRDY) \|\| \
emilmont	77:869cf507173a	413	((FLAG) == RCC_FLAG_LSERDY) \|\| ((FLAG) == RCC_FLAG_LSIRDY) \|\| \
emilmont	77:869cf507173a	414	((FLAG) == RCC_FLAG_PINRST) \|\| ((FLAG) == RCC_FLAG_PORRST) \|\| \
emilmont	77:869cf507173a	415	((FLAG) == RCC_FLAG_SFTRST) \|\| ((FLAG) == RCC_FLAG_IWDGRST)\|\| \
emilmont	77:869cf507173a	416	((FLAG) == RCC_FLAG_WWDGRST)\|\| ((FLAG) == RCC_FLAG_LPWRRST)\|\| \
emilmont	77:869cf507173a	417	((FLAG) == RCC_FLAG_OBLRST)\|\| ((FLAG) == RCC_FLAG_LSECSS))
emilmont	77:869cf507173a	418
emilmont	77:869cf507173a	419	#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
emilmont	77:869cf507173a	420	#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
emilmont	77:869cf507173a	421
emilmont	77:869cf507173a	422	/**
emilmont	77:869cf507173a	423	* @}
emilmont	77:869cf507173a	424	*/
emilmont	77:869cf507173a	425
emilmont	77:869cf507173a	426	/**
emilmont	77:869cf507173a	427	* @}
emilmont	77:869cf507173a	428	*/
emilmont	77:869cf507173a	429
emilmont	77:869cf507173a	430	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	431	/* Exported functions ------------------------------------------------------- */
emilmont	77:869cf507173a	432
emilmont	77:869cf507173a	433	/* Function used to set the RCC clock configuration to the default reset state */
emilmont	77:869cf507173a	434	void RCC_DeInit(void);
emilmont	77:869cf507173a	435
emilmont	77:869cf507173a	436	/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
emilmont	77:869cf507173a	437	void RCC_HSEConfig(uint8_t RCC_HSE);
emilmont	77:869cf507173a	438	ErrorStatus RCC_WaitForHSEStartUp(void);
emilmont	77:869cf507173a	439	void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);
emilmont	77:869cf507173a	440	void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);
emilmont	77:869cf507173a	441	void RCC_MSICmd(FunctionalState NewState);
emilmont	77:869cf507173a	442	void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
emilmont	77:869cf507173a	443	void RCC_HSICmd(FunctionalState NewState);
emilmont	77:869cf507173a	444	void RCC_LSEConfig(uint8_t RCC_LSE);
emilmont	77:869cf507173a	445	void RCC_LSICmd(FunctionalState NewState);
emilmont	77:869cf507173a	446	void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);
emilmont	77:869cf507173a	447	void RCC_PLLCmd(FunctionalState NewState);
emilmont	77:869cf507173a	448	void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
emilmont	77:869cf507173a	449	void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState);
emilmont	77:869cf507173a	450	void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);
emilmont	77:869cf507173a	451
emilmont	77:869cf507173a	452	/* System, AHB and APB busses clocks configuration functions ******************/
emilmont	77:869cf507173a	453	void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
emilmont	77:869cf507173a	454	uint8_t RCC_GetSYSCLKSource(void);
emilmont	77:869cf507173a	455	void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
emilmont	77:869cf507173a	456	void RCC_PCLK1Config(uint32_t RCC_HCLK);
emilmont	77:869cf507173a	457	void RCC_PCLK2Config(uint32_t RCC_HCLK);
emilmont	77:869cf507173a	458	void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
emilmont	77:869cf507173a	459
emilmont	77:869cf507173a	460	/* Peripheral clocks configuration functions **********************************/
emilmont	77:869cf507173a	461	void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
emilmont	77:869cf507173a	462	void RCC_RTCCLKCmd(FunctionalState NewState);
emilmont	77:869cf507173a	463	void RCC_RTCResetCmd(FunctionalState NewState);
emilmont	77:869cf507173a	464
emilmont	77:869cf507173a	465	void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
emilmont	77:869cf507173a	466	void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
emilmont	77:869cf507173a	467	void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
emilmont	77:869cf507173a	468
emilmont	77:869cf507173a	469	void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
emilmont	77:869cf507173a	470	void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
emilmont	77:869cf507173a	471	void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
emilmont	77:869cf507173a	472
emilmont	77:869cf507173a	473	void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
emilmont	77:869cf507173a	474	void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
emilmont	77:869cf507173a	475	void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
emilmont	77:869cf507173a	476
emilmont	77:869cf507173a	477	/* Interrupts and flags management functions **********************************/
emilmont	77:869cf507173a	478	void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
emilmont	77:869cf507173a	479	FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
emilmont	77:869cf507173a	480	void RCC_ClearFlag(void);
emilmont	77:869cf507173a	481	ITStatus RCC_GetITStatus(uint8_t RCC_IT);
emilmont	77:869cf507173a	482	void RCC_ClearITPendingBit(uint8_t RCC_IT);
emilmont	77:869cf507173a	483
emilmont	77:869cf507173a	484	#ifdef __cplusplus
emilmont	77:869cf507173a	485	}
emilmont	77:869cf507173a	486	#endif
emilmont	77:869cf507173a	487
emilmont	77:869cf507173a	488	#endif /* __STM32L1xx_RCC_H */
emilmont	77:869cf507173a	489
emilmont	77:869cf507173a	490	/**
emilmont	77:869cf507173a	491	* @}
emilmont	77:869cf507173a	492	*/
emilmont	77:869cf507173a	493
emilmont	77:869cf507173a	494	/**
emilmont	77:869cf507173a	495	* @}
emilmont	77:869cf507173a	496	*/
emilmont	77:869cf507173a	497
emilmont	77:869cf507173a	498	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/