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TARGET_NUCLEO_L152RE/stm32l1xx_fsmc.h@89:552587b429a1, 2014-09-12 (annotated)
- Committer:
- bogdanm
- Date:
- Fri Sep 12 16:41:52 2014 +0100
- Revision:
- 89:552587b429a1
- Parent:
- 81:7d30d6019079
Release 89 of the mbed library
Main changes:
- low power optimizations for Nordic targets
- code structure changes for Freescale K64F targets
- bug fixes in various backends
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32l1xx_fsmc.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| emilmont | 77:869cf507173a | 5 | * @version V1.3.0 |
| emilmont | 77:869cf507173a | 6 | * @date 31-January-2014 |
| emilmont | 77:869cf507173a | 7 | * @brief This file contains all the functions prototypes for the FSMC firmware |
| emilmont | 77:869cf507173a | 8 | * library. |
| emilmont | 77:869cf507173a | 9 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 10 | * @attention |
| emilmont | 77:869cf507173a | 11 | * |
| bogdanm | 81:7d30d6019079 | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 13 | * |
| bogdanm | 81:7d30d6019079 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 81:7d30d6019079 | 15 | * are permitted provided that the following conditions are met: |
| bogdanm | 81:7d30d6019079 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 81:7d30d6019079 | 17 | * this list of conditions and the following disclaimer. |
| bogdanm | 81:7d30d6019079 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 81:7d30d6019079 | 19 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 81:7d30d6019079 | 20 | * and/or other materials provided with the distribution. |
| bogdanm | 81:7d30d6019079 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 81:7d30d6019079 | 22 | * may be used to endorse or promote products derived from this software |
| bogdanm | 81:7d30d6019079 | 23 | * without specific prior written permission. |
| emilmont | 77:869cf507173a | 24 | * |
| bogdanm | 81:7d30d6019079 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 81:7d30d6019079 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 81:7d30d6019079 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 81:7d30d6019079 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 81:7d30d6019079 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 81:7d30d6019079 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 81:7d30d6019079 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 81:7d30d6019079 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 81:7d30d6019079 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 81:7d30d6019079 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| emilmont | 77:869cf507173a | 35 | * |
| emilmont | 77:869cf507173a | 36 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 37 | */ |
| emilmont | 77:869cf507173a | 38 | |
| emilmont | 77:869cf507173a | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 40 | #ifndef __STM32L1xx_FSMC_H |
| emilmont | 77:869cf507173a | 41 | #define __STM32L1xx_FSMC_H |
| emilmont | 77:869cf507173a | 42 | |
| emilmont | 77:869cf507173a | 43 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 44 | extern "C" { |
| emilmont | 77:869cf507173a | 45 | #endif |
| emilmont | 77:869cf507173a | 46 | |
| emilmont | 77:869cf507173a | 47 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 48 | #include "stm32l1xx.h" |
| emilmont | 77:869cf507173a | 49 | |
| emilmont | 77:869cf507173a | 50 | /** @addtogroup STM32L1xx_StdPeriph_Driver |
| emilmont | 77:869cf507173a | 51 | * @{ |
| emilmont | 77:869cf507173a | 52 | */ |
| emilmont | 77:869cf507173a | 53 | |
| emilmont | 77:869cf507173a | 54 | /** @addtogroup FSMC |
| emilmont | 77:869cf507173a | 55 | * @{ |
| emilmont | 77:869cf507173a | 56 | */ |
| emilmont | 77:869cf507173a | 57 | |
| emilmont | 77:869cf507173a | 58 | /* Exported types ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 59 | |
| emilmont | 77:869cf507173a | 60 | /** |
| emilmont | 77:869cf507173a | 61 | * @brief Timing parameters For NOR/SRAM Banks |
| emilmont | 77:869cf507173a | 62 | */ |
| emilmont | 77:869cf507173a | 63 | |
| emilmont | 77:869cf507173a | 64 | typedef struct |
| emilmont | 77:869cf507173a | 65 | { |
| emilmont | 77:869cf507173a | 66 | uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| emilmont | 77:869cf507173a | 67 | the duration of the address setup time. |
| emilmont | 77:869cf507173a | 68 | This parameter can be a value between 0 and 0xF. |
| emilmont | 77:869cf507173a | 69 | @note It is not used with synchronous NOR Flash memories. */ |
| emilmont | 77:869cf507173a | 70 | |
| emilmont | 77:869cf507173a | 71 | uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| emilmont | 77:869cf507173a | 72 | the duration of the address hold time. |
| emilmont | 77:869cf507173a | 73 | This parameter can be a value between 0 and 0xF. |
| emilmont | 77:869cf507173a | 74 | @note It is not used with synchronous NOR Flash memories.*/ |
| emilmont | 77:869cf507173a | 75 | |
| emilmont | 77:869cf507173a | 76 | uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| emilmont | 77:869cf507173a | 77 | the duration of the data setup time. |
| emilmont | 77:869cf507173a | 78 | This parameter can be a value between 0 and 0xFF. |
| emilmont | 77:869cf507173a | 79 | @note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ |
| emilmont | 77:869cf507173a | 80 | |
| emilmont | 77:869cf507173a | 81 | uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| emilmont | 77:869cf507173a | 82 | the duration of the bus turnaround. |
| emilmont | 77:869cf507173a | 83 | This parameter can be a value between 0 and 0xF. |
| emilmont | 77:869cf507173a | 84 | @note It is only used for multiplexed NOR Flash memories. */ |
| emilmont | 77:869cf507173a | 85 | |
| emilmont | 77:869cf507173a | 86 | uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. |
| emilmont | 77:869cf507173a | 87 | This parameter can be a value between 1 and 0xF. |
| emilmont | 77:869cf507173a | 88 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ |
| emilmont | 77:869cf507173a | 89 | |
| emilmont | 77:869cf507173a | 90 | uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue |
| emilmont | 77:869cf507173a | 91 | to the memory before getting the first data. |
| emilmont | 77:869cf507173a | 92 | The parameter value depends on the memory type as shown below: |
| emilmont | 77:869cf507173a | 93 | - It must be set to 0 in case of a CRAM |
| emilmont | 77:869cf507173a | 94 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| emilmont | 77:869cf507173a | 95 | - It may assume a value between 0 and 0xF in NOR Flash memories |
| emilmont | 77:869cf507173a | 96 | with synchronous burst mode enable */ |
| emilmont | 77:869cf507173a | 97 | |
| emilmont | 77:869cf507173a | 98 | uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. |
| emilmont | 77:869cf507173a | 99 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| emilmont | 77:869cf507173a | 100 | }FSMC_NORSRAMTimingInitTypeDef; |
| emilmont | 77:869cf507173a | 101 | |
| emilmont | 77:869cf507173a | 102 | /** |
| emilmont | 77:869cf507173a | 103 | * @brief FSMC NOR/SRAM Init structure definition |
| emilmont | 77:869cf507173a | 104 | */ |
| emilmont | 77:869cf507173a | 105 | |
| emilmont | 77:869cf507173a | 106 | typedef struct |
| emilmont | 77:869cf507173a | 107 | { |
| emilmont | 77:869cf507173a | 108 | uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. |
| emilmont | 77:869cf507173a | 109 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| emilmont | 77:869cf507173a | 110 | |
| emilmont | 77:869cf507173a | 111 | uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are |
| emilmont | 77:869cf507173a | 112 | multiplexed on the databus or not. |
| emilmont | 77:869cf507173a | 113 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| emilmont | 77:869cf507173a | 114 | |
| emilmont | 77:869cf507173a | 115 | uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to |
| emilmont | 77:869cf507173a | 116 | the corresponding memory bank. |
| emilmont | 77:869cf507173a | 117 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| emilmont | 77:869cf507173a | 118 | |
| emilmont | 77:869cf507173a | 119 | uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. |
| emilmont | 77:869cf507173a | 120 | This parameter can be a value of @ref FSMC_Data_Width */ |
| emilmont | 77:869cf507173a | 121 | |
| emilmont | 77:869cf507173a | 122 | uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| emilmont | 77:869cf507173a | 123 | valid only with synchronous burst Flash memories. |
| emilmont | 77:869cf507173a | 124 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| emilmont | 77:869cf507173a | 125 | |
| emilmont | 77:869cf507173a | 126 | uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| emilmont | 77:869cf507173a | 127 | valid only with asynchronous Flash memories. |
| emilmont | 77:869cf507173a | 128 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| emilmont | 77:869cf507173a | 129 | |
| emilmont | 77:869cf507173a | 130 | uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| emilmont | 77:869cf507173a | 131 | the Flash memory in burst mode. |
| emilmont | 77:869cf507173a | 132 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| emilmont | 77:869cf507173a | 133 | |
| emilmont | 77:869cf507173a | 134 | uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
| emilmont | 77:869cf507173a | 135 | memory, valid only when accessing Flash memories in burst mode. |
| emilmont | 77:869cf507173a | 136 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
| emilmont | 77:869cf507173a | 137 | |
| emilmont | 77:869cf507173a | 138 | uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| emilmont | 77:869cf507173a | 139 | clock cycle before the wait state or during the wait state, |
| emilmont | 77:869cf507173a | 140 | valid only when accessing memories in burst mode. |
| emilmont | 77:869cf507173a | 141 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| emilmont | 77:869cf507173a | 142 | |
| emilmont | 77:869cf507173a | 143 | uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. |
| emilmont | 77:869cf507173a | 144 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| emilmont | 77:869cf507173a | 145 | |
| emilmont | 77:869cf507173a | 146 | uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait |
| emilmont | 77:869cf507173a | 147 | signal, valid for Flash memory access in burst mode. |
| emilmont | 77:869cf507173a | 148 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| emilmont | 77:869cf507173a | 149 | |
| emilmont | 77:869cf507173a | 150 | uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. |
| emilmont | 77:869cf507173a | 151 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| emilmont | 77:869cf507173a | 152 | |
| emilmont | 77:869cf507173a | 153 | uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. |
| emilmont | 77:869cf507173a | 154 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| emilmont | 77:869cf507173a | 155 | |
| emilmont | 77:869cf507173a | 156 | FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ |
| emilmont | 77:869cf507173a | 157 | |
| emilmont | 77:869cf507173a | 158 | FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ |
| emilmont | 77:869cf507173a | 159 | }FSMC_NORSRAMInitTypeDef; |
| emilmont | 77:869cf507173a | 160 | |
| emilmont | 77:869cf507173a | 161 | /* Exported constants --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 162 | |
| emilmont | 77:869cf507173a | 163 | /** @defgroup FSMC_Exported_Constants |
| emilmont | 77:869cf507173a | 164 | * @{ |
| emilmont | 77:869cf507173a | 165 | */ |
| emilmont | 77:869cf507173a | 166 | |
| emilmont | 77:869cf507173a | 167 | /** @defgroup FSMC_NORSRAM_Bank |
| emilmont | 77:869cf507173a | 168 | * @{ |
| emilmont | 77:869cf507173a | 169 | */ |
| emilmont | 77:869cf507173a | 170 | #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 171 | #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) |
| emilmont | 77:869cf507173a | 172 | #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) |
| emilmont | 77:869cf507173a | 173 | #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) |
| emilmont | 77:869cf507173a | 174 | |
| emilmont | 77:869cf507173a | 175 | #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ |
| emilmont | 77:869cf507173a | 176 | ((BANK) == FSMC_Bank1_NORSRAM2) || \ |
| emilmont | 77:869cf507173a | 177 | ((BANK) == FSMC_Bank1_NORSRAM3) || \ |
| emilmont | 77:869cf507173a | 178 | ((BANK) == FSMC_Bank1_NORSRAM4)) |
| emilmont | 77:869cf507173a | 179 | /** |
| emilmont | 77:869cf507173a | 180 | * @} |
| emilmont | 77:869cf507173a | 181 | */ |
| emilmont | 77:869cf507173a | 182 | |
| emilmont | 77:869cf507173a | 183 | /** @defgroup NOR_SRAM_Controller |
| emilmont | 77:869cf507173a | 184 | * @{ |
| emilmont | 77:869cf507173a | 185 | */ |
| emilmont | 77:869cf507173a | 186 | |
| emilmont | 77:869cf507173a | 187 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing |
| emilmont | 77:869cf507173a | 188 | * @{ |
| emilmont | 77:869cf507173a | 189 | */ |
| emilmont | 77:869cf507173a | 190 | |
| emilmont | 77:869cf507173a | 191 | #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 192 | #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) |
| emilmont | 77:869cf507173a | 193 | #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ |
| emilmont | 77:869cf507173a | 194 | ((MUX) == FSMC_DataAddressMux_Enable)) |
| emilmont | 77:869cf507173a | 195 | |
| emilmont | 77:869cf507173a | 196 | /** |
| emilmont | 77:869cf507173a | 197 | * @} |
| emilmont | 77:869cf507173a | 198 | */ |
| emilmont | 77:869cf507173a | 199 | |
| emilmont | 77:869cf507173a | 200 | /** @defgroup FSMC_Memory_Type |
| emilmont | 77:869cf507173a | 201 | * @{ |
| emilmont | 77:869cf507173a | 202 | */ |
| emilmont | 77:869cf507173a | 203 | |
| emilmont | 77:869cf507173a | 204 | #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 205 | #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) |
| emilmont | 77:869cf507173a | 206 | #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) |
| emilmont | 77:869cf507173a | 207 | #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ |
| emilmont | 77:869cf507173a | 208 | ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ |
| emilmont | 77:869cf507173a | 209 | ((MEMORY) == FSMC_MemoryType_NOR)) |
| emilmont | 77:869cf507173a | 210 | |
| emilmont | 77:869cf507173a | 211 | /** |
| emilmont | 77:869cf507173a | 212 | * @} |
| emilmont | 77:869cf507173a | 213 | */ |
| emilmont | 77:869cf507173a | 214 | |
| emilmont | 77:869cf507173a | 215 | /** @defgroup FSMC_Data_Width |
| emilmont | 77:869cf507173a | 216 | * @{ |
| emilmont | 77:869cf507173a | 217 | */ |
| emilmont | 77:869cf507173a | 218 | |
| emilmont | 77:869cf507173a | 219 | #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 220 | #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) |
| emilmont | 77:869cf507173a | 221 | #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ |
| emilmont | 77:869cf507173a | 222 | ((WIDTH) == FSMC_MemoryDataWidth_16b)) |
| emilmont | 77:869cf507173a | 223 | |
| emilmont | 77:869cf507173a | 224 | /** |
| emilmont | 77:869cf507173a | 225 | * @} |
| emilmont | 77:869cf507173a | 226 | */ |
| emilmont | 77:869cf507173a | 227 | |
| emilmont | 77:869cf507173a | 228 | /** @defgroup FSMC_Burst_Access_Mode |
| emilmont | 77:869cf507173a | 229 | * @{ |
| emilmont | 77:869cf507173a | 230 | */ |
| emilmont | 77:869cf507173a | 231 | |
| emilmont | 77:869cf507173a | 232 | #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 233 | #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) |
| emilmont | 77:869cf507173a | 234 | #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ |
| emilmont | 77:869cf507173a | 235 | ((STATE) == FSMC_BurstAccessMode_Enable)) |
| emilmont | 77:869cf507173a | 236 | /** |
| emilmont | 77:869cf507173a | 237 | * @} |
| emilmont | 77:869cf507173a | 238 | */ |
| emilmont | 77:869cf507173a | 239 | |
| emilmont | 77:869cf507173a | 240 | /** @defgroup FSMC_AsynchronousWait |
| emilmont | 77:869cf507173a | 241 | * @{ |
| emilmont | 77:869cf507173a | 242 | */ |
| emilmont | 77:869cf507173a | 243 | #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 244 | #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) |
| emilmont | 77:869cf507173a | 245 | #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ |
| emilmont | 77:869cf507173a | 246 | ((STATE) == FSMC_AsynchronousWait_Enable)) |
| emilmont | 77:869cf507173a | 247 | |
| emilmont | 77:869cf507173a | 248 | /** |
| emilmont | 77:869cf507173a | 249 | * @} |
| emilmont | 77:869cf507173a | 250 | */ |
| emilmont | 77:869cf507173a | 251 | |
| emilmont | 77:869cf507173a | 252 | /** @defgroup FSMC_Wait_Signal_Polarity |
| emilmont | 77:869cf507173a | 253 | * @{ |
| emilmont | 77:869cf507173a | 254 | */ |
| emilmont | 77:869cf507173a | 255 | |
| emilmont | 77:869cf507173a | 256 | #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 257 | #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) |
| emilmont | 77:869cf507173a | 258 | #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ |
| emilmont | 77:869cf507173a | 259 | ((POLARITY) == FSMC_WaitSignalPolarity_High)) |
| emilmont | 77:869cf507173a | 260 | |
| emilmont | 77:869cf507173a | 261 | /** |
| emilmont | 77:869cf507173a | 262 | * @} |
| emilmont | 77:869cf507173a | 263 | */ |
| emilmont | 77:869cf507173a | 264 | |
| emilmont | 77:869cf507173a | 265 | /** @defgroup FSMC_Wrap_Mode |
| emilmont | 77:869cf507173a | 266 | * @{ |
| emilmont | 77:869cf507173a | 267 | */ |
| emilmont | 77:869cf507173a | 268 | |
| emilmont | 77:869cf507173a | 269 | #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 270 | #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) |
| emilmont | 77:869cf507173a | 271 | #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ |
| emilmont | 77:869cf507173a | 272 | ((MODE) == FSMC_WrapMode_Enable)) |
| emilmont | 77:869cf507173a | 273 | |
| emilmont | 77:869cf507173a | 274 | /** |
| emilmont | 77:869cf507173a | 275 | * @} |
| emilmont | 77:869cf507173a | 276 | */ |
| emilmont | 77:869cf507173a | 277 | |
| emilmont | 77:869cf507173a | 278 | /** @defgroup FSMC_Wait_Timing |
| emilmont | 77:869cf507173a | 279 | * @{ |
| emilmont | 77:869cf507173a | 280 | */ |
| emilmont | 77:869cf507173a | 281 | |
| emilmont | 77:869cf507173a | 282 | #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 283 | #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) |
| emilmont | 77:869cf507173a | 284 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ |
| emilmont | 77:869cf507173a | 285 | ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) |
| emilmont | 77:869cf507173a | 286 | |
| emilmont | 77:869cf507173a | 287 | /** |
| emilmont | 77:869cf507173a | 288 | * @} |
| emilmont | 77:869cf507173a | 289 | */ |
| emilmont | 77:869cf507173a | 290 | |
| emilmont | 77:869cf507173a | 291 | /** @defgroup FSMC_Write_Operation |
| emilmont | 77:869cf507173a | 292 | * @{ |
| emilmont | 77:869cf507173a | 293 | */ |
| emilmont | 77:869cf507173a | 294 | |
| emilmont | 77:869cf507173a | 295 | #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 296 | #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) |
| emilmont | 77:869cf507173a | 297 | #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ |
| emilmont | 77:869cf507173a | 298 | ((OPERATION) == FSMC_WriteOperation_Enable)) |
| emilmont | 77:869cf507173a | 299 | |
| emilmont | 77:869cf507173a | 300 | /** |
| emilmont | 77:869cf507173a | 301 | * @} |
| emilmont | 77:869cf507173a | 302 | */ |
| emilmont | 77:869cf507173a | 303 | |
| emilmont | 77:869cf507173a | 304 | /** @defgroup FSMC_Wait_Signal |
| emilmont | 77:869cf507173a | 305 | * @{ |
| emilmont | 77:869cf507173a | 306 | */ |
| emilmont | 77:869cf507173a | 307 | |
| emilmont | 77:869cf507173a | 308 | #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 309 | #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) |
| emilmont | 77:869cf507173a | 310 | #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ |
| emilmont | 77:869cf507173a | 311 | ((SIGNAL) == FSMC_WaitSignal_Enable)) |
| emilmont | 77:869cf507173a | 312 | /** |
| emilmont | 77:869cf507173a | 313 | * @} |
| emilmont | 77:869cf507173a | 314 | */ |
| emilmont | 77:869cf507173a | 315 | |
| emilmont | 77:869cf507173a | 316 | /** @defgroup FSMC_Extended_Mode |
| emilmont | 77:869cf507173a | 317 | * @{ |
| emilmont | 77:869cf507173a | 318 | */ |
| emilmont | 77:869cf507173a | 319 | |
| emilmont | 77:869cf507173a | 320 | #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 321 | #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) |
| emilmont | 77:869cf507173a | 322 | |
| emilmont | 77:869cf507173a | 323 | #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ |
| emilmont | 77:869cf507173a | 324 | ((MODE) == FSMC_ExtendedMode_Enable)) |
| emilmont | 77:869cf507173a | 325 | |
| emilmont | 77:869cf507173a | 326 | /** |
| emilmont | 77:869cf507173a | 327 | * @} |
| emilmont | 77:869cf507173a | 328 | */ |
| emilmont | 77:869cf507173a | 329 | |
| emilmont | 77:869cf507173a | 330 | /** @defgroup FSMC_Write_Burst |
| emilmont | 77:869cf507173a | 331 | * @{ |
| emilmont | 77:869cf507173a | 332 | */ |
| emilmont | 77:869cf507173a | 333 | |
| emilmont | 77:869cf507173a | 334 | #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 335 | #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) |
| emilmont | 77:869cf507173a | 336 | #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ |
| emilmont | 77:869cf507173a | 337 | ((BURST) == FSMC_WriteBurst_Enable)) |
| emilmont | 77:869cf507173a | 338 | /** |
| emilmont | 77:869cf507173a | 339 | * @} |
| emilmont | 77:869cf507173a | 340 | */ |
| emilmont | 77:869cf507173a | 341 | |
| emilmont | 77:869cf507173a | 342 | /** @defgroup FSMC_Address_Setup_Time |
| emilmont | 77:869cf507173a | 343 | * @{ |
| emilmont | 77:869cf507173a | 344 | */ |
| emilmont | 77:869cf507173a | 345 | |
| emilmont | 77:869cf507173a | 346 | #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) |
| emilmont | 77:869cf507173a | 347 | |
| emilmont | 77:869cf507173a | 348 | /** |
| emilmont | 77:869cf507173a | 349 | * @} |
| emilmont | 77:869cf507173a | 350 | */ |
| emilmont | 77:869cf507173a | 351 | |
| emilmont | 77:869cf507173a | 352 | /** @defgroup FSMC_Address_Hold_Time |
| emilmont | 77:869cf507173a | 353 | * @{ |
| emilmont | 77:869cf507173a | 354 | */ |
| emilmont | 77:869cf507173a | 355 | |
| emilmont | 77:869cf507173a | 356 | #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) |
| emilmont | 77:869cf507173a | 357 | |
| emilmont | 77:869cf507173a | 358 | /** |
| emilmont | 77:869cf507173a | 359 | * @} |
| emilmont | 77:869cf507173a | 360 | */ |
| emilmont | 77:869cf507173a | 361 | |
| emilmont | 77:869cf507173a | 362 | /** @defgroup FSMC_Data_Setup_Time |
| emilmont | 77:869cf507173a | 363 | * @{ |
| emilmont | 77:869cf507173a | 364 | */ |
| emilmont | 77:869cf507173a | 365 | |
| emilmont | 77:869cf507173a | 366 | #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) |
| emilmont | 77:869cf507173a | 367 | |
| emilmont | 77:869cf507173a | 368 | /** |
| emilmont | 77:869cf507173a | 369 | * @} |
| emilmont | 77:869cf507173a | 370 | */ |
| emilmont | 77:869cf507173a | 371 | |
| emilmont | 77:869cf507173a | 372 | /** @defgroup FSMC_Bus_Turn_around_Duration |
| emilmont | 77:869cf507173a | 373 | * @{ |
| emilmont | 77:869cf507173a | 374 | */ |
| emilmont | 77:869cf507173a | 375 | |
| emilmont | 77:869cf507173a | 376 | #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) |
| emilmont | 77:869cf507173a | 377 | |
| emilmont | 77:869cf507173a | 378 | /** |
| emilmont | 77:869cf507173a | 379 | * @} |
| emilmont | 77:869cf507173a | 380 | */ |
| emilmont | 77:869cf507173a | 381 | |
| emilmont | 77:869cf507173a | 382 | /** @defgroup FSMC_CLK_Division |
| emilmont | 77:869cf507173a | 383 | * @{ |
| emilmont | 77:869cf507173a | 384 | */ |
| emilmont | 77:869cf507173a | 385 | |
| emilmont | 77:869cf507173a | 386 | #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) |
| emilmont | 77:869cf507173a | 387 | |
| emilmont | 77:869cf507173a | 388 | /** |
| emilmont | 77:869cf507173a | 389 | * @} |
| emilmont | 77:869cf507173a | 390 | */ |
| emilmont | 77:869cf507173a | 391 | |
| emilmont | 77:869cf507173a | 392 | /** @defgroup FSMC_Data_Latency |
| emilmont | 77:869cf507173a | 393 | * @{ |
| emilmont | 77:869cf507173a | 394 | */ |
| emilmont | 77:869cf507173a | 395 | |
| emilmont | 77:869cf507173a | 396 | #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) |
| emilmont | 77:869cf507173a | 397 | |
| emilmont | 77:869cf507173a | 398 | /** |
| emilmont | 77:869cf507173a | 399 | * @} |
| emilmont | 77:869cf507173a | 400 | */ |
| emilmont | 77:869cf507173a | 401 | |
| emilmont | 77:869cf507173a | 402 | /** @defgroup FSMC_Access_Mode |
| emilmont | 77:869cf507173a | 403 | * @{ |
| emilmont | 77:869cf507173a | 404 | */ |
| emilmont | 77:869cf507173a | 405 | |
| emilmont | 77:869cf507173a | 406 | #define FSMC_AccessMode_A ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 407 | #define FSMC_AccessMode_B ((uint32_t)0x10000000) |
| emilmont | 77:869cf507173a | 408 | #define FSMC_AccessMode_C ((uint32_t)0x20000000) |
| emilmont | 77:869cf507173a | 409 | #define FSMC_AccessMode_D ((uint32_t)0x30000000) |
| emilmont | 77:869cf507173a | 410 | #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ |
| emilmont | 77:869cf507173a | 411 | ((MODE) == FSMC_AccessMode_B) || \ |
| emilmont | 77:869cf507173a | 412 | ((MODE) == FSMC_AccessMode_C) || \ |
| emilmont | 77:869cf507173a | 413 | ((MODE) == FSMC_AccessMode_D)) |
| emilmont | 77:869cf507173a | 414 | |
| emilmont | 77:869cf507173a | 415 | /** |
| emilmont | 77:869cf507173a | 416 | * @} |
| emilmont | 77:869cf507173a | 417 | */ |
| emilmont | 77:869cf507173a | 418 | |
| emilmont | 77:869cf507173a | 419 | /** |
| emilmont | 77:869cf507173a | 420 | * @} |
| emilmont | 77:869cf507173a | 421 | */ |
| emilmont | 77:869cf507173a | 422 | |
| emilmont | 77:869cf507173a | 423 | /** |
| emilmont | 77:869cf507173a | 424 | * @} |
| emilmont | 77:869cf507173a | 425 | */ |
| emilmont | 77:869cf507173a | 426 | |
| emilmont | 77:869cf507173a | 427 | /* Exported macro ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 428 | /* Exported functions ------------------------------------------------------- */ |
| emilmont | 77:869cf507173a | 429 | /* NOR/SRAM Controller functions **********************************************/ |
| emilmont | 77:869cf507173a | 430 | void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); |
| emilmont | 77:869cf507173a | 431 | void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); |
| emilmont | 77:869cf507173a | 432 | void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); |
| emilmont | 77:869cf507173a | 433 | void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 434 | |
| emilmont | 77:869cf507173a | 435 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 436 | } |
| emilmont | 77:869cf507173a | 437 | #endif |
| emilmont | 77:869cf507173a | 438 | |
| emilmont | 77:869cf507173a | 439 | #endif /*__STM32L1xx_FSMC_H */ |
| emilmont | 77:869cf507173a | 440 | /** |
| emilmont | 77:869cf507173a | 441 | * @} |
| emilmont | 77:869cf507173a | 442 | */ |
| emilmont | 77:869cf507173a | 443 | |
| emilmont | 77:869cf507173a | 444 | /** |
| emilmont | 77:869cf507173a | 445 | * @} |
| emilmont | 77:869cf507173a | 446 | */ |
| emilmont | 77:869cf507173a | 447 | |
| emilmont | 77:869cf507173a | 448 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
