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TARGET_NUCLEO_L152RE/stm32l1xx_adc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: 81:7d30d6019079

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32l1xx_adc.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
emilmont	77:869cf507173a	5	* @version V1.3.0
emilmont	77:869cf507173a	6	* @date 31-January-2014
emilmont	77:869cf507173a	7	* @brief This file contains all the functions prototypes for the ADC firmware
emilmont	77:869cf507173a	8	* library.
emilmont	77:869cf507173a	9	******************************************************************************
emilmont	77:869cf507173a	10	* @attention
emilmont	77:869cf507173a	11	*
bogdanm	81:7d30d6019079	12	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	13	*
bogdanm	81:7d30d6019079	14	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	81:7d30d6019079	15	* are permitted provided that the following conditions are met:
bogdanm	81:7d30d6019079	16	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	81:7d30d6019079	17	* this list of conditions and the following disclaimer.
bogdanm	81:7d30d6019079	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	81:7d30d6019079	19	* this list of conditions and the following disclaimer in the documentation
bogdanm	81:7d30d6019079	20	* and/or other materials provided with the distribution.
bogdanm	81:7d30d6019079	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	81:7d30d6019079	22	* may be used to endorse or promote products derived from this software
bogdanm	81:7d30d6019079	23	* without specific prior written permission.
emilmont	77:869cf507173a	24	*
bogdanm	81:7d30d6019079	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	81:7d30d6019079	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	81:7d30d6019079	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	81:7d30d6019079	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	81:7d30d6019079	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	81:7d30d6019079	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	81:7d30d6019079	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	81:7d30d6019079	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	81:7d30d6019079	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	81:7d30d6019079	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	35	*
emilmont	77:869cf507173a	36	******************************************************************************
emilmont	77:869cf507173a	37	*/
emilmont	77:869cf507173a	38
emilmont	77:869cf507173a	39	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	40	#ifndef __STM32L1xx_ADC_H
emilmont	77:869cf507173a	41	#define __STM32L1xx_ADC_H
emilmont	77:869cf507173a	42
emilmont	77:869cf507173a	43	#ifdef __cplusplus
emilmont	77:869cf507173a	44	extern "C" {
emilmont	77:869cf507173a	45	#endif
emilmont	77:869cf507173a	46
emilmont	77:869cf507173a	47	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	48	#include "stm32l1xx.h"
emilmont	77:869cf507173a	49
emilmont	77:869cf507173a	50	/** @addtogroup STM32L1xx_StdPeriph_Driver
emilmont	77:869cf507173a	51	* @{
emilmont	77:869cf507173a	52	*/
emilmont	77:869cf507173a	53
emilmont	77:869cf507173a	54	/** @addtogroup ADC
emilmont	77:869cf507173a	55	* @{
emilmont	77:869cf507173a	56	*/
emilmont	77:869cf507173a	57
emilmont	77:869cf507173a	58	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	59
emilmont	77:869cf507173a	60	/**
emilmont	77:869cf507173a	61	* @brief ADC Init structure definition
emilmont	77:869cf507173a	62	*/
emilmont	77:869cf507173a	63
emilmont	77:869cf507173a	64	typedef struct
emilmont	77:869cf507173a	65	{
emilmont	77:869cf507173a	66	uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
emilmont	77:869cf507173a	67	This parameter can be a value of @ref ADC_Resolution */
emilmont	77:869cf507173a	68
emilmont	77:869cf507173a	69	FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
emilmont	77:869cf507173a	70	Scan (multichannel) or Single (one channel) mode.
emilmont	77:869cf507173a	71	This parameter can be set to ENABLE or DISABLE */
emilmont	77:869cf507173a	72
emilmont	77:869cf507173a	73	FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
emilmont	77:869cf507173a	74	Continuous or Single mode.
emilmont	77:869cf507173a	75	This parameter can be set to ENABLE or DISABLE. */
emilmont	77:869cf507173a	76
emilmont	77:869cf507173a	77	uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
emilmont	77:869cf507173a	78	trigger of a regular group. This parameter can be a value
emilmont	77:869cf507173a	79	of @ref ADC_external_trigger_edge_for_regular_channels_conversion */
emilmont	77:869cf507173a	80
emilmont	77:869cf507173a	81	uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
emilmont	77:869cf507173a	82	to digital conversion of regular channels. This parameter
emilmont	77:869cf507173a	83	can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
emilmont	77:869cf507173a	84
emilmont	77:869cf507173a	85	uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
emilmont	77:869cf507173a	86	This parameter can be a value of @ref ADC_data_align */
emilmont	77:869cf507173a	87
emilmont	77:869cf507173a	88	uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done
emilmont	77:869cf507173a	89	using the sequencer for regular channel group.
emilmont	77:869cf507173a	90	This parameter must range from 1 to 27. */
emilmont	77:869cf507173a	91	}ADC_InitTypeDef;
emilmont	77:869cf507173a	92
emilmont	77:869cf507173a	93	typedef struct
emilmont	77:869cf507173a	94	{
emilmont	77:869cf507173a	95	uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.
emilmont	77:869cf507173a	96	This parameter can be a value
emilmont	77:869cf507173a	97	of @ref ADC_Prescaler */
emilmont	77:869cf507173a	98	}ADC_CommonInitTypeDef;
emilmont	77:869cf507173a	99
emilmont	77:869cf507173a	100	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	101
emilmont	77:869cf507173a	102	/** @defgroup ADC_Exported_Constants
emilmont	77:869cf507173a	103	* @{
emilmont	77:869cf507173a	104	*/
emilmont	77:869cf507173a	105	#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
emilmont	77:869cf507173a	106	#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)
emilmont	77:869cf507173a	107
emilmont	77:869cf507173a	108	/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase
emilmont	77:869cf507173a	109	* @{
emilmont	77:869cf507173a	110	*/
emilmont	77:869cf507173a	111	#define ADC_PowerDown_Delay ((uint32_t)0x00010000)
emilmont	77:869cf507173a	112	#define ADC_PowerDown_Idle ((uint32_t)0x00020000)
emilmont	77:869cf507173a	113	#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)
emilmont	77:869cf507173a	114
emilmont	77:869cf507173a	115	#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) \|\| \
emilmont	77:869cf507173a	116	((DWON) == ADC_PowerDown_Idle) \|\| \
emilmont	77:869cf507173a	117	((DWON) == ADC_PowerDown_Idle_Delay))
emilmont	77:869cf507173a	118	/**
emilmont	77:869cf507173a	119	* @}
emilmont	77:869cf507173a	120	*/
emilmont	77:869cf507173a	121
emilmont	77:869cf507173a	122
emilmont	77:869cf507173a	123	/** @defgroup ADC_Prescaler
emilmont	77:869cf507173a	124	* @{
emilmont	77:869cf507173a	125	*/
emilmont	77:869cf507173a	126	#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	127	#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)
emilmont	77:869cf507173a	128	#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)
emilmont	77:869cf507173a	129
emilmont	77:869cf507173a	130	#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) \|\| \
emilmont	77:869cf507173a	131	((PRESCALER) == ADC_Prescaler_Div2) \|\| \
emilmont	77:869cf507173a	132	((PRESCALER) == ADC_Prescaler_Div4))
emilmont	77:869cf507173a	133	/**
emilmont	77:869cf507173a	134	* @}
emilmont	77:869cf507173a	135	*/
emilmont	77:869cf507173a	136
emilmont	77:869cf507173a	137
emilmont	77:869cf507173a	138
emilmont	77:869cf507173a	139	/** @defgroup ADC_Resolution
emilmont	77:869cf507173a	140	* @{
emilmont	77:869cf507173a	141	*/
emilmont	77:869cf507173a	142	#define ADC_Resolution_12b ((uint32_t)0x00000000)
emilmont	77:869cf507173a	143	#define ADC_Resolution_10b ((uint32_t)0x01000000)
emilmont	77:869cf507173a	144	#define ADC_Resolution_8b ((uint32_t)0x02000000)
emilmont	77:869cf507173a	145	#define ADC_Resolution_6b ((uint32_t)0x03000000)
emilmont	77:869cf507173a	146
emilmont	77:869cf507173a	147	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) \|\| \
emilmont	77:869cf507173a	148	((RESOLUTION) == ADC_Resolution_10b) \|\| \
emilmont	77:869cf507173a	149	((RESOLUTION) == ADC_Resolution_8b) \|\| \
emilmont	77:869cf507173a	150	((RESOLUTION) == ADC_Resolution_6b))
emilmont	77:869cf507173a	151
emilmont	77:869cf507173a	152	/**
emilmont	77:869cf507173a	153	* @}
emilmont	77:869cf507173a	154	*/
emilmont	77:869cf507173a	155
emilmont	77:869cf507173a	156	/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
emilmont	77:869cf507173a	157	* @{
emilmont	77:869cf507173a	158	*/
emilmont	77:869cf507173a	159	#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
emilmont	77:869cf507173a	160	#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
emilmont	77:869cf507173a	161	#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
emilmont	77:869cf507173a	162	#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
emilmont	77:869cf507173a	163
emilmont	77:869cf507173a	164	#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) \|\| \
emilmont	77:869cf507173a	165	((EDGE) == ADC_ExternalTrigConvEdge_Rising) \|\| \
emilmont	77:869cf507173a	166	((EDGE) == ADC_ExternalTrigConvEdge_Falling) \|\| \
emilmont	77:869cf507173a	167	((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
emilmont	77:869cf507173a	168	/**
emilmont	77:869cf507173a	169	* @}
emilmont	77:869cf507173a	170	*/
emilmont	77:869cf507173a	171
emilmont	77:869cf507173a	172	/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
emilmont	77:869cf507173a	173	* @{
emilmont	77:869cf507173a	174	*/
emilmont	77:869cf507173a	175
emilmont	77:869cf507173a	176	/* TIM2 */
emilmont	77:869cf507173a	177	#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)
emilmont	77:869cf507173a	178	#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
emilmont	77:869cf507173a	179	#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
emilmont	77:869cf507173a	180
emilmont	77:869cf507173a	181	/* TIM3 */
emilmont	77:869cf507173a	182	#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
emilmont	77:869cf507173a	183	#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)
emilmont	77:869cf507173a	184	#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)
emilmont	77:869cf507173a	185
emilmont	77:869cf507173a	186	/* TIM4 */
emilmont	77:869cf507173a	187	#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)
emilmont	77:869cf507173a	188	#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)
emilmont	77:869cf507173a	189
emilmont	77:869cf507173a	190	/* TIM6 */
emilmont	77:869cf507173a	191	#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)
emilmont	77:869cf507173a	192
emilmont	77:869cf507173a	193	/* TIM9 */
emilmont	77:869cf507173a	194	#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	195	#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)
emilmont	77:869cf507173a	196
emilmont	77:869cf507173a	197	/* EXTI */
emilmont	77:869cf507173a	198	#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
emilmont	77:869cf507173a	199
emilmont	77:869cf507173a	200	#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) \|\| \
emilmont	77:869cf507173a	201	((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) \|\| \
emilmont	77:869cf507173a	202	((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) \|\| \
emilmont	77:869cf507173a	203	((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) \|\| \
emilmont	77:869cf507173a	204	((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) \|\| \
emilmont	77:869cf507173a	205	((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) \|\| \
emilmont	77:869cf507173a	206	((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) \|\| \
emilmont	77:869cf507173a	207	((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) \|\| \
emilmont	77:869cf507173a	208	((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) \|\| \
emilmont	77:869cf507173a	209	((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) \|\| \
emilmont	77:869cf507173a	210	((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) \|\| \
emilmont	77:869cf507173a	211	((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
emilmont	77:869cf507173a	212	/**
emilmont	77:869cf507173a	213	* @}
emilmont	77:869cf507173a	214	*/
emilmont	77:869cf507173a	215
emilmont	77:869cf507173a	216	/** @defgroup ADC_data_align
emilmont	77:869cf507173a	217	* @{
emilmont	77:869cf507173a	218	*/
emilmont	77:869cf507173a	219
emilmont	77:869cf507173a	220	#define ADC_DataAlign_Right ((uint32_t)0x00000000)
emilmont	77:869cf507173a	221	#define ADC_DataAlign_Left ((uint32_t)0x00000800)
emilmont	77:869cf507173a	222
emilmont	77:869cf507173a	223	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) \|\| \
emilmont	77:869cf507173a	224	((ALIGN) == ADC_DataAlign_Left))
emilmont	77:869cf507173a	225	/**
emilmont	77:869cf507173a	226	* @}
emilmont	77:869cf507173a	227	*/
emilmont	77:869cf507173a	228
emilmont	77:869cf507173a	229	/** @defgroup ADC_channels
emilmont	77:869cf507173a	230	* @{
emilmont	77:869cf507173a	231	*/
emilmont	77:869cf507173a	232	/* ADC Bank A Channels -------------------------------------------------------*/
emilmont	77:869cf507173a	233	#define ADC_Channel_0 ((uint8_t)0x00)
emilmont	77:869cf507173a	234	#define ADC_Channel_1 ((uint8_t)0x01)
emilmont	77:869cf507173a	235	#define ADC_Channel_2 ((uint8_t)0x02)
emilmont	77:869cf507173a	236	#define ADC_Channel_3 ((uint8_t)0x03)
emilmont	77:869cf507173a	237
emilmont	77:869cf507173a	238	#define ADC_Channel_6 ((uint8_t)0x06)
emilmont	77:869cf507173a	239	#define ADC_Channel_7 ((uint8_t)0x07)
emilmont	77:869cf507173a	240	#define ADC_Channel_8 ((uint8_t)0x08)
emilmont	77:869cf507173a	241	#define ADC_Channel_9 ((uint8_t)0x09)
emilmont	77:869cf507173a	242	#define ADC_Channel_10 ((uint8_t)0x0A)
emilmont	77:869cf507173a	243	#define ADC_Channel_11 ((uint8_t)0x0B)
emilmont	77:869cf507173a	244	#define ADC_Channel_12 ((uint8_t)0x0C)
emilmont	77:869cf507173a	245
emilmont	77:869cf507173a	246
emilmont	77:869cf507173a	247	/* ADC Bank B Channels -------------------------------------------------------*/
emilmont	77:869cf507173a	248	#define ADC_Channel_0b ADC_Channel_0
emilmont	77:869cf507173a	249	#define ADC_Channel_1b ADC_Channel_1
emilmont	77:869cf507173a	250	#define ADC_Channel_2b ADC_Channel_2
emilmont	77:869cf507173a	251	#define ADC_Channel_3b ADC_Channel_3
emilmont	77:869cf507173a	252
emilmont	77:869cf507173a	253	#define ADC_Channel_6b ADC_Channel_6
emilmont	77:869cf507173a	254	#define ADC_Channel_7b ADC_Channel_7
emilmont	77:869cf507173a	255	#define ADC_Channel_8b ADC_Channel_8
emilmont	77:869cf507173a	256	#define ADC_Channel_9b ADC_Channel_9
emilmont	77:869cf507173a	257	#define ADC_Channel_10b ADC_Channel_10
emilmont	77:869cf507173a	258	#define ADC_Channel_11b ADC_Channel_11
emilmont	77:869cf507173a	259	#define ADC_Channel_12b ADC_Channel_12
emilmont	77:869cf507173a	260
emilmont	77:869cf507173a	261	/* ADC Common Channels (ADC Bank A and B) ------------------------------------*/
emilmont	77:869cf507173a	262	#define ADC_Channel_4 ((uint8_t)0x04)
emilmont	77:869cf507173a	263	#define ADC_Channel_5 ((uint8_t)0x05)
emilmont	77:869cf507173a	264
emilmont	77:869cf507173a	265	#define ADC_Channel_13 ((uint8_t)0x0D)
emilmont	77:869cf507173a	266	#define ADC_Channel_14 ((uint8_t)0x0E)
emilmont	77:869cf507173a	267	#define ADC_Channel_15 ((uint8_t)0x0F)
emilmont	77:869cf507173a	268	#define ADC_Channel_16 ((uint8_t)0x10)
emilmont	77:869cf507173a	269	#define ADC_Channel_17 ((uint8_t)0x11)
emilmont	77:869cf507173a	270	#define ADC_Channel_18 ((uint8_t)0x12)
emilmont	77:869cf507173a	271	#define ADC_Channel_19 ((uint8_t)0x13)
emilmont	77:869cf507173a	272	#define ADC_Channel_20 ((uint8_t)0x14)
emilmont	77:869cf507173a	273	#define ADC_Channel_21 ((uint8_t)0x15)
emilmont	77:869cf507173a	274	#define ADC_Channel_22 ((uint8_t)0x16)
emilmont	77:869cf507173a	275	#define ADC_Channel_23 ((uint8_t)0x17)
emilmont	77:869cf507173a	276	#define ADC_Channel_24 ((uint8_t)0x18)
emilmont	77:869cf507173a	277	#define ADC_Channel_25 ((uint8_t)0x19)
emilmont	77:869cf507173a	278
emilmont	77:869cf507173a	279	#define ADC_Channel_27 ((uint8_t)0x1B)
emilmont	77:869cf507173a	280	#define ADC_Channel_28 ((uint8_t)0x1C)
emilmont	77:869cf507173a	281	#define ADC_Channel_29 ((uint8_t)0x1D)
emilmont	77:869cf507173a	282	#define ADC_Channel_30 ((uint8_t)0x1E)
emilmont	77:869cf507173a	283	#define ADC_Channel_31 ((uint8_t)0x1F)
emilmont	77:869cf507173a	284
emilmont	77:869cf507173a	285	#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
emilmont	77:869cf507173a	286	#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
emilmont	77:869cf507173a	287
emilmont	77:869cf507173a	288	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) \|\| ((CHANNEL) == ADC_Channel_1) \|\| \
emilmont	77:869cf507173a	289	((CHANNEL) == ADC_Channel_2) \|\| ((CHANNEL) == ADC_Channel_3) \|\| \
emilmont	77:869cf507173a	290	((CHANNEL) == ADC_Channel_4) \|\| ((CHANNEL) == ADC_Channel_5) \|\| \
emilmont	77:869cf507173a	291	((CHANNEL) == ADC_Channel_6) \|\| ((CHANNEL) == ADC_Channel_7) \|\| \
emilmont	77:869cf507173a	292	((CHANNEL) == ADC_Channel_8) \|\| ((CHANNEL) == ADC_Channel_9) \|\| \
emilmont	77:869cf507173a	293	((CHANNEL) == ADC_Channel_10) \|\| ((CHANNEL) == ADC_Channel_11) \|\| \
emilmont	77:869cf507173a	294	((CHANNEL) == ADC_Channel_12) \|\| ((CHANNEL) == ADC_Channel_13) \|\| \
emilmont	77:869cf507173a	295	((CHANNEL) == ADC_Channel_14) \|\| ((CHANNEL) == ADC_Channel_15) \|\| \
emilmont	77:869cf507173a	296	((CHANNEL) == ADC_Channel_16) \|\| ((CHANNEL) == ADC_Channel_17) \|\| \
emilmont	77:869cf507173a	297	((CHANNEL) == ADC_Channel_18) \|\| ((CHANNEL) == ADC_Channel_19) \|\| \
emilmont	77:869cf507173a	298	((CHANNEL) == ADC_Channel_20) \|\| ((CHANNEL) == ADC_Channel_21) \|\| \
emilmont	77:869cf507173a	299	((CHANNEL) == ADC_Channel_22) \|\| ((CHANNEL) == ADC_Channel_23) \|\| \
emilmont	77:869cf507173a	300	((CHANNEL) == ADC_Channel_24) \|\| ((CHANNEL) == ADC_Channel_25) \|\| \
emilmont	77:869cf507173a	301	((CHANNEL) == ADC_Channel_27) \|\| ((CHANNEL) == ADC_Channel_28) \|\| \
emilmont	77:869cf507173a	302	((CHANNEL) == ADC_Channel_29) \|\| ((CHANNEL) == ADC_Channel_30) \|\| \
emilmont	77:869cf507173a	303	((CHANNEL) == ADC_Channel_31))
emilmont	77:869cf507173a	304	/**
emilmont	77:869cf507173a	305	* @}
emilmont	77:869cf507173a	306	*/
emilmont	77:869cf507173a	307
emilmont	77:869cf507173a	308	/** @defgroup ADC_sampling_times
emilmont	77:869cf507173a	309	* @{
emilmont	77:869cf507173a	310	*/
emilmont	77:869cf507173a	311
emilmont	77:869cf507173a	312	#define ADC_SampleTime_4Cycles ((uint8_t)0x00)
emilmont	77:869cf507173a	313	#define ADC_SampleTime_9Cycles ((uint8_t)0x01)
emilmont	77:869cf507173a	314	#define ADC_SampleTime_16Cycles ((uint8_t)0x02)
emilmont	77:869cf507173a	315	#define ADC_SampleTime_24Cycles ((uint8_t)0x03)
emilmont	77:869cf507173a	316	#define ADC_SampleTime_48Cycles ((uint8_t)0x04)
emilmont	77:869cf507173a	317	#define ADC_SampleTime_96Cycles ((uint8_t)0x05)
emilmont	77:869cf507173a	318	#define ADC_SampleTime_192Cycles ((uint8_t)0x06)
emilmont	77:869cf507173a	319	#define ADC_SampleTime_384Cycles ((uint8_t)0x07)
emilmont	77:869cf507173a	320
emilmont	77:869cf507173a	321	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) \|\| \
emilmont	77:869cf507173a	322	((TIME) == ADC_SampleTime_9Cycles) \|\| \
emilmont	77:869cf507173a	323	((TIME) == ADC_SampleTime_16Cycles) \|\| \
emilmont	77:869cf507173a	324	((TIME) == ADC_SampleTime_24Cycles) \|\| \
emilmont	77:869cf507173a	325	((TIME) == ADC_SampleTime_48Cycles) \|\| \
emilmont	77:869cf507173a	326	((TIME) == ADC_SampleTime_96Cycles) \|\| \
emilmont	77:869cf507173a	327	((TIME) == ADC_SampleTime_192Cycles) \|\| \
emilmont	77:869cf507173a	328	((TIME) == ADC_SampleTime_384Cycles))
emilmont	77:869cf507173a	329	/**
emilmont	77:869cf507173a	330	* @}
emilmont	77:869cf507173a	331	*/
emilmont	77:869cf507173a	332
emilmont	77:869cf507173a	333	/** @defgroup ADC_Delay_length
emilmont	77:869cf507173a	334	* @{
emilmont	77:869cf507173a	335	*/
emilmont	77:869cf507173a	336
emilmont	77:869cf507173a	337	#define ADC_DelayLength_None ((uint8_t)0x00)
emilmont	77:869cf507173a	338	#define ADC_DelayLength_Freeze ((uint8_t)0x10)
emilmont	77:869cf507173a	339	#define ADC_DelayLength_7Cycles ((uint8_t)0x20)
emilmont	77:869cf507173a	340	#define ADC_DelayLength_15Cycles ((uint8_t)0x30)
emilmont	77:869cf507173a	341	#define ADC_DelayLength_31Cycles ((uint8_t)0x40)
emilmont	77:869cf507173a	342	#define ADC_DelayLength_63Cycles ((uint8_t)0x50)
emilmont	77:869cf507173a	343	#define ADC_DelayLength_127Cycles ((uint8_t)0x60)
emilmont	77:869cf507173a	344	#define ADC_DelayLength_255Cycles ((uint8_t)0x70)
emilmont	77:869cf507173a	345
emilmont	77:869cf507173a	346	#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) \|\| \
emilmont	77:869cf507173a	347	((LENGTH) == ADC_DelayLength_Freeze) \|\| \
emilmont	77:869cf507173a	348	((LENGTH) == ADC_DelayLength_7Cycles) \|\| \
emilmont	77:869cf507173a	349	((LENGTH) == ADC_DelayLength_15Cycles) \|\| \
emilmont	77:869cf507173a	350	((LENGTH) == ADC_DelayLength_31Cycles) \|\| \
emilmont	77:869cf507173a	351	((LENGTH) == ADC_DelayLength_63Cycles) \|\| \
emilmont	77:869cf507173a	352	((LENGTH) == ADC_DelayLength_127Cycles) \|\| \
emilmont	77:869cf507173a	353	((LENGTH) == ADC_DelayLength_255Cycles))
emilmont	77:869cf507173a	354
emilmont	77:869cf507173a	355	/**
emilmont	77:869cf507173a	356	* @}
emilmont	77:869cf507173a	357	*/
emilmont	77:869cf507173a	358
emilmont	77:869cf507173a	359	/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
emilmont	77:869cf507173a	360	* @{
emilmont	77:869cf507173a	361	*/
emilmont	77:869cf507173a	362	#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
emilmont	77:869cf507173a	363	#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
emilmont	77:869cf507173a	364	#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
emilmont	77:869cf507173a	365	#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
emilmont	77:869cf507173a	366
emilmont	77:869cf507173a	367	#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) \|\| \
emilmont	77:869cf507173a	368	((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) \|\| \
emilmont	77:869cf507173a	369	((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) \|\| \
emilmont	77:869cf507173a	370	((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
emilmont	77:869cf507173a	371	/**
emilmont	77:869cf507173a	372	* @}
emilmont	77:869cf507173a	373	*/
emilmont	77:869cf507173a	374
emilmont	77:869cf507173a	375
emilmont	77:869cf507173a	376	/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
emilmont	77:869cf507173a	377	* @{
emilmont	77:869cf507173a	378	*/
emilmont	77:869cf507173a	379
emilmont	77:869cf507173a	380
emilmont	77:869cf507173a	381	/* TIM2 */
emilmont	77:869cf507173a	382	#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)
emilmont	77:869cf507173a	383	#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)
emilmont	77:869cf507173a	384
emilmont	77:869cf507173a	385	/* TIM3 */
emilmont	77:869cf507173a	386	#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)
emilmont	77:869cf507173a	387
emilmont	77:869cf507173a	388	/* TIM4 */
emilmont	77:869cf507173a	389	#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)
emilmont	77:869cf507173a	390	#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
emilmont	77:869cf507173a	391	#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
emilmont	77:869cf507173a	392	#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
emilmont	77:869cf507173a	393
emilmont	77:869cf507173a	394	/* TIM7 */
emilmont	77:869cf507173a	395	#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)
emilmont	77:869cf507173a	396
emilmont	77:869cf507173a	397	/* TIM9 */
emilmont	77:869cf507173a	398	#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	399	#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)
emilmont	77:869cf507173a	400
emilmont	77:869cf507173a	401	/* TIM10 */
emilmont	77:869cf507173a	402	#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)
emilmont	77:869cf507173a	403
emilmont	77:869cf507173a	404	/* EXTI */
emilmont	77:869cf507173a	405	#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
emilmont	77:869cf507173a	406
emilmont	77:869cf507173a	407	#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) \|\| \
emilmont	77:869cf507173a	408	((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) \|\| \
emilmont	77:869cf507173a	409	((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) \|\| \
emilmont	77:869cf507173a	410	((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) \|\| \
emilmont	77:869cf507173a	411	((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) \|\| \
emilmont	77:869cf507173a	412	((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) \|\| \
emilmont	77:869cf507173a	413	((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) \|\| \
emilmont	77:869cf507173a	414	((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) \|\| \
emilmont	77:869cf507173a	415	((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) \|\| \
emilmont	77:869cf507173a	416	((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) \|\| \
emilmont	77:869cf507173a	417	((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) \|\| \
emilmont	77:869cf507173a	418	((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
emilmont	77:869cf507173a	419	/**
emilmont	77:869cf507173a	420	* @}
emilmont	77:869cf507173a	421	*/
emilmont	77:869cf507173a	422
emilmont	77:869cf507173a	423	/** @defgroup ADC_injected_channel_selection
emilmont	77:869cf507173a	424	* @{
emilmont	77:869cf507173a	425	*/
emilmont	77:869cf507173a	426	#define ADC_InjectedChannel_1 ((uint8_t)0x18)
emilmont	77:869cf507173a	427	#define ADC_InjectedChannel_2 ((uint8_t)0x1C)
emilmont	77:869cf507173a	428	#define ADC_InjectedChannel_3 ((uint8_t)0x20)
emilmont	77:869cf507173a	429	#define ADC_InjectedChannel_4 ((uint8_t)0x24)
emilmont	77:869cf507173a	430
emilmont	77:869cf507173a	431	#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) \|\| \
emilmont	77:869cf507173a	432	((CHANNEL) == ADC_InjectedChannel_2) \|\| \
emilmont	77:869cf507173a	433	((CHANNEL) == ADC_InjectedChannel_3) \|\| \
emilmont	77:869cf507173a	434	((CHANNEL) == ADC_InjectedChannel_4))
emilmont	77:869cf507173a	435	/**
emilmont	77:869cf507173a	436	* @}
emilmont	77:869cf507173a	437	*/
emilmont	77:869cf507173a	438
emilmont	77:869cf507173a	439	/** @defgroup ADC_analog_watchdog_selection
emilmont	77:869cf507173a	440	* @{
emilmont	77:869cf507173a	441	*/
emilmont	77:869cf507173a	442
emilmont	77:869cf507173a	443	#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
emilmont	77:869cf507173a	444	#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
emilmont	77:869cf507173a	445	#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
emilmont	77:869cf507173a	446	#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
emilmont	77:869cf507173a	447	#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
emilmont	77:869cf507173a	448	#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
emilmont	77:869cf507173a	449	#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
emilmont	77:869cf507173a	450
emilmont	77:869cf507173a	451	#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) \|\| \
emilmont	77:869cf507173a	452	((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) \|\| \
emilmont	77:869cf507173a	453	((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) \|\| \
emilmont	77:869cf507173a	454	((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) \|\| \
emilmont	77:869cf507173a	455	((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) \|\| \
emilmont	77:869cf507173a	456	((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) \|\| \
emilmont	77:869cf507173a	457	((WATCHDOG) == ADC_AnalogWatchdog_None))
emilmont	77:869cf507173a	458	/**
emilmont	77:869cf507173a	459	* @}
emilmont	77:869cf507173a	460	*/
emilmont	77:869cf507173a	461
emilmont	77:869cf507173a	462	/** @defgroup ADC_interrupts_definition
emilmont	77:869cf507173a	463	* @{
emilmont	77:869cf507173a	464	*/
emilmont	77:869cf507173a	465
emilmont	77:869cf507173a	466	#define ADC_IT_AWD ((uint16_t)0x0106)
emilmont	77:869cf507173a	467	#define ADC_IT_EOC ((uint16_t)0x0205)
emilmont	77:869cf507173a	468	#define ADC_IT_JEOC ((uint16_t)0x0407)
emilmont	77:869cf507173a	469	#define ADC_IT_OVR ((uint16_t)0x201A)
emilmont	77:869cf507173a	470
emilmont	77:869cf507173a	471	#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) \|\| ((IT) == ADC_IT_EOC) \|\| \
emilmont	77:869cf507173a	472	((IT) == ADC_IT_JEOC)\|\| ((IT) == ADC_IT_OVR))
emilmont	77:869cf507173a	473	/**
emilmont	77:869cf507173a	474	* @}
emilmont	77:869cf507173a	475	*/
emilmont	77:869cf507173a	476
emilmont	77:869cf507173a	477	/** @defgroup ADC_flags_definition
emilmont	77:869cf507173a	478	* @{
emilmont	77:869cf507173a	479	*/
emilmont	77:869cf507173a	480
emilmont	77:869cf507173a	481	#define ADC_FLAG_AWD ((uint16_t)0x0001)
emilmont	77:869cf507173a	482	#define ADC_FLAG_EOC ((uint16_t)0x0002)
emilmont	77:869cf507173a	483	#define ADC_FLAG_JEOC ((uint16_t)0x0004)
emilmont	77:869cf507173a	484	#define ADC_FLAG_JSTRT ((uint16_t)0x0008)
emilmont	77:869cf507173a	485	#define ADC_FLAG_STRT ((uint16_t)0x0010)
emilmont	77:869cf507173a	486	#define ADC_FLAG_OVR ((uint16_t)0x0020)
emilmont	77:869cf507173a	487	#define ADC_FLAG_ADONS ((uint16_t)0x0040)
emilmont	77:869cf507173a	488	#define ADC_FLAG_RCNR ((uint16_t)0x0100)
emilmont	77:869cf507173a	489	#define ADC_FLAG_JCNR ((uint16_t)0x0200)
emilmont	77:869cf507173a	490
emilmont	77:869cf507173a	491	#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))
emilmont	77:869cf507173a	492
emilmont	77:869cf507173a	493	#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) \|\| ((FLAG) == ADC_FLAG_EOC) \|\| \
emilmont	77:869cf507173a	494	((FLAG) == ADC_FLAG_JEOC) \|\| ((FLAG)== ADC_FLAG_JSTRT) \|\| \
emilmont	77:869cf507173a	495	((FLAG) == ADC_FLAG_STRT) \|\| ((FLAG)== ADC_FLAG_OVR) \|\| \
emilmont	77:869cf507173a	496	((FLAG) == ADC_FLAG_ADONS) \|\| ((FLAG)== ADC_FLAG_RCNR) \|\| \
emilmont	77:869cf507173a	497	((FLAG) == ADC_FLAG_JCNR))
emilmont	77:869cf507173a	498	/**
emilmont	77:869cf507173a	499	* @}
emilmont	77:869cf507173a	500	*/
emilmont	77:869cf507173a	501
emilmont	77:869cf507173a	502	/** @defgroup ADC_thresholds
emilmont	77:869cf507173a	503	* @{
emilmont	77:869cf507173a	504	*/
emilmont	77:869cf507173a	505
emilmont	77:869cf507173a	506	#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
emilmont	77:869cf507173a	507
emilmont	77:869cf507173a	508	/**
emilmont	77:869cf507173a	509	* @}
emilmont	77:869cf507173a	510	*/
emilmont	77:869cf507173a	511
emilmont	77:869cf507173a	512	/** @defgroup ADC_injected_offset
emilmont	77:869cf507173a	513	* @{
emilmont	77:869cf507173a	514	*/
emilmont	77:869cf507173a	515
emilmont	77:869cf507173a	516	#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
emilmont	77:869cf507173a	517
emilmont	77:869cf507173a	518	/**
emilmont	77:869cf507173a	519	* @}
emilmont	77:869cf507173a	520	*/
emilmont	77:869cf507173a	521
emilmont	77:869cf507173a	522	/** @defgroup ADC_injected_length
emilmont	77:869cf507173a	523	* @{
emilmont	77:869cf507173a	524	*/
emilmont	77:869cf507173a	525
emilmont	77:869cf507173a	526	#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
emilmont	77:869cf507173a	527
emilmont	77:869cf507173a	528	/**
emilmont	77:869cf507173a	529	* @}
emilmont	77:869cf507173a	530	*/
emilmont	77:869cf507173a	531
emilmont	77:869cf507173a	532	/** @defgroup ADC_injected_rank
emilmont	77:869cf507173a	533	* @{
emilmont	77:869cf507173a	534	*/
emilmont	77:869cf507173a	535
emilmont	77:869cf507173a	536	#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
emilmont	77:869cf507173a	537
emilmont	77:869cf507173a	538	/**
emilmont	77:869cf507173a	539	* @}
emilmont	77:869cf507173a	540	*/
emilmont	77:869cf507173a	541
emilmont	77:869cf507173a	542	/** @defgroup ADC_regular_length
emilmont	77:869cf507173a	543	* @{
emilmont	77:869cf507173a	544	*/
emilmont	77:869cf507173a	545
emilmont	77:869cf507173a	546	#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))
emilmont	77:869cf507173a	547
emilmont	77:869cf507173a	548	/**
emilmont	77:869cf507173a	549	* @}
emilmont	77:869cf507173a	550	*/
emilmont	77:869cf507173a	551
emilmont	77:869cf507173a	552	/** @defgroup ADC_regular_rank
emilmont	77:869cf507173a	553	* @{
emilmont	77:869cf507173a	554	*/
emilmont	77:869cf507173a	555
emilmont	77:869cf507173a	556	#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))
emilmont	77:869cf507173a	557
emilmont	77:869cf507173a	558	/**
emilmont	77:869cf507173a	559	* @}
emilmont	77:869cf507173a	560	*/
emilmont	77:869cf507173a	561
emilmont	77:869cf507173a	562	/** @defgroup ADC_regular_discontinuous_mode_number
emilmont	77:869cf507173a	563	* @{
emilmont	77:869cf507173a	564	*/
emilmont	77:869cf507173a	565
emilmont	77:869cf507173a	566	#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
emilmont	77:869cf507173a	567
emilmont	77:869cf507173a	568	/**
emilmont	77:869cf507173a	569	* @}
emilmont	77:869cf507173a	570	*/
emilmont	77:869cf507173a	571
emilmont	77:869cf507173a	572	/** @defgroup ADC_Bank_Selection
emilmont	77:869cf507173a	573	* @{
emilmont	77:869cf507173a	574	*/
emilmont	77:869cf507173a	575	#define ADC_Bank_A ((uint8_t)0x00)
emilmont	77:869cf507173a	576	#define ADC_Bank_B ((uint8_t)0x01)
emilmont	77:869cf507173a	577	#define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) \|\| ((BANK) == ADC_Bank_B))
emilmont	77:869cf507173a	578
emilmont	77:869cf507173a	579	/**
emilmont	77:869cf507173a	580	* @}
emilmont	77:869cf507173a	581	*/
emilmont	77:869cf507173a	582
emilmont	77:869cf507173a	583	/**
emilmont	77:869cf507173a	584	* @}
emilmont	77:869cf507173a	585	*/
emilmont	77:869cf507173a	586
emilmont	77:869cf507173a	587	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	588	/* Exported functions ------------------------------------------------------- */
emilmont	77:869cf507173a	589
emilmont	77:869cf507173a	590	/* Function used to set the ADC configuration to the default reset state *****/
emilmont	77:869cf507173a	591	void ADC_DeInit(ADC_TypeDef* ADCx);
emilmont	77:869cf507173a	592
emilmont	77:869cf507173a	593	/* Initialization and Configuration functions *********************************/
emilmont	77:869cf507173a	594	void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
emilmont	77:869cf507173a	595	void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
emilmont	77:869cf507173a	596	void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
emilmont	77:869cf507173a	597	void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
emilmont	77:869cf507173a	598	void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
emilmont	77:869cf507173a	599	void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank);
emilmont	77:869cf507173a	600
emilmont	77:869cf507173a	601	/* Power saving functions *****************************************************/
emilmont	77:869cf507173a	602	void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);
emilmont	77:869cf507173a	603	void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);
emilmont	77:869cf507173a	604
emilmont	77:869cf507173a	605	/* Analog Watchdog configuration functions ************************************/
emilmont	77:869cf507173a	606	void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
emilmont	77:869cf507173a	607	void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
emilmont	77:869cf507173a	608	void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
emilmont	77:869cf507173a	609
emilmont	77:869cf507173a	610	/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */
emilmont	77:869cf507173a	611	void ADC_TempSensorVrefintCmd(FunctionalState NewState);
emilmont	77:869cf507173a	612
emilmont	77:869cf507173a	613	/* Regular Channels Configuration functions ***********************************/
emilmont	77:869cf507173a	614	void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
emilmont	77:869cf507173a	615	void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
emilmont	77:869cf507173a	616	FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
emilmont	77:869cf507173a	617	void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
emilmont	77:869cf507173a	618	void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
emilmont	77:869cf507173a	619	void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
emilmont	77:869cf507173a	620	void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
emilmont	77:869cf507173a	621	uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
emilmont	77:869cf507173a	622
emilmont	77:869cf507173a	623	/* Regular Channels DMA Configuration functions *******************************/
emilmont	77:869cf507173a	624	void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
emilmont	77:869cf507173a	625	void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
emilmont	77:869cf507173a	626
emilmont	77:869cf507173a	627	/* Injected channels Configuration functions **********************************/
emilmont	77:869cf507173a	628	void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
emilmont	77:869cf507173a	629	void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
emilmont	77:869cf507173a	630	void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
emilmont	77:869cf507173a	631	void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
emilmont	77:869cf507173a	632	void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
emilmont	77:869cf507173a	633	void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
emilmont	77:869cf507173a	634	FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
emilmont	77:869cf507173a	635	void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
emilmont	77:869cf507173a	636	void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
emilmont	77:869cf507173a	637	uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
emilmont	77:869cf507173a	638
emilmont	77:869cf507173a	639	/* Interrupts and flags management functions **********************************/
emilmont	77:869cf507173a	640	void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
emilmont	77:869cf507173a	641	FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
emilmont	77:869cf507173a	642	void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
emilmont	77:869cf507173a	643	ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
emilmont	77:869cf507173a	644	void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
emilmont	77:869cf507173a	645
emilmont	77:869cf507173a	646	#ifdef __cplusplus
emilmont	77:869cf507173a	647	}
emilmont	77:869cf507173a	648	#endif
emilmont	77:869cf507173a	649
emilmont	77:869cf507173a	650	#endif /__STM32L1xx_ADC_H /
emilmont	77:869cf507173a	651
emilmont	77:869cf507173a	652	/**
emilmont	77:869cf507173a	653	* @}
emilmont	77:869cf507173a	654	*/
emilmont	77:869cf507173a	655
emilmont	77:869cf507173a	656	/**
emilmont	77:869cf507173a	657	* @}
emilmont	77:869cf507173a	658	*/
emilmont	77:869cf507173a	659
emilmont	77:869cf507173a	660	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/